Operational amplifier circuit, operational amplifier chip and electronic device

Abstract

This application relates to an operational amplifier circuit, an op-amp chip, and an electronic device. At the first input differential pair of the first differential input circuit, a first auxiliary differential pair of the same type but with a proportionally reduced switching transistor size is connected in parallel. The gates of the first auxiliary differential pair are connected to a first differential voltage adjustment circuit, which is configured to adjust the output voltage. When voltage offset occurs in the operational amplifier circuit, the calibration voltage between the output and the gates of the first auxiliary differential pair is adjusted to create a gate-source voltage difference, causing current imbalance between the first auxiliary differential pairs. An equivalent input offset compensation voltage is introduced into the input stage through this imbalance current. This input offset compensation voltage has the opposite polarity and direction to the offset voltage, thereby canceling out the offset voltage and achieving offset calibration. This approach achieves high op-amp offset voltage calibration accuracy while maintaining hardware cost.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to an operational amplifier circuit, an operational amplifier chip, and an electronic device. Background Technology

[0002] With the rapid development of science and technology, electronic products are becoming increasingly diverse. Operational amplifiers, as core components for signal amplification, processing, and conversion, are widely used in electronic products. Operational amplifiers are prone to operational amplifier misalignment, which occurs when the input is zero and the output is non-zero due to mismatched internal component parameters. This phenomenon severely affects the operating accuracy of the operational amplifier.

[0003] To mitigate operational amplifier offset, current methods primarily employ self-zeroing, chopping, and linear calibration techniques to calibrate the operational amplifier's offset voltage. However, self-zeroing and chopping techniques require clock signals, increasing hardware costs; while linear calibration is susceptible to temperature drift, resulting in poor calibration accuracy. Summary of the Invention

[0004] Therefore, it is necessary to provide an operational amplifier circuit, operational amplifier chip, and electronic device that can balance hardware cost and have high operational amplifier offset voltage calibration accuracy to address the above problems.

[0005] This application provides an operational amplifier circuit, including a first differential input circuit, a gain output circuit, and a first adjustable differential circuit. The first differential input circuit includes a first input differential pair transistor; the first output terminal and the second output terminal of the first input differential pair transistor are respectively connected to the gain output circuit. The first adjustable differential circuit includes a first differential voltage adjustment circuit, a first auxiliary differential pair transistor, and a first current bias circuit. The first auxiliary differential pair transistor includes a first switching transistor and a second switching transistor. The first terminal of the first switching transistor and the first terminal of the second switching transistor are respectively connected to the first current bias circuit, and the second terminal of the first switching transistor is connected to... The first output terminal of the first input differential pair transistor is connected to the first output terminal of the second switch transistor, and the second terminal of the second switch transistor is connected to the second output terminal of the first input differential pair transistor. The gates of the first switch transistor and the second switch transistor are respectively connected to the first differential voltage adjustment circuit. The first differential voltage adjustment circuit is used to adjust the differential calibration voltage output to the gates of the first switch transistor and the second switch transistor. The first auxiliary differential pair transistor is of the same type as the first input differential pair transistor, and the switching transistor size of the first auxiliary differential pair transistor is K1 times the switching transistor size of the first input differential pair transistor, where K1 is greater than 0 and less than 1.

[0006] In one embodiment, the first differential voltage regulation circuit includes a second current bias circuit and an adjustable resistor circuit. The first output terminal of the second current bias circuit is connected to the first terminal of the adjustable resistor circuit and the gate of the first switching transistor, and the second output terminal of the second current bias circuit is connected to the second terminal of the adjustable resistor circuit and the gate of the second switching transistor.

[0007] In one embodiment, the adjustable resistor circuit includes a first resistor circuit and a second resistor circuit, wherein a first terminal of the first resistor circuit serves as the first terminal of the adjustable resistor circuit, a second terminal of the first resistor circuit is grounded, a first terminal of the second resistor circuit serves as the second terminal of the adjustable resistor circuit, and a second terminal of the second resistor circuit is grounded; wherein at least one of the first resistor circuit and the second resistor circuit is configured to have an adjustable resistance value.

[0008] In one embodiment, the first resistor circuit includes a first adjustable resistor, and the second resistor circuit includes a second adjustable resistor.

[0009] In one embodiment, the second current bias circuit includes a first current source and a second current source, which are respectively connected to a power supply. The first current source is connected to a first terminal of the adjustable resistor circuit and the gate of the first switching transistor, and the second current source is connected to a second terminal of the adjustable resistor circuit and the gate of the second switching transistor.

[0010] In one embodiment, the first differential input circuit further includes a third current bias circuit, wherein the first input differential pair is connected to the third current bias circuit; wherein the output current of the first current bias circuit is K1 times the output current of the third current bias circuit.

[0011] In one embodiment, the operational amplifier circuit further includes a second differential input circuit and a second adjustable differential circuit; the second differential input circuit includes a second input differential pair of transistors of a different type than the first input differential pair, and the first and second output terminals of the second input differential pair are respectively connected to the gain output circuit; the second adjustable differential circuit includes a second differential voltage adjustment circuit, a second auxiliary differential pair of transistors, and a fourth current bias circuit, the second auxiliary differential pair of transistors including a third switch and a fourth switch, the first terminals of the third switch and the fourth switch being respectively connected to the fourth current bias circuit, the third switch... The second terminal of the switch is connected to the first output terminal of the second input differential pair, the second terminal of the fourth switch is connected to the second output terminal of the second input differential pair, and the gates of the third and fourth switches are respectively connected to the second differential voltage adjustment circuit. The second differential voltage adjustment circuit is used to adjust the differential calibration voltage output to the gates of the third and fourth switches. The second auxiliary differential pair is of the same type as the second input differential pair, and the switching transistor size of the second auxiliary differential pair is K2 times the switching transistor size of the second input differential pair, where K2 is greater than 0 and less than 1.

[0012] In one embodiment, the second differential input circuit further includes a fifth current bias circuit, the second input differential pair is connected to the fifth current bias circuit, and the output current of the fourth current bias circuit is K2 times the output current of the fifth current bias circuit.

[0013] This application also provides an operational amplifier chip, including the above-described operational amplifier circuit.

[0014] This application also provides an electronic device including the above-described operational amplifier chip.

[0015] In the aforementioned operational amplifier circuit, operational amplifier chip, and electronic device, the operational amplifier circuit has a first auxiliary differential pair of the same type and proportionally reduced in size connected in parallel at the first input differential pair of the first differential input circuit. The gates of the first auxiliary differential pair are connected to a first differential voltage adjustment circuit, which is configured to adjust the magnitude of the output differential calibration voltage. This scheme allows for the adjustment of the differential calibration voltage between the gates of the first auxiliary differential pair when voltage offset occurs in the operational amplifier circuit, creating a gate-source voltage difference and causing current imbalance between the first auxiliary differential pairs. This imbalance current introduces an equivalent input offset compensation voltage at the input stage. This input offset compensation voltage has the opposite polarity and direction to the offset voltage, thus canceling out the offset voltage and achieving offset calibration.

[0016] The above scheme connects an additional adjustable differential circuit in parallel at the first differential input circuit for offset calibration, eliminating the need for an additional clock. The first auxiliary differential pair is of the same type as the first input differential pair, giving them a common physical temperature coefficient and fundamentally eliminating systematic temperature drift caused by different carrier types. By proportionally reducing the size of the switching transistors in the first auxiliary differential pair, it naturally operates at a smaller bias current, reducing power consumption and allowing the transconductance of the first auxiliary differential pair to enter a less sensitive operating region to temperature and process variations. This results in extremely high temperature stability, achieving high operational amplifier offset voltage calibration accuracy while maintaining hardware cost-effectiveness. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the operational amplifier circuit structure in one embodiment of this application;

[0019] Figure 2 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0024] Figure 7 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the operational amplifier circuit structure in another embodiment of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] 10-First differential input circuit, 20-Gain output circuit, 30-First adjustable differential circuit, 11-First input differential pair transistors, 12-Third current bias circuit, 31-First differential voltage adjustment circuit, 32-First auxiliary differential pair transistors, 33-First current bias circuit, M1-First switching transistor, M2-Second switching transistor; 21-Adjustable resistor circuit, 22-Second current bias circuit; 221-First current source, 222-Second current source, 211 - First resistor circuit, 212 - Second resistor circuit, Z1 - First adjustable resistor, R1 - First resistor, Z2 - Second adjustable resistor, R2 - Second resistor; 50 - Second differential input circuit, 60 - Second adjustable differential circuit, 51 - Second input differential pair transistors, 52 - Fifth current bias circuit, 61 - Second differential voltage adjustment circuit, 62 - Second auxiliary differential pair transistors, 63 - Fourth current bias circuit, M3 - Third switching transistor, M4 - Fourth switching transistor. Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0031] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0032] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0034] Please see Figure 1 This application provides an operational amplifier circuit, including a first differential input circuit 10, a gain output circuit 20, and a first adjustable differential circuit 30. The first differential input circuit 10 includes a first input differential pair transistor 11; the first output terminal and the second output terminal of the first input differential pair transistor 11 are respectively connected to the gain output circuit 20. The first adjustable differential circuit 30 includes a first differential voltage adjustment circuit 31, a first auxiliary differential pair transistor 32, and a first current bias circuit 33. The first auxiliary differential pair transistor 32 includes a first switching transistor M1 and a second switching transistor M2. The first terminal of the first switching transistor M1 and the first terminal of the second switching transistor M2 are respectively connected to the first current bias circuit 33. The second terminal of the switching transistor M1 is connected to the first output terminal of the first input differential pair transistor 11, and the second terminal of the second switching transistor M2 is connected to the second output terminal of the first input differential pair transistor 11. The gates of the first switching transistor M1 and the second switching transistor M2 are respectively connected to the first differential voltage adjustment circuit 31. The first differential voltage adjustment circuit 31 is used to adjust the differential calibration voltage output to the gates of the first switching transistor M1 and the second switching transistor M2. The first auxiliary differential pair transistor 32 is of the same type as the first input differential pair transistor 11, and the switching transistor size of the first auxiliary differential pair transistor 32 is K1 times the switching transistor size of the first input differential pair transistor 11, where K1 is greater than 0 and less than 1.

[0035] An operational amplifier circuit refers to a high-precision analog integrated circuit that includes a differential input stage, a gain stage, and an output stage, used to amplify voltage signals. In this embodiment, the operational amplifier circuit adds offset voltage calibration-related circuitry to the original signal amplification. The first differential input circuit 10 refers to the circuit module in the operational amplifier circuit responsible for receiving differential input signals (i.e., VINP and VINN in the figure) and performing preliminary conversion. It typically includes a pair of differential transistors, namely the first input differential pair 11. The first input differential pair 11 refers to the two transistors that constitute the core of the first differential input circuit 10, with their gates receiving non-inverting and inverting input signals, respectively. The gain output circuit 20 refers to the circuit connected after the input stage, which converts the differential current signal output from the input stage into a high-gain voltage signal. It typically includes an intermediate gain stage (such as a cascode amplifier) ​​and an output stage, and is the main part of the operational amplifier that realizes voltage amplification. The specific structure is not limited and can be selected according to actual needs.

[0036] The first adjustable differential circuit 30 is an additional circuit used to compensate and adjust the offset voltage generated by the first differential input circuit 10. This circuit converts the gate voltage difference into a high-precision input stage compensation signal by introducing a first auxiliary differential pair matched with the first input differential pair transistor 11. The first differential voltage adjustment circuit 31 refers to a circuit used to generate and adjust a differential calibration voltage. Its structure is not unique, as long as it can generate a differential calibration voltage (hereinafter referred to as calibration voltage) between the gates of the first auxiliary differential pair transistor 32. The first auxiliary differential pair transistor 32 refers to two transistors in the first adjustable differential circuit 30 that are of the same type as the first input differential pair transistor 11 but proportional in size (K1 times). These transistors convert the differential calibration voltage into a compensation current, and because they are of the same type and process as the input transistors, they ensure the temperature stability of the transconductance ratio.

[0037] The first switch M1 and the second switch M2 are two transistors in the first auxiliary differential pair 32. Their types are not unique. In the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) scenario, both the first switch M1 and the second switch M2 refer to MOSFET transistors. Their first terminal, second terminal, and gate correspond to the source (S), drain (D), and gate (G) of the MOSFET, respectively. That is, both the first switch M1 and the second switch M2 are PMOS transistors. In this embodiment, the source of the switch is connected to the first current bias circuit 33 (for input current), the drain is connected to the output node of the input stage (i.e., the first differential input circuit 10), and the gate receives the calibration voltage.

[0038] The first current bias circuit 33 refers to the circuit that provides static operating current to the first auxiliary differential pair transistors 32. Its type is not unique and is not limited here. For example, in one embodiment, it can be implemented using a current mirror.

[0039] The differential calibration voltage refers to the differential voltage generated by the first adjustable differential circuit 30, used to control the calibration amount. The first auxiliary differential pair 32 and the first input differential pair 11 are of the same type, meaning that the two switching transistors in the first auxiliary differential pair 32 (both of the same type) are of the same type as the two switching transistors in the first input differential pair 11, that is, they belong to the same conductivity type (such as PMOS) and the same manufacturing process level. The switching transistor size refers to the width-to-length ratio (W / L) of the switching transistor. K1 times indicates that the size of the auxiliary transistor (i.e., the width-to-length ratio, usually referring to the width) is K1 times that of the input transistor. Setting K1 to less than 1 reduces the operating current of the auxiliary transistor proportionally, allowing it to enter a more stable operating region with transconductance temperature characteristics.

[0040] Through the regulation of the first differential voltage regulation circuit 31, under the action of the current output by the first current bias circuit 33, the first differential voltage regulation circuit 31 can generate a differential calibration voltage Vos_trim_R, which is applied between the gates of the auxiliary floating MOS pair (i.e., the first auxiliary differential pair transistor 32), forming a gate-source voltage difference. The first auxiliary differential pair transistor 32 operates in the saturation region, and its drain current change is proportional to the gate-source voltage difference. Correspondingly, at this time, ΔI_trim = gm_aux × Vos_trim_R, where ΔI_trim represents the drain current change, gm_aux represents the transconductance of the first auxiliary differential pair transistor 32 (the first switching transistor M1 is the same as the first switching transistor M1), and Vos_trim_R represents the (differential) calibration voltage. The change in drain current of the first auxiliary differential pair transistor 32 is injected into the bias node or load node of the first input differential pair transistor 11 through a current mirror or direct coupling, thereby introducing an equivalent input offset compensation voltage Vos_trim_new in the input stage. The calibration operation is achieved by canceling the offset voltage with the input offset compensation voltage.

[0041] It is understandable that offset calibration of operational amplifier circuits can be performed at the factory or during operation, depending on actual needs, and no limitation is made here.

[0042] In the aforementioned operational amplifier circuit, a first auxiliary differential pair 32 of the same type but with a proportionally reduced switching transistor size is connected in parallel at the first input differential pair 11 of the first differential input circuit 10. The gate of the first auxiliary differential pair 32 is connected to a first differential voltage adjustment circuit 31, which is configured to adjust the output voltage. This scheme allows for the adjustment of the differential calibration voltage between the output and the gate of the first auxiliary differential pair 32 when voltage offset occurs in the operational amplifier circuit, creating a gate-source voltage difference and causing current imbalance between the first auxiliary differential pair 32. This imbalance current introduces an equivalent input offset compensation voltage at the input stage. This input offset compensation voltage has the opposite polarity and direction to the offset voltage, thus canceling out the offset voltage and achieving offset calibration.

[0043] The above scheme connects an additional adjustable differential circuit 30 in parallel at the first differential input circuit 10 for offset calibration, eliminating the need for an additional clock. The first auxiliary differential pair 32 is of the same type as the first input differential pair 11, giving them a common physical temperature coefficient and fundamentally eliminating systematic temperature drift caused by different carrier types. By proportionally reducing the size of the switching transistor in the first auxiliary differential pair 32, it naturally operates at a smaller bias current, reducing power consumption and allowing the transconductance of the first auxiliary differential pair 32 to enter a less sensitive operating region to temperature and process variations. This results in extremely high temperature stability, achieving high operational amplifier offset voltage calibration accuracy while maintaining hardware cost-effectiveness.

[0044] The structure of the first differential voltage regulation circuit 31 is not unique. In one embodiment, the first differential voltage regulation circuit 31 may include two voltage sources, wherein at least one voltage source is configured to be voltage adjustable, so that differential calibration voltages are applied to the gates of the first switch M1 and the second switch M2 respectively through the two voltage sources.

[0045] In another embodiment, the first differential voltage regulation circuit 31 may also be configured in other forms, for example, see [link to relevant documentation]. Figure 2 In one embodiment, the first differential voltage regulation circuit 31 includes a second current bias circuit 22 and an adjustable resistor circuit 21. The first output terminal of the second current bias circuit 22 is connected to the first terminal of the adjustable resistor circuit 21 and the gate of the first switching transistor M1, and the second output terminal of the second current bias circuit 22 is connected to the second terminal of the adjustable resistor circuit 21 and the gate of the second switching transistor M2.

[0046] The second current bias circuit 22 refers to the circuit located in the first differential voltage regulation circuit 31 that provides operating current to the adjustable resistor circuit 21. In some embodiments, it generates two matched currents, each flowing through the adjustable resistor circuit 21 to generate a calibration voltage. It is understood that the second current bias circuit 22 can be two independent matched current sources, or a mirror image of a single current source; this is not limited thereto. The adjustable resistor circuit 21 refers to a resistor network whose resistance value can be adjusted by an external signal to generate a programmable differential voltage.

[0047] The above scheme, through the combination of a current bias circuit and an adjustable resistor, can generate a stable and controllable calibration voltage. The current bias circuit provides a stable bias, so that the value of the calibration voltage depends mainly on the resistance difference of the adjustable resistors. The calibration value can be precisely and linearly programmed digitally or analogly, simplifying the calibration process and improving repeatability.

[0048] It is understandable that the structure of the adjustable resistor circuit 21 is not unique. Any circuit that can change the calibration voltage applied between the gates of the first switch M1 and the second switch M2 by adjusting the resistance value is acceptable, and there is no specific limitation.

[0049] For example, please refer to Figure 3 , Figure 4 and Figure 5 In one embodiment, the adjustable resistor circuit 21 includes a first resistor circuit 211 and a second resistor circuit 212. The first end of the first resistor circuit 211 serves as the first end of the adjustable resistor circuit 21, and the second end of the first resistor circuit 211 is grounded. The first end of the second resistor circuit 212 serves as the second end of the adjustable resistor circuit 21, and the second end of the second resistor circuit 212 is grounded. At least one of the first resistor circuit 211 and the second resistor circuit 212 is configured to have an adjustable resistance value.

[0050] Figure 3 The embodiment shown has an adjustable resistance value for the first resistor circuit 211 (its output voltage is adjustable), while the resistance value for the second resistor circuit 212 is fixed (its output voltage is constant), thereby generating a differential voltage injected into the gate of the first auxiliary differential pair transistor 32.

[0051] Figure 4 In the embodiment shown, the resistance value of the first resistor circuit 211 is fixed (its output voltage is fixed), while the resistance value of the second resistor circuit 212 is adjustable (its output voltage is adjustable), thereby generating a differential voltage injected into the gate of the first auxiliary differential pair transistor 32.

[0052] Figure 5In the embodiment shown, the resistance values ​​of both the first resistor circuit 211 and the second resistor circuit 212 are adjustable, so that the output voltage of both can be adjusted, thereby generating a differential voltage injected into the gate of the first auxiliary differential pair transistor 32.

[0053] In this circuit, the first resistor circuit 211 and the second resistor circuit 212 refer to two independent branches that constitute the adjustable resistor circuit 21. The first resistor circuit 211 is used to convert the current output from the second current bias circuit 22 into a voltage and transmit it to the gate of the first switching transistor M1. The second resistor circuit 212 is used to convert the current output from the second current bias circuit 22 into a voltage and transmit it to the gate of the second switching transistor M2. Therefore, to change the calibration voltage between the gates, it is only necessary to change the relative value of the two voltages output to the gates. Thus, this can be achieved by changing the resistance value of at least one of the circuits in the first resistor circuit 211 and the second resistor circuit 212.

[0054] In some embodiments, the voltage (bias voltage) output by the first resistor circuit 211 to the gate of the first switching transistor M1 is in the range of 0 to VDD-VTH, where VDD is the positive power supply voltage, referring to the voltage of the positive power supply that provides operating energy to the operational amplifier circuit. VTH represents the threshold voltage of the field-effect transistor, referring to the absolute value of the minimum gate-source voltage required to cause the transistor channel to begin strong inversion and form a conductive channel.

[0055] Similarly, the voltage (bias voltage) output from the second resistor circuit 212 to the gate of the second switching transistor M2 is in the range of 0 to VDD-VTH. In this way, the first adjustable differential circuit 30 does not affect the normal operating range of the operational amplifier circuit and does not consume the operating voltage margin.

[0056] The above scheme grounds one end of each of the two resistor circuits, forming a simple common-mode level reference and simplifying the bias design. By designing at least one resistor circuit with an adjustable resistance value, a differential adjustment mode can be achieved. This not only allows for flexible generation of positive and negative bidirectional calibration voltages but also facilitates better symmetry in layout design, suppresses common-mode interference, and improves calibration accuracy.

[0057] Taking the example where both the first resistor circuit 211 and the second resistor circuit 212 are configured with adjustable resistance values, please continue reading. Figure 5 In one embodiment, the first resistor circuit 211 includes a first adjustable resistor Z1, and the second resistor circuit 212 includes a second adjustable resistor Z2. This allows a resistor circuit to be constructed using only a single adjustable resistor, resulting in a simple circuit structure and reduced hardware costs.

[0058] Please see Figure 6In one embodiment, the first resistor circuit 211 includes a first adjustable resistor Z1 and a first resistor R1 connected in series, with one end of the series connection serving as the first end of the first resistor circuit 211 and the other end of the series connection serving as the second end of the first resistor circuit 211; the second resistor circuit 212 includes a second adjustable resistor Z2 and a second resistor R2 connected in series, with one end of the series connection serving as the first end of the second resistor circuit 212 and the other end of the series connection serving as the second end of the second resistor circuit 212.

[0059] It is understood that in other embodiments, the resistors may also be adjustable resistors connected in parallel with fixed resistors to form the first resistor circuit 211 and the second resistor circuit 212, and no specific limitation is made.

[0060] The above scheme uses a series combination of a fixed resistor and an adjustable resistor to form a resistive circuit. This allows the adjustable resistor to be varied within a small range to achieve fine adjustment of the calibration voltage, effectively reducing the requirements for the accuracy and adjustment resolution of the adjustable resistor itself.

[0061] Please see Figures 3-6 In one embodiment, the second current bias circuit 22 includes a first current source 221 and a second current source 222. The first current source 221 and the second current source 222 are respectively connected to a power supply (positive current source VDD). The first current source 221 is connected to the first terminal of the adjustable resistor circuit 21 and the gate of the first switching transistor M1. The second current source 222 is connected to the second terminal of the adjustable resistor circuit 21 and the gate of the second switching transistor M2.

[0062] This embodiment uses two independent current sources connected to a power source to form a second current bias circuit 22 for explanation. It can be understood that the power sources connected to the first current source 221 and the second current source 222 can be the same or different; there is no specific limitation.

[0063] In another embodiment, the output currents of the first current source 221 and the second current source 222 may also be set differently, without being limited to any specific configuration.

[0064] The above scheme, by employing two matched independent current sources to drive the two resistor branches respectively, ensures a high degree of consistency in the current flowing through the first resistor circuit 211 and the second resistor circuit 212. This fundamentally eliminates the additional errors introduced by bias current mismatch, making the final calibration voltage strictly and uniquely determined by the resistance difference between the two resistor circuits, greatly improving the accuracy and predictability of the calibration voltage.

[0065] Please see Figure 1 or Figure 2In one embodiment, the first differential input circuit 10 further includes a third current bias circuit 12, and the first input differential pair transistor 11 is connected to the third current bias circuit 12; wherein, the output current of the first current bias circuit 33 is K1 times the output current of the third current bias circuit 12.

[0066] The third current bias circuit 12 refers to the circuit module that provides tail current or operating point bias current to the first input differential pair transistor 11. The common source or common source node of the first input differential pair transistor 11 is connected to the output terminal of the third current bias circuit 12 to receive the bias current provided by it.

[0067] The above solution, by precisely setting the bias current of the auxiliary differential pair to K1 times the bias current of the input pair transistors (the same as the size reduction ratio), ensures that the first input differential pair transistor 11 and the first auxiliary differential pair transistor 32 operate at a completely proportional current density, thereby maximizing the advantages of temperature stability and reducing the impact of temperature drift.

[0068] The above-described embodiments are applicable to linear calibration scenarios for operational amplifiers with various current levels. The value of K1 can be adjusted according to requirements, which can reduce the sensitivity to the current level and has high applicability.

[0069] Please see Figure 7 In one embodiment, the operational amplifier circuit further includes a second differential input circuit 50 and a second adjustable differential circuit 60; the second differential input circuit 50 includes a second input differential pair 51 of a different type from the first input differential pair 11, and the first and second output terminals of the second input differential pair 51 are respectively connected to the gain output circuit 20; the second adjustable differential circuit 60 includes a second differential voltage adjustment circuit 61, a second auxiliary differential pair 62, and a fourth current bias circuit 63, the second auxiliary differential pair 62 includes a third switch M3 and a fourth switch M4, and the first terminals of the third switch M3 and the fourth switch M4 are respectively connected to the fourth current bias circuit. 63. The second terminal of the third switch M3 is connected to the first output terminal of the second input differential pair 51, and the second terminal of the fourth switch M4 is connected to the second output terminal of the second input differential pair 51. The gates of the third switch M3 and the fourth switch M4 are respectively connected to the second differential voltage adjustment circuit 61. The second differential voltage adjustment circuit 61 is used to adjust the differential calibration voltage output to the gates of the third switch M3 and the fourth switch. The second auxiliary differential pair 62 is of the same type as the second input differential pair 51, and the switching transistor size of the second auxiliary differential pair 62 is K2 times the switching transistor size of the second input differential pair 51, where K2 is greater than 0 and less than 1.

[0070] The second differential input circuit 50 refers to another set of differential input circuits that are complementary to the type of the first differential input circuit 10. Taking the first differential input circuit 10 as a PMOS type as an example, the corresponding second differential input circuit 50 should be an NMOS type circuit, that is, its second input differential pair transistor 51 uses NMOS transistors. Correspondingly, in actual scenarios, in on-rail input op-amps, when the input common-mode voltage is close to VSS (such as VSS to VDD-VTH), the second differential input circuit 50 operates; while when the input common-mode voltage is close to VDD (such as VDD to VDD-VTH), the first differential input circuit 10 operates. VSS is the negative power supply voltage or ground, referring to the negative power supply or reference ground voltage that provides operating energy to the operational amplifier circuit. When the first differential input circuit 10 is operating, offset calibration can be performed based on the first adjustable differential circuit 30; when the second differential input circuit 50 is operating, offset calibration is performed based on the second adjustable differential circuit 60.

[0071] The third switch M3 and the fourth switch M4 refer to the two NMOS transistors in the second auxiliary differential pair 62. Their connection relationship and function are completely symmetrical with those of the switches in the first auxiliary differential pair 32, but their polarities are opposite. The fourth current bias circuit 63 refers to the circuit that provides the static operating current for the second auxiliary differential pair 62. It can also include two current sources, connected in a similar manner to the first current source 221 and the second current source 222, except that these two current sources are connected to VSS.

[0072] It is understood that the structure of the second adjustable differential circuit 60 can be configured to be the same as that of the first adjustable differential circuit 30. The difference lies in the type of the second auxiliary differential pair transistor 62 and the power supply connected to it. The second adjustable differential circuit 60 is connected to VSS, while the first adjustable differential circuit 30 is connected to VDD.

[0073] The above scheme adds a second differential input circuit 50 and a second adjustable differential circuit 60 to the operational amplifier circuit, forming a full-range calibration of rail-to-rail input, so that no matter which end of the power rail (VDD or VSS) the input voltage signal is close to, the corresponding calibration path can be activated and work in its optimal state.

[0074] Please see Figure 7 In one embodiment, the second differential input circuit 50 further includes a fifth current bias circuit 52, the second input differential pair transistor 51 is connected to the fifth current bias circuit 52, and the output current of the fourth current bias circuit 63 is K2 times the output current of the fifth current bias circuit 52.

[0075] The fifth current bias circuit 52 refers to the circuit that provides the quiescent operating current to the second input differential pair transistor 51. In this embodiment, the fifth current bias circuit 52 is also connected to VSS, and it follows a K2 ratio with the fourth current bias circuit 63 to ensure the temperature stability of the NMOS side calibration path.

[0076] The above scheme, by limiting the ratio of the input bias current between the second differential input circuit 50 and the second input differential pair transistor 51, enables the rail-to-rail calibration scheme to achieve the same excellent low temperature drift and high precision calibration effect in the entire region, thus realizing true full-range performance optimization.

[0077] Furthermore, you can refer to the following: Figure 8 For rail-to-rail structures, the PMOS side (first differential input circuit 10) and the NMOS side (second differential input circuit 50) are calibrated separately, which can achieve calibration matching for the entire rail-to-rail input design. The calibration accuracy can be made to be as close as possible to the resistor accuracy (the resistance value of the adjustable resistor circuit 21), effectively aligning the calibration results.

[0078] In a more detailed embodiment, the above calibration scheme can be expressed as follows: when the input common-mode voltage is VDD to VDD-VTH, offset calibration is performed using the first adjustable differential circuit 30, specifically expressed as: Vos_trim_new=(K1×gmp1)×Vos_trim_R / gmp1, which simplifies to: Vos_trim_new=K1×Vos_trim_R, where Vos_trim_new represents the input offset compensation voltage, Vos_trim_R represents the differential calibration voltage, K1 is the ratio of the above-mentioned switch transistor dimensions, and gmp1 is the transconductance of the PMOS switch transistor. In some embodiments, Vos_trim_R can be expressed as the product of the resistance difference (resistance difference) between the first resistor circuit 211 and the second resistor circuit 212 and the output current of the second current bias circuit 22.

[0079] When the input common-mode voltage is VSS to VDD-VTH, the second adjustable differential circuit 60 is used for offset calibration, which can be expressed as: Vos_trim_new=(K2×gmn1)×Vos_trim_R / gmn1, which simplifies to: Vos_trim_new=K2×Vos_trim_R. Similarly, Vos_trim_new represents the input offset compensation voltage, and Vos_trim_R represents the differential calibration voltage (K2 is the ratio of the above switch dimensions, and gmn1 is the transconductance of the NMOS switch).

[0080] This application also provides an operational amplifier chip, including the above-described operational amplifier circuit.

[0081] Specifically, the structure and implementation of the operational amplifier circuit are as shown in the above embodiments and accompanying drawings, and will not be repeated here.

[0082] This application also provides an electronic device including the above-described operational amplifier chip.

[0083] Similarly, the structure and implementation of the operational amplifier circuit in the operational amplifier chip are as shown in the above embodiments and accompanying drawings, and will not be repeated here. It is understood that the type of electronic device is not unique; it can be a mobile phone, tablet, smartwatch, etc., and is not specifically limited.

[0084] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An operational amplifier circuit, characterized in that, include: The first differential input circuit includes a first input differential pair transistor; A gain output circuit, wherein the first and second output terminals of the first input differential pair transistors are respectively connected to the gain output circuit; The first adjustable differential calibration circuit includes a first differential voltage adjustment circuit, a first auxiliary differential pair transistor, and a first current bias circuit. The first auxiliary differential pair transistor includes a first switch transistor and a second switch transistor. The first terminals of the first switch transistor and the second switch transistor are respectively connected to the first current bias circuit. The second terminal of the first switch transistor is connected to the first output terminal of the first input differential pair transistor. The second terminal of the second switch transistor is connected to the second output terminal of the first input differential pair transistor. The gates of the first switch transistor and the second switch transistor are respectively connected to the first differential voltage adjustment circuit. The first differential voltage adjustment circuit is used to adjust the differential calibration voltage output to the gate of the first switch and the gate of the second switch. The first auxiliary differential pair transistor and the first input differential pair transistor are of the same type, and the switching transistor size of the first auxiliary differential pair transistor is K1 times the switching transistor size of the first input differential pair transistor, where K1 is greater than 0 and less than 1.

2. The operational amplifier circuit according to claim 1, characterized in that, The first differential voltage regulation circuit includes a second current bias circuit and an adjustable resistor circuit. The first output terminal of the second current bias circuit is connected to the first terminal of the adjustable resistor circuit and the gate of the first switching transistor. The second output terminal of the second current bias circuit is connected to the second terminal of the adjustable resistor circuit and the gate of the second switching transistor.

3. The operational amplifier circuit according to claim 2, characterized in that, The adjustable resistor circuit includes a first resistor circuit and a second resistor circuit. The first end of the first resistor circuit serves as the first end of the adjustable resistor circuit, and the second end of the first resistor circuit is grounded. The first end of the second resistor circuit serves as the second end of the adjustable resistor circuit, and the second end of the second resistor circuit is grounded. At least one of the first resistor circuit and the second resistor circuit is configured to have an adjustable resistance value.

4. The operational amplifier circuit according to claim 3, characterized in that, The first resistor circuit includes a first adjustable resistor, and the second resistor circuit includes a second adjustable resistor.

5. The operational amplifier circuit according to claim 2, characterized in that, The second current bias circuit includes a first current source and a second current source. The first current source and the second current source are respectively connected to a power supply. The first current source is connected to the first terminal of the adjustable resistor circuit and the gate of the first switching transistor. The second current source is connected to the second terminal of the adjustable resistor circuit and the gate of the second switching transistor.

6. The operational amplifier circuit according to claim 1, characterized in that, The first differential input circuit further includes a third current bias circuit, and the first input differential pair is connected to the third current bias circuit; wherein the output current of the first current bias circuit is K1 times the output current of the third current bias circuit.

7. The operational amplifier circuit according to any one of claims 1-6, characterized in that, The operational amplifier circuit also includes a second differential input circuit and a second adjustable differential circuit; The second differential input circuit includes a second input differential pair of transistors of a different type than the first input differential pair. The first and second output terminals of the second input differential pair are respectively connected to the gain output circuit. The second adjustable differential circuit includes a second differential voltage adjustment circuit, a second auxiliary differential pair of transistors, and a fourth current bias circuit. The second auxiliary differential pair of transistors includes a third switch and a fourth switch. The first terminals of the third and fourth switches are respectively connected to the fourth current bias circuit. The second terminal of the third switch is connected to the first output terminal of the second input differential pair of transistors. The second terminal of the fourth switch is connected to the second output terminal of the second input differential pair of transistors. The gates of the third and fourth switches are respectively connected to the second differential voltage adjustment circuit. The second differential voltage adjustment circuit is used to adjust the differential calibration voltage output to the gates of the third and fourth switches. The second auxiliary differential pair of transistors is of the same type as the second input differential pair of transistors, and the switching transistor size of the second auxiliary differential pair of transistors is K2 times the switching transistor size of the second input differential pair of transistors, where K2 is greater than 0 and less than 1.

8. The operational amplifier circuit according to claim 7, characterized in that, The second differential input circuit further includes a fifth current bias circuit, the second input differential pair is connected to the fifth current bias circuit, and the output current of the fourth current bias circuit is K2 times the output current of the fifth current bias circuit.

9. An operational amplifier chip, characterized in that, Includes the operational amplifier circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the operational amplifier chip as described in claim 9.

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