Non-volatile memory and its automatic repair method
By introducing a test array and a self-healing mechanism into the MRAM memory, the bit flipping problem caused by read interference rate is solved, achieving self-healing and improved reliability, and is suitable for MRAM memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-30
AI Technical Summary
During the reading process, the stability factor Δ of MRAM memory temporarily decreases due to read interference rate (RDR), causing bit flips. The cumulative number of flips exceeds the error correction code's capability, affecting product reliability, especially in high-temperature and frequent read scenarios.
Design a non-volatile memory comprising a main array and a test array. The test array is read synchronously during each read operation of the main array via a read circuit. The number of flipped bits is counted, and if a threshold is exceeded, a refresh operation is initiated to automatically repair the flipped bits.
It enables timely repair of flipped bits without external interference, reduces the impact of read interference rate, improves product reliability, reduces the occupation of ECC error correction capability, and provides greater flexibility and reliability.
Smart Images
Figure CN122314062A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory design technology, and in particular to a non-volatile memory and its automatic repair method. Background Technology
[0002] For MRAM (Magnetic Random Access Memory), the Read Disturbance Rate (RDR) problem essentially stems from the fact that during MRAM reads, the current flowing through the read junction (MTJ) causes a temporary decrease in the stability factor Δ, thus accelerating MTJ flipping. When continuously reading the array (read-only), some bits will flip due to RDR, and this number accumulates. When the accumulated number exceeds the error correction capability of the ECC (Error Correction Code), a read error occurs, affecting product reliability. Furthermore, the Δ value is lower at high temperatures, making the RDR problem more severe and significantly limiting the reliability of high-reliability applications under high-temperature conditions. Therefore, for applications with significant RDR effects, such as high-temperature and frequent read scenarios, ensuring data read reliability is a crucial technical issue that must be considered. Summary of the Invention
[0003] In view of this, the present invention provides a non-volatile memory and an automatic repair method thereof, which can mitigate the impact of read interference rate.
[0004] In a first aspect, the present invention provides a non-volatile memory, comprising: The main array is used to store data and ECC verification data; Test array; The read circuit is used to perform a read operation on the test array for each read operation performed on the main array; A refresh start circuit is used to count the number of flipped bits in the test array based on the data read out each time, determine whether the number of flipped bits is greater than or equal to a preset threshold, and if so, start the refresh operation of the test array and the main array. A write circuit is used to perform refresh operations on the test array and the main array.
[0005] Optionally, the write circuit is used to write back the test array to its initial state to refresh the test array, and is also used in conjunction with the read circuit to perform a read-then-write operation on the main array to refresh the main array.
[0006] Optionally, the non-volatile memory further includes: A read / write control circuit is used to control the operation of the read circuit and the write circuit; The command module is used to send read commands or write commands to the read / write control circuit; The command detection module is used to detect the commands given to the read / write control circuit by the command module. When the command is detected to be a read command for the main array, the read command for the test array is also given to the read / write control circuit so that the test array performs a read operation every time the main array performs a read operation.
[0007] Optionally, the main array and the test array share the write circuit, or the write circuit includes: The first sub-write circuit is used for writing operations to the main array; The second sub-write circuit is used to write to the test array.
[0008] Optionally, the main array and the test array share the read circuit, or the read circuit includes: The first sub-read circuit is used for reading operations on the main array; The second sub-read circuit is used to perform read operations on the test array.
[0009] Optionally, the non-volatile memory further includes: The ECC error correction code circuit is used to correct errors in the data read from the main array by the read circuit.
[0010] Optionally, if all bits of the test array are initially in the AP state, then the refresh start circuit counts the number of bits in the P state. The initial state of all bits in the test array is P state, and the refresh start circuit counts the number of bits in AP state.
[0011] Optionally, the non-volatile memory is an MRAM memory.
[0012] Optionally, the MTJs of the test array and the main array may have the same critical size, or the critical size of the test array MTJ may be smaller than the critical size of the main array MTJ.
[0013] Secondly, the present invention provides an automatic repair method for non-volatile memory, the method comprising: The test array is initialized so that all bits of the test array are in the initial state; For each read operation performed on the main array, a read operation is also performed on the test array; Based on the data read from the test array each time, count the number of flipped bits in the test array; Determine whether the number of flipped bits is greater than or equal to a preset threshold. If so, initiate the refresh operation of the test array and the main array. Perform refresh operations on the test array and the main array.
[0014] The non-volatile memory and its automatic repair method provided by this invention involve reading the test array after each read from the main array. After each read of the test array, the number of flipped bits in the test array is counted. When the number of flipped bits in the test array is greater than or equal to a preset threshold, a refresh operation is initiated for both the main array and the test array. This brings the following benefits: the repair process requires no external intervention, promptly writing back the flipped bits affected by RDR interference to their initial state, achieving self-repair. It can restore bits with temporarily reduced stability factor Δ, reducing the burden on ECC error correction capabilities, improving product reliability, and significantly mitigating the impact of read interference rate, providing greater flexibility in device and design selection. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the structure of a non-volatile memory in one embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a non-volatile memory in another embodiment of the present invention; Figure 3 This is a flowchart illustrating an automatic repair method for non-volatile memory according to an embodiment of the present invention. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0018] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0019] This invention proposes a non-volatile memory, such as... Figure 1 As shown, the memory includes: Main array 110 is used to store data and ECC check data; Test array 111; The read circuit 112 is used to perform a read operation on the test array 111 for each read operation performed on the main array 110; The refresh start circuit 113 is used to count the number of flipped bits in the test array 111 based on the data read out each time, and determine whether the number of flipped bits is greater than or equal to a preset threshold. If so, the refresh operation of the test array 111 and the main array 110 is started. The write circuit 114 is used to perform refresh operations on the test array 111 and the main array 110.
[0020] In this embodiment, the main array 110 is divided into a data subarray 1101 and an ECC subarray 1102, and the bit structure of the data subarray 1101 and the ECC subarray 1102 is the same. The data subarray 1101 is used to store data, and the ECC subarray 1102 is used to store ECC check data. The ECC check data is obtained by ECC encoding of the data stored in the data subarray.
[0021] Test array 111 is initialized so that all bits are in the initial state, which can be the AP state.
[0022] For each read operation performed by the main array 110, the test array 111 also performs one read operation, and the number of reads is the same for both. The read operation frequency is reflected by counting the number of toggled bits in the test array. By configuring the test array, the read operation frequency of the memory can be automatically detected, exhibiting adaptive behavior.
[0023] The non-volatile memory provided in this invention reads the test array after each read from the main array. After each read of the test array, the number of flipped bits in the test array is counted. When the number of flipped bits in the test array is greater than or equal to a preset threshold, a refresh operation is initiated for both the main array and the test array. This brings the following benefits: the repair process requires no external intervention, promptly writes the flipped bits affected by RDR interference back to their initial state, achieving self-repair. It can restore bits with temporarily reduced stability factor Δ, reducing the occupation of ECC error correction capability, improving product reliability, and significantly mitigating the impact of read interference rate, providing more flexibility in device and design selection.
[0024] In one implementation, the write circuit 114 is specifically used to: perform a write-back operation on the test array 111 to the initial state, and can perform multiple writes to ensure that all bits are written to the initial state in order to refresh the test array 111; it is also used in conjunction with the read circuit 112 to perform a read-then-write operation on the main array 110 in order to refresh the main array 110.
[0025] For test array 111, the initial state of all bits of test array 111 can be AP state (data is 1), then refresh start circuit 113 counts the number of bits in P state; during refresh operation, test array 111 is written back to AP state.
[0026] If all bits of the test array 111 are initially in the P state (data is 0), the refresh start circuit 113 counts the number of bits in the AP state. During the refresh operation, the test array 111 is written back to the P state.
[0027] refer to Figure 1 The memory also includes an ECC error correction circuit 118 and an I / O module 119, serving as the transmission channel after data is read from the main array 110. The ECC error correction circuit 118 is used to correct errors in the data read from the main array 110 by the read circuit 112. Combined with the correction by the ECC error correction circuit 118, correct data can be written into the main array 110. As one implementation method, refer to Figure 1 The memory also includes: The read / write control circuit 115 is used to control the operation of the read circuit 112 and the write circuit 114; Command module 116 is used to send read commands or write commands to read / write control circuit 115; The command detection module 117 is used to detect the commands given to the read / write control circuit 115 by the command module 116. When the command is detected to be a read command for the main array, the read command for the test array is also given to the read / write control circuit 115 so that the test array 111 performs a read operation every time the main array 110 performs a read operation.
[0028] The self-testing and automatic repair process of the non-volatile memory in this embodiment of the invention is as follows: First, the test array is initialized, assuming it is all written to AP state (data is 1). Subsequently, during the chip's operation, the command detection module 117 continuously detects the commands sent to the read / write control circuit 115. When the command is detected as a read command for the main array, the read command for the test array is also sent to the read / write control circuit 115. Then, for each read operation performed by the read circuit 112 on the main array, a read operation is also performed on the test array.
[0029] The refresh start circuit 113 first counts the number of bits whose state has flipped (data is 0), and compares the number of flipped bits with a preset threshold N. When the number of flipped bits is greater than or equal to the preset threshold N, the refresh operation of the test array and the main array will be started. For example, the refresh command can be given to the read / write control circuit 115, and then the read / write control circuit controls the write circuit 114 to perform the refresh operation.
[0030] The write circuit 114 performs a write-back operation to the test array 111 in the AP state. It can perform multiple writes to ensure that all bits are written to the AP state. It performs a read-then-write operation on the main array 110 and, combined with ECC correction, writes the correct data into the main array 110.
[0031] Furthermore, in one embodiment, such as Figure 1 As shown, the main array 110 and the test array 111 can share the read circuit 112 and the write circuit 114.
[0032] As another implementation method, such as Figure 2 As shown, the main array 110 and the test array 111 can also employ different read and write circuits. The read circuit 112 may include a first sub-read circuit 1121 and a second sub-read circuit 1122. The first sub-read circuit 1121 is used to perform read operations on the main array 110; the second sub-read circuit 1122 is used to perform read operations on the test array 111. The write circuit 114 may include a first sub-write circuit 1141 and a second sub-write circuit 1142. The first sub-write circuit 1141 is used to perform write operations on the main array 110; the second sub-write circuit 1142 is used to perform write operations on the test array 111.
[0033] Of course, only one of the write circuit and the read circuit can be used, depending on factors such as the ease of implementation and the area occupied. This application does not impose any special limitations.
[0034] As one implementation, the non-volatile memory provided in this embodiment of the invention can be an MRAM memory, but is not limited thereto; for example, it can also be a FeRAM.
[0035] Taking MRAM memory as an example, the bit core structure of both the test array and the main array is a magnetic tunnel junction (MTJ). The MTJs of the test array and the main array can have the same critical dimension (CD), or the MTJ of the test array can use a smaller CD, while the MTJ of the main array can use a larger CD. That is, the critical dimension of the MTJ in the test array is smaller than the critical dimension of the MTJ in the main array. This will be explained in detail below.
[0036] Scenario 1: The primary array and test array use the same MTJ size, and both arrays have the same stability factor Δ for their MTJs. Under the same number of reads, they have the same flip probability. However, in practice, each read from the primary array may not be to the same address, while the test array performs a read operation every time. Therefore, the flip probability of the test array is higher than that of the primary array. Although this is stricter, it ensures the effectiveness of the detection. The number of bits required for the test array can be calculated and determined based on the primary array capacity, bit error rate, confidence requirements, etc.
[0037] Scenario 2: The main array and test array use different MTJ sizes. The main array uses an MTJ with a larger CD (Distributed Error Rate), while the test array uses an MTJ with a smaller CD. Since a smaller CD results in a smaller stability factor Δ, it is more prone to flips. Thus, the test array has a smaller stability factor Δ, leading to a higher flip probability for the same number of reads. In practice, each read from the main array may not be the same address, while the test array performs a read operation every time. Therefore, the flip probability of the test array is even greater than that of the main array. Although this is stricter, it ensures the effectiveness of the detection. The number of bits required for the test array can be calculated and determined based on the main array capacity, bit error rate, confidence requirements, etc.
[0038] The preset threshold in this embodiment can be calculated and determined by combining the ratio of the test array to the main array, the size of their respective MTJs, and the requirements for bit error rate and confidence.
[0039] On the other hand, another embodiment of the present invention also provides an automatic repair method for non-volatile memory, such as... Figure 3 As shown, the method includes the following steps: S301, initialize the test array so that all bits of the test array are in the initial state; S302: For each read operation performed on the main array, a read operation is also performed on the test array. S303, based on the data read from the test array each time, count the number of flipped bits in the test array; S304, Determine whether the number of flipped bits is greater than or equal to a preset threshold. If so, proceed to step S305. S305, initiate refresh operations for the test array and the main array; S306 performs refresh operations on the test array and the main array.
[0040] As one implementation method, the command module can detect the commands sent to the read / write control circuit. When the command is detected as a read command for the main array, the read command for the test array is also sent to the read / write control circuit, so that the test array performs a read operation every time the main array performs a read operation.
[0041] The automatic repair method for non-volatile memory in this invention can be implemented based on the memory described in the foregoing embodiments, achieving the same technical effects: the repair process requires no external intervention, promptly writing back bits that have been flipped due to RDR interference to their initial state, thus realizing self-repair. It can restore bits whose stability factor Δ is temporarily reduced, reducing the load on ECC error correction capabilities, improving product reliability, and significantly mitigating the impact of read interference rate, providing greater flexibility in device and design selection.
[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A non-volatile memory, characterized in that, include: The main array is used to store data and ECC verification data; Test array; The read circuit is used to perform a read operation on the test array for each read operation performed on the main array; A refresh start circuit is used to count the number of flipped bits in the test array based on the data read out each time, determine whether the number of flipped bits is greater than or equal to a preset threshold, and if so, start the refresh operation of the test array and the main array. A write circuit is used to perform refresh operations on the test array and the main array.
2. The non-volatile memory according to claim 1, characterized in that, The write circuit is used to write back the test array to its initial state to refresh the test array. It is also used in conjunction with the read circuit to perform a read-then-write operation on the main array to refresh the main array.
3. The non-volatile memory according to claim 1, characterized in that, The non-volatile memory also includes: A read / write control circuit is used to control the operation of the read circuit and the write circuit; The command module is used to send read commands or write commands to the read / write control circuit; The command detection module is used to detect the commands given to the read / write control circuit by the command module. When the command is detected to be a read command for the main array, the read command for the test array is also given to the read / write control circuit so that the test array performs a read operation every time the main array performs a read operation.
4. The non-volatile memory according to claim 1, characterized in that, The main array and the test array share the write circuit, or the write circuit includes: The first sub-write circuit is used for writing operations to the main array; The second sub-write circuit is used to write to the test array.
5. The non-volatile memory according to claim 1, characterized in that, The main array and the test array share the read circuit, or the read circuit includes: The first sub-read circuit is used for reading operations on the main array; The second sub-read circuit is used to perform read operations on the test array.
6. The non-volatile memory according to claim 1, characterized in that, The non-volatile memory also includes: The ECC error correction code circuit is used to correct errors in the data read from the main array by the read circuit.
7. The non-volatile memory according to claim 1, characterized in that, If all bits of the test array are initially in the AP state, then the refresh start circuit counts the number of bits in the P state. The initial state of all bits in the test array is P state, and the refresh start circuit counts the number of bits in AP state.
8. The non-volatile memory according to claim 1, characterized in that, The non-volatile memory is an MRAM memory.
9. The non-volatile memory according to claim 8, characterized in that, The test array and the main array MTJ can have the same critical size, or the critical size of the test array MTJ can be smaller than the critical size of the main array MTJ.
10. An automatic repair method for non-volatile memory, characterized in that, The method includes: The test array is initialized so that all bits of the test array are in the initial state; For each read operation performed on the main array, a read operation is also performed on the test array; Based on the data read from the test array each time, count the number of flipped bits in the test array; Determine whether the number of flipped bits is greater than or equal to a preset threshold. If so, initiate the refresh operation of the test array and the main array. Perform refresh operations on the test array and the main array.