An ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays

Abstract

This application provides an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays, relating to the field of integrated circuit technology. An oscillator is connected to the pixel infrared detector, counter, and pulse generation unit respectively; the counter and pulse generation unit are both connected to a memory unit; the memory unit is connected to a bus; each pixel is connected to the column-level decoding unit of its column via the bus; the input of the column-level decoding unit is connected to the bus. This application, by employing a pixel structure where the oscillator is directly driven by photocurrent for integration, reduces circuit complexity and area overhead without significantly increasing additional power consumption, which is beneficial for realizing highly integrated small pixel arrays. It eliminates the need for a highly complex ADC structure or additional analog modules, achieving an optimized trade-off between power consumption, area, and accuracy. Reducing the number of buses and wiring resources, lowering bus parasitic capacitance and dynamic power consumption of the readout switches, helps to reduce the layout area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays. Background Technology

[0002] Infrared focal plane arrays are widely used in infrared imaging, target tracking, night vision surveillance, autonomous driving assistance, industrial inspection, and space remote sensing. With the increasing demands for resolution, sensitivity, and frame rate in infrared imaging systems, infrared focal plane arrays are evolving towards larger scales and higher pixel densities, significantly increasing the number of pixels integrated per unit area. As array sizes continue to expand, the power consumption and area of ​​individual pixel circuits directly impact the overall chip power consumption and layout size. Achieving low power consumption and high precision analog-to-digital conversion within a limited area has become a key technical challenge in the design of infrared focal plane readout circuits.

[0003] Existing infrared photocurrent readout structures typically employ analog units such as transimpedance amplifiers, integrating amplifiers, or comparators at the pixel level to achieve photocurrent integration and voltage conversion. These structures rely on high-power analog circuitry, resulting in large pixel areas and high power consumption, which is detrimental to achieving high-density small pixel arrays. Furthermore, in large-scale arrays, the number of column-level readout buses is large, consuming significant wiring resources, increasing bus parasitic capacitance and switching activity, limiting readout speed, and introducing additional power consumption. Summary of the Invention

[0004] In view of the above problems, this application proposes an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays to overcome the shortcomings of the prior art.

[0005] In a first aspect, embodiments of this application provide an ADC pixel and column-level coarse and fine quantization readout circuit applicable to infrared arrays, including: a pixel array and a column-level decoding unit; Each pixel in the pixel array includes an oscillator, which is connected to the pixel infrared detector, the counter, and the pulse generation unit respectively, and is used to integrate and oscillate the received photocurrent to output an oscillation signal. Both the counter and the pulse generation unit are connected to the storage unit. The counter is used to count the period of the received oscillation signal and generate a coarse quantization result; the pulse generation unit is used to receive and generate a sampling signal based on the oscillation signal and the enable signal. The storage unit is connected to the bus and is used to receive and synchronously latch the coarse quantization result and the system synchronization clock at the current moment based on the sampled signal and the oscillation signal. The system synchronization clock at the current moment is the fine quantization result. Each pixel is connected to the column-level decoding unit of its column via a bus. During the sampling phase, the bus transmits the system synchronization clock to each pixel, and during the readout phase, it transmits the coarse quantization result and fine quantization result latched in the corresponding storage unit of each pixel in a time-division manner. The input of the column-level decoding unit is connected to the bus and is used to decode and recover the coarse quantization result and the fine quantization result, and output quantized data.

[0006] Optionally, the input terminal of the oscillator is connected to the signal output terminal of the pixel infrared detector via a control switch transistor; The output terminal of the oscillator is connected to the input terminal of the counter and the input terminal of the pulse generation unit, respectively. The oscillator integrates an equivalent integral capacitor and a threshold switching structure. The photocurrent directly charges and discharges the equivalent integral capacitor. When the voltage across the equivalent integral capacitor reaches a preset upper or lower switching threshold, the threshold switching structure triggers a level switch to generate the oscillation signal.

[0007] Optionally, the ADC pixel and column-level coarse and fine quantization readout circuit further includes: a control unit; The control unit is connected to the bus, the pulse generation unit, and the storage unit, respectively. The control unit is used to send an enable signal to the pulse generation unit, which enables the pixel array to be in the sampling phase or the readout phase in each working cycle; The control unit is also configured to control the bus to transmit the system synchronization clock to each pixel during the sampling phase, and to send coarse and fine quantization row selection signals to the storage unit during the readout phase, and to control the bus to send the coarse quantization result and the fine quantization result to the column-level decoding unit.

[0008] Optionally, the input terminal of the pulse generation unit is connected to the output terminal of the oscillator and the output terminal of the control unit, respectively; The output terminal of the pulse generation unit is connected to the input terminal of the storage unit and the reset terminal of the counter, respectively. The pulse generation unit monitors the oscillation signal during the sampling phase, generates the sampling signal and the sampling signal is valid. When the oscillation signal has its first falling edge, the sampling signal changes from valid to invalid. After the sampling signal becomes invalid, a reset pulse is generated. The reset pulse is transmitted to the counter to reset the counter.

[0009] Optionally, the pulse generation unit includes: a trigger, a first inverter, a second inverter, a first AND gate, a second AND gate, a first delay unit, and a second delay unit; The input terminal of the trigger receives the oscillation signal and the enable signal, and the output terminal is connected to the input terminal of the first inverter; The output of the first inverter is connected to one input of the first AND gate, the other input of the first AND gate receives the enable signal, and the output of the first AND gate is connected to the input of the first delay unit and outputs the sampling signal. The output terminal of the first delay unit is connected to the input terminal of the second delay unit and the input terminal of the second inverter, respectively; The output of the second delay and the output of the second inverter are respectively connected to the two inputs of the second AND gate. The output of the second AND gate is connected to the counter and outputs the reset pulse.

[0010] Optionally, when the sampling signal changes from valid to invalid, the storage unit synchronously latches the coarse quantization result and the system synchronization clock at the current moment, where the system synchronization clock at the current moment is the fine quantization result.

[0011] Optionally, in each working cycle, the full cycle time of the system synchronization clock is equal to the effective time of the enable signal, and the pixel array is enabled to be in the sampling phase during the effective time of the enable signal.

[0012] Optionally, during the readout phase, for the pixel unit in the i-th row: When the coarse quantization row selection signal corresponding to the i-th row is valid, the coarse quantization results latched by all pixel units in the i-th row are output in parallel to the column-level decoding unit through the bus; When the fine quantization row selection signal corresponding to the i-th row is valid, the fine quantization results latched by all pixel units in the i-th row are output in parallel to the column-level decoding unit through the bus.

[0013] Optionally, the difference between the fine-grained results obtained from two samplings in two adjacent working cycles is: The time difference between the two falling edges is: , of which 2 N This represents the total number of states counted by the system's synchronization clock. The full cycle time of the system's synchronization clock; Based on the difference between the actual integration time and the working period T, this actual integration time is denoted as... Then coarse quantization count The actual integration time is:

[0014] When the oscillation integration time is the working period T, the number of oscillations of the counter is quantized as D[i], which includes an integer part and a fractional part. Then the corrected quantization result D c [i1] ​​is represented as:

[0015] In the above formula, D c [i] represents the coarse quantization result corresponding to the i-th pixel.

[0016] Optionally, the oscillator includes a ring oscillation structure or a current-controlled delay unit structure.

[0017] The ADC pixel and column-level coarse and fine quantization readout circuit applicable to infrared arrays proposed in this application includes: a pixel array and a column-level decoding unit; each pixel in the pixel array includes: an oscillator, which is connected to the pixel infrared detector, a counter and a pulse generation unit respectively, for integrating and oscillating the received photocurrent and outputting an oscillation signal.

[0018] The counter and pulse generation unit are both connected to the storage unit. The counter is used to count the period of the received oscillation signal and generate a coarse quantization result. The pulse generation unit is used to receive and generate a sampling signal based on the oscillation signal and the enable signal. The storage unit is connected to the bus and is used to receive and synchronously latch the coarse quantization result and the system synchronization clock at the current moment based on the sampling signal and the oscillation signal. The system synchronization clock at the current moment is the fine quantization result.

[0019] Each pixel is connected to the column-level decoding unit of its column via a bus. During the sampling phase, the bus transmits the system synchronization clock to each pixel. During the readout phase, it transmits the coarse quantization result and fine quantization result latched in the corresponding storage unit of each pixel in a time-division manner. The input of the column-level decoding unit is connected to the bus and is used to decode and recover the coarse quantization result and fine quantization result, and output quantized data.

[0020] This application employs a pixel structure that uses photocurrent to directly drive an oscillator for integration, removing traditional high-power analog units such as transimpedance amplifiers, integrators, or comparators from the pixel end. This reduces circuit complexity and area overhead without significantly increasing power consumption, facilitating the realization of highly integrated small pixel arrays. Simultaneously, this application improves effective quantization accuracy by introducing a phase fine quantization mechanism on top of count quantization through a coarse-fine joint quantization method, without adding a highly complex ADC structure or additional analog modules, achieving an optimized trade-off between power consumption, area, and accuracy.

[0021] The ADC pixel and column-level coarse and fine quantization readout circuit for infrared arrays proposed in this application can generate sampling and reset signals according to a predetermined timing even when the photocurrent is too small. This latches the system synchronization clock and coarse quantization results at the corresponding time and resets the counter after latching. This solves the problem caused by traditional structures when the photocurrent is too small. The intermediate node potential of the counter TSPC will not drift over time and enter a metastable state, avoiding significant charge leakage and additional static power consumption, which is extremely beneficial for power consumption control and improves readout accuracy. At the same time, the normal generation of the sampling signal will no longer cause potential drift in the sampling module or unit, improving the accuracy and stability of the sampling results.

[0022] The current-mode pipelined readout method using a column-level shared bus allows coarse and fine quantization results to be output using the same group of buses in a time-division manner at the column level. This reduces the number of buses and wiring resources, as well as bus parasitic capacitance and dynamic power consumption. It is suitable for large-scale infrared focal plane array readout circuits and has broad application prospects and high practicality. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a modular schematic diagram of an ADC pixel and column-level coarse and fine quantization readout circuit applicable to an infrared array according to an embodiment of this application; Figure 2 This is a timing diagram of the operation of the ADC pixel and column-level coarse and fine quantization readout circuit of the infrared array according to an embodiment of this application; Figure 3 This is a preferred bus multiplexing control timing diagram illustrated in the embodiments of this application; Figure 4 These are timing diagrams of a conventional pulse generation unit exemplified in the embodiments of this application under different photocurrent magnitudes; Figure 5 This is a circuit diagram illustrating a preferred pulse generation unit 40 in an embodiment of this application; Figure 6 This is the corresponding embodiment in this application. Figure 5 The timing diagram of the pulse generation unit 40 under different photocurrent magnitudes is shown. Detailed Implementation

[0024] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0025] This application provides an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays, referring to... Figure 1 The modular structure shown includes a pixel array and column-level decoding units. Figure 1 The example shows the pixel Pixel 1 in the first row of a column in a pixel array, ..., the pixel k in the nth row, and the column-level decoding unit corresponding to that column.

[0026] Each pixel in the pixel array includes an oscillator 20, which is connected to the pixel infrared detector 10, the counter 30, and the pulse generation unit 40, respectively. The oscillator 20 is used to measure the received photocurrent I. sig The oscillator performs integration and oscillation conversion, outputting an oscillation signal. Typically, the input of oscillator 20 needs to be connected to the signal output of pixel infrared detector 10 via a control switch TG; oscillator 20 directly outputs the photocurrent I... sig As a charge / discharge driving source, it completes the photocurrent I sig The integral and oscillation conversion produces an oscillating signal whose frequency is linearly positively correlated with the photocurrent amplitude.

[0027] Both counter 30 and pulse generation unit 40 are connected to storage unit 50. Counter 30 is used to count the period of the received oscillation signal to generate coarse quantization results; pulse generation unit 40 is used to receive and generate quantization results based on the oscillation signal and enable signal. A sampling signal SH is generated. Storage unit 50 is connected to bus 60. Storage unit 50 receives and synchronously latches the coarse quantization result D at the current moment based on the sampling signal SH and the oscillation signal. c ( Figure 1 In the example of D c <N:1> indicates) and the system synchronization clock SCK ( Figure 1 (Example: SCK<N:1>) The current system synchronization clock SCK is the fine-quantization result D. f ( Figure 1 In the example of D c <N:1> indicates).

[0028] Each pixel is connected to its column-level decoding unit 70 via bus 60. During the sampling phase, bus 60 transmits the system synchronization clock SCK to each pixel, and during the readout phase, it transmits the coarse quantization result D latched in the corresponding memory unit of each pixel in a time-division multiplexing manner. c And the refined quantification result D f Naturally, it is understandable that the input of the column-level decoding unit 70 is connected to the bus 60, and the column-level decoding unit 70 is used to process the coarse quantization result D. c And the refined quantification result D f Decode and recover the data, and output the quantized data, that is, output the quantized data corresponding to the pixel.

[0029] Depend on Figure 1 It can be seen that: the output terminal of oscillator 20 is connected to the input terminal of counter 30 and the input terminal of pulse generation unit 40 respectively; oscillator 20 integrates an equivalent integrating capacitor and a threshold switching structure, and the photocurrent I... sig The equivalent integral capacitor is directly charged and discharged. When the voltage across the equivalent integral capacitor reaches a preset upper or lower flip threshold, the threshold flipping structure triggers a level flip, generating an oscillation signal. Preferably, the oscillator 20 comprises a ring oscillation structure or a current-controlled delay unit structure, and the photocurrent I... sig The charging and discharging speed of the modulation delay unit is adjusted to change the oscillation frequency.

[0030] In addition, the ADC pixel and column-level coarse and fine quantization readout circuit also includes: a control unit; Figure 1 For simplicity, only the execution unit is shown in the diagram. The control unit is connected to the bus 60, the pulse generation unit 40, and the storage unit 50, respectively.

[0031] The control unit is used to send an enable signal to the pulse generation unit 40. The enable signal Used to enable the pixel array to be in the sampling or readout phase within each working cycle T; the working cycle T includes the sampling phase and the readout phase, and the oscillator 20 oscillates continuously throughout the entire cycle.

[0032] The control unit is also used to control the bus 60 to transmit the system synchronization clock SCK to each pixel during the sampling phase, and to send coarse and fine quantization row selection signals to the storage unit during the readout phase. , ( Figure 1 The first row's pixel Pixel 1 is shown, therefore its corresponding coarse quantization row selection signal is... 1. Quantize row selection signal The control bus 60 sends the coarse quantization result D to the column-level decoding unit 70. c And the refined quantification result D f .

[0033] In one embodiment of this application, preferably, the input terminal of the pulse generation unit 40 is connected to the output terminal of the oscillator 20 and the output terminal of the control unit, respectively; the output terminal of the pulse generation unit 40 is connected to the input terminal of the storage unit 50 and the reset terminal of the counter 30, respectively. During the sampling phase, the pulse generation unit 40 monitors the oscillation signal, generates a sampling signal SH, and the sampling signal SH is valid. When the oscillation signal experiences its first falling edge, the sampling signal SH changes from valid to invalid. After the sampling signal SH changes from valid to invalid, a reset pulse RST is generated. This reset pulse RST is transmitted to the counter 30 to reset the counter 30. Therefore, the sampling signal SH and the reset pulse RST have non-overlapping timing.

[0034] The ADC pixel and column-level coarse and fine quantization readout circuit proposed in this application, within each operating cycle T, has a full cycle time of the system synchronization clock. With enable signal The effective time is equal, enabling signal During the effective time period, the enabled pixel array is in the sampling phase.

[0035] Combination Figure 2 The timing diagram shown is as follows. Figure 2 In this application, OSC represents the oscillation signal. The working principle of the ADC pixel and column-level coarse and fine quantization readout circuit for infrared arrays proposed in this application is as follows: The system working period T is determined by the sampling ( ) and read out ( It consists of two phases. The sampling phase records coarse and fine quantization values. and During the readout phase, the column-level pipeline sequentially reads the sampled readings of each row, while the oscillator remains oscillating throughout the period. When the sampled signal... When the pixel enters the sampling stage, the pulse generation unit 40 generates a sampling signal SH. The sampling signal SH is active high, and the timing of the rising edge of the sampling signal SH is not important. Figure 2 The example shows its rising edge and enable signal. The rising edge of the sampling signal is at the same time as the first falling edge of the oscillation signal. The falling edge of the sampling signal is crucial. When the first falling edge of the oscillation signal arrives, the sampling signal SH also becomes low and invalid. That is, the falling edge of the sampling signal SH needs to become a falling edge simultaneously with the first falling edge of the oscillation signal (except when the photocurrent is too small). When the sampling signal SH changes from valid to invalid within the pixel, the current counter value D is simultaneously latched by the storage unit 50. c And the current system synchronization clock SCK, which is also the fine quantization result D. f Among them: D c Indicates the oscillation time Integer period count within D;f This indicates that the sampling time is at the full cycle of the system synchronization clock SCK. The phase position within the time frame. The system synchronization clock SCK only... The sampling phase runs. The refined quantization result D f It reflects the subdivision position of the oscillation edge relative to the system time base.

[0036] Since each pixel is connected to the infrared detector 10, the pixel infrared detector 10 generates photogenerated carriers under the action of incident infrared radiation, and forms a photocurrent I under the action of a bias electric field. sig Photocurrent I sig The amplitude is proportional to the intensity of the incident infrared radiation, thus realizing the conversion of optical signals into electrical signals.

[0037] The photocurrent I sig The input to the oscillator 20 within the pixel is via the switching transistor TG. Preferably, a light-controlled oscillator (LCO) can be used. The oscillator 20 internally includes an equivalent integrating capacitor and a threshold switching structure. The photocurrent I... sig The integrating capacitor is directly charged and discharged. When the capacitor voltage reaches a set threshold, it triggers a flip-flop, generating a periodic oscillation signal.

[0038] Within a single oscillation period, according to the charge conservation principle, we have:

[0039] in, For the oscillation period, This represents the change in charge corresponding to the capacitor oscillating between the upper and lower threshold values. From this, the oscillation frequency can be obtained:

[0040] From the above relationship, it can be seen that the oscillation frequency is approximately linearly proportional to the input photocurrent. Since the charging and discharging current of the oscillator 20 is entirely provided by the photocurrent, the oscillation process itself completes the regulation of the photocurrent I. sig The integration and frequency conversion can be performed without introducing additional high-power analog units such as transimpedance amplifiers, integrators, or comparators. In other words, the main energy required for oscillation comes from the photocurrent I. sig It does not rely on the static bias current of additional analog integration branches, thereby reducing the additional power consumption at the pixel end.

[0041] During the points time By counting the oscillating signals internally, coarse quantization results can be obtained:

[0042] The counting result D cEquivalent to photocurrent I sig The current-time-digital conversion path is realized by integrating in the time domain over a complete period T.

[0043] In terms of circuit implementation, the oscillator 20 can preferably be constructed using a ring oscillation structure or a current-controlled delay unit structure. The photocurrent modulates the charging and discharging speed of the delay unit, thereby changing the oscillation frequency. Since the integration and oscillation functions are completed in the same structure, the current-voltage-digital multi-stage conversion process is reduced, the circuit complexity and area overhead are decreased, and it is beneficial to realize a highly integrated array with a small pixel size.

[0044] When the incident infrared radiation is weak, the photocurrent I sig When the size is extremely small, the system's full cycle time can be appropriately extended. Increasing the count value corresponding to a unit photocurrent improves the resolution of weak signals and expands the effective dynamic range. Since the integration process is still driven by the photocurrent I... sig Direct drive completion, with extended sampling time, does not introduce additional analog integration power consumption, thus improving quantization accuracy in low-current regions without significantly increasing pixel-level power consumption. This mechanism allows the system to achieve dynamic range optimization by adjusting the oscillation period under both strong and weak signal conditions, enhancing the readout circuit's adaptability to different radiation intensity scenarios.

[0045] Furthermore, for detailed quantification, combined with Figure 2 As shown in the timing diagram, the difference between the fine quantization results obtained from two samplings in two adjacent work cycles T is: The time difference between the two falling edges is: , of which 2 N This represents the total number of count states for the SCK code. This is the full cycle time of the system synchronization clock SCK.

[0046] Due to potential phase deviation between the sampling edge and the oscillation period, there is a difference between the actual integration time and the working period T. This true integration time is denoted as... Therefore, coarse quantization counting. The actual integration time is:

[0047] When the oscillation integration time is the working period T, the number of oscillations of counter 20 is quantized as D[i], which includes integer and fractional parts. The corrected quantization result is expressed as:

[0048] In the above formula, D c[i] represents the coarse quantization result corresponding to the i-th pixel. The above correction term reflects the time deviation ratio between the sampling edge and the oscillation phase. By converting the fine quantization result into an equivalent period fraction, the overall quantization accuracy can be improved. Since the fine quantization result is only used for off-chip digital computation, no additional comparison stage or analog operation unit is needed at the pixel end; only the fine quantization result D is latched. f This enables high-precision correction, thereby improving the effective resolution of the ADC without increasing pixel power consumption and area. Furthermore, the fine-quantization sampling employs a falling edge triggering method for the oscillation signal and is set to not overlap with the flip edge of counter 20, thus avoiding uncertainties caused by the coincidence of sampling and counting edges and improving the overall system stability.

[0049] During the readout phase (when) (When), for the pixel unit in the i-th row, we have: When the coarse row selection signal corresponding to the i-th row When it is effective (i.e.) (At time), the coarse quantization result D latched by all pixel units in the i-th row. c The output is parallel to the column-level decoding unit 70 via bus 60; when the fine-quantization row selection signal corresponding to the i-th row... When it is effective (i.e.) (At time), the fine quantization result D latched by all pixel units in the i-th row f The output is sent in parallel to the column-level decoding unit 70 via bus 60. Here, i is a positive integer between 1 and K (assuming the pixel array has K rows).

[0050] For bus 60, combined with Figure 3 The bus multiplexing control timing diagram shown illustrates that it performs different functions at different working stages to achieve multiplexing. Figure 3 In the middle, Bus indicates a bus, when At this time, the pixel is in the sampling phase. Bus 60 serves as the transmission channel for the system time reference signal. The system synchronization clock SCK is transmitted to each pixel in the array through bus 60. Each pixel latches the current SCK code when the sampling signal SH arrives. This is used to refine the recording of results.

[0051] when At that time, the pixel enters the readout phase. The array sequentially selects and outputs data row by row. For the first... row pixels, when At that time, pixel i will latch the coarse quantization result. The output is sent to the column-level decoding unit 70 via bus 60; when At that time, pixel i will latch the fine quantization result. Output to column-level decoding unit 70 via the same bus. Coarse quantization result. Compared with the detailed results The data is transmitted in segments over time to achieve time-division multiplexing of the same group of N buses, and data recovery is completed in conjunction with column-level decoding and bias control signals.

[0052] Because the bus is used to transmit the system time base during the sampling phase and to transmit the quantization results during the readout phase, and the coarse quantization results... Compared with the detailed results By using a time-segmented output method, there is no need to configure separate buses for different data types, thereby reducing wiring and parasitic load. At the same time, using a current-mode bus drive reduces signal swing, lowers charging and discharging power consumption, and improves readout efficiency, making it suitable for large-scale infrared focal plane array structures.

[0053] In one embodiment of this application, the pulse generation unit 40 differs from the traditional pulse generation unit structure. In conventional technology, due to the requirement of a small pixel area for infrared arrays, multi-bit counters typically employ a TSPC structure. If the TSPC is not reset (RST) for an extended period, the intermediate node potential of the TSPC will drift over time and enter a metastable state, causing significant charge leakage and additional static power consumption, which is detrimental to power consumption control and may even affect readout accuracy. Simultaneously, the failure to properly generate the sampling signal SH in conventional technology can also lead to potential drift in the sampling module or unit, thereby affecting the accuracy and stability of the sampling results.

[0054] Reference Figure 4 The timing diagrams of the conventional pulse generation unit under different photocurrent magnitudes are shown. Figure 4 The timing diagram on the left shows the timing when the photocurrent is sufficiently large, while the timing diagram on the right shows the timing when the photocurrent is too small. When the photocurrent is sufficiently large, a normal oscillation signal OSC can be generated, and the output signal DOWN1 of the trigger is... ST As the oscillation signal OSC changes, the sampling signal SH is generated at the falling edge of the oscillation signal OSC. It is a pulse signal that lasts for only a very short period of time, followed by the reset signal RST.

[0055] When the photocurrent is too small, a normal oscillation signal OSC cannot be generated, and the oscillation signal OSC is almost zero. Therefore, the output signal DOWN1 of the trigger will be... STConsequently, the value becomes 0, and neither the sampling signal SH nor the reset signal RST is generated. This results in the TSPC not being RST (i.e., the counter not being reset) for an extended period when the photocurrent is too low. Consequently, the intermediate node potential of the TSPC drifts over time and enters a metastable state, causing significant charge leakage and additional static power consumption, which is detrimental to power control and may even affect readout accuracy. Furthermore, the failure to generate the sampling signal SH properly also causes potential drift in the sampling module or unit, further affecting the accuracy and stability of the sampling results.

[0056] This application creatively proposes a completely new pulse generation unit 40, referring to... Figure 5 The circuit structure diagram of the pulse generation unit 40 shown includes: a trigger 401, a first inverter 402, a second inverter 406, a first AND gate 403, a second AND gate 407, a first delay unit 404, and a second delay unit 405.

[0057] The input of flip-flop 401 receives the oscillation signal OSC and the enable signal. The output terminal is connected to the input terminal of the first inverter 402; VDD represents the power supply voltage.

[0058] The output of the first inverter 402 is connected to one input of the first AND gate 403, and the other input of the first AND gate 403 receives an enable signal. The output of the first AND gate 403 is connected to the input of the first delay unit 404, and outputs the sampling signal SH.

[0059] The output of the first delay unit 404 is connected to the input of the second delay unit 405 and the input of the second inverter 406, respectively; the outputs of the second delay unit 405 and the second inverter 406 are connected to the two inputs of the second AND gate 407, and the output of the second AND gate 407 is connected to the counter ( Figure 5 (Not shown in the image) is connected and outputs a reset pulse RST.

[0060] Based on the aforementioned novel pulse generation unit 40, its corresponding timing reference Figure 6 The timing diagrams shown are for different photocurrent magnitudes. Figure 6 The timing diagram on the left shows the timing when the photocurrent is sufficiently large, while the timing diagram on the right shows the timing when the photocurrent is too small. When the photocurrent is sufficiently large, a normal oscillation signal OSC can be generated, and the output signal DOWN1 of the trigger is... STAs the oscillation signal OSC changes, the sampling signal SH differs from the sampling signal generated by the traditional structure. It is no longer a pulse signal, but maintains a high level validity period for a longer time. It becomes low and invalid at the falling edge of the oscillation signal OSC. After becoming invalid, a reset signal RST is generated, which is a pulse signal.

[0061] When the photocurrent is too small, a normal oscillation signal OSC cannot be generated, and the oscillation signal OSC is almost zero. Therefore, the output signal DOWN1 of the trigger will be... ST The oscillation signal OSC is also zero. Although the oscillation signal OSC is zero, the sampling signal SH will still be valid before the falling edge of the enable signal. It will change from valid to invalid at the falling edge of the enable signal, thus generating a pulse-shaped reset signal RST. That is, even when the photocurrent is too small, the sampling signal SH and the reset signal RST can be generated according to a predetermined timing sequence, thereby latching the corresponding SCK value and coarse quantization result, and resetting the counter 30 after latching. This solves the problem caused by the traditional structure when the photocurrent is too small. The intermediate node potential of the counter TSPC will not drift over time and enter a metastable state, preventing significant charge leakage and additional static power consumption, which is extremely beneficial for power consumption control and improves readout accuracy. At the same time, the normal generation of the sampling signal SH will no longer cause potential drift in the sampling module or unit, improving the accuracy and stability of the sampling results.

[0062] In summary, the ADC pixel and column-level coarse and fine quantization readout circuit for infrared arrays proposed in this application includes: a pixel array and a column-level decoding unit; each pixel in the pixel array includes: an oscillator, which is connected to the pixel infrared detector, counter and pulse generation unit respectively, for integrating and oscillating the received photocurrent and outputting an oscillation signal.

[0063] The counter and pulse generation unit are both connected to the storage unit. The counter is used to count the period of the received oscillation signal and generate a coarse quantization result. The pulse generation unit is used to receive and generate a sampling signal based on the oscillation signal and the enable signal. The storage unit is connected to the bus and is used to receive and synchronously latch the coarse quantization result and the system synchronization clock at the current moment based on the sampling signal and the oscillation signal. The system synchronization clock at the current moment is the fine quantization result.

[0064] Each pixel is connected to the column-level decoding unit of its column via a bus. During the sampling phase, the bus transmits the system synchronization clock to each pixel. During the readout phase, it transmits the coarse quantization result and fine quantization result latched in the corresponding storage unit of each pixel in a time-division manner. The input of the column-level decoding unit is connected to the bus and is used to decode and recover the coarse quantization result and fine quantization result, and output quantized data.

[0065] The readout circuit proposed in this application introduces an oscillator, counter, pulse generation and storage within the pixel, and combines coarse and fine joint quantization mechanism to transform the traditional high-power analog integration and high-complexity ADC stage into a digital processing method based on time domain counting and phase sampling; at the same time, a bus multiplexing readout structure is adopted at the column level to reduce the number of wirings, thereby achieving a readout circuit that balances low power consumption, small area and high precision.

[0066] By employing a pixel structure that directly drives an oscillator for integration using photocurrent, it removes traditional high-power analog units such as transimpedance amplifiers, integrators, or comparators from the pixel end. This reduces circuit complexity and area overhead without significantly increasing power consumption, which is beneficial for achieving highly integrated small pixel arrays. Simultaneously, through a coarse-fine joint quantization method, it introduces a phase fine quantization mechanism on top of count quantization, improving effective quantization accuracy without adding a highly complex ADC structure or additional analog modules, thus achieving an optimized trade-off between power consumption, area, and accuracy.

[0067] Coarse quantization records the number of oscillation cycles using a counter, while fine quantization quantizes the oscillation phase using a time-to-digital conversion method. Fine quantization only requires edge-triggered sampling of the system synchronization clock, resulting in lower hardware overhead. Furthermore, fine quantization sampling is triggered on the falling edge of the oscillation signal and is set to not overlap with the counter's topping edge, thereby reducing the risk of bit errors caused by edge overlap and improving quantization stability and robustness.

[0068] In terms of column-level readout, this application adopts a current-mode pipeline readout method with bus time multiplexing, so that coarse and fine quantization results are output through the same set of buses at different time periods, and decoding and bias control are completed at the column end. This reduces the number of buses and wiring resources, reduces bus parasitic capacitance and dynamic power consumption of readout switches, and helps to reduce the layout area. It is suitable for large-scale infrared focal plane array readout circuits and has broad application prospects and high practicality.

[0069] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0070] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0071] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. An ADC pixel and column-level coarse-fine quantization readout circuit suitable for infrared arrays, characterized in that, include: Pixel array and column-level decoding unit; Each pixel in the pixel array includes an oscillator, which is connected to the pixel infrared detector, the counter, and the pulse generation unit respectively, and is used to integrate and oscillate the received photocurrent to output an oscillation signal. Both the counter and the pulse generation unit are connected to the storage unit. The counter is used to count the period of the received oscillation signal and generate a coarse quantization result; the pulse generation unit is used to receive and generate a sampling signal based on the oscillation signal and the enable signal. The storage unit is connected to the bus and is used to receive and synchronously latch the coarse quantization result and the system synchronization clock at the current moment based on the sampled signal and the oscillation signal. The system synchronization clock at the current moment is the fine quantization result. Each pixel is connected to the column-level decoding unit of its column via a bus. During the sampling phase, the bus transmits the system synchronization clock to each pixel, and during the readout phase, it transmits the coarse quantization result and fine quantization result latched in the corresponding storage unit of each pixel in a time-division manner. The input of the column-level decoding unit is connected to the bus and is used to decode and recover the coarse quantization result and the fine quantization result, and output quantized data. 2.The ADC pixel and column-level coarse-fine quantization readout circuit of claim 1, wherein, The input terminal of the oscillator is connected to the signal output terminal of the pixel infrared detector through a control switch transistor; The output terminal of the oscillator is connected to the input terminal of the counter and the input terminal of the pulse generation unit, respectively. The oscillator integrates an equivalent integral capacitor and a threshold switching structure. The photocurrent directly charges and discharges the equivalent integral capacitor. When the voltage across the equivalent integral capacitor reaches a preset upper or lower switching threshold, the threshold switching structure triggers a level switch to generate the oscillation signal. 3.The ADC pixel and column-level coarse-fine quantization readout circuit of claim 1, wherein, The ADC pixel and column-level coarse and fine quantization readout circuit also includes: a control unit; The control unit is connected to the bus, the pulse generation unit, and the storage unit, respectively. The control unit is used to send an enable signal to the pulse generation unit, which enables the pixel array to be in the sampling phase or the readout phase in each working cycle; The control unit is also configured to control the bus to transmit the system synchronization clock to each pixel during the sampling phase, and to send coarse and fine quantization row selection signals to the storage unit during the readout phase, and to control the bus to send the coarse quantization result and the fine quantization result to the column-level decoding unit. 4.The ADC pixel and column-level coarse-fine quantization readout circuit of claim 3, wherein, The input terminal of the pulse generation unit is connected to the output terminal of the oscillator and the output terminal of the control unit, respectively. The output terminal of the pulse generation unit is connected to the input terminal of the storage unit and the reset terminal of the counter, respectively. The pulse generation unit monitors the oscillation signal during the sampling phase, generates the sampling signal and the sampling signal is valid. When the oscillation signal has its first falling edge, the sampling signal changes from valid to invalid. After the sampling signal becomes invalid, a reset pulse is generated. The reset pulse is transmitted to the counter to reset the counter.

5. The ADC pixel and column-level coarse-fine quantization readout circuit of claim 1, wherein, The pulse generation unit includes: a trigger, a first inverter, a second inverter, a first AND gate, a second AND gate, a first delay unit, and a second delay unit; The input terminal of the trigger receives the oscillation signal and the enable signal, and the output terminal is connected to the input terminal of the first inverter; The output of the first inverter is connected to one input of the first AND gate, the other input of the first AND gate receives the enable signal, and the output of the first AND gate is connected to the input of the first delay unit and outputs the sampling signal. The output terminal of the first delay unit is connected to the input terminal of the second delay unit and the input terminal of the second inverter, respectively; The output of the second delay and the output of the second inverter are respectively connected to the two inputs of the second AND gate. The output of the second AND gate is connected to the counter and outputs the reset pulse.

6. The ADC pixel and column-level coarse and fine quantization readout circuit according to claim 4, characterized in that, When the sampled signal changes from valid to invalid, the storage unit synchronously latches the coarse quantization result and the system synchronization clock at the current moment, where the system synchronization clock at the current moment is the fine quantization result.

7. The ADC pixel and column-level coarse and fine quantization readout circuit according to claim 3, characterized in that, Within each working cycle, the full cycle time of the system synchronization clock is equal to the effective time of the enable signal, during which the pixel array is enabled to be in the sampling phase.

8. The ADC pixel and column-level coarse and fine quantization readout circuit according to claim 3, characterized in that, During the readout phase, for the pixel unit in the i-th row: When the coarse quantization row selection signal corresponding to the i-th row is valid, the coarse quantization results latched by all pixel units in the i-th row are output in parallel to the column-level decoding unit through the bus; When the fine quantization row selection signal corresponding to the i-th row is valid, the fine quantization results latched by all pixel units in the i-th row are output in parallel to the column-level decoding unit through the bus.

9. The ADC pixel and column-level coarse and fine quantization readout circuit according to claim 1, characterized in that, The difference between the fine-grained results obtained from two samplings in two adjacent work cycles is: The time difference between the two falling edges is: , of which 2 N This represents the total number of states counted by the system's synchronization clock. The full cycle time of the system's synchronization clock; Based on the difference between the actual integration time and the working period T, this actual integration time is denoted as... Then coarse quantization count The actual integration time is: When the oscillation integration time is the working period T, the oscillation number of times of the counter is quantized as D[i], which contains an integer and a fractional part, then the modified quantization result D c [i1] is represented as: In the above formula, D c [i] represents the coarse quantization result corresponding to the i-th pixel.

10. The ADC pixel and column-level coarse and fine quantization readout circuit according to claim 1, characterized in that, The oscillator includes: a ring oscillation structure or a current-controlled delay unit structure.

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