Network-on-chip router device and communication system for hybrid topology

Abstract

This application discloses an on-chip network router device and communication system for hybrid topology, including a pop-out module, a buffer module group, a control module, a selection module group, an arbitration module, and a register module group. The pop-out module is used to output local address data from multi-source input data to the neuron end and transmit non-local address data to the buffer module group. The buffer module group is used to synchronously and temporarily store non-local address data. The control module is used to generate control signals for regulating read enable and gating actions based on the data storage status of the buffer module group. The selection module group is used to select one path from multiple valid data paths for transmission to the arbitration module based on the control signals. The arbitration module is used to perform address matching and transmission conflict arbitration on the selected multiple data paths and forward the valid data to the corresponding register module group. The register module group is used to update the hop count of the arbitrated data stream and then forward it to the ring topology on-chip network.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an on-chip network router device and communication system for hybrid topology structures. Background Technology

[0002] Research on spiking neural networks (SNNs) continues to deepen in the fields of neuromorphic computing, low-power artificial intelligence (AI), and neuromorphic computing. The continuous improvement of hardware computing power, the ongoing optimization of related algorithms, and the increasing application demands across various industries are driving a continuous expansion in the scale of neurons in spiking neural networks. Network-on-chip (NoC) has become the mainstream design solution for neuromorphic chip communication systems due to its high performance, scalability, support for massive parallel transmission, low latency, and low power consumption. The design and optimization of its topology, routing algorithms, and router microstructures have become core research directions for achieving efficient communication in neuromorphic computing. While spiking neural network simulations based on field-programmable gate arrays (FPGAs) can accommodate a large number of neurons and synapses, they suffer from inefficient area utilization and Manhattan interconnection issues, making it difficult to meet the high fan-in / output requirements of large-scale spiking neural network systems. This further highlights the necessity of optimizing the design of network-on-chip routers.

[0003] In existing neuromorphic computing communication systems, on-chip network routers mainly consist of buffers, crossbar switches, routing computing units, and control logic. Among these, the crossbar switch is the component with the largest area in the router, while the buffer accounts for 46% of the router's total power consumption and 17% of its area consumption. The control logic and routing computing units consume only a small amount of energy and area, and the area consumption of the router's crossbar switch is positively correlated with the number of router ports determined by the topology. To adapt to different communication needs, existing on-chip networks mostly adopt a single ring topology or a mesh topology. On-chip network routers with a single ring topology have a simple structure and a small number of ports, while on-chip networks with a single mesh topology have the advantages of high aggregation bandwidth, short network diameter, and multiple path options. Therefore, researchers have proposed applying a hybrid ring and mesh topology to the neuronal interconnection of neuromorphic processors to combine the technical advantages of both topologies.

[0004] Currently, there are no dedicated on-chip network routers adapted to hybrid ring and mesh topologies. When traditional routers for single topologies are directly ported to on-chip networks with hybrid ring-mesh topologies, efficient data interaction between mesh and ring networks cannot be achieved. Furthermore, the resource configuration and data transmission control methods of traditional routers are difficult to adapt to the transmission requirements of multi-source data under hybrid topologies, which can easily lead to problems such as data congestion, high transmission latency, and low throughput. In addition, redundant port and buffer configurations can result in ineffective consumption of area and power consumption, or data loss due to insufficient configuration. This makes it impossible to meet the high reliability and high scalability requirements of large-scale spiking neural network systems. Summary of the Invention

[0005] In view of this, this application provides an on-chip network router device and communication system for hybrid topology, which can meet the high reliability and high scalability requirements of large-scale spiking neural network systems.

[0006] According to a first aspect of this application, an on-chip network router device for hybrid topology is provided. The on-chip network router device is a routing node connecting mesh topology on-chip network and ring topology on-chip network. The on-chip network router device includes a pop-up module, a buffer module group, a control module, a selection module group, an arbitration module, and a register module group. The pop-up module receives multi-source input data from the ring topology on-chip network and the mesh topology on-chip network and performs local address determination. It directly outputs valid data with a destination local address to the neuron end and transmits valid data with a destination non-local address to the buffer module group. The buffer module group is used to synchronously and temporarily store the non-local address data transmitted by the pop-up module. The control module is signal-connected to the buffer module group and is used to generate control signals according to the data storage status of the buffer module group. The control signals are used to respectively regulate the read enable action of the buffer module group and the gating action of the selection module group. The selection module group is signal-connected to the control module, the buffer module group, the neuron input terminal and the arbitration module respectively, and is used to select one channel from multiple valid data according to the control signal and transmit it to the arbitration module. The arbitration module is signal-connected to the selection module group and the register module group, and is used to perform address matching and transmission conflict arbitration on the selected multi-channel data, and forward the valid data to the corresponding register module group. The register module group is signal-connected to the arbitration module and other routing nodes of the ring topology on-chip network, and is used to update the hop count of the arbitrated data stream before forwarding it to the ring topology on-chip network.

[0007] According to a second aspect of this application, a communication system is provided, the communication system comprising: Mesh topology network on-chip; Ring topology network-on-a-chip; Neuron ends; and, The on-chip network router device for hybrid topology as described in any of the first aspects.

[0008] By means of the above technical solutions, the on-chip network router device and communication system for hybrid topology provided in this application, wherein the on-chip network router device for hybrid topology serves as a dedicated connection routing node adapted to mesh and ring topology on-chip networks, and through the collaborative work of various modules, can accurately solve various technical problems existing in the porting of traditional routers to hybrid topologies. Specifically, the pop-up module's local address determination of multi-source input data enables precise data routing, avoiding redundant transmission of invalid data. The synchronous temporary storage function of the buffer module group effectively avoids data congestion and loss issues, while reasonable module configuration avoids the waste of area and power consumption caused by buffer redundancy. The control module generates control signals based on the storage status of the buffer module group, enabling precise control of buffer module read enable and selection module gating actions, ensuring resource configuration matches data transmission needs. The on-demand gating of the selection module group, combined with the address matching and transmission conflict arbitration of the arbitration module, effectively adapts to the multi-source data transmission control requirements under hybrid topologies, significantly improving data transmission throughput, reducing transmission latency, and achieving efficient data interaction between mesh and ring topology on-chip networks. The hop count update and directed forwarding of the register module group ensure the accuracy and continuity of data transmission to the ring topology on-chip network. Overall, the complete data processing and transmission logic formed by these modules not only solves the problems of low transmission efficiency and unreasonable resource configuration in traditional routers, but also ensures high reliability of data transmission. Furthermore, the modular design and flexible transmission control logic can adapt to the communication needs of large-scale spiking neural network systems, meeting their high scalability requirements.

[0009] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1This illustration shows a functional module diagram of an on-chip network router device for hybrid topology provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of the module connection structure of an on-chip network router device for hybrid topology provided in an embodiment of this application; In the picture: 10-Pop-up module; 20 - Buffer Module Group, 201 - Synchronization Buffer Module; 30 - Control module; 40 - Select Module Group, 401 - Select Module; 50 - Arbitration Module; 60 - Register Module Group, 601 - Register Module. Detailed Implementation

[0011] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of the present application can be combined with each other.

[0012] Currently, there are no dedicated on-chip network routers adapted to hybrid ring and mesh topologies. When traditional routers for single topologies are directly ported to on-chip networks with hybrid ring-mesh topologies, efficient data interaction between mesh and ring networks cannot be achieved. Furthermore, the resource configuration and data transmission control methods of traditional routers are difficult to adapt to the transmission requirements of multi-source data under hybrid topologies, which can easily lead to problems such as data congestion, high transmission latency, and low throughput. In addition, redundant port and buffer configurations can result in ineffective consumption of area and power consumption, or data loss due to insufficient configuration. This makes it impossible to meet the high reliability and high scalability requirements of large-scale spiking neural network systems.

[0013] To address the aforementioned problems, embodiments of the present invention provide an on-chip network router device for hybrid topologies. This on-chip network router device is a routing node connecting mesh topology on-chip networks and ring topology on-chip networks. For example... Figure 1As shown, the on-chip network router device includes a pop-up module 10, a buffer module group 20, a control module 30, a selection module group 40, an arbitration module 50, and a register module group 60. The pop-up module 10 receives multi-source input data from ring topology on-chip networks and mesh topology on-chip networks and performs local address determination. Valid data destined for the local address is directly output to the neuron, while valid data destined for a non-local address is transmitted to the buffer module group 20. The buffer module group 20 is used for synchronous temporary storage of non-local address data transmitted by the pop-up module. The control module 30 is signal-connected to the buffer module group 20 and is used to generate control signals based on the data storage status of the buffer module group 20. These control signals are used to adjust... The read enable action of the control buffer module group 20 and the gating action of the selection module group 40 are respectively connected to the control module 30, the buffer module group 20, the neuron input terminal and the arbitration module 50. The selection module group 40 is used to select one path from multiple valid data according to the control signal and transmit it to the arbitration module 50. The arbitration module 50 is connected to the selection module group 40 and the register module group 60. It is used to perform address matching and transmission conflict arbitration on the selected multiple data, and forward the valid data to the corresponding register module group 60. The register module group 60 is connected to the arbitration module 50 and other routing nodes of the ring topology on-chip network. It is used to update the hop count of the data stream after arbitration and forward it to the ring topology on-chip network.

[0014] The pop-up module 10 serves as the core module for multi-source data reception and initial data splitting in the on-chip network router device. The router's external ports A, B, and C are respectively connected to the module's three pop-in ports ein1, ein2, and ein3. A and B are used to receive data from other routers in a ring topology on-chip network, while C is used to receive data from other routers in a mesh topology on-chip network. The module also includes a local pop-up port eoutn and three corresponding pop-up ports eout1, eout2, and eout3. eoutn is directly connected to the router's external port Nout, serving as a dedicated port for outputting local address data to the neural network. Pop-up ports eout1, eout2, and eout3 are all connected one-to-one with the buffer module group 20. The core function of this module is to detect valid data input to ein1, ein2, and ein3 via ports A / B / C in real time and accurately identify the destination address within the valid data, thereby achieving targeted splitting of multi-source data in mixed ring and mesh topologies. The specific routing logic and its connection with the buffer module group 20 work as follows: If the destination address is detected as a non-local address, the pop-up module 10 will transmit the valid data to the buffer module group 20 one by one through the corresponding port links of ein1-eout1, ein2-eout2, and ein3-eout3, using the synchronous storage function of the buffer module group 20 to support subsequent data processing; if the destination address is detected as a local address, the valid data will be directly output from the Nout port to the neuron end through eoutn, realizing direct and efficient transmission of local data; if ein1, ein2, and ein3 simultaneously detect valid data containing local addresses, the pop-up module 10 will further identify the hop count of each valid data, and following the Old-First priority principle, output the valid data with the largest hop count from the Nout port to the neuron end through eoutn, while the remaining valid data will be transmitted to the buffer module group 20 along their respective eout1, eout2, and eout3 ports. This can solve the transmission conflict problem of multiple local address data competing for the Nout port, and also avoid redundant retention of valid data. The pop-up module 10 connects to the ring and mesh networks via ports A / B / C to achieve unified reception of multi-source data. Then, it transmits non-local address valid data to the buffer module group 20 through a one-to-one port signal connection. This not only ensures the orderliness of this type of data transmission, but also accurately adapts to the multi-source parallel data input characteristics under the hybrid mesh and ring topology, laying the foundation for low-latency, high-throughput data processing of the entire router device.

[0015] In specific application scenarios, the pop-up module 10 is equipped with multiple pop-in ports, local pop-up ports, and multiple pop-up ports that are connected one-to-one with the multiple pop-in ports. All pop-up ports are signal-connected to the buffer module group 20. The local pop-up port is the local address data output terminal and is signal-connected to the neuron terminal. The pop-up module 10 detects the valid data input by the multiple pop-in ports and identifies the destination address in the valid data. If the destination address is not the local address, the valid data is transmitted to the buffer module group 20 one by one through the pop-up ports corresponding to each pop-in port. If the destination address is the local address, the valid data is output from the local pop-up port to the neuron terminal. If multiple pop-in ports detect valid data of the local address at the same time, the hop count of each valid data is identified, the valid data with the largest hop count is output from the local pop-up port, and the remaining valid data is transmitted to the buffer module group 20 along the corresponding pop-up port.

[0016] Specifically, the pop-up module 10, as the core module for multi-source data reception and initial data splitting in the on-chip network router device, can be equipped with three pop-in ports ein1, ein2, ein3, a local pop-out port eoutn, and three pop-out ports eout1, eout2, eout3 that are connected one-to-one with the pop-in ports. Among them, the pop-out ports eout1, eout2, and eout3 are all connected to the buffer module group 20 one-to-one with each other. The local pop-out port eoutn is a dedicated output terminal for local address data that is directly connected to the neuron terminal. The core function of this module is to detect the valid data input by ein1, ein2, and ein3 in real time and accurately identify the destination address in the valid data, thereby realizing the directional splitting of data. The specific routing logic and its connection with the buffer module group 20 work as follows: If the destination address is detected as a non-local address, the pop-up module 10 will transmit the valid data to the buffer module group 20 one by one through the corresponding port links ein1-eout1, ein2-eout2, and ein3-eout3, using the synchronous storage function of the buffer module group 20 to support subsequent data processing; if the destination address is detected as a local address, the valid data will be directly output from the local pop-up port eoutn to the neuron end, realizing direct and efficient transmission of local data; if ein1, ein2, and ein3 simultaneously detect valid data containing a local address, the pop-up module 10 will further identify each valid data. The hop count follows the Old-First priority principle, outputting the valid data with the highest hop count from eoutn to the neuron. The remaining valid data are transmitted to the buffer module group 20 along their respective eout1, eout2, and eout3 ports. This not only solves the transmission conflict problem of multiple local address data competing for the eoutn port, but also avoids redundant retention of valid data. The one-to-one port signal connection design between the pop-up module 10 and the buffer module group 20 also ensures the orderly transmission of non-local address valid data to the buffer module group 20. This adapts to the multi-source parallel data input characteristics under the mesh and ring hybrid topology, laying the foundation for low-latency, high-throughput data processing of the entire router device.

[0017] In specific application scenarios, the buffer module group 20 includes multiple synchronous buffer modules 201 that are signal-connected one-to-one with the multiple pop-up ports of the pop-up module. Each synchronous buffer module 201 has the same structure and function. Each synchronous buffer module 201 is provided with multiple buffer input ports and multiple buffer output ports. The buffer input ports include a clock input port, a reset input port, a write data input port, a write enable input port, and a read enable input port. The buffer output ports include a read data output port, a full state output port, and an empty state output port. The write data input port is connected to the corresponding pop-up port of the pop-up module 10 to receive data, and the read enable port... The input port is connected to the control module 30 to receive the read enable control signal, and the read data output port is connected to the selection module group 40 to output the stored data. When the full state output port outputs a high level, it indicates that the synchronous buffer module 201 is full of data and write operations are prohibited. When the empty state output port outputs a high level, it indicates that the synchronous buffer module 201 has no data and read operations are prohibited. When the clock input port inputs a signal rising edge, if the reset input port inputs a high level, the module signal initialization is completed. If the reset input port inputs a low level, data write and read operations are performed according to the signals of the write enable input port and the read enable input port.

[0018] Specifically, such as Figure 2As shown, the buffer module group 20 serves as the core unit for implementing multi-source data synchronous temporary storage in the on-chip network router device. It may contain three synchronous buffer modules 201 whose signals are connected one-to-one with the pop-out ports eout1, eout2, and eout3 of the pop-out module 10. Each synchronous buffer module 201 is a FIFO buffer operating under the same clock domain, with identical structure and function. Each synchronous buffer module 201 has five buffer input ports: clk (clock input port), rst (reset input port), wdata (write data input port), w_en (write enable input port), and r_en (read enable input port), and three buffer output ports: rdata (read...). The system includes three output ports: wdata (full, empty), full (full status output port), and empty (empty status output port). The wdata port is connected one-to-one with the corresponding eout port of the pop-up module 10, used to receive valid data from non-local addresses transmitted by the pop-up module 10. The r_en port is connected to the control output ports conflag1 and conflag2 of the control module 30, used to receive read enable control signals issued by the control module 30. The rdata port is connected to the selection module input ports S1 and S2 of the selection module group 40, used to output stored valid data to the selection module group 40. The empty port also outputs data to the status detection input port C1 of the control module 30. C2 and C3 provide feedback on the internal data storage status of the module; the functions of each port are coordinated with the module's action logic. When the full port outputs a high level, it indicates that the synchronous buffer module 201 is full of data, and write operations are prohibited. When the empty port outputs a high level, it indicates that there is no data inside the module, and read operations are prohibited. This effectively avoids data overflow and invalid read operations. When the clk port input signal rises, if the rst port inputs a high level, the signal initialization of the synchronous buffer module 201 is completed. If the rst port inputs a low level, the corresponding data write and read operations are executed according to the enable signals of the w_en and r_en ports, enabling clock synchronization control for data writing and reading. The buffer module group 2... The design of one-to-one connection with the port of the pop-up module 10 ensures the orderly reception and storage of non-local address data. The bidirectional signal connection with the control module 30 enables real-time feedback of data storage status and precise control of read enable actions. The port connection with the selection module group 40 provides a transmission link for the targeted reading of stored data. Overall, it can avoid the blocking and loss problems caused by rate mismatch in multi-source data transmission under hybrid topology, and also lay the storage foundation for subsequent on-demand selection and arbitration of data. At the same time, through the design of multi-module parallel storage, it can adapt to the multi-source data input characteristics of mesh and ring hybrid topologies, helping the router device achieve the goal of low latency and high throughput data processing.

[0019] Correspondingly, the synchronization buffer module 201 can be a synchronization buffer that operates in the same clock domain. The effective data write and read operations of the synchronization buffer module 201 are synchronized with the clock signal input at the clock input port.

[0020] Specifically, the synchronization buffer module 201, as the core component of the buffer module group 20, is a synchronous FIFO buffer that adapts to the same clock domain for both mesh and ring hybrid topologies. Its clock input port is clk. The write operation of valid data relies on its own wdata (write data input port) and w_en (write enable input port) in conjunction with the corresponding pop-up port of the pop-up module 10. The read operation of valid data is completed through its own rdata (read data output port) and r_en (read enable input port) in conjunction with the input port of the selection module group 40. Furthermore, the valid data write and read operations of this module are strictly synchronized with the clock signal input at the clk port. This synchronous clock design is the core technical feature of this module. Combined with the initialization function of the module's own rst (reset input port), it allows the synchronization buffer module 201 to receive valid data from non-local addresses transmitted by the pop-up module 10 via eout1, eout2, and eout3 ports, while simultaneously controlling the read operation. The clock rhythms of output module 10, control module 30, and selection module group 40 are kept highly consistent. This not only avoids data write errors, read stuttering, or data loss caused by clock domain asynchrony, but also allows the module to accurately perform read operations under the synchronous clock signal of clk after receiving the conflag1 and conflag2 control signals from control module 30 at the r_en port. The stored valid data is then transmitted to the S1 and S2 ports of selection module group 40 via the rdata port, achieving efficient timing linkage between data storage and subsequent gating. At the same time, the synchronous design of the clk port makes the hardware logic of the synchronization buffer module 201 simpler, which can meet the design requirements of low power consumption and small area of ​​the router in this application. Its parallel synchronous storage characteristics can also adapt to the parallel input requirements of multi-source data in the mesh and ring hybrid topology, effectively avoiding the rate mismatch problem of multi-source data transmission, and laying the timing foundation for the entire router device to achieve high throughput and low latency data processing.

[0021] In specific application scenarios, the control module 30 is equipped with multiple status detection input ports matching the number of multiple synchronous buffer modules 201, as well as multiple control output ports. Each status detection input port is connected to the empty status output port of each synchronous buffer module 201 in a one-to-one correspondence. The multiple control output ports are simultaneously connected to the read enable input port of the buffer module group 20 and the gating control input port of the selection module group 40. The control module 30 determines the low level input of the empty status output port as valid data in the corresponding synchronous buffer module 201. If valid data is detected in all synchronous buffer modules 201, the control module 30 generates control signals using a cyclic arbitration scheme and outputs them to the selection module group 40 and the buffer module group 20 through each control output port, thereby regulating the gating action of the selection module group 40 and the read enable action of the buffer module group 20, respectively.

[0022] Specifically, such as Figure 2 As shown, the control module 30, as the core control unit of the on-chip network router device, may have three status detection input ports C1, C2, and C3 matching the number of the three synchronization buffer modules 201, and two control output ports conflag1 and conflag2. Each status detection input port C1, C2, and C3 is connected to the empty state output port of each synchronization buffer module 201 in a one-to-one correspondence signal connection. The two control output ports conflag1 and conflag2 are simultaneously connected to the read enable input port r_en of the buffer module group 20 and the gating control input port flag of the selection module group 40, forming a linkage control link. The core control logic and connection relationship of this module are as follows: the control module 30 determines the low level input of the empty port in the synchronization buffer module 201 as valid data in the corresponding synchronization buffer module 201, and can perceive the storage status of each synchronization buffer module 201 in real time. If valid data is detected in all synchronization buffer modules 201, the control module 30 will generate an appropriate control signal using a cyclic arbitration scheme and synchronously output the control signal to the selection module group 40 and the buffer module group 20 through the conflag1 and conflag2 ports. This will precisely control the gating action of the selection module group 40 and the read enable action of the buffer module group 20, realizing the timing linkage between data reading of the buffer module group 20 and data gating of the selection module group 40. This can avoid invalid read operations of the buffer module group 20 and blind selection problems of the selection module group 40, and ensure the orderliness of multi-source data transmission through the cyclic arbitration scheme. It can effectively adapt to the multi-source data transmission control requirements under the hybrid mesh and ring topology. At the same time, this linkage control design can simplify the router's control logic, reduce the consumption of invalid hardware actions, meet the router's design goals of low power consumption and low latency, and also lay the control foundation for the efficient execution of subsequent data gating and arbitration.

[0023] In a specific application scenario, the selection module group 40 includes multiple selection modules 401 with identical structure and function. Each selection module 401 is provided with multiple selection data input ports, one gating control input port, and one selection data output port. The gating control input ports of each selection module 401 are connected to the control output ports of the control module 30 in a one-to-one correspondence. The selection data input ports include ports that are connected to the read data output ports of different synchronization buffer modules 201 and ports that are connected to the input terminals of neurons. The selection data output ports are connected to the arbitration module 50. The selection module 401 selects one valid data from the multiple selection data input ports according to the control signal received by the gating control input port, and outputs the selected valid data from the selection data output port to the arbitration module 50.

[0024] Specifically, such as Figure 2As shown, the selection module group 40 serves as the core unit for on-demand selection of multi-source data in the on-chip network router device. It may include two selection modules 401 with identical structure and function. Each selection module 401 has three selection data input ports S1, S2, and S3, one selection control input port flag, and one selection data output port data. The selection control input port flag of each selection module 401 is connected to the control output ports conflag1 and conflag2 of the control module 30 in a one-to-one correspondence. Among the selection data input ports, S1 and S2 are connected to the read data output ports rdata of different synchronization buffer modules 201, S3 is connected to the neuron input terminal Nin, and the selection data output port data is connected to the arbitration data input ports AR1 and AR2 of the arbitration module 50 in a one-to-one correspondence, forming a complete data selection link. The core function and connection relationship of this module are: the selection module 401 can receive the data from the control module 30 according to the selection control input port flag. The onflag1 / conflag2 control signals precisely select one valid data path from the stored data of the synchronization buffer module 201 accessed by ports S1, S2, and S3, and the input data of the neuron input terminal Nin. The selected valid data is then directed from the selected data output port data to the arbitration module 50. This one-to-one control signal connection design enables the control module 30 to precisely control the selection action of the selection module 401. The design of the multi-source data input port effectively connects the temporary stored data of the buffer module group 20 with the input data of the neuron, realizing on-demand selection of multi-source parallel data in a hybrid topology and avoiding the blind transmission and retention of invalid data. At the same time, the design of the two selection modules 401 working in parallel can adapt to the multi-source data transmission characteristics of mesh and ring hybrid topologies, greatly improving the efficiency of data selection and transmission. It can provide an orderly data source for the address matching and transmission conflict arbitration of the subsequent arbitration module 50, and also meets the overall design goal of low latency and high throughput of this router device.

[0025] In specific application scenarios, the arbitration module 50 is provided with multiple arbitration data input ports matching the number of multiple selection modules 401 in the selection module group 40, as well as multiple arbitration data output ports; each arbitration data input port is connected to the selection data output port of each selection module 401 in a one-to-one correspondence signal, and each arbitration data output port is connected to the register module group 60 in a corresponding signal; the arbitration module 50 is used to detect the destination address of the valid data input by each arbitration data input port, match the valid data with the address direction corresponding to each arbitration data output port, and forward the valid data to the register module group 60 using the matched arbitration data output port; if the valid data of multiple arbitration data input ports compete for the same arbitration data output port, the arbitration module 50 identifies the number of hops in each data path, outputs the valid data with the largest number of hops from that arbitration data output port, and outputs the remaining valid data from other arbitration data output ports.

[0026] Specifically, such as Figure 2As shown, the arbitration module 50, as the core unit for data address matching and transmission conflict arbitration in the on-chip network router device, is a key link connecting the selection module group 40 and the register module group 60. It may have two arbitration data input ports AR1 and AR2, matching the number of the two selection modules 401 in the selection module group 40, and two arbitration data output ports AO1 and AO2. Each arbitration data input port AR1 and AR2 is connected to the selection data output port data of each selection module 401 in a one-to-one correspondence, and each arbitration data output port AO1 and AO2 is connected to the register input port R of the register module group 60 in a one-to-one correspondence, forming a directional data transmission and arbitration link. The core function and connection relationship of this module are as follows: the arbitration module 50 will detect the destination address of the valid data input into each arbitration data input port AR1 and AR2 in real time, match the valid data with the preset corresponding address direction of each arbitration data output port AO1 and AO2, and then forward the valid data to the register module through the matched arbitration data output ports AO1 / AO2. Block group 60, with its one-to-one signal connection design, ensures the directionality and accuracy of data transmission, avoiding data transmission errors. If valid data from multiple arbitration data input ports contends for the same arbitration data output port, arbitration module 50 will follow the Old-First principle to identify the hop count of each valid data stream, outputting the valid data with the highest hop count from that arbitration data output port, and outputting the remaining valid data from other arbitration data output ports. This arbitration logic effectively solves the problem of output port contention for multi-source data in hybrid topologies, avoiding data congestion and delays, ensuring smooth data transmission, and significantly improving the router's data transmission throughput and reducing transmission latency. Through address matching and conflict arbitration, arbitration module 50 can complete the ordered processing of multi-source data after selection, laying an orderly data source foundation for subsequent hop count updates of register module group 60 and directional forwarding of the ring topology on-chip network. Its simple hardware arbitration logic also fits the router's overall design goals of low power consumption and low latency, perfectly adapting to the multi-source data transmission requirements of mesh and ring hybrid topologies.

[0027] In specific application scenarios, the register module group 60 includes multiple register modules 601 that are signal-connected one-to-one with the multiple arbitration data output ports of the arbitration module 50. Each register module 601 has the same structure and function. Each register module 601 has a register input port and a register output port. The register input port is signal-connected to the corresponding arbitration data output port, and the register output port is signal-connected to other routing nodes of the ring topology on-chip network. When the clock signal rises, if valid data is input into the register input port of the register module 601 and the corresponding routing node of the ring topology on-chip network allows input, the register module 601 increments the hop count in the valid data by 1, and then forwards the updated valid data from the register output port to other routing nodes of the ring topology on-chip network.

[0028] Specifically, such as Figure 2As shown, register module group 60 is the final core unit in the on-chip network router device that realizes data hop count update and directional forwarding. It can contain two register modules 601 that match the number of arbitration data output ports of arbitration module 50. The structure and function of each register module 601 are completely the same. Each register module 601 has a registered input port R and a registered output port RO. The registered input port R is connected to the arbitration data output ports AO1 and AO2 of arbitration module 50 in a one-to-one signal connection. The registered output port RO is connected to the external ports M and N of the router in a one-to-one signal connection. It also establishes signal connections with other routing nodes of the ring topology on-chip network through ports M and N, forming a directional data transmission link from the arbitration module to the ring topology network. The core function and connection relationship of this module are as follows: At the rising edge of the clock signal, if there is valid data input to the register input port R of register module 601, and the corresponding routing node of the ring topology on-chip network allows input, register module 601 will increment the hop count in the valid data by 1, completing the hop count update. Then, the updated valid data is forwarded from the M / N port to other routing nodes of the ring topology on-chip network via register output port RO. This one-to-one signal connection design ensures the directionality and accuracy of the valid data arbitrated by arbitration module 50 to the ring topology network, avoiding data transmission errors. The hop count increment design also meets the routing counting requirements of the ring topology, allowing subsequent... The routing node can accurately identify the data transmission hop count and adapt to the Old-First priority principle of the entire router. The triggering logic of "forwarding only when the routing node allows input" can effectively avoid invalid data transmission and transmission congestion in the ring topology network, thereby improving the reliability of cross-topology data transmission. At the same time, the design of the two register modules 601 working in parallel can adapt to the transmission characteristics of multi-source data in the hybrid mesh and ring topology, ensuring the efficiency of data forwarding. This aligns with the overall design goal of low latency and high throughput of the router and can also complete the last link of cross-topology data transmission from mesh topology to ring topology, realizing efficient data interaction between on-chip networks in hybrid mesh and ring topologies.

[0029] In specific application scenarios, the on-chip network router device is equipped with multiple ring input ports, one mesh input port, one neuron input port, one neuron output port, and multiple ring output ports. The multiple ring input ports are used to receive data from other routers in the ring topology on-chip network, the mesh input port is used to receive data from other routers in the mesh topology on-chip network, the neuron input port is the neuron data input end, the neuron output port is the local address data output end and is connected to the neuron end, and the multiple ring output ports are connected to the multiple register output ports of the register module group in a one-to-one correspondence, serving as ports for forwarding valid data to the ring topology on-chip network.

[0030] In summary, the on-chip network router device for hybrid topologies provided by this invention eliminates redundant components such as cross switches found in traditional routers, significantly reducing hardware area and power consumption. Through the collaborative work of the pop-up module, buffer module group, control module, selection module group, arbitration module, and register module group, it achieves high-throughput, low-latency, and low-congestion transmission of mesh-to-ring topology data. The buffer module group's buffering design avoids data loss and rate mismatch issues; the arbitration module resolves port contention; the selection module's dynamic gating reduces data lag; and the control module's cyclic arbitration enables precise adaptation of resource allocation to transmission requirements. Furthermore, the on-chip network router device possesses excellent scalability and high reliability. The arbitration module can adapt to variable inputs, and the control module can adapt to new routing strategies through firmware updates, meeting the needs of network expansion at different scales. The collaborative design of multiple modules also achieves fault tolerance and complete data transmission, ensuring stable system operation. It perfectly adapts to the core requirements of large-scale spiking neural networks for high fan-in / output, high scalability, and high fault tolerance in communication systems, achieving the overall design goals of low power consumption and low latency.

[0031] Those skilled in the art will understand that the above-described on-chip network router device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0032] Based on the above, Figure 1 , 2 The illustrated on-chip network router device for hybrid topologies, correspondingly, also provides a communication system in this embodiment. The communication system includes: a mesh topology on-chip network; a ring topology on-chip network; a neuron endpoint; and, as described above... Figure 1 , 2 The illustrated on-chip network router device is designed for hybrid topologies.

[0033] The communication system provided in this application has the beneficial effects of any of the above embodiments of the on-chip network router device for hybrid topology, as described in any of the above embodiments. These effects will not be elaborated upon here. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An on-chip network router device for hybrid topology architectures, characterized in that, The on-chip network router device is a routing node connecting a mesh topology on-chip network and a ring topology on-chip network. The on-chip network router device includes a pop-up module, a buffer module group, a control module, a selection module group, an arbitration module, and a register module group. The pop-up module receives multi-source input data from the ring topology on-chip network and the mesh topology on-chip network and performs local address determination. It directly outputs valid data with a destination local address to the neuron end and transmits valid data with a destination non-local address to the buffer module group. The buffer module group is used to synchronously and temporarily store the non-local address data transmitted by the pop-up module. The control module is signal-connected to the buffer module group and is used to generate control signals according to the data storage status of the buffer module group. The control signals are used to respectively regulate the read enable action of the buffer module group and the gating action of the selection module group. The selection module group is signal-connected to the control module, the buffer module group, the neuron input terminal and the arbitration module respectively, and is used to select one channel from multiple valid data according to the control signal and transmit it to the arbitration module. The arbitration module is signal-connected to the selection module group and the register module group, and is used to perform address matching and transmission conflict arbitration on the selected multi-channel data, and forward the valid data to the corresponding register module group. The register module group is signal-connected to the arbitration module and other routing nodes of the ring topology on-chip network, and is used to update the hop count of the arbitrated data stream before forwarding it to the ring topology on-chip network.

2. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The pop-up module is provided with multiple pop-in ports, a local pop-up port, and multiple pop-up ports that are connected to the multiple pop-in ports one by one. The multiple pop-up ports are all connected to the buffer module group. The local pop-up port is a local address data output terminal and is connected to the neuron terminal signal. The pop-up module detects the valid data input by the multiple pop-in ports and identifies the destination address in the valid data. If the destination address is not a local address, the valid data is transmitted to the buffer module group one by one through the pop-up ports corresponding to each pop-in port. If the destination address is a local address, the valid data is output from the local pop-up port to the neuron end; if the multiple pop-up ports detect valid data of the local address at the same time, the hop count of each valid data is identified, the valid data with the largest hop count is output from the local pop-up port, and the remaining valid data is transmitted to the buffer module group along the corresponding pop-up port.

3. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The buffer module group includes multiple synchronous buffer modules that are signal-connected one-to-one with the multiple pop-up ports of the pop-up module, and each synchronous buffer module has the same structure and function. Each of the aforementioned synchronization buffer modules is provided with multiple buffer input ports and multiple buffer output ports. The buffer input ports include a clock input port, a reset input port, a write data input port, a write enable input port, and a read enable input port. The buffer output ports include a read data output port, a full state output port, and an empty state output port. The write data input port is connected to the corresponding pop-up port of the pop-up module to receive data. The read enable input port is connected to the control module signal to receive a read enable control signal. The read data output port is connected to the selection module group signal to output stored data. When the full-state output port outputs a high level, it indicates that the internal data of the synchronization buffer module is full, and write operations are prohibited. When the empty-state output port outputs a high level, it indicates that there is no data inside the synchronization buffer module, and read operations are prohibited. When the clock input port receives a rising edge signal, if the reset input port receives a high level, the module signal initialization is completed. If the reset input port receives a low level, data write and read operations are performed according to the signals of the write enable input port and the read enable input port.

4. The on-chip network router device for hybrid topology according to claim 3, characterized in that, The synchronization buffer module is a synchronization buffer that operates in the same clock domain. The effective data write and read operations of the synchronization buffer module are synchronized with the clock signal input at the clock input port.

5. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The control module is provided with multiple status detection input ports matching the number of the multiple synchronization buffer modules, and multiple control output ports; each of the status detection input ports is connected to the empty status output port of each of the synchronization buffer modules in a one-to-one correspondence signal, and the multiple control output ports are simultaneously connected to the read enable input port of the buffer module group and the gating control input port of the selection module group. The control module determines that a low level input to the empty state output port is valid data in the corresponding synchronous buffer module. If valid data is detected in all synchronous buffer modules, the control module generates control signals using a cyclic arbitration scheme and outputs them to the selection module group and the buffer module group through each control output port, thereby regulating the gating action of the selection module group and the read enable action of the buffer module group, respectively.

6. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The selection module group includes multiple selection modules with the same structure and function. Each selection module is provided with multiple selection data input ports, one gating control input port and one selection data output port. Each selection module's gating control input port is connected to each control output port of the control module in a one-to-one correspondence. The selection data input port includes a port connected to the read data output port of different synchronization buffer modules and a port connected to the neuron's input terminal. The selection data output port is connected to the arbitration module. The selection module selects one valid data from multiple selection data input ports based on the control signal received by the selection control input port, and outputs the selected valid data from the selection data output port to the arbitration module.

7. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The arbitration module is provided with multiple arbitration data input ports matching the number of multiple selection modules in the selection module group, and multiple arbitration data output ports; each arbitration data input port is connected to the selection data output port of each selection module in a one-to-one correspondence, and each arbitration data output port is connected to the corresponding signal of the register module group. The arbitration module is used to detect the destination address of the valid data input by each arbitration data input port, match the valid data with the address direction corresponding to each arbitration data output port, and then forward the valid data to the register module group using the matched arbitration data output port. If valid data from multiple arbitration data input ports compete for the same arbitration data output port, the arbitration module identifies the number of hops in each data stream, outputs the valid data with the largest number of hops from that arbitration data output port, and outputs the remaining valid data from other arbitration data output ports.

8. The on-chip network router device for hybrid topology according to claim 1, characterized in that, The register module group includes multiple register modules that are signal-connected one-to-one with the multiple arbitration data output ports of the arbitration module. The structure and function of each register module are the same. Each register module has a register input port and a register output port. The register input port is signal-connected to the corresponding arbitration data output port, and the register output port is signal-connected to other routing nodes of the ring topology on-chip network. When the clock signal rises, if valid data is input into the register input port of the register module and the corresponding routing node of the ring topology on-chip network allows input, the register module will increment the hop count in the valid data by 1, and then forward the updated valid data from the register output port to other routing nodes of the ring topology on-chip network.

9. The on-chip network router device for hybrid topology according to any one of claims 1-8, characterized in that, The on-chip network router device has multiple ring input ports, one mesh input port, one neuron input port, one neuron output port, and multiple ring output ports. The multiple ring input ports are used to receive data from other routers in the ring topology on-chip network, the mesh input port is used to receive data from other routers in the mesh topology on-chip network, the neuron input port is the neuron data input terminal, the neuron output port is the local address data output terminal and is connected to the neuron terminal, and the multiple ring output ports are connected to the multiple register output ports of the register module group in a one-to-one correspondence, serving as ports for forwarding valid data to the ring topology on-chip network.

10. A communication system, characterized in that, The communication system includes: Mesh topology network on-chip; Ring topology network-on-a-chip; Neuron ends; and, The on-chip network router device for hybrid topology as described in any one of claims 1 to 9.

Images