A low-power, monolithically integrated adaptive electronic signal processing system

Abstract

This invention belongs to the field of bioelectronics and edge computing technology, specifically a low-power, monolithically integrated adaptive electronic signal processing system. The system integrates a signal input interface, a two-stage low-noise amplification and filtering module, a neuromorphic signal processing array, and a back-end drive output module. The front end employs a low-noise instrumentation amplifier with high common-mode rejection ratio and a multi-feedback bandpass filter to achieve high-fidelity extraction of weak temporal signals. The signal processing array uses a fully analog synapse-neuron nested primitive circuit, utilizing physical mechanisms such as pulse time-dependent plasticity to achieve decode-free adaptive feature encoding of non-stationary signals. This system uses a four-layer circuit board integration, resulting in extremely low single-channel static power consumption and an end-to-end signal processing delay of less than 5 ms. The system architecture completely eliminates the digital decoding delay of the von Neumann architecture, providing a highly reliable hardware-level solution for portable monitoring and closed-loop adaptive driving of weak signals.

Description

Technical Field

[0001] This invention belongs to the field of bioelectronics and edge computing technology, specifically relating to a low-power monolithic integrated adaptive electronic signal processing system. Background Technology

[0002] In the design of complex electronic interfaces and edge computing systems, achieving real-time, low-power, and high-precision processing of weak, non-stationary signals (such as microvolt-level time-series environmental potentials and biophysical electrical signals) has always been a core challenge in this field. These weak signals are usually accompanied by strong background noise and unpredictable dynamic drift, which places extremely high demands on the system's accurate front-end sensing and adaptive back-end interpretation capabilities.

[0003] Traditional electronic signal processing systems are generally based on the classic von Neumann architecture, whose signal links heavily rely on analog-to-digital converters (ADCs), digital signal processors (DSPs), or microcontrollers (MCUs). This architecture essentially extracts signal features through predefined software algorithms and fixed filtering parameters. This not only requires enormous computing resources, but also, when faced with highly random and non-stationary signals, the rigid algorithm model is simply unable to autonomously adapt to long-term physical drift of sensor interface impedance or dynamic changes in the external environment, resulting in extremely poor robustness in cross-scenario or complex operating conditions. Even more critically, when digital logic chips perform high-frequency clock-driven instruction throughput operations, system power consumption often reaches tens or even hundreds of milliwatts; and the frequent signal conversions between the analog and digital domains inevitably introduce at least twenty milliseconds of computational latency. These inherent defects of the "power wall" and long latency severely limit the engineering deployment of traditional architectures in power-sensitive portable devices, passive sensing nodes, and scenarios requiring millisecond-level transient physical closed-loop control.

[0004] Furthermore, in the front-end acquisition and conditioning stage of weak signals, millivolt or even microvolt-level signals are easily overwhelmed by the prevalent power frequency interference and broadband noise floor in the environment. Existing lightweight signal acquisition devices, in pursuit of system miniaturization, often have to simplify multi-stage filtering networks and common-mode rejection circuits, making it difficult to balance miniaturization with high anti-interference performance, which can easily lead to severe distortion of the underlying signals. Meanwhile, in the emerging field of neuromorphic electronics, although underlying biomimetic devices (such as artificial synapses and memristors) have shown excellent adaptive potential, current mainstream technologies are mostly limited to performance verification or discrete testing of single devices. The industry is severely lacking in complete hardware systems that can deeply monolithically integrate a high common-mode rejection ratio analog front-end, neuromorphic signal processing array, and back-end driver network.

[0005] Therefore, the fields of microelectronics and automatic control urgently need a new system architecture that overturns the traditional digital processing approach. This architecture must break away from the dependence on traditional software decoding algorithms and directly respond to dynamic signals by endowing the underlying hardware with physical-level adaptive capabilities. At the same time, the system also needs to overcome the integration barriers of multi-level signal chains, achieving a high degree of monolithic integration from front-end precision acquisition and intermediate pulse encoding to back-end direct drive, thereby providing a truly end-to-end ultra-low latency processing system under extremely low power consumption physical benchmarks. Summary of the Invention

[0006] The purpose of this invention is to provide a high-performance, low-power, monolithically integrated adaptive electronic signal processing system.

[0007] The low-power monolithically integrated adaptive electronic signal processing system provided by this invention is monolithically integrated from a high-precision front-end analog circuit and a neuromorphic processing array with biomimetic adaptive characteristics. Utilizing the advantages of both circuit architectures, the front-end analog circuit, serving as the peripheral signal extraction module for the neuromorphic processing array, is tightly integrated with the back-end driving module at the system-level granularity, providing a new paradigm for processing weak, non-stationary biological and environmental electrical signals; specifically, it includes:

[0008] The front-end signal acquisition module receives weak analog electrical signals from external input via a microelectrode array;

[0009] A two-stage amplification and filtering module, connected to the output of the front-end signal acquisition module, includes a cascaded first-stage low-noise variable gain amplifier and a second-stage multiple feedback (MFB) bandpass filter, used to amplify the weak analog electrical signal with low noise and extract the target frequency band.

[0010] The neuromorphic signal processing array (also known as the neuromorphic primitive circuit array) is connected to the output of the two-stage amplification and filtering module. It integrates a multi-channel synapse-neuron nested primitive circuit to receive the extracted analog signal and dynamically adjust the weight based on the physical pulse time-dependent plasticity (STDP) mechanism to encode the analog signal into a frequency-modulated pulse (PFM) signal in real time for output.

[0011] The back-end drive output module, connected to the output of the neuromorphic signal processing array, includes a cascaded variable gain amplifier, a buffer stage, a fourth-order low-pass filter, and a resistor divider clamping network; it is used to amplify and limit the power of the frequency-modulated pulse signal to drive an external physical actuator.

[0012] The power management module, connected to the above modules, is used to provide system-level low-noise regulated power supply and perform dynamic power consumption optimization.

[0013] The above modules achieve high-density monolithic integration through multilayer printed circuit boards (PCBs).

[0014] Furthermore:

[0015] The physical interface of the front-end signal acquisition module is adapted to a multi-channel microelectrode array: the microelectrode array contains 42 to 44 signal acquisition channels, the electrode contact diameter is no greater than 25 μm, and its interface working impedance matching range is 1-100 kΩ.

[0016] The specific circuit topology parameters of the two-stage amplification and filtering module are as follows:

[0017] The first-stage low-noise variable gain amplifier uses an ultra-low noise instrumentation amplifier circuit. Its voltage gain is hardware adjustable in the range of 1 to 500 times, the input equivalent noise density is not higher than 0.8 nV / √Hz, and the single-stage common-mode rejection ratio (CMRR) is ≥120 dB.

[0018] The second-stage multiple feedback (MFB) bandpass filter is used to filter out system baseline drift and high-frequency ambient noise, and its passband frequency is set from 0.33 Hz to 40 Hz;

[0019] The two-stage amplification and filtering module is also connected in parallel with a right leg drive (RLD) common-mode rejection feedback circuit, which makes the actual common-mode rejection ratio of the entire front-end acquisition link reach more than 80 dB.

[0020] The working mechanism of the neuromorphic signal processing array is as follows:

[0021] The array contains 12 independent parallel processing channels;

[0022] The synaptic device in each channel receives the time-varying voltage signal input from the front end, and its own conductance weight is dynamically and nonlinearly adjusted in the range of 0.1 nS to 100 nS.

[0023] The frequency response range of the encoded output frequency modulated pulse (PFM) signal is 1 Hz to 40 Hz, and the pulse firing frequency is highly linearly correlated with the envelope amplitude of the input signal.

[0024] The output characteristics of the backend driver output module are as follows:

[0025] The input frequency-modulated pulse signal is shaped and amplified, and the output drive pulse width is adjustable from 100 μs to 1000 μs, while the output voltage amplitude is controlled from 0.1 V to 2.0 V.

[0026] The system features ultra-low power consumption and low latency hardware integration.

[0027] All active modules of the system are integrated on a 4-layer high-density PCB board;

[0028] Under stable operating conditions, the average power consumption of a single signal processing channel is less than 0.67 mW;

[0029] From receiving the input signal from the front-end signal acquisition module to outputting the drive pulse from the back-end drive output module, the end-to-end delay of the entire pure hardware signal link is strictly less than 5 ms.

[0030] The system of this invention uses a four-layer FR-4 printed circuit board (PCB) to achieve hardware interconnection; and uses pure analog signal stream communication to enable the front-end circuit to effectively drive the neuromorphic processing array, thereby achieving real-time, low-power multi-channel signal adaptive processing.

[0031] The low-power monolithically integrated adaptive electronic signal processing system is obtained through the following steps:

[0032] (1) Determine the specifications and structure of the front-end signal acquisition and filtering circuit: including designing the system's channel multiple feedback (MFB) topology, input impedance, signal amplification factor and filtering bandwidth;

[0033] (2) Design of neuromorphic processing array and back-end driving circuit: The neuromorphic processing array is used as the core unit to extract nonlinear features and perform pulse coding operation, and the back-end circuit performs amplification, low-pass filtering and voltage clamping protection operation;

[0034] (3) Monolithic interconnection of front-end analog circuit and neuromorphic processing array: control impedance routing and interlayer via stitching technology are used to reduce parasitic inductance;

[0035] (4) Fabrication and assembly of on-chip adaptive electronic signal processing system and peripheral power supply system to ensure hard-wired connection from signal acquisition terminal to processing system to minimize signal distortion;

[0036] (5) Package the heterogeneous integrated system and perform closed-loop testing using a dedicated tester.

[0037] The front-end circuit is designed to have a high input impedance of greater than 1 GΩ (at 1 kHz frequency), low noise performance of 1.8 μVrms and linear phase response characteristics within a bandwidth of 0.33-40 Hz;

[0038] The neuromorphic processing array is packaged in POD_LQFP64 and mounted on the four-layer FR-4 PCB. Its parasitic inductance is strictly controlled within the range of less than 0.5 nH to ensure signal fidelity.

[0039] The voltage clamping operation of the back-end circuit is to clamp the output signal to ±2V through a resistor voltage divider network, with the tolerance controlled within 1%, so as to achieve overvoltage protection.

[0040] The front-end two-stage amplification module includes an INA849DGKR low-noise variable gain amplifier for weak signal amplification and a TLV9162IDSGR operational amplifier for precise signal conditioning.

[0041] The buffer stage of the back-end circuit module uses a TLV9162IDSGR operational amplifier, and the cutoff frequency of the fourth-order low-pass filter is set to 600 Hz.

[0042] The low-power monolithically integrated adaptive electronic signal processing system of this invention also relates to the interconnection and signal conditioning methods for monolithically integrated front-end analog circuits and neuromorphic processing arrays. Specifically, due to issues such as extremely low-frequency baseline drift and 50 Hz and 60 Hz power frequency interference, system-level conditioning is required before and after the signal is fed into the neuromorphic processing array in the physical connection and signal transmission between the front and rear stages of the system. This includes:

[0043] (1) Introduce a multiple feedback (MFB) topology at the front end for signal conditioning to optimize the signal-to-noise ratio of the input signal;

[0044] (2) Common-mode noise suppression is achieved by configuring the right leg drive (RLD) circuit; specifically, the power frequency interference of 50 Hz and 60 Hz is significantly suppressed by inverting and amplifying the common-mode signal before feedback.

[0045] (3) After the net signal is obtained by the front-end circuit, it is fed into the neuromorphic processing array in LQFP64 package through impedance-controlled low parasitic PCB traces.

[0046] (4) The pulse signal output by the neuromorphic array is cascaded, filtered at 600 Hz and clamped at ±2 V to directly drive the external load.

[0047] The right leg drive (RLD) circuit is implemented using a TLV9162IDSGR operational amplifier configuration;

[0048] The peripheral support module includes a 390 mAh lithium-ion battery, which is regulated to ±5 V dual power rails by a TPS61093DSKT buck-boost converter, and is equipped with a power management module consisting of a TPS7A20L12.

[0049] The testing method for this adaptive system involved in this invention comprises the following steps:

[0050] (1) Perform high-density physical packaging on the prepared monolithic integrated system.

[0051] (2) Before testing, connect the external head-mounted electrodes directly to the signal acquisition system via hard wires to minimize uncontrollable signal distortion and ensure high fidelity and reliability of the input signal.

[0052] (3) When the power management unit is turned on, the TPS61093DSKT converter stabilizes the battery voltage at ±5 V dual power rails, providing a stable and low-noise DC power bias for the front-end INA849DGKR and the subsequent operational amplifier.

[0053] (4) Input a weak timing test electrical signal and use an oscilloscope to monitor the net signal after being amplified by the front-end MFB topology, as well as the controlled drive waveform output by the back-end fourth-order low-pass filter.

[0054] The low-power, monolithically integrated adaptive electronic signal processing system provided by this invention achieves a good combination of heterogeneous processing systems. It solves technical problems such as signal attenuation, pulse distortion caused by parasitic inductance, and power frequency interference that exist when analog front-ends and neuromorphic arrays are tightly integrated. It realizes low-noise acquisition, high-fidelity amplification, hardware-level neuromorphic adaptive processing, and real-time drive output of complex non-stationary electrical signals, and is particularly suitable for scenarios such as weak signal monitoring and low-power edge control without decoding.

[0055] In this invention, on the one hand, the precision front-end constructed using the INA849DGKR and TLV9162IDSGR effectively suppresses low-frequency and common-mode noise, improving the accuracy of the underlying neuromorphic synaptic feature mapping; on the other hand, the neuromorphic processing array, combined with a strictly controlled four-layer FR-4 PCB layout and interlayer via stitching technology, completes adaptive signal encoding with extremely low parasitic interference. This system combines low-noise precision commercial analog circuits (such as those from Texas Instruments) with laboratory-grade neuromorphic hardware, propelling ultra-low-power weak signal processing and closed-loop control systems from theory to practical engineering deployment. Attached Figure Description

[0056] Figure 1 This is the overall hardware architecture of the low-power monolithic integrated adaptive electronic signal processing system of the present invention.

[0057] Figure 2 This is a diagram of the underlying circuit topology of the front-end circuit module (including INA849DGKR and TLV9162IDSGR) of the present invention.

[0058] Figure 3 This is a schematic diagram of the structure of the multi-channel neuromorphic primitive circuit array of the present invention.

[0059] Figure 4This is a comparison diagram of the input and output signal waveforms before and after adaptive processing in the system of the present invention.

[0060] In the diagram, the numbers represent: 1 is a ferroelectric floating gate transistor, 2 is a capacitor, and 3 is a threshold switching memristor. Detailed Implementation

[0061] The present invention will be further described below with reference to the embodiments and accompanying drawings.

[0062] This embodiment selects a system integrating a 12-channel neuromorphic primitive circuit (NPC) array, which is a low-power monolithic adaptive electronic signal processing system.

[0063] The following description provides many specific details, such as the structure, materials, dimensions, and processing techniques of the device. However, as will be understood by those skilled in the art, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, the various parts of the device may be constructed from materials or commercially available chips known to those skilled in the art.

[0064] Figure 1 The overall hardware architecture of a low-power, monolithically integrated adaptive electronic signal processing system is shown. Specifically, it includes:

[0065] (1) Determine the scale and structure of the front-end circuit: Design a multiple feedback (MFB) topology to ensure a high input impedance of more than 1 GΩ at 1 kHz frequency, and achieve extremely low noise performance of only 1.8 μVrms and linear phase response within a bandwidth of 0.33-40 Hz.

[0066] (2) Design of neuromorphic array and back-end circuit: Texas Instruments (TI) commercial chips are selected to build the peripheral circuit and perform signal cascade amplification, filtering and clamping protection.

[0067] (3) Fabrication of interconnect layer for multi-module monolithic integration: Four-layer FR-4 PCB is designed using controlled impedance routing and interlayer via stitching technology.

[0068] (4) The on-chip fabrication system is assembled and connected to a 390 mAh lithium-ion battery and a corresponding power management chip.

[0069] (5) Perform hard-wired connection tests on the system to verify the pure hardware adaptive closed-loop processing capability.

[0070] Figure 2 and Figure 3 The diagrams show the bottom-level circuit topology of the front-end circuit module and the structural schematic of the multi-channel neuromorphic primitive circuit array of the present invention.

[0071] The structure of the low-power monolithically integrated adaptive electronic signal processing system of the present invention is described below. System structure: It includes front-end circuitry, a multi-channel neuromorphic primitive circuit array, back-end circuitry, and an external power supply support module. All active components of the system, except for the NPC array, use commercially available chips from Texas Instruments, and the PCB layout of the entire system strictly adheres to the IPC-2221 Class 3 manufacturing standard to ensure high reliability for both medical and industrial applications.

[0072] The specific circuit deployment is as follows: at the front-end signal acquisition end, an input buffer and a two-stage amplifier are provided (as shown in Figure 2). The first stage of weak signal amplification uses an INA849DGKR low-noise variable gain amplifier, and the second stage of precise signal conditioning uses a TLV9162IDSGR operational amplifier.

[0073] The 12-channel neuromorphic primitive circuit processing array (as shown in Figure 3) consists of 12 independent neuromorphic primitive circuits arranged in parallel. Each neuromorphic primitive circuit employs a synapse-neuron nested topology, specifically including: a ferroelectric floating-gate transistor 1, a capacitor 2, and a threshold-switching memristor 3. Regarding the connections between the components: the ferroelectric floating-gate transistor acts as an electronic synapse, connected in series with the threshold-switching memristor (specifically, the source of the ferroelectric floating-gate transistor is electrically connected to one end of the threshold-switching memristor); the capacitor is connected in parallel with the threshold-switching memristor, together forming the neuron's integration-discharge functional module. During operation, the input signal is applied to the gate of the ferroelectric floating-gate transistor, and the modulated current is injected into the parallel capacitor and threshold-switching memristor for charging and integration. When the threshold is reached, an action potential pulse is output from the other end of the threshold-switching memristor. The entire 12-channel processing array is packaged in a POD_LQFP64 package and mounted on a four-layer FR-4 PCB. The parasitic inductance is controlled to below 0.5 nH through through-hole stitching technology between layers.

[0074] The back-end drive circuit consists of a variable gain amplifier, a buffer stage based on the TLV9162IDSGR, a fourth-order low-pass filter with a cutoff frequency of 600 Hz, and a resistor divider network with a tolerance of 1% to clamp the output stably within ±2 V. The peripheral support modules include a TPS61093DSKT buck-boost converter (converting the 390mAh lithium battery voltage to a stable ±5 V dual power rail), a TPS7A20L12 power management module, and a right leg drive (RLD) circuit configured with the TLV9162IDSGR. During system operation, external environmental signals or electrodes are connected via a hardwired network. The RLD circuit inverts and amplifies the common-mode signal before feeding it back to the front end, completely suppressing power frequency interference in the 50 Hz and 60 Hz bands, providing the neuromorphic array with the highest fidelity pure signal input.

[0075] Figure 4 The diagram shows a comparison of the input and output signal waveforms before and after adaptive processing in the system of the present invention. The comparison reveals that the weak, non-stationary signal input at the front end, after undergoing... Figure 2 The front-end amplification and filtering shown Figure 3 After adaptive feature encoding, the neuromorphic array shown is successfully converted into a controlled pulse waveform with a pulse width of 100-1000 μs and a frequency that dynamically evolves with the input features at the output, and the highest level is safely clamped within ±2 V. This waveform response directly demonstrates the high efficiency and reliability of the monolithic integrated system of this invention in extracting weak signals and performing fully hardware adaptive conditioning under extremely low power consumption.

Claims

1. A low-power, monolithically integrated adaptive electronic signal processing system, characterized in that, include: The front-end signal acquisition module receives weak analog electrical signals from external input via a microelectrode array; A two-stage amplification and filtering module is connected to the output of the front-end signal acquisition module. It includes a cascaded first-stage low-noise variable gain amplifier and a second-stage multiple feedback bandpass filter, which are used to amplify the weak analog electrical signal with low noise and extract the target frequency band. The neuromorphic signal processing array is connected to the output of the two-stage amplification and filtering module. It integrates a multi-channel synapse-neuron nested primitive circuit to receive the extracted analog signal and dynamically adjust the weight based on the physical pulse time-dependent plasticity mechanism to encode the analog signal into a frequency-modulated pulse signal for output in real time. The back-end drive output module, connected to the output of the neuromorphic signal processing array, includes a cascaded variable gain amplifier, a buffer stage, a fourth-order low-pass filter, and a resistor divider clamping network; it is used to amplify and limit the power of the frequency-modulated pulse signal to drive an external physical actuator. The power management module, connected to the above modules, is used to provide system-level low-noise regulated power supply and perform dynamic power consumption optimization. The above modules achieve high-density monolithic integration through multilayer printed circuit boards.

2. The adaptive electronic signal processing system according to claim 1, characterized in that, The physical interface of the front-end signal acquisition module is adapted to a multi-channel microelectrode array: the microelectrode array contains 42 to 44 signal acquisition channels, the electrode contact diameter is no greater than 25 μm, and its interface working impedance matching range is 1-100 kΩ.

3. The adaptive electronic signal processing system according to claim 1, characterized in that, The specific circuit topology parameters of the two-stage amplification and filtering module are as follows: The first-stage low-noise variable gain amplifier adopts an ultra-low noise instrumentation amplifier circuit, with its voltage gain adjustable in hardware within the range of 1 to 500 times, input equivalent noise density not higher than 0.8 nV / √Hz, and single-stage common-mode rejection ratio ≥120 dB; The second-stage multiple feedback bandpass filter is used to filter out system baseline drift and high-frequency environmental noise, and its passband frequency is set from 0.33 Hz to 40 Hz; The two-stage amplification and filtering module is also connected in parallel with a right leg drive common-mode rejection feedback circuit, so that the actual common-mode rejection ratio of the entire front-end acquisition link reaches more than 80 dB.

4. The adaptive electronic signal processing system according to claim 1, characterized in that, The working mechanism of the neuromorphic signal processing array is as follows: The array contains 12 independent parallel processing channels; The synaptic device in each channel receives the time-varying voltage signal input from the front end, and its own conductance weight is dynamically and nonlinearly adjusted in the range of 0.1 nS to 100 nS. The frequency response range of the coded output frequency-modulated pulse signal is 1 Hz to 40 Hz, and the pulse firing frequency is highly linearly correlated with the envelope amplitude of the input signal.

5. The adaptive electronic signal processing system according to claim 1, characterized in that, The output characteristics of the backend driver output module are as follows: The input frequency-modulated pulse signal is shaped and amplified, and the output drive pulse width is adjustable from 100 μs to 1000 μs, while the output voltage amplitude is controlled from 0.1 V to 2.0 V.

6. The adaptive electronic signal processing system according to claim 1, characterized in that, It features ultra-low power consumption and low latency hardware integration. All active modules are integrated on a 4-layer high-density PCB board; Under stable operating conditions, the average power consumption of a single signal processing channel is less than 0.67 mW; From receiving the input signal from the front-end signal acquisition module to outputting the drive pulse from the back-end drive output module, the end-to-end delay of the entire pure hardware signal link is strictly less than 5 ms.

7. The adaptive electronic signal processing system according to claim 1, characterized in that, This involves interconnection and signal conditioning for monolithic integration of front-end analog circuits and neuromorphic processing arrays, specifically including: (1) Introduce a multiple feedback (MFB) topology at the front end for signal conditioning to optimize the signal-to-noise ratio of the input signal; (2) Common-mode noise suppression is achieved by configuring the right leg drive (RLD) circuit; specifically, the power frequency interference of 50 Hz and 60 Hz is significantly suppressed by inverting and amplifying the common-mode signal before feedback. (3) After the net signal is obtained by the front-end circuit, it is fed into the neuromorphic processing array in LQFP64 package through impedance-controlled low parasitic PCB traces. (4) The pulse signal output by the neuromorphic array is cascaded, filtered at 600 Hz and clamped at ±2 V to directly drive the external load.

8. The test method for the adaptive electronic signal processing system as described in claim 1, characterized in that, The specific steps are as follows: (1) Perform high-density physical packaging on the prepared monolithic integrated system; (2) Before testing, connect the external head-mounted electrodes directly to the signal acquisition system via hard wires to minimize uncontrollable signal distortion and ensure high fidelity and reliability of the input signal; (3) When the power management unit is turned on, the TPS61093DSKT converter stabilizes the battery voltage at ±5 V dual power rails, providing a stable and low-noise DC power bias for the front-end INA849DGKR and the subsequent operational amplifiers. (4) Input a weak timing test electrical signal and use an oscilloscope to monitor the net signal after being amplified by the front-end MFB topology, as well as the controlled drive waveform output by the back-end fourth-order low-pass filter.

Images