A high security active equalization system

Abstract

The application discloses a high-safety active balancing system, which comprises a battery pack, a DC / DC converter, a switch array and a master control unit; the switch array is connected between the DC / DC converter and each cell of the battery pack and is used for selecting the cell to be charged; the active balancing system further comprises a first hardware enabling switch, a second hardware enabling switch and a hardware timing protection device; the first hardware enabling switch is connected in series with a power supply circuit or a control circuit of the DC / DC converter; the second hardware enabling switch is connected in series with a control circuit of the switch array; the control ends of the first hardware enabling switch and the second hardware enabling switch are connected with the hardware timing protection device respectively; the hardware timing protection device is provided with a timing reset module; the hardware timing protection device is connected with the master control unit; and the hardware timing protection device controls the simultaneous opening and closing of the first hardware enabling switch and the second hardware enabling switch according to fault information to block the balancing action.

Description

Technical Field

[0001] This invention relates to the field of battery management technology, and more specifically, to a high-safety active balancing system. Background Technology

[0002] Active balancing technology is a key means to improve battery pack consistency, effectively extending battery pack lifespan and preventing safety issues such as overcharging and over-discharging caused by uneven cell voltage. There are many existing active balancing methods for batteries. One method involves isolating the total voltage drop of the battery pack and charging the low-voltage batteries, thus bringing them to the same charge level as the other batteries and achieving balance. This method requires only one isolated DC / DC converter and switch array, easily handling currents above 2A, making it advantageous in both performance and cost.

[0003] However, this solution also has a significant safety issue: a failure mode could result in continuous charging of one of the battery cells, eventually leading to excessively high cell voltage and a safety hazard. This problem may occur in the following situations:

[0004] 1. If the DC / DC control switch is damaged and the DC / DC module cannot be turned off in the software, it may cause overvoltage of the battery cell regardless of which cell is selected in the switch array.

[0005] 2. If the switch array or its selection circuit is damaged, all energy may be forced to be diverted to the undesired battery cell, resulting in overcharging of the battery cell.

[0006] 3. Software crash: In this state, the software is unable to switch or stop balancing, and energy continues to be transferred to the battery cells being charged, which may lead to a safety accident. Summary of the Invention

[0007] Therefore, this invention proposes a high-safety active balancing system, which aims to solve the safety problem of cell overcharging that may occur in the case of DC / DC malfunction, switch array failure or software crash in existing active balancing schemes.

[0008] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0009] A high-safety active balancing system includes a battery pack, a DC / DC converter, a switch array, and a main control MCU. The switch array is connected between the DC / DC converter and each cell of the battery pack for selecting the cell to be charged. The system also includes: a first hardware enable switch connected in series in the power supply circuit or control circuit of the DC / DC converter; a second hardware enable switch connected in series in the control circuit of the switch array; and a hardware timing protection device connected to the control terminals of the first and second hardware enable switches respectively. The hardware timing protection device has a timing reset module. The hardware timing protection device is connected to the main control MCU. Based on fault information, the hardware timing protection device controls the simultaneous opening and closing of the first and second hardware enable switches to block the balancing action.

[0010] Preferably, the fault information includes: when the main control MCU software fails, the hardware timing protection device does not receive the reset signal periodically sent by the main control MCU to the timing reset module, then the hardware timing protection device controls the output terminals of both the first hardware enable switch and the second hardware enable switch to be turned off; when the DC / DC converter fails, the main control MCU detects the DC / DC converter failure and sends an instruction to turn off all switches to the hardware timing protection device, then the hardware timing protection device controls the output terminals of both the first hardware enable switch and the second hardware enable switch to be turned off, blocking the equalization operation; when the switch array fails, the main control MCU detects the switch array failure and sends an instruction to turn off all switches to the hardware timing protection device, then the hardware timing protection device controls the output terminals of both the first hardware enable switch and the second hardware enable switch to be turned off, blocking the equalization operation.

[0011] Preferably, the hardware timing protection device reuses the equalization control circuit of the AFE chip. The AFE chip is equipped with an equalization timeout protection module and an equalization register. The AFE chip is connected to the control terminals of the first hardware enable switch and the second hardware enable switch. The main control MCU operates the equalization register at regular intervals. When the equalization timeout protection module senses that the main control MCU has not operated the equalization register for a set time, the AFE chip controls the first hardware enable switch and the second hardware enable switch to be turned off through the equalization control circuit.

[0012] Preferably, the voltage sampling channel of the AFE chip is connected to each cell, and the AFE chip automatically turns off the equalization output during voltage sampling to eliminate the impact of sampling line current voltage drop on sampling accuracy.

[0013] Preferably, the first hardware enable switch and the second hardware enable switch are relays, MOSFETs, or optocouplers.

[0014] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0015] 1. Dual hardware redundancy: By setting independent hardware enable switches for DC / DC and switch array respectively, the other path can still cut off the equalization when one component fails, avoiding a single fault from causing a safety accident;

[0016] 2. Independent hardware watchdog: The enable switch is controlled by a hardware timer protection device independent of the MCU. Even if the software crashes, the equalizer will be automatically turned off after a timeout, which solves the safety problem caused by software failure.

[0017] 3. AFE function multiplexing: Creatively utilizes the balanced timeout function built into the AFE chip as a hardware timing device, without adding extra hardware costs. Moreover, AFE register operations require specific interfaces and timings, making it difficult for abnormal software to operate erroneously, resulting in high reliability.

[0018] 4. Sampling interference elimination: When reusing the AFE equalization control circuit, the characteristic of shutting down equalization during AFE sampling is automatically obtained, which solves the problem of inaccurate voltage detection caused by the voltage drop of the sampling line during high current equalization, and realizes that "equalization-sampling" do not interfere with each other. Attached Figure Description

[0019] Figure 1 This is a circuit block diagram of Embodiment 1 of the present invention; Figure 2 This is a flowchart of the control method of the present invention; Figure 3 The specific circuit diagram for the multiplexing of the AFE equalization timeout function. Detailed Implementation

[0020] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0021] See Figure 1 As shown, the high-safety active balancing system in this embodiment includes a battery pack (composed of cells Cell1~Celln connected in series) 1, a DC / DC converter 2, a switch array 3, a main control MCU 4, and a hardware timing protection device. The switch array 3 is connected between the DC / DC converter 2 and each cell of the battery pack 1 to select the cell to be charged. In this embodiment, the switch array adopts a relay matrix or a MOSFET switch array, and its specific structure is a conventional design in the art, which will not be described in detail here.

[0022] This embodiment adds a first hardware enable switch K1 and a second hardware enable switch K2. The first hardware enable switch K1 is connected in series in the input power supply circuit of the DC / DC converter 2, and the second hardware enable switch K2 is connected in series in the control circuit of the switch array 3. The control terminals of the first hardware enable switch K1 and the second hardware enable switch K2 are connected to the equalization control output terminal (EQ_OUT) of the AFE chip 5.

[0023] The hardware timing protection device reuses the equalization control circuit of AFE chip 5. AFE chip 5 is selected from models with equalization timeout protection, such as TI's BQ769xx series or Maxim Integrated's MAX178xx series. This type of AFE chip 5 has a built-in timer. When the main control MCU4 fails to operate the equalization register through the I2C / SPI interface of AFE chip 5 for a set time (e.g., 30 seconds), AFE chip 5 automatically disconnects the first hardware enable switch K1 and the second hardware enable switch K2, turning off the equalization output.

[0024] The working principle of this invention is as follows:

[0025] During normal operation, the main control MCU4 refreshes the equalization register of the AFE chip 5 periodically (e.g., every 10 seconds) via the I2C interface. The EQ_OUT pin of the AFE chip 5 remains high, keeping the first hardware enable switch K1 and the second hardware enable switch K2 on. When the system detects that the voltage of a certain battery cell is too low and needs equalization, the main control MCU4 controls the switch array 3 to select that battery cell and starts the DC / DC converter 2 for energy transfer.

[0026] The system will automatically enter safety protection mode when the following faults occur:

[0027] (1) When the main control MCU software fails, the hardware timing protection device does not receive the reset signal sent periodically by the main control MCU to the timing reset module. In this case, the hardware timing protection device controls the output terminals of the first hardware enable switch K1 and the second hardware enable switch K2 to be closed, and the equalization action is stopped.

[0028] (2) When the DC / DC converter fails, the main control MCU detects the DC / DC converter failure and sends an instruction to shut down all switches to the hardware timing protection device. The hardware timing protection device then controls the outputs of both the first hardware enable switch K1 and the second hardware enable switch K2 to close, blocking the equalization operation. The simultaneous closure of both hardware enable switches is necessary to prevent the failure of the DC / DC converter from affecting the first hardware enable switch K1 and thus preventing the equalization operation from being blocked. Therefore, by closing both hardware enable switches simultaneously, even if one fails and cannot be shut down, the circuit can be broken through the second switch.

[0029] (3) When the switch array fails, the main control MCU detects the switch array failure and sends an instruction to close all switches to the hardware timing protection device. The hardware timing protection device then controls the output terminals of the first hardware enable switch K1 and the second hardware enable switch K2 to be closed, blocking the equalization action. The principle of simultaneously closing the two hardware enable switches is as described above.

[0030] Furthermore, the voltage sampling channel of AFE chip 5 is connected to each battery cell. During voltage sampling, AFE chip 5 automatically shuts down the equalization output to eliminate the impact of sampling line current voltage drop on sampling accuracy. AFE chip 5 has internal sampling control logic that automatically shuts down the equalization output (EQ_OUT set low) before starting voltage sampling, and restores the equalization output after sampling is complete and stable. Utilizing this characteristic, this embodiment can achieve time-division multiplexing of "equalization-sampling" during the equalization process: When AFE chip 5 needs to collect battery cell voltage, it automatically briefly shuts down EQ_OUT → the first hardware enable switch K1 and the second hardware enable switch K2 are opened → the equalization current drops to zero → there is no voltage drop on the sampling line → AFE chip 5 collects accurate voltage → after sampling is completed, EQ_OUT is restored → equalization continues. The entire process is automatically completed by AFE chip 5 without intervention from the main control MCU4, ensuring sampling accuracy and simplifying software design. For the specific circuit of the equalization timeout function multiplexing of AFE chip 5, please refer to [link to circuit details]. Figure 3 .

[0031] Combination Figure 2 As shown, this invention also proposes a highly secure active equalization control method based on the above system, comprising the following steps:

[0032] Step S1: The system is powered on and initialized. The main control MCU4 is configured to set the equalization timeout time of the AFE chip 5 to T (T is 20~60 seconds).

[0033] Step S2: The main control MCU4 periodically (period less than T) writes the equalization register to the AFE chip 5, refreshes the timeout timer, and maintains the enabled output;

[0034] Step S3: When equalization is required, the main control MCU4 controls the switch array 3 to select the target cell and starts the DC / DC converter 2;

[0035] Step S4: AFE chip 5 automatically turns off the equalization output at the voltage sampling time and automatically turns it off after the sampling is completed;

[0036] Step S51: When the main control MCU4 software crashes, the main control MCU4 cannot refresh the equalization register within time T. The AFE chip 5 automatically cuts off the output of the first hardware enable switch K1 and the second hardware enable switch K2, and equalization stops.

[0037] Step S52: When the DC / DC converter or the switch array fails, the main control MCU detects the DC / DC converter failure and sends an instruction to shut down all switches to the hardware timing protection device. The hardware timing protection device then controls the output terminals of the first hardware enable switch K1 and the second hardware enable switch K2 to be turned off, thus blocking the equalization action.

[0038] Step S53: When the switch array fails, the main control MCU detects the switch array failure and sends an instruction to turn off all switches to the hardware timing protection device. The hardware timing protection device then controls the output terminals of the first hardware enable switch K1 and the second hardware enable switch K2 to be turned off, blocking the equalization action.

[0039] The embodiments described above are for illustrative purposes only and are not intended to limit the scope of the invention. All equivalent changes and modifications made to the invention by those skilled in the art should fall within the scope of the appended claims.

Claims

1. A high-safety active balancing system, comprising a battery pack, a DC / DC converter, a switch array, and a main control MCU; the switch array is connected between the DC / DC converter and each cell of the battery pack, for selecting the cell to be charged, characterized in that, Also includes: The first hardware enable switch is connected in series in the power supply circuit or control circuit of the DC / DC converter; A second hardware enable switch is connected in series in the control loop of the switch array; A hardware timing protection device is connected to the control terminals of the first hardware enable switch and the second hardware enable switch, respectively; the hardware timing protection device has a timing reset module; the hardware timing protection device is connected to the main control MCU; The hardware timing protection device controls the simultaneous opening and closing of the first hardware enable switch and the second hardware enable switch based on the fault information to block the balancing action.

2. The high-security active balancing system according to claim 1, characterized in that, The fault information includes: When the main control MCU software fails, if the hardware timing protection device does not receive the reset signal periodically sent by the main control MCU to the timing reset module, the hardware timing protection device controls the output terminals of both the first hardware enable switch and the second hardware enable switch to be turned off. When the DC / DC converter fails, the main control MCU detects the DC / DC converter failure and sends an instruction to shut down all switches to the hardware timing protection device. Then, the hardware timing protection device controls the output terminals of the first hardware enable switch and the second hardware enable switch to be turned off to block the equalization action. When the switch array fails, the main control MCU detects the switch array failure and sends an instruction to shut down all switches to the hardware timing protection device. The hardware timing protection device then controls the output terminals of the first hardware enable switch and the second hardware enable switch to be turned off, thus blocking the equalization action.

3. The high-security active balancing system according to claim 2, characterized in that, The hardware timing protection device reuses the equalization control circuit of the AFE chip. The AFE chip is equipped with an equalization timeout protection module and an equalization register. The AFE chip is connected to the control terminals of the first hardware enable switch and the second hardware enable switch. The main control MCU operates the equalization register at regular intervals; when the equalization timeout protection module senses that the main control MCU has not operated the equalization register for a set time, the AFE chip controls the first hardware enable switch and the second hardware enable switch to be turned off through the equalization control circuit.

4. The high-security active balancing system according to claim 3, characterized in that, The voltage sampling channel of the AFE chip is connected to each of the battery cells. During voltage sampling, the AFE chip automatically turns off the equalization output to eliminate the impact of sampling line current voltage drop on sampling accuracy.

5. The high-security active balancing system according to claim 1, characterized in that, The first hardware enable switch and the second hardware enable switch are relays, MOSFETs, or optocouplers.

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