A storage access method, system, device and storage medium

Abstract

The application discloses a storage access method, system, device and storage medium, wherein the method comprises the following steps: identifying the current execution state of each hardware in the physical flash memory, and constructing a state view of the full-amount hardware state of the physical flash memory based on all the current execution states; performing striping combination processing on each hardware based on the state view, generating a plurality of redundant array of independent disks (RAID) strips, and establishing a mapping relationship between the RAID strips and corresponding logical block addresses; responding to and analyzing a storage access request from the outside world, locating the corresponding target hardware based on the logical block address and the mapping relationship obtained through the analysis; determining the real-time state of the target hardware based on the state view; if the first condition is met, performing degradation read scheduling processing; and if the second condition is met, performing operation unit parallel read-write scheduling processing. The method disclosed by the application reduces the time delay in the storage access process.

Description

Technical Field

[0001] This invention relates to the field of computer storage technology, and in particular to a storage access method, system, device and storage medium. Background Technology

[0002] In the field of storage technology, NAND flash memory (non-volatile semiconductor memory) is widely used due to its high storage density and fast read / write speeds. However, there are significant time differences between its read, write, and erase operations, with read operations taking approximately 100 seconds. A write operation takes about 1ms, while an erase operation takes up to 10ms, and only one operation can be performed on a single physical medium at any given time.

[0003] Traditional flash memory access uses a sequential execution mechanism. When three types of operations occur concurrently, read requests must wait for write and erase operations to complete, which can easily lead to a surge in read latency. In particular, erase operations can increase read latency by a hundredfold. At the same time, write operations rely on erase operations and can occupy flash memory parallel operation unit resources for a long time, resulting in a write blocking effect.

[0004] To alleviate the above problems, existing technologies mainly adopt either a tiered suspension operation or a solution of writing data to memory temporarily and then batch flushing it. The former allows read operations to interrupt write operations within the same parallel operation unit, which can reduce read latency to some extent, but after the write operation is interrupted, the context needs to be saved and re-verified upon resumption, resulting in a high interruption cost. The latter temporarily stores the write data in memory and then writes it to flash memory in batches, which reduces the number of write operations, but is limited by memory capacity, so the number of cached requests is limited, and only delayed aggregation refresh can be achieved. The fixed amount of data flushed in batches will still cause read-write conflicts, and cannot fundamentally solve the latency fluctuation problem of flash memory access, making it difficult to meet the core requirements of upper-layer services for low-latency and predictable storage access. Summary of the Invention

[0005] This invention provides a storage access method, system, device, and storage medium to solve the technical problem of how to improve existing storage access methods and achieve the effect of reducing storage access latency.

[0006] To address the aforementioned technical problems, the present invention provides a storage access method, comprising: Identify the current execution state of each hardware component in the physical flash memory, and construct a state view of the full hardware state of the physical flash memory based on all current execution states; Based on the state view, each piece of hardware is striped together to generate several independent redundant disk array stripes, and a mapping relationship between the independent redundant disk array stripes and the corresponding logical block addresses is established. Respond to and parse external storage access requests, locate the corresponding independent disk redundant array stripe based on the parsed logical block address and the mapping relationship, and locate the target hardware corresponding to the storage access request based on the independent disk redundant array stripe; Based on the state view, the real-time state of the target hardware is determined; If the real-time status meets the first condition, then the data to be accessed corresponding to the target hardware is read from other conflict-free stripes in the same independent disk redundant array group as the target hardware; If the real-time state meets the second condition, the storage access request will be scheduled to be executed in parallel on a non-conflicting stripe corresponding to another idle operation unit in the physical flash memory.

[0007] As one preferred embodiment, identifying the current execution state of each hardware component in the physical flash memory and constructing a state view of the full hardware state of the physical flash memory based on all current execution states includes: Based on the open channel mechanism, the hardware in the physical flash memory is mapped to the server side, and the read, write and erase execution status of each hardware is collected in real time to obtain the current execution status of each hardware and the physical association between each hardware. The current execution state and the physical association are integrated to generate a state view of the entire physical flash memory hardware.

[0008] As a preferred embodiment, the step of performing striping combination processing on each of the hardware components based on the state view to generate several independent redundant disk array stripes, and establishing a mapping relationship between the independent redundant disk array stripes and their corresponding logical block addresses, includes: Based on the state view, striping combination processing is performed on each of the hardware components to form several independent disk redundant array stripes; wherein, each independent disk redundant array stripe is composed of contiguous storage blocks in physical flash memory, and each stripe corresponds to an independent hardware region of physical flash memory. Logical block addresses are sequentially arranged into consecutive storage blocks corresponding to each independent disk redundant array stripe, so that each independent disk redundant array stripe is associated with a unique logical block address, thus establishing a one-to-one mapping relationship between the independent disk redundant array stripe and the logical block address.

[0009] As one preferred embodiment, the step of locating the corresponding independent redundant disk array stripe based on the parsed logical block address and the mapping relationship, and locating the target hardware corresponding to the storage access request based on the independent redundant disk array stripe, includes: The storage access request is subjected to encapsulation information stripping and data parsing to extract the logical block address from the storage access request; Based on the mapping relationship, the independent disk redundant array stripe corresponding to the logical block address is located in the forward direction; Based on the association between the independent disk redundant array stripe and the physical flash memory hardware, the target hardware corresponding to the storage access request is located in reverse. The target hardware includes at least the independent disk redundant array stripe and the parallel operation unit to which the stripe belongs.

[0010] As one preferred embodiment, determining the real-time state of the target hardware based on the state view further includes: If the real-time status is a conflict-free idle state, the read and write operations corresponding to the storage access request are directly executed on the target hardware, and the current execution status of the corresponding hardware in the status view is updated in real time after the operation is completed.

[0011] As one preferred embodiment, the first condition includes the target hardware being in an erase operation conflict state; Determining the real-time state of the target hardware based on the state view further includes: If the real-time state is an erase operation conflict state, the direct read operation on the target hardware will be converted into a stripe-level data read operation; The stripe-level data reading operation includes: reading the stripe data corresponding to other normal hardware in the independent disk redundant array stripe to which the target hardware belongs, excluding the hardware to be erased, and performing parallel reading of the stripe data of each normal hardware to obtain the first stripe data; Based on the first stripe data, the logical block address data corresponding to the target hardware is recovered, and the degraded read scheduling result of the stripe-level data read operation is generated.

[0012] As one preferred embodiment, the second condition includes the target hardware being in a write operation conflict state; Determining the real-time state of the target hardware based on the state view further includes: If the real-time state is a write operation conflict state, then based on the state view, identify the idle parallel operation units in the physical flash memory other than the parallel operation unit to which the target hardware belongs; The read operation in the storage access request is scheduled to be executed in the conflict-free stripe corresponding to the idle parallel operation unit; The read / write conflict ratio is determined based on the read / write speed characteristics of the physical flash memory, and the write operation of the parallel operation unit to which the target hardware belongs and the read operation of the idle parallel operation unit are controlled to be carried out synchronously and in parallel according to the read / write conflict ratio, so as to generate the parallel scheduling result of read / write requests.

[0013] Another aspect of the present invention provides a storage access system, comprising: The identification module is used to identify the current execution state of each hardware component in the physical flash memory, and to construct a state view of the full hardware state of the physical flash memory based on all current execution states. The construction module is used to perform striping combination processing on each of the hardware based on the state view, generate several independent disk redundant array stripes, and establish a mapping relationship between the independent disk redundant array stripes and the corresponding logical block addresses. The parsing module is used to respond to and parse external storage access requests, locate the corresponding independent disk redundant array stripe based on the parsed logical block address and the mapping relationship, and locate the target hardware corresponding to the storage access request based on the independent disk redundant array stripe. The detection module is used to determine the real-time status of the target hardware based on the status view. The first access module is used to read the data to be accessed corresponding to the target hardware from other non-conflicting stripes in the same independent disk redundant array group as the target hardware if the real-time status meets the first condition. The second access module is used to schedule the storage access request to be executed in parallel on the non-conflicting stripe corresponding to other idle operation units in the physical flash memory if the real-time state meets the second condition.

[0014] Another embodiment of the present invention provides a storage access device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the storage access method as described above.

[0015] In another embodiment of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, wherein when the device containing the computer-readable storage medium executes the computer program, the storage access method described above is implemented.

[0016] Compared with the prior art, the beneficial effects of the present invention are at least one of the following: 1) This invention constructs a state view of the full hardware status of physical flash memory, and based on the view, completes the mapping construction of hardware striping combination with independent disk redundant array stripes and logical block addresses, enabling upper-layer services to accurately perceive the read, write, and erase execution status of the underlying hardware. At the same time, it realizes the accurate positioning of logical block addresses to physical target hardware, and opens up the association link between physical flash memory hardware and upper-layer access requests from the bottom layer.

[0017] For the target hardware of storage access requests, this invention completes real-time status detection through a status view and executes differentiated access processing strategies according to different statuses. This effectively avoids the resource contention problem caused by the serial execution of read, write, and erase operations in traditional storage access. It not only solves the problem of latency surge caused by read requests waiting for erase and write operations, but also improves the overall utilization of hardware resources through the parallel scheduling of idle operation units. This frees the read latency of disk access from the passive dependence on the underlying hardware operations, and realizes the controllability and predictability of read latency.

[0018] 2) This invention relies on the striping design and redundancy check capability of the independent disk redundant array. For erase operation conflicts, it executes the data reading strategy of the same group of conflict-free stripes, which ensures the continuity and integrity of data access. At the same time, based on the parallel characteristics of the physical flash memory operation unit, for write operation conflicts, the access request is scheduled to the conflict-free stripe of other idle operation units for execution, realizing the parallel development of read and write operations and breaking the operation serial limitation within a single operation unit. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of a storage access method in one embodiment of the present invention; Figure 2 This is a structural block diagram of a storage access system in one embodiment of the present invention; Figure 3 This is a structural block diagram of a storage access device in one embodiment of the present invention; Figure label: Among them, 11 is the identification module; 12 is the construction module; 13 is the parsing module; 14 is the detection module; 15 is the first access module; 16 is the second access module; 21 is the processor; and 22 is the memory. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0022] In the description of this invention, it should be noted that, unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the invention. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] One embodiment of the present invention provides a storage access method; for details, please refer to [link to specific documentation]. Figure 1 , Figure 1 The diagram shown is a schematic flowchart of a storage access method according to one embodiment of the present invention, which includes steps S1-S6: S1: Identify the current execution state of each piece of hardware in the physical flash memory, and build a state view of the full hardware state of the physical flash memory based on all current execution states.

[0024] This embodiment addresses the issues of read / write / erase operation conflicts and uncontrollable read latency caused by the lack of transparency in the underlying hardware state during physical flash memory access. It provides a method for constructing a full hardware state view of physical flash memory. By using an open channel mechanism, it achieves direct mapping between physical flash memory hardware and the server side, completing the full collection and integration of hardware execution states. This lays the foundation for accurate scheduling of subsequent storage access requests and effective avoidance of operation conflicts.

[0025] This embodiment focuses on NAND flash memory, a non-volatile storage medium and the core storage carrier for storage devices such as solid-state drives and distributed storage nodes. NAND flash memory operations exhibit significant time differences, with read operations having a latency of approximately 100ms. The write operation has a latency of about 1ms, and the erase operation has a latency of about 10ms. Moreover, only one operation can be performed on a single physical medium at any given time. In traditional storage access schemes, the execution status of the underlying hardware cannot be perceived in real time, which can easily lead to read requests waiting for write and erase operations to complete, causing a surge in read latency. However, this embodiment constructs a state view of the full hardware status, allowing the server to accurately grasp the hardware operating status of the NAND flash memory, thus solving the technical pain point of opaque hardware status from the bottom layer.

[0026] In this embodiment, a state view of the full hardware state of the physical flash memory is constructed. First, the hardware in the physical flash memory is mapped to the server side based on the OpenChannel mechanism. It should be noted that the OpenChannel mechanism is a hardware virtualization mapping technology for NAND flash memory. Its core is to break the traditional black-box design of flash memory, directly expose and map the actual hardware structure of the physical flash memory to the server side, so that the server software can directly perceive and manage the underlying hardware of the physical flash memory.

[0027] In this embodiment, the physical flash memory hardware includes at least Plane and Block. Plane is an independent parallel operation unit inside the NAND flash memory. Each Plane consists of multiple Blocks and is equipped with independent control circuits, including page cache, data path and control logic. Different Planes can perform read and write operations simultaneously. Block is the core unit of storage management of NAND flash memory and also the smallest unit of data erasure operation. This invention does not limit the specific number of Plane and Block, and can be flexibly set according to the actual hardware specifications of NAND flash memory.

[0028] After the mapping is completed based on the open channel mechanism, the server collects the read, write, and erase execution status of all mapped Plane and Block hardware in real time. The read, write, and erase execution status includes idle status, read operation execution status, write operation execution status, and erase operation execution status. At the same time, the physical relationship between each hardware is collected, that is, the Plane information to which each Block belongs, the hardware layout information of each Plane in the physical flash memory, etc., to ensure that the server can grasp the overall status and physical relationship of the physical flash memory hardware.

[0029] After acquiring the read, write, and erase execution states of each hardware component in the physical flash memory and obtaining the physical relationships between hardware components, the current execution states and the physical relationships between hardware components are integrated to generate a state view of all hardware components in the physical flash memory. Preferably, during the integration process, the server stores the identification information of each hardware component, its corresponding read, write, and erase execution states, and its physical relationships in a structured manner. The hardware identification information is a unique hardware number for each Plane and Block. The structured storage format can be a table, a linked list, etc., and this invention does not limit this to any particular format, as long as it can achieve the corresponding storage of hardware states and physical relationships.

[0030] It should be noted that the state view generated in this embodiment is a full hardware state view, covering all Plane and Block hardware of the physical flash memory, without any hardware state omissions. Moreover, the hardware execution state in the state view is a dynamic state collected in real time, which can be updated in real time as the physical flash memory hardware is operated, ensuring that the hardware state obtained by the server is consistent with the actual operating state of the physical flash memory.

[0031] In this embodiment, the real-time acquisition of the read, write, and erase execution status of each hardware component of the physical flash memory adopts a combination of hardware status polling and interrupt notification. Specifically, the server polls the status of the mapped Plane and Block hardware at preset time intervals. The preset time interval can be flexibly set according to the real-time requirements of actual storage access, for example, it can be set to 10. This ensures timely capture of hardware state changes. Simultaneously, when the physical flash memory's hardware execution state changes, such as switching from idle to write operation execution state or from erase operation execution state to idle state, the hardware control circuit will proactively send an interrupt notification to the server. Upon receiving the interrupt notification, the server will immediately update the corresponding hardware state. By combining polling and interrupts, the real-time nature of state acquisition is guaranteed while reducing server resource consumption, balancing the efficiency and reliability of state acquisition.

[0032] S2: Based on the state view, perform striping combination processing on each hardware component to generate several independent redundant disk array stripes, and establish a mapping relationship between the independent redundant disk array stripes and the corresponding logical block addresses.

[0033] This embodiment addresses the problems of inaccurate mapping between physical hardware and logical addresses and insufficient exploitation of hardware resource parallelism during NAND flash memory storage access, which lead to operational conflicts and low access efficiency. It provides a striping combination and address mapping method based on a full hardware state view. By performing software-level striping processing on the physical flash memory hardware and combining it with the ordered arrangement of logical block addresses to achieve one-to-one mapping, it lays the hardware-logic association foundation for accurate location of subsequent storage access requests and stripe-level conflict scheduling.

[0034] In this embodiment, striping and combining processing is performed on each hardware component based on the state view to form several independent redundant array of disks (RAID) stripes. It should be noted that striping and combining processing refers to the logical partitioning and combination of physical flash memory hardware through server-side software programs. This differs from hardware-level striping design and offers greater flexibility, allowing for dynamic adjustments based on real-time hardware status. This invention does not limit the specific programming language of the software program; any programming language capable of implementing hardware logical combinations, such as C or C++, can be used.

[0035] In this embodiment, the hardware core of the physical flash memory is a Block and a Plane. A Block is the smallest unit of data erasure and also the smallest physical granularity for striping. Each independent Redundancy Disk Array (RDA) stripe is composed of consecutive Blocks in the physical flash memory, and each stripe corresponds to an independent hardware region of the physical flash memory. That is, the Blocks belonging to different stripes do not physically overlap. Preferably, each stripe corresponds to a different Plane in the physical flash memory. Utilizing the independent parallel operation characteristics of the Plane, hardware support is provided for subsequent stripe-level parallel access and conflict scheduling. Furthermore, during the striping process, hardware in a conflict-driven execution state is avoided based on the state view in step S1. Blocks in a conflict-free, idle state are preferentially selected for combination, ensuring that the generated independent RDA stripes have a directly accessible hardware foundation. This invention does not limit the number of Blocks contained in each stripe; it can be flexibly set according to the actual storage system's IO access requirements and the hardware specifications of the physical flash memory. For example, each stripe may contain 16 or 32 consecutive Blocks.

[0036] After completing the software-level striping of independent disk redundant array stripes, logical block addresses are sequentially arranged into contiguous storage blocks corresponding to each independent disk redundant array stripe. This ensures that each independent disk redundant array stripe is associated with a unique logical block address, establishing a one-to-one mapping relationship between independent disk redundant array stripes and logical block addresses. It should be noted that the logical block address (LBA) is the basic descriptive unit for upper-layer services to access data areas. Its corresponding data area size is 4K or 512B, and it is the core address identifier for upper-layer services to initiate storage access requests. In this embodiment, the arrangement of logical block addresses follows a sequential arrangement principle, that is, logical block addresses are bound sequentially to the combined independent disk redundant array stripes according to their numbers from smallest to largest. This ensures that upper-layer services can access contiguous hardware areas in the physical flash memory through consecutive logical block addresses, improving the continuity of data read and write operations.

[0037] When establishing the mapping relationship, the unique identification information of the independent disk redundant array stripe and the corresponding logical block address are stored in a structured manner. The storage format can be key-value pairs, mapping tables, etc. This invention does not limit the format, as long as it can achieve accurate association between stripe and logical block address and facilitate subsequent fast query. For example, an address mapping table can be constructed with the stripe number as the key and the corresponding logical block address as the value and stored in the server-side memory for direct retrieval during subsequent access requests.

[0038] Preferably, after establishing a one-to-one mapping relationship between independent disk redundant array stripes and logical block addresses, the mapping relationship is validated to ensure that each logical block address corresponds to only one independent disk redundant array stripe, and each stripe has a unique logical block address bound to it, with no duplicate mappings or empty mappings.

[0039] Specifically, the validity check includes address uniqueness verification and stripe integrity verification. Address uniqueness verification is used to detect whether multiple stripes are bound to the same logical block address. Stripe integrity verification is used to detect whether there are empty stripes without bound logical block addresses. If an invalid mapping is detected, the server will immediately re-execute the logical block address arrangement and mapping operation until all mapping relationships are valid. It should be noted that the mapping relationship in this embodiment is a fixed mapping relationship. The mapping relationship will not change unless the physical flash memory hardware is re-striped, ensuring the stability of the location of upper-layer business storage access requests. If subsequent changes in hardware status or adjustments to storage requirements require re-striping, the method in this embodiment can be used to regenerate stripes and establish mapping relationships.

[0040] S3: Responds to and parses external storage access requests, locates the corresponding independent disk redundant array stripe based on the parsed logical block address and mapping relationship, and locates the target hardware corresponding to the storage access request based on the independent disk redundant array stripe.

[0041] This embodiment addresses the problems of low access efficiency and inaccurate request scheduling caused by inaccurate parsing of external storage access requests and unclear physical hardware location links during NAND flash memory storage access. It provides a method for achieving accurate request parsing and hardware location. By extracting the core address identifier through hierarchical parsing of access requests and combining it with a pre-established mapping relationship, it completes the hierarchical location from logical address to RAID stripe and then to physical target hardware. This provides accurate operation objects for subsequent hardware status detection and conflict scheduling, solving the technical pain point of the disconnect between logical address and physical hardware location and the easy occurrence of access errors in traditional solutions.

[0042] In this embodiment, the system first responds to external storage access requests and then performs encapsulation information stripping and data parsing on the storage access requests to extract the logical block addresses from the requests. It should be noted that external storage access requests are initiated by upper-layer services and include types such as read and write requests. During transmission, these requests carry various encapsulation information, including non-core data such as transport protocol headers, verification information, and request identifiers. In this embodiment, the stripping of encapsulation information removes these non-core data, retaining only the core data segments related to data access, ensuring efficient subsequent parsing. The logical block address (LBA) is the basic descriptive unit of a data region for upper-layer services, corresponding to a data region size of 4K or 512B. It is the core address identifier for data interaction between upper-layer services and the underlying physical flash memory hardware. This invention does not limit the transport protocol of the storage access request; any access protocol suitable for NAND flash memory storage devices, such as SCSI or NVMe, can be used. The encapsulation information stripping method under different protocols can be adaptively adjusted, as long as the logical block address in the request can be accurately extracted.

[0043] After extracting the logical block address from the storage access request, the independent disk redundant array stripe corresponding to the logical block address is located forward based on the mapping relationship between the independent disk redundant array stripe and the logical block address established in step S2.

[0044] Preferably, the mapping relationship established in step S2 is stored on the server side in the form of a structured mapping table. This mapping table records the correspondence between each logical block address and a unique RAID stripe. The forward positioning process involves querying the key-value pair of the mapping table, using the extracted logical block address as the query key, to quickly match the unique identifier of the RAID stripe bound to that address, thereby determining the corresponding independent disk redundant array stripe. It should be noted that forward positioning is the positioning process from the logical address layer to the stripe layer. Relying on the pre-established one-to-one mapping relationship, the positioning operation can be executed without blocking and quickly. The positioning latency can be controlled at the microsecond level, which will not affect the overall processing efficiency of storage access requests. Furthermore, this invention does not limit the query method of the mapping table; sequential query, hash query, etc., can be used. Hash query, due to its higher query efficiency, can be used as the preferred method in this embodiment.

[0045] After obtaining the corresponding independent redundant disk array stripe through forward positioning, the target hardware corresponding to the storage access request is obtained through reverse positioning based on the association between the independent redundant disk array stripe and the physical flash memory hardware. The target hardware includes at least the independent redundant disk array stripe and the parallel operation unit to which the stripe belongs. It should be noted that the association between the RAID stripe and the physical flash memory hardware is established synchronously during the striping combination process in step S2, recording which consecutive blocks in the physical flash memory constitute each RAID stripe and the Plane information to which the stripe belongs. The parallel operation unit is the Plane inside the NAND flash memory. This Plane is an independent parallel operation unit, composed of multiple blocks and equipped with independent control circuitry. In this embodiment, the reverse positioning is a positioning process from the stripe layer to the physical hardware layer. That is, through the hardware association information of the located RAID stripe, the physical block set and the Plane to which the stripe belongs are determined. The final target hardware is a complete physical access unit, which includes both the data storage block set and the operation control unit Plane to which it belongs, ensuring that the subsequent status detection and operation scheduling of the target hardware can cover the entire dimension of storage and operation.

[0046] In this embodiment, after locating the target hardware, the location result can be validated to ensure that the located target hardware is an actual hardware region existing in the physical flash memory, and that the mapping relationship between the hardware and the logical block address has not failed. Specifically, the validation includes hardware existence validation and mapping validation. Hardware existence validation is used to detect whether the located Block or Plane is a valid hardware unit of the physical flash memory. Mapping validation is used to detect whether the mapping relationship between the current logical block address and the RAID stripe is consistent with the mapping relationship established in step S2. If the validation result is invalid, the request parsing and location operation is re-executed; if the validation result is valid, the location result is used as the basis for subsequent processing and called by the target hardware real-time status detection in step S4. It should be noted that the validation is an optional optimization step, which can be selected whether to execute according to the access accuracy requirements of the actual storage system. This invention does not impose a mandatory limitation on this step.

[0047] S4: Determine the real-time status of the target hardware based on the status view.

[0048] This embodiment addresses the problem of surged read latency and low resource utilization caused by physical hardware operation conflicts during NAND flash memory storage access. It provides a differentiated storage access processing method based on the real-time state of the target hardware. By accurately determining the state of the target hardware, three processing strategies are executed: direct access, degraded read, and parallel scheduling. This solves the technical pain point of serial execution of read, write, and erase operations in traditional storage access schemes, and achieves predictable read latency and maximized hardware resource utilization.

[0049] Traditional NAND flash memory access schemes employ a uniform sequential execution mechanism without differentiating the real-time hardware state. Read requests must passively wait for write and erase operations to complete, which can easily lead to a hundredfold increase in read latency. Furthermore, the serial operation limitations within a single plane prevent the full exploitation of hardware parallel capabilities. In contrast, this embodiment, based on the full hardware state view constructed in step S1, performs targeted processing on the three states of the target hardware: conflict-free idle, erase operation conflict, and write operation conflict. This ensures fast access in conflict-free scenarios while avoiding read request blocking in conflict scenarios through degraded reads and parallel scheduling, allowing the storage access processing strategy to be deeply adapted to the actual hardware state.

[0050] In this embodiment, the real-time state of the target hardware is determined based on the state view. When the real-time state is a conflict-free idle state, the read and write operations corresponding to the storage access request are directly executed on the target hardware. After the operation is completed, the current execution state of the corresponding hardware in the state view is updated in real time. It should be noted that the conflict-free idle state refers to the hardware state in which the target hardware has not performed any read, write, or erase operations and there are no pending operations in the queue. The target hardware in this state can directly respond to the storage access request without any scheduling processing, which is the optimal scenario for storage access.

[0051] In this embodiment, the process of determining the real-time status of the target hardware based on the status view is a process of directly querying the status information of the corresponding identifier of the target hardware in the status view. The query result is kept synchronized with the actual status of the physical flash memory hardware in real time to ensure the accuracy of the status determination. After directly executing a read or write operation, the status of the hardware in the status view will be updated immediately. If it is a short-term read or write operation, the status will be updated to the corresponding operation execution status. After the operation is completed, it will be restored to the conflict-free idle state immediately to ensure the dynamic effectiveness of the status view. This invention does not limit the triggering method of status update. It can adopt the method of active reporting after the operation is completed or timed polling update, as long as the real-time update is guaranteed.

[0052] S5: If the real-time status meets the first condition, then read the data to be accessed corresponding to the target hardware from other conflict-free stripes in the same independent disk redundant array group as the target hardware.

[0053] In this embodiment, if step S4 determines that the real-time state of the target hardware meets the first condition, then step S5 is executed. The first condition is that the target hardware is in an erase operation conflict state. At this time, the direct read operation on the target hardware is converted into a stripe-level data read operation, and the data to be accessed corresponding to the target hardware is read from other conflict-free stripes in the same independent disk redundant array group as the target hardware.

[0054] It should be noted that the erase operation conflict state refers to the state in which the target hardware is performing an erase operation. Since the NAND flash erase operation has a latency of about 10ms, which is 100 times the latency of the read operation, if the read request is executed after the erase operation is completed, the read latency will increase significantly. Therefore, this embodiment avoids this problem by using a degraded read mechanism. Degraded read is a stripe-level data recovery method that relies on RAID redundancy check capability and is also a supplementary application to RAID check capability.

[0055] Specifically, the stripe-level data read operation requires reading the stripe data corresponding to other normal hardware in the independent disk redundancy array group to which the target hardware belongs, excluding the hardware to be erased. Parallel reading is performed on the stripe data of each normal hardware to obtain the first stripe data. Preferably, this parallel reading is implemented based on the independent parallel operation characteristics of NAND flash memory planes. Different conflict-free stripes correspond to different idle planes, and each plane performs data read operations simultaneously, which greatly improves data read efficiency. After obtaining the first stripe data, the logical block address data corresponding to the target hardware is recovered based on the first stripe data through hardware-accelerated RAID check calculation, and a degraded read scheduling result is generated. This invention does not limit the specific RAID architecture. Architectures with data redundancy recovery capabilities, such as RAID5 and RAID6, can be used. For example, when using a RAID5-4+1 architecture, reading the data of 4 conflict-free stripes is sufficient to recover the target data corresponding to the hardware to be erased through check calculation.

[0056] S6: If the real-time state meets the second condition, the storage access request will be scheduled to be executed in parallel on the non-conflicting stripe corresponding to other idle operation units in the physical flash memory.

[0057] In this embodiment, if step S4 determines that the real-time state of the target hardware meets the second condition, then step S6 is executed. The second condition is that the target hardware is in a write operation conflict state. At this time, the storage access request is scheduled to be executed in parallel on the non-conflicting stripe corresponding to other idle operation units in the physical flash memory.

[0058] It should be noted that a write operation conflict state refers to the state in which the target hardware is performing a write operation to disk. The parallel operation unit is the plane inside the NAND flash memory. Since the operations within the same plane are serial, if a read request continues to be executed within the same plane, the read request will be blocked by the write operation. Therefore, this embodiment solves this problem by using a multi-plane parallel scheduling method.

[0059] Specifically, firstly, based on the state view, idle plane parallel operation units in the physical flash memory, excluding the plane belonging to the target hardware, are identified. This identification process involves a full-domain query of the state information of all planes in the state view, only needing to filter out planes in a conflict-free idle state. Then, the plane belonging to the target hardware continues to perform write operations, while read operations in storage access requests are scheduled to the conflict-free stripes corresponding to the identified idle planes, achieving cross-plane parallelism of read and write operations. Finally, based on the logical block address read / write planning of the upper-layer business and combined with the read / write speed characteristics of the physical flash memory, the read / write conflict ratio is determined. Based on the read / write conflict ratio, the write operations of the plane belonging to the target hardware and the read operations of the idle planes are controlled to be carried out synchronously and in parallel, generating a parallel scheduling result for read and write requests. The read / write conflict ratio is 1ms for NAND flash write operations and 100ms for read operations. The read / write operation resource allocation ratio is calculated based on the latency characteristics. This ratio enables precise control over the parallel read / write process, avoiding new operational conflicts. Furthermore, after the write operation to disk of the target hardware's plane is completed, the corresponding cache resources of that plane will be immediately reclaimed for subsequent write operations, improving the system's flush capability.

[0060] It should be noted that during the degraded read processing in step S5 and the parallel scheduling processing in step S6, all selections of conflict-free stripes and idle planes are based on the full hardware status view constructed in step S1. This ensures that the selected hardware is in a directly accessible conflict-free idle state. Furthermore, this invention does not specifically limit the number of stripes read in parallel during degraded reads or the number of idle planes selected during parallel scheduling; these can be flexibly set according to the actual RAID group architecture and the hardware specifications of the physical flash memory, as long as the recovery of the target data or the parallel execution of read requests can be achieved. Simultaneously, after the scheduling operations in steps S5 and S6 are completed, the current execution status of the corresponding hardware in the status view needs to be updated in real time. If a hardware status switch is involved, such as updating the status of an idle plane to the read operation execution status after a read operation, it should immediately revert to the conflict-free idle state after the operation is completed. This ensures that the status view always remains consistent with the actual state of the physical flash memory hardware, providing accurate status information for subsequent storage access request processing.

[0061] The present invention also provides a specific embodiment of a storage access method to illustrate the beneficial effects of this solution.

[0062] This embodiment uses an enterprise-grade NAND flash solid-state drive as the application platform. This solid-state drive employs a hardware architecture of 31+1 dies, with each die containing 4 parallel operation units (Plane). A single Plane consists of several consecutive Blocks, with each Block serving as the smallest unit for erasure. The Logical Block Address (LBA) uses a standard 4KB data area specification. The underlying implementation uses the Open Channel mechanism to map the physical NAND flash memory to the server-side hardware. Disk access control is achieved through the storage access method of this invention, thereby verifying the beneficial effects of the solution in reducing read latency, improving resource utilization, and achieving operational predictability. In this embodiment, the native read, write, and erase operation latencies of the NAND flash memory are 100ms and 100ms respectively. In traditional access schemes, erase operations can easily cause read latency to surge to the 10ms level, and write operations can easily cause read request blocking latency exceeding 1ms. However, this solution achieves predictable read latency and significant optimization of storage performance through end-to-end hardware status awareness, striped mapping, and differentiated conflict handling.

[0063] In this embodiment, the server first maps all Planes and Blocks of the solid-state drive to its local machine based on the Open Channel mechanism. Then, through hardware status polling and interrupt notification, it collects the read / write / erase execution status and physical relationships of each hardware component in real time, integrating them to generate a status view containing the full hardware status. This view can synchronize hardware status changes in real time; for example, when a Plane switches from an idle state to an erase operation state, the server can notify the user within 10 seconds. The state update is completed within the server. Subsequently, the server filters out consecutive blocks with no conflicts and in an idle state based on the state view, performs striping combination processing to generate RAID5 stripes (using a 4+1 redundancy architecture), and arranges LBAs in numerical order into the blocks corresponding to each RAID stripe, establishing a one-to-one mapping relationship between LBAs and RAID stripes. Each stripe corresponds to an independent plane hardware area. Upper-layer services can accurately record the physical hardware location corresponding to each LBA through this mapping relationship, providing a basis for subsequent conflict judgment and scheduling. At the same time, a special mark is added to the write operation to indicate whether it needs to be flushed to disk immediately, breaking the traditional limitation of "flushing to disk only when the stripe is full" and realizing flexible control of write to disk behavior.

[0064] When an upper-layer service initiates a read storage access request, the server first parses the request to extract the target LBA. Based on the mapping relationship between the LBA and RAID stripes, it forward-locates the corresponding RAID stripe, and then reverse-locates the target hardware (including the RAID stripe and its associated plane) through the association relationship between the stripe and the physical hardware. If the target hardware is in a conflict-free idle state, the server directly performs the read operation on the target hardware, with the read latency consistently at 100% of the native NAND flash memory latency. The system updates the status view in real time after the operation is completed. If the target hardware's plane is in an erase operation conflict state, the server immediately converts the direct read operation into a stripe-level data read operation, reading data from the other four conflict-free stripes in the same RAID5 group. Parallel reading is achieved by utilizing the idle planes corresponding to each stripe. After reading, the data corresponding to the target LBA is recovered through hardware-accelerated RAID checksum calculation. The total latency of the entire downgrade read process is controlled within 500ms. Within this range, compared to the 10ms read latency of traditional solutions, the latency is reduced by more than 95%, completely avoiding the problem of read latency surge caused by erase operations.

[0065] If the target hardware's plane is in a write operation conflict state, the server quickly identifies other free planes in the SSD based on the state view, allowing the target plane to continue the write operation, while simultaneously scheduling read requests to the conflict-free stripes corresponding to the free planes for parallel execution. This achieves a parallel operation mode of "one plane writes, multiple planes read". The server, combining the upper-layer LBA read / write planning with the 1:10 read / write speed characteristic of NAND flash memory, determines the read / write conflict ratio to be 1:10. Based on this ratio, it controls the synchronous parallel execution of write and read operations, ensuring non-blocking execution of read requests while maintaining a stable read latency of 100ms. The server immediately reclaims the cache resources corresponding to the target plane after the write operation to disk is completed, and uses them for caching subsequent write operations. Compared with the traditional batch flushing method, the cache resource utilization rate is improved by more than 80%. At the same time, through the upper-layer LBA read and write planning, it can actively suggest that some low-priority planes perform fast flushing, further avoiding read and write conflicts, and making the write to disk behavior completely within the controllable range of the upper-layer business.

[0066] In this embodiment, for the block erasure operation, the server accurately records the distribution of valid data in each block through the state view and LBA-physical hardware mapping relationship. When it is detected that the percentage of valid data in a certain block is extremely low, the upper-layer business actively triggers a data migration operation to migrate the valid data in that block to other conflict-free blocks. After the migration is completed, the erasure operation is performed, and the erasure location and timing are determined autonomously by the upper-layer business, realizing the predictability of the erasure operation. At the same time, in the entire storage access process, the server realizes global control of all hardware through the state view, and coordinates the resource allocation between multiple planes. This breaks the limitation of the traditional solution that only considers the operation priority within a single plane, and fully explores the hardware parallel capabilities of the 128 concurrent write resource items and 256 concurrent plane resource items of the solid-state drive. Within a 1ms time window, 10 read requests can be processed in parallel, achieving a read performance of 100,000 IOPS. Compared with the traditional solution, the read throughput is improved by more than 10 times.

[0067] The practical application results of this embodiment show that the method of the present invention effectively solves the technical problems of large read latency fluctuation, serial blocking of read, write and erase operations, low resource utilization, and uncontrollable lower-level operations in traditional storage access schemes. It achieves microsecond-level predictability of read latency, reduces read latency fluctuation to less than 5%, and improves hardware parallelism and cache resource utilization. This allows for comprehensive optimization of the read performance, resource utilization, and operational controllability of the storage system, and can perfectly adapt to the enterprise-level storage access requirements of high IOPS, low latency, and high reliability.

[0068] Another embodiment of the present invention provides a storage access system; for details, please refer to [link to relevant documentation]. Figure 2 , Figure 2 The diagram shown is a structural block diagram of a storage access system according to one embodiment of the present invention, which includes: The identification module 11 is used to identify the current execution state of each hardware component in the physical flash memory, and to construct a state view of the full hardware state of the physical flash memory based on all current execution states. Module 12 is used to perform striping combination processing on each hardware based on the status view, generate several independent disk redundant array stripes, and establish a mapping relationship between the independent disk redundant array stripes and the corresponding logical block addresses. The parsing module 13 is used to respond to and parse external storage access requests, locate the corresponding independent disk redundant array stripe based on the parsed logical block address and mapping relationship, and locate the target hardware corresponding to the storage access request based on the independent disk redundant array stripe. The detection module 14 is used to determine the real-time status of the target hardware based on the status view. The first access module 15 is used to read the data to be accessed corresponding to the target hardware from other non-collision stripes in the same independent disk redundant array group as the target hardware if the real-time status meets the first condition. The second access module 16 is used to schedule the storage access request to be executed in parallel on the non-conflicting stripe corresponding to other idle operation units in the physical flash memory if the real-time state meets the second condition.

[0069] Another embodiment of the present invention provides a storage access device; for details, please refer to [link to relevant documentation]. Figure 2 This is a structural block diagram of a storage access device provided in an embodiment of the present invention. The storage access device includes a processor 21, a memory 22, and a computer program stored in the memory 22 and configured to be executed by the processor 21. When the processor 21 executes the computer program, it implements the steps described in the above-described storage access method embodiment, for example... Figure 1 The steps S1 to S6 described above; or, when the processor 21 executes the computer program, it implements the functions of each module in the above-described device embodiments, such as the identification module 11.

[0070] For example, the computer program may be divided into one or more modules, which are stored in the memory 22 and executed by the processor 21 to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the storage access device.

[0071] The storage access device may include, but is not limited to, processor 21 and memory 22. Those skilled in the art will understand that the schematic diagram is merely an example of a storage access device and does not constitute a limitation on the storage access device. It may include more or fewer components than illustrated, or combine certain components, or different components. For example, the storage access device may also include input / output devices, network access devices, buses, etc.

[0072] The processor 21 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. The processor 21 is the control center of the storage access device, connecting various parts of the storage access device via various interfaces and lines.

[0073] The memory 22 can be used to store the computer programs and / or modules. The processor 21 implements various functions of the storage access device by running or executing the computer programs and / or modules stored in the memory 22 and calling the data stored in the memory 22. The memory 22 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital card (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0074] If the modules integrated into the storage access device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0075] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0076] Accordingly, embodiments of the present invention provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform steps in the storage access method of the above embodiments, for example... Figure 1 Steps S1 to S6 as described above.

[0077] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A storage access method, characterized in that, include: Identify the current execution state of each hardware component in the physical flash memory, and construct a state view of the full hardware state of the physical flash memory based on all current execution states; Based on the state view, each piece of hardware is striped together to generate several independent redundant disk array stripes, and a mapping relationship between the independent redundant disk array stripes and the corresponding logical block addresses is established. Respond to and parse external storage access requests, locate the corresponding independent disk redundant array stripe based on the parsed logical block address and the mapping relationship, and locate the target hardware corresponding to the storage access request based on the independent disk redundant array stripe; Based on the state view, the real-time state of the target hardware is determined; If the real-time status meets the first condition, then the data to be accessed corresponding to the target hardware is read from other conflict-free stripes in the same independent disk redundant array group as the target hardware. If the real-time state meets the second condition, the storage access request will be scheduled to be executed in parallel on a non-conflicting stripe corresponding to another idle operation unit in the physical flash memory.

2. The storage access method as described in claim 1, characterized in that, The process of identifying the current execution state of each hardware component in the physical flash memory and constructing a state view of the full hardware state of the physical flash memory based on all current execution states includes: Based on the open channel mechanism, the hardware in the physical flash memory is mapped to the server side, and the read, write and erase execution status of each hardware is collected in real time to obtain the current execution status of each hardware and the physical association between each hardware. The current execution state and the physical association are integrated to generate a state view of the entire physical flash memory hardware.

3. The storage access method as described in claim 1, characterized in that, The process of striping and combining the hardware components based on the state view to generate several independent redundant disk array stripes, and establishing a mapping relationship between the independent redundant disk array stripes and their corresponding logical block addresses, includes: Based on the state view, striping combination processing is performed on each of the hardware components to form several independent disk redundant array stripes; wherein, each independent disk redundant array stripe is composed of contiguous storage blocks in physical flash memory, and each stripe corresponds to an independent hardware region of physical flash memory. Logical block addresses are sequentially arranged into consecutive storage blocks corresponding to each independent disk redundant array stripe, so that each independent disk redundant array stripe is associated with a unique logical block address, thus establishing a one-to-one mapping relationship between the independent disk redundant array stripe and the logical block address.

4. The storage access method as described in claim 1, characterized in that, The process of locating the corresponding independent redundant array stripe based on the parsed logical block address and the mapping relationship, and locating the target hardware corresponding to the storage access request based on the independent redundant array stripe, includes: The storage access request is subjected to encapsulation information stripping and data parsing to extract the logical block address from the storage access request; Based on the mapping relationship, the independent disk redundant array stripe corresponding to the logical block address is located in the forward direction; Based on the association between the independent disk redundant array stripe and the physical flash memory hardware, the target hardware corresponding to the storage access request is located in reverse. The target hardware includes at least the independent disk redundant array stripe and the parallel operation unit to which the stripe belongs.

5. The storage access method as described in claim 1, characterized in that, Determining the real-time state of the target hardware based on the state view further includes: If the real-time status is a conflict-free idle state, the read and write operations corresponding to the storage access request are directly executed on the target hardware, and the current execution status of the corresponding hardware in the status view is updated in real time after the operation is completed.

6. The storage access method as described in claim 1, characterized in that, The first condition includes the target hardware being in an erase operation conflict state; Determining the real-time state of the target hardware based on the state view further includes: If the real-time state is an erase operation conflict state, the direct read operation on the target hardware will be converted into a stripe-level data read operation; The stripe-level data reading operation includes: reading the stripe data corresponding to other normal hardware in the independent disk redundant array stripe to which the target hardware belongs, excluding the hardware to be erased, and performing parallel reading of the stripe data of each normal hardware to obtain the first stripe data; Based on the first stripe data, the logical block address data corresponding to the target hardware is recovered, and the degraded read scheduling result of the stripe-level data read operation is generated.

7. The storage access method as described in claim 1, characterized in that, The second condition includes the target hardware being in a write operation conflict state; Determining the real-time state of the target hardware based on the state view further includes: If the real-time state is a write operation conflict state, then based on the state view, identify the idle parallel operation units in the physical flash memory other than the parallel operation unit to which the target hardware belongs; The read operation in the storage access request is scheduled to be executed in the conflict-free stripe corresponding to the idle parallel operation unit; The read / write conflict ratio is determined based on the read / write speed characteristics of the physical flash memory, and the write operation of the parallel operation unit to which the target hardware belongs and the read operation of the idle parallel operation unit are controlled to be carried out synchronously and in parallel according to the read / write conflict ratio, so as to generate the parallel scheduling result of read / write requests.

8. A storage access system, characterized in that, include: The identification module is used to identify the current execution state of each hardware component in the physical flash memory, and to construct a state view of the full hardware state of the physical flash memory based on all current execution states. The construction module is used to perform striping combination processing on each of the hardware based on the state view, generate several independent disk redundant array stripes, and establish a mapping relationship between the independent disk redundant array stripes and the corresponding logical block addresses. The parsing module is used to respond to and parse external storage access requests, locate the corresponding independent disk redundant array stripe based on the parsed logical block address and the mapping relationship, and locate the target hardware corresponding to the storage access request based on the independent disk redundant array stripe. The detection module is used to determine the real-time status of the target hardware based on the status view. The first access module is used to read the data to be accessed corresponding to the target hardware from other non-conflicting stripes in the same independent disk redundant array group as the target hardware if the real-time status meets the first condition. The second access module is used to schedule the storage access request to be executed in parallel on the non-conflicting stripe corresponding to other idle operation units in the physical flash memory if the real-time state meets the second condition.

9. A storage access device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the memory access method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the device containing the computer-readable storage medium executes the computer program, it implements the storage access method as described in any one of claims 1 to 7.

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