FPGA-based high-density surface electromyography signal hardware filtering device and method

Abstract

The application provides a high-density surface electromyography signal hardware filtering device and method based on FPGA, comprising: an sEMG signal input module for collecting multi-channel noisy surface electromyography signals and at least one reference noise signal; an LMS adaptive filtering calculation module for receiving the noisy surface electromyography signals and the reference noise signal, adopting a fixed-point number operation system and executing an LMS adaptive filtering algorithm through a parallel pipeline structure to output a filtered error signal; a data buffer and output interface module for buffering and outputting the filtered surface electromyography signals; and an FPGA main control module connected with the sEMG signal input module, the LMS adaptive filtering calculation module and the data buffer and output interface module for controlling the work of each module. The application realizes the LMS adaptive filtering algorithm on the FPGA platform, and solves the problems of insufficient real-time performance and large processing delay of software filtering when facing high-density multi-channel sEMG signal processing.

Description

Technical Field

[0001] This application relates to the field of bioelectric signal processing and programmable logic device technology, specifically to a hardware filtering device and method for high-density surface electromyography signals based on FPGA. Background Technology

[0002] Surface electromyography (sEMG) signals contain rich information related to human movement. They record muscle electrical activity by measuring the spatiotemporal superposition of motor unit action potentials (MUAPs) generated by multiple motor units (MUs) during muscle contraction. Unlike traditional invasive electrodes, sEMG signals are widely used due to their non-invasive nature and ease of acquisition. sEMG analysis is becoming increasingly important in many applications, such as the clinical diagnosis of neuromuscular abnormalities, control of prostheses and industrial robots, muscle fatigue detection, and force quantification. To meet the demands of multi-channel, high real-time processing, traditional software-based LMS adaptive filtering algorithms are no longer sufficient for large-scale, multi-channel data processing. Therefore, it is necessary to deploy the LMS (Least Mean Square) algorithm on a high-performance hardware platform, especially an FPGA, to achieve real-time processing and noise reduction of a large number of channel signals.

[0003] Currently, FPGAs are widely used in the field of bioelectrical signal processing due to their parallel computing capabilities and low latency. FPGA-based LMS adaptive filters can significantly improve filtering speed and reduce system power consumption through efficient parallel data processing and pipelined architecture. Addressing the high-density acquisition requirements of sEMG signals, this invention proposes a 128-channel LMS adaptive filtering system. This system, through pipelined and parallel processing on the FPGA platform, effectively solves the latency problem in real-time signal processing and significantly improves the system's bandwidth and processing power.

[0004] A search revealed Chinese invention patent application CN 202410501574.0, entitled "Adaptive Filtering Method, Apparatus, Computer Equipment, and Storage Medium," which proposes a method for optimizing the step size factor of an LMS adaptive filter using a denoising neural network (DnCNN). While this patent proposes improving filtering accuracy by optimizing the step size factor through a denoising neural network, it relies heavily on the training process and computational resources of the neural network, and is primarily designed for single-channel or limited-channel signal processing, making it difficult to meet the demands of high-channel-count and real-time requirements.

[0005] Chinese invention patent application CN202420998796.3, entitled "A Device for Acquiring Surface Electromyography Signals," replaces the traditional discrete component architecture by using a high-performance integrated chip AD8232 and its peripheral circuitry to construct a pre-processing unit. While this patent reduces power consumption and enhances physical anti-interference capabilities through the integration of the AD8232 chip and shielding layer, its inherent drawback lies in using a microcontroller (MCU) for serial secondary filtering. This results in significant computational delay and poor real-time performance when the number of channels is increased. Furthermore, its filtering parameters are limited by the peripheral components of the analog circuitry, making it difficult to meet the stringent requirements of real-time processing of high-density bioelectrical signals. Summary of the Invention

[0006] In view of one of the defects in the prior art, the purpose of this application is to provide a high-density surface electromyography signal hardware filtering device and method based on FPGA.

[0007] A first aspect of this application provides a high-density surface electromyography (EMG) signal hardware filtering device based on FPGA, comprising: The sEMG signal input module is used to acquire multi-channel noisy surface electromyography signals and at least one reference noise signal. The LMS adaptive filtering calculation module is connected to the output of the sEMG signal input module. It is used to receive the noisy surface electromyography signal and the reference noise signal, and executes the LMS adaptive filtering algorithm through a fixed-point number arithmetic system and a parallel pipelined structure to output the filtered error signal. A data caching and output interface module is connected to the LMS adaptive filtering calculation module and is used to cache and output the data from the LMS adaptive filtering calculation module. The FPGA main control module is connected to the sEMG signal input module, the adaptive filtering control module, the LMS adaptive filtering calculation module, and the data buffer and output interface module, and is used to control the operation of each module.

[0008] Optionally, the sEMG signal input module includes multiple high-precision analog-to-digital converters to form a multi-channel data acquisition array; In this configuration, at least one acquisition channel is configured to acquire the inherent noise of the acquisition circuit as the reference noise signal X(n), while the remaining channels acquire the noisy surface electromyography signal d(n).

[0009] Optionally, the LMS adaptive filtering calculation module includes: an input processing module, a filtering calculation module, an error calculation module, and a weight update module; The input processing unit is connected to the output terminal of the sEMG signal input module, receives the digitized noisy surface electromyography signal d(n) and the reference noise signal X(n), and after sign expansion and amplitude normalization processing, outputs the processed signals to the filtering calculation unit, the error calculation unit and the weight update unit respectively. The filtering calculation unit receives the reference noise signal output by the input processing unit, calculates the filtered output y(n), and outputs it to the error calculation unit. The error calculation unit simultaneously receives the noisy surface electromyography signal output by the input processing unit and y(n) output by the filtering calculation unit, calculates the error signal e(n), and outputs it to the weight update unit. The weight update unit receives e(n) output by the error calculation unit and the reference noise signal output by the input processing unit, updates the weight coefficients, and then feeds them back to the filter calculation unit to form an adaptive filter closed-loop connection.

[0010] Optionally, the LMS adaptive filtering calculation module adopts a fixed-point arithmetic system, and sets bit width control and quantization strategies at the input end, multiply-accumulate operation end and weight update end respectively; Specifically, the input processing unit performs symbol expansion and amplitude normalization on the digitized signal, ensuring that the normalized input samples meet the following requirements: ; In the filtering calculation unit, the weight coefficients are stored in a 32-bit signed fixed-point format. The input sample and the weight coefficients are multiplied and summed to form an extended-width bit product. The bit width of the extended-width bit product is greater than the sum of the bit widths of the input sample and the weight coefficients. In the weight update unit, the weight coefficients are updated using the error signal and the step size factor. It adopts a 16-bit signed fixed-point format and is in negative power of 2 form, with an initial value of ; The weight update unit performs a multiplication operation with μ through arithmetic shift operations, and can be adjusted in stages according to the convergence speed and steady-state error requirements.

[0011] Optionally, the filtering calculation unit uses a 7th-order adaptive FIR structure as a finite impulse response structure to model the interference noise channel in the surface electromyography signal; The 7th-order adaptive FIR structure operates based on the fixed-point arithmetic system. During the accumulation process, an accumulator structure with guard bits is used, and the multiplication and addition results are truncated and quantized before output, retaining the high significant bits and discarding the low decimal places.

[0012] Optionally, in the weight update unit, the error signal e(n) and the weight update amount Δw(k) = μ e(n) X(n k), using extended bit-width operations; In the formula, μ is the step size parameter; X (n k) is the reference noise signal at the nth time. Input sample at time k.

[0013] Optionally, the LMS adaptive filtering calculation module adopts a parallel pipelined structure, which is a multi-channel parallel and single-channel multi-stage serial pipelined approach. Specifically, the filter output calculation, error calculation, and weight update are organized into a single-channel multi-stage pipeline, forming an adaptive filter closed loop within one sampling period. This loop allows for continuous data path processing of a single input sampling point, including filter output calculation, error calculation, weight update, and write-back.

[0014] Optionally, the LMS adaptive filtering calculation module includes multiple LMS sub-modules configured in parallel; The LMS submodules are respectively connected to the noisy sEMG signals output by different sEMG signal input modules. The LMS submodules are time-division multiplexed by storing input data, filtered data and weight parameters. Each LMS submodule has a multi-stage pipeline formed by the filter output calculation, error calculation, and weight update.

[0015] Optionally, the parallel pipelined structure divides the critical path by registers, so that the multiplication, addition tree and weight update write-back are in different pipeline stages; The parallel pipelined structure uses an enable signal and a valid flag to synchronize sampling, so that the computation triggered by each input sample completes filtering output, error calculation, and weight update after a predetermined pipeline delay.

[0016] A second aspect of this application provides a method for using a high-density surface electromyography signal hardware filtering device based on FPGA, comprising: The sEMG signal input module synchronously acquires multi-channel noisy surface electromyography signals d(n) and at least one reference noise signal X(n); The LMS adaptive filtering calculation module receives a noisy surface electromyography signal d(n) and at least one reference noise signal X(n), and filters the received signals. The FPGA main control module controls the LMS adaptive filtering calculation module, which uses a fixed-point arithmetic system to process the acquired data and executes the LMS adaptive filtering algorithm through a parallel pipelined structure, and outputs the filtered error signal. The filtered sEMG signal is buffered through the data buffer and output interface module and then output to an external processing device or host computer system.

[0017] This application provides a high-density surface electromyography (SEMG) signal hardware filtering device based on FPGA. It employs a fixed-point arithmetic system and a parallel pipelined structure to execute the LMS adaptive filtering algorithm. The device synchronously acquires multi-channel noisy SEMG signals and reference noise signals through an sEMG signal input module, providing a data foundation. The LMS adaptive filtering calculation module, using a fixed-point arithmetic system adapted to FPGA hardware resources and a parallel pipelined structure, efficiently executes the LMS adaptive filtering algorithm. This significantly improves filtering real-time performance and shortens processing latency while reducing hardware resource consumption. The filtered signal is then stably output through a data buffer and output interface module. Furthermore, the FPGA main control module provides unified and coordinated control of all modules. This solution addresses the problems of insufficient real-time performance, large latency, and limited noise immunity in multi-channel SEMG signal processing using existing software-based or general-purpose processor-based filtering methods. It can stably and efficiently output high-quality filtered signals and possesses good configurability and scalability.

[0018] Other technical effects resulting from the additional features will be further illustrated in the corresponding embodiments. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a design diagram of an FPGA-based surface electromyography signal hardware filtering system according to an exemplary embodiment; Figure 2 This is a schematic diagram illustrating the structure of the LMS adaptive filtering algorithm according to an exemplary embodiment; Figure 3 This is a schematic diagram of an LMS hardware filtering structure according to an exemplary embodiment; Figure 4 This is a physical diagram of an FPGA-based surface electromyography signal hardware filtering system according to an exemplary embodiment. Figure 5 This is a diagram illustrating the effect of a host computer displaying a filtered sEMG signal according to an exemplary embodiment. Figure 6 This is a diagram illustrating the effect of a host computer displaying an unfiltered sEMG signal according to an exemplary embodiment. Figure 7 This is a comparison diagram of FIR ordinary filtering, LMS adaptive filtering, and sEMG signals according to an exemplary embodiment. Figure 8 This is a flowchart illustrating a method for a hardware filtering device for high-density surface electromyography signals based on an FPGA, according to an exemplary embodiment. Detailed Implementation

[0020] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all fall within the protection scope of the present application. Parts not described in detail in the following embodiments can be implemented using existing technology.

[0021] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0023] In the description of the embodiments in this application, "multiple" means two or more, unless otherwise explicitly specified. In this application, unless otherwise explicitly specified and limited, the terms "installed," "connected," "linked," "fixed," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or devices.

[0025] Existing software-based or general-purpose processor-based implementations suffer from insufficient real-time performance, large processing latency, and difficulty in meeting the requirements of multi-channel surface electromyography (EMG) signal processing. To address these issues, this application provides a high-density surface EMG signal hardware filtering device based on an FPGA to resolve these problems.

[0026] Reference Figure 1 As shown in one embodiment of this application, a high-density surface electromyography (sEMG) signal hardware filtering device based on FPGA includes: an sEMG signal input module, an LMS adaptive filtering calculation module, a data buffer and output interface module, and an FPGA main control module.

[0027] The system comprises: an sEMG signal input module for acquiring multi-channel noisy surface electromyography (EMG) signals and at least one reference noise signal; an LMS adaptive filtering calculation module connected to the output of the sEMG signal input module for receiving the noisy EMG signals and the reference noise signal, executing the LMS adaptive filtering algorithm using a fixed-point arithmetic system and a parallel pipelined structure, and outputting the filtered error signal; a data buffer and output interface module connected to the LMS adaptive filtering calculation module for buffering and outputting the data from the LMS adaptive filtering calculation module; and an FPGA main control module connected to the sEMG signal input module, the LMS adaptive filtering calculation module, and the data buffer and output interface module for controlling the operation of each module.

[0028] Specifically, firstly, the sEMG signal input module synchronously acquires multi-channel noisy surface electromyography (d(n)) signals at a sampling rate of 2kHz through multiple high-precision analog-to-digital converters (RHD2132), and acquires inherent noise of the circuit (such as power frequency interference, electromyographic movement drift, etc., i.e., X(n)) through a separately set reference channel; then, the FPGA main control module starts and coordinates the control of each module. After receiving the noisy signal and the reference noise signal, the LMS adaptive filtering calculation module calculates the signal based on the fixed-point arithmetic system (including input amplitude normalization, multiply-accumulate extended bit width operation). The LMS adaptive filtering algorithm is executed through a parallel pipelined structure (multi-level cascaded sub-modules, including delay lines, parallel multiplication units, addition and accumulation networks, dedicated difference units, and weight update units) to complete the closed-loop operation of filtering output calculation, error signal e(n) solution, and weight update. Finally, the data buffer and output interface module buffers and frames the filtered error signal (i.e., pure surface electromyography signal) and outputs it to an external processing device or host computer system for subsequent analysis, display, or storage.

[0029] The FPGA main control module is electrically connected to the other modules to control them. The output of the sEMG signal input module is connected to the input of the LMS adaptive filtering calculation module. The output of the LMS adaptive filtering calculation module is connected to the input of the data buffer and output interface module. The device deploys the LMS adaptive filtering algorithm through the FPGA platform to realize real-time adaptive filtering of multi-channel sEMG signals.

[0030] The embodiments described above in this application, by deploying the LMS adaptive filtering algorithm on an FPGA platform and combining it with a parallel pipelined structure and register-based critical path partitioning design, solve the pain points of insufficient real-time performance and large processing latency in traditional software or general-purpose processor serial processing methods. This achieves "a complete LMS update loop is completed in each sampling cycle," meeting the online processing requirements of high-density multi-channel signals. Simultaneously, by employing a fixed-point arithmetic system and targeted bit-width control and quantization strategies, and adapting to the FPGA's DSP multiplier resources, it ensures the ability to distinguish weak effective components of surface electromyography signals while reducing hardware resource consumption and suppressing fixed-point quantization noise. Combined with the time-division multiplexing design of the LMS submodule, it further reduces the occupation of core resources within the FPGA. All modules are uniformly and collaboratively controlled by the FPGA main control module, achieving stable output of high-quality filtered signals without relying on software calculations from general-purpose processors.

[0031] The configuration of step size μ and control initialization are all completed in the LMS adaptive filter calculation module. The FPGA main control module mainly controls the data flow and ADC acquisition to ensure the timing stability of the entire system and the implementation of the pipeline architecture.

[0032] Based on the above embodiments, the FPGA-based high-density surface electromyography (SEMG) signal hardware filtering device further includes a power management module, which is connected to the sEMG signal input module, the LMS adaptive filtering calculation module, the data buffer and output interface module, and the FPGA main control module to provide power.

[0033] It should be noted that the LMS adaptive filtering algorithm used in this application embodiment is implemented in an FPGA to achieve a pipelined parallel filtering structure. This can solve the problems of insufficient real-time performance and large processing delay in software filtering when dealing with high-density, multi-channel sEMG signal processing. The following is a theoretical introduction to the LMS adaptive filtering algorithm: During the sEMG signal filtering process, relevant signals such as Figure 2As shown, the adaptive filter cancels the noise carried by the signal d(n) by calculating the output signal y(n), thereby obtaining the filtered error signal e(n). This signal is not only the filtered sEMG signal, but also the cost function used to calculate and evaluate the mean square error. y(n) can be obtained by filtering the noise signal X(n) with an adaptive weighted FIR filter, as shown in Equation (1).

[0034] (1) In the formula, Here, L represents the weight coefficients of the filter, and L is the order of the filter. To represent the current nth time... Tap coefficient.

[0035] Error signal As shown in equation (2).

[0036] (2) In the formula, This is a surface electromyography signal containing noise; Let n be the output signal of the adaptive filter at time n. Error signal The least mean square root is used as the optimal statistical criterion, and the cost function is defined. : (3) In the formula, : Mathematical expectation operator, used to measure the long-term average level of error; This is the square of the error signal.

[0037] in, The change over time characterizes the convergence speed and convergence accuracy of the filter. When When the minimum value is reached, the filter's weight coefficients can reach their optimal value. Equation (4) uses the steepest descent method, along the cost function... The weight vector of the adaptive filter taps is updated in the direction of fastest descent (negative gradient direction). Search cost function Find the minimum point of the performance surface and solve for the optimal weight vector. ,available: (4) In the formula, Let be the gradient operator, representing the cost function. For weight vector The partial derivatives; Therefore, the formula for calculating the weight coefficients of the LMS adaptive filter is updated as follows: (5) In the formula, This represents the weight vector at the nth iteration. This represents the weight vector at the (n+1)th iteration. This is the step size factor, used to control the convergence speed of the adaptive filter.

[0038] In some specific embodiments of this application, the sEMG signal input module includes multiple high-precision analog-to-digital converters to form a multi-channel data acquisition array.

[0039] In this configuration, at least one acquisition channel is configured to acquire the inherent noise of the acquisition circuit as a reference noise signal x(n), while the remaining channels acquire the noisy surface electromyography signal d(n).

[0040] Specifically, in one embodiment, the sEMG signal input module, addressing the small amplitude, low signal-to-noise ratio, and significant non-stationary characteristics of surface electromyography (sEMG) signals, uses a high-precision analog-to-digital converter (RHD2132) as the data acquisition unit. The RHD2132 is configured via the SPI protocol to amplify the input sEMG signals at the front end and simultaneously acquire multi-channel sEMG signals at a sampling rate of 2kHz. The RHD2132 can perform polling sampling of 32 channels. In this application, one RHD2132 sampling data is selected as a reference channel that does not contact the skin. The inherent noise in the acquisition circuit, such as power frequency signal interference and electromyographic drift, is represented by signal X(n). The remaining channels input noisy sEMG signals, denoted as d(n). This application uses four RHD2132s to form a 128-channel sEMG acquisition device. Each channel returns a 16-bit signed number, which is then processed by the LMS adaptive filtering calculation module.

[0041] Reference Figure 3 As shown, it should be noted that in the above embodiment, the system acquires a total of 128 channels of surface electromyography (sEMG) signals, implemented by four RHD2132 acquisition chips, each providing 32 acquisition channels. To reduce hardware resource consumption and improve system real-time performance, the 128 channels are processed in groups of four within the FPGA, with one channel serving as the reference noise signal X(n) and the remaining three channels serving as the noisy sEMG signal d(n). The system uses three LMS adaptive filtering calculation modules to filter the three noisy channels respectively, sharing the same reference signal. The FPGA control module polls and schedules each channel group, allowing the 128 channels to enter the LMS filtering calculation module sequentially through time-division multiplexing, thereby achieving real-time adaptive filtering processing of multi-channel surface electromyography signals.

[0042] Of course, the above is only a preferred embodiment of this application. In other embodiments, other numbers of high-precision analog-to-digital converters can be used to form a multi-channel data acquisition array. The specific acquisition chip can also be other products and is not limited to the example above.

[0043] In some specific embodiments of this application, the LMS adaptive filtering calculation module includes: an input processing unit, a filtering calculation unit, an error calculation unit, and a weight update unit.

[0044] The input processing unit is connected to the output of the sEMG signal input module. It receives the digitized noisy surface electromyography signal d(n) and the reference noise signal X(n). After sign expansion and amplitude normalization, the processed signals are output to the filtering calculation unit, the error calculation unit, and the weight update unit, respectively. The filtering calculation unit receives the reference noise signal output from the input processing unit, calculates the filtered output y(n), and outputs it to the error calculation unit. The error calculation unit simultaneously receives the noisy surface electromyography signal output from the input processing unit and the y(n) output from the filtering calculation unit, calculates the error signal e(n), and outputs it to the weight update unit. The weight update unit receives the e(n) output from the error calculation unit and the reference noise signal output from the input processing unit, updates the filter weight coefficients, and then feeds them back to the filtering calculation unit, forming an adaptive filtering closed-loop connection.

[0045] The sEMG signal input module consists of the original sEMG signal and the noise signal. These two signals are respectively for d(n) and X(n), i.e., the digitized signals. The LMS adaptive filter needs to perform calculations using these two signals to complete the filtering.

[0046] Specifically, the input terminal of the input processing unit is connected to the sEMG signal input module, and its output terminal is connected to the filtering calculation unit and the error calculation unit, respectively, to provide the filtering calculation unit with the normalized reference noise signal. That is, inputting samples and providing noisy surface electromyography signals to the error calculation unit. The filtering calculation unit simultaneously receives the reference noise signal output from the input processing unit and the weight coefficients fed back from the weight update unit, and its output filtering result... The data is sent to the error calculation unit; the error calculation unit calculates the data according to the error calculation unit. and Calculate error signal That is, e(n) = d(n) - y(n). This signal is output to the data buffer and output interface module as a filtered surface electromyography signal, and sent to the weight update unit. The weight update unit also receives the reference noise signal delay chain data from the input processing unit, updates the weight coefficients using the error signal and step size factor, and sends the new weights back to the filtering calculation unit, thus forming a complete adaptive filtering closed-loop connection.

[0047] In the embodiments described above, hardware filtering cannot perform efficient floating-point operations like software filtering, and floating-point operations consume significant FPGA resources. Therefore, the LMS adaptive filtering calculation module in this embodiment adopts a fixed-point arithmetic architecture to adapt to the FPGA's DSP multiplier resources, and sets corresponding bit width control and quantization strategies at the input, multiply-accumulate, and weight update ends.

[0048] In some specific embodiments of this application, the LMS adaptive filtering calculation module adopts a fixed-point arithmetic system, and bit width control and quantization strategies are set at the input end, multiply-accumulate end and weight update end, respectively.

[0049] Specifically, the input processing unit performs symbol expansion and amplitude normalization on the digitized signal, ensuring that the normalized input sample satisfies... In the filtering calculation unit, the weight coefficients are stored in a 32-bit signed fixed-point format. The input sample and the weight coefficients are multiplied and accumulated to form an extended-width product. The bit width of the extended-width product is greater than the sum of the bit widths of the input sample and the weight coefficients. In the weight update unit, the weight coefficients are updated using the error signal and the step size factor. It adopts a 16-bit signed fixed-point format and is in negative power of 2 form, with an initial value of .

[0050] The weight update unit performs a multiplication operation with μ through arithmetic shift operations, and can be adjusted in stages according to the convergence speed and steady-state error requirements.

[0051] In the embodiments described above, the LMS adaptive filtering calculation module employs a fixed-point arithmetic system, and differentiated bit-width control and quantization strategies are set at the input, multiply-accumulate, and weight update ends, respectively. Specifically, the amplitude normalization at the input end ensures that the samples satisfy... This avoids the overflow risk in fixed-point multiplication; the filtering calculation unit uses a 32-bit signed fixed-point format to store the weight coefficients and generates an extended bit-width product, which, while ensuring accumulation accuracy, suppresses the accumulation of fixed-point noise through truncation quantization; the weight update unit updates the step size factor. Set to a negative power of 2 (initial value) Multiplication is performed through arithmetic shift operations, reducing the occupation of DSP multiplier resources inside the FPGA and lowering hardware costs and power consumption; the step size factor supports graded adjustment, ensuring the stability of the filter during startup.

[0052] In some specific embodiments of this application, the filtering calculation unit uses a 7th-order adaptive FIR structure as a finite impulse response structure to model the interference noise channel in the surface electromyography signal.

[0053] Among them, the 7th-order adaptive FIR structure operates based on the fixed-point arithmetic system. In the accumulation process, an accumulator structure with guard bits is used, and the multiplication and addition results are truncated and quantized before output, retaining the high significant bits and discarding the low decimal parts.

[0054] Specifically, the filtering calculation unit uses a 7th-order adaptive FIR structure to model the interference noise channel in the surface electromyography signal and operates based on a fixed-point arithmetic system. During the accumulation process, an accumulator structure with guard bits is introduced to prevent data overflow during multi-tap multiplication and accumulation. Before the multiplication and accumulation result is output, truncated quantization is performed to retain the high significant bits and discard the low decimal places. This avoids the problems of increased multiplication and accumulation times and decreased convergence speed caused by higher-order filters. The accumulator with guard bits ensures numerical stability and calculation accuracy during fixed-point arithmetic. Truncation quantization effectively suppresses the accumulation of fixed-point quantization noise without affecting the filtering effect and controls the bit width growth of the data path. Under the premise of ensuring the filtering effect, the 7th-order structure forms a better engineering compromise between "noise modeling capability, convergence stability, hardware resources, and processing latency", enabling a real-time operation mode of "completing a complete LMS update loop in each sampling period" at the target sampling rate.

[0055] In this embodiment, a 7th-order adaptive FIR structure is used as the core of LMS calculation. The reason is that the main energy of sEMG signals is concentrated in the lower frequency band, and typical interferences (power frequency, motion artifacts, crosstalk of adjacent muscle groups, etc.) have finite-order correlation within a short time window. A low-order adaptive FIR is sufficient to model the noise channel. At the same time, a higher order will significantly increase the number of multiply-accumulate operations and the computational load of weight updates per sampling period, resulting in increased latency, increased resource consumption, and reduced convergence speed.

[0056] It should be noted that the input processing unit receives the digital signal from the sEMG signal input module, performs sign expansion after serial reception and alignment, and converts it into a signed fixed-point format, which includes 1 sign bit and several decimal places; at the same time, it performs amplitude normalization processing on the digital signal, and performs equivalent shift scaling by multiplying by a preset scaling factor or performing equivalent shift scaling, so that the normalized input sample satisfies |X(n)|<1. In the filtering calculation unit, the accumulation process adopts an accumulator structure with guard bits to adapt to the carry requirements of 7th order multi-tap summation; before the intermediate result obtained by multiplying and adding is written to the subsequent register or used for error calculation, truncation quantization is performed to retain the sign bit and a preset number of significant bits. The significant bits include integer bits and significant fractional bits, and the lowest fractional bits of 8 to 16 are discarded. In the weight update unit, the weights can be adjusted to 2 in stages according to the convergence speed and steady-state error requirements. - ¹¹、2 - ¹ 0 2 - ¹³ or 2 - ¹ 4 The weight update unit performs a multiplication operation with the step size parameter μ through arithmetic shift operations.

[0057] For example: First, the sEMG digital data from the ADC is serially received and aligned, then sign-extended and converted into a 16-bit signed fixed-point input sample X(n) inside the FPGA, which includes one sign bit and several decimal places. To avoid overflow during subsequent multiplication and accumulation, the system performs amplitude normalization on the input sample. The normalization method is to multiply the input sample by a preset scaling factor or perform an equivalent shift scaling, so that the normalized input satisfies |X(n)|<1 (preferably making its peak value fall within the range of 0.5 to 0.9), thereby ensuring the resolution capability of weak effective components of sEMG while reserving dynamic margin for subsequent operations.

[0058] Subsequently, during the multiplication and addition calculation of the filtered output y(n), the weight coefficients w(k) are stored and updated in a 32-bit signed fixed-point format, and the input sample X(n) is... After the weights w(k) and k enter the multiplication unit, they form an extended-width product (the product width is greater than the sum of the input and weight widths). During the accumulation process, an accumulator structure with guard bits is used to cover the carry requirements of 7th-order multi-tap summation. Before the multiplication-accumulation result is written to the subsequent register or used for error calculation, the intermediate result is truncated and quantized. Specifically, the sign bit and a preset number of significant bits (including integer bits and significant fractional bits) are retained, and the lowest number of fractional bits are discarded. In this embodiment, the number of discarded bits is set to 8 to 16 bits, which reduces hardware resource consumption and suppresses fixed-point quantization noise without significantly affecting the effective information of sEMG. The reason for discarding the low-significant bits is that the low-significant part contributes less to the filter output and weight update and is more susceptible to quantization noise. Retaining significant bits is more conducive to maintaining numerical stability and avoiding unbounded growth of the multiplication-accumulation link width.

[0059] In some specific embodiments of this application, in the weight update unit, the error signal e(n) and the weight update amount Δw(k) = μ e(n) X (n k), using extended bit-width operations; In the formula, μ is the step size parameter; X (n k) is the reference noise signal at the nth time. Input sample at time k.

[0060] Specifically, in the weight update stage, the error signal e(n) and the update amount Δw(k) = μ·e(n)·X(n) k) Extended bit-width operations are also used; the step size parameter μ is represented in 16-bit signed fixed-point format and written to the LMS adaptive filter calculation module by the control module through registers or configuration interfaces; to facilitate hardware implementation and ensure stability, the step size parameter μ is preferably set to a negative power of 2, so that multiplication scaling can be equivalently implemented by shift operations, reducing the use of DSP resources. Excessive DSP use will lead to insufficient internal FPGA resources. During the system initialization phase, the control module assigns a conservative initial value to μ to ensure that the filter does not diverge during the startup phase, and the initial step size is set to μ=2. - ¹² (i.e., 1 / 4096); when faster convergence is needed, the μ fraction can be adjusted to 2. - ¹¹、2 - ¹ 0 With larger step sizes, μ can be adjusted to 2 when improved stability or jitter suppression is required. - ¹³、2 - ¹ 4 By using smaller step sizes, a trade-off is achieved between convergence speed and steady-state error. This ensures that the weight updates have sufficient effective increments to guarantee convergence speed while avoiding divergence and overflow caused by excessively large updates, thus enabling real-time closed-loop adaptive filtering suitable for sEMG signals.

[0061] The weight update unit performs a multiplication operation with μ through arithmetic shift operations, and can be adjusted in stages according to the convergence speed and steady-state error requirements.

[0062] The embodiments described above in this application achieve an optimized balance between hardware resource efficiency and algorithm performance by designing a fixed-point step factor μ and a negative power of 2, combined with the extended bit-width operation of the weight update unit. The use of a 16-bit signed fixed-point step factor in a negative power of 2 format allows multiplication scaling to be implemented through simple shift operations, reducing the occupancy of the DSP hard core in the FPGA and effectively avoiding implementation bottlenecks caused by insufficient resources. Simultaneously, the extended bit-width operation ensures the accuracy of the calculation of the error signal and the weight update amount, providing sufficient effective increments to maintain convergence speed during the update process while avoiding algorithm divergence caused by excessively large step sizes or update overflow.

[0063] In some specific embodiments of this application, the LMS adaptive filtering calculation module adopts a parallel pipelined structure, which is a multi-channel parallel and single-channel multi-stage serial pipelined approach.

[0064] Specifically, the filter output calculation, error calculation, and weight update are organized into a single-channel multi-stage pipeline, forming an adaptive filtering closed loop that performs filter output calculation, error calculation, weight update, and write-back on a continuous data path for an input sampling point within a sampling period.

[0065] Specifically, in terms of hardware implementation, this application organizes the "filter output calculation - error calculation - weight update write-back" of LMS into a continuous data path closed loop through a parallel and pipelined structure. Compared with the serial structure of software programs, when facing high-density sEMG signals, the parallel and pipelined structure can improve the real-time data processing capability and reduce data latency. The LMS module of this application adopts a pipelined structure with cascaded multi-level sub-modules: after the input sample is delayed to form an input vector, it enters a multi-parallel multiplication unit and an addition accumulation network to generate y(n). The error e(n) = d(n) - y(n) is calculated by a dedicated differential unit. Subsequently, the error and the input vector are updated in parallel in the weight update unit and written back to the weight storage unit, forming an adaptive feedback loop.

[0066] It should be noted that the parallel pipelined structure sets up multiple parallel-running LMS sub-modules at the module level, each corresponding to a different signal input channel, to achieve synchronous processing of multi-channel data. Within a single LMS sub-module, the filter output calculation, error calculation, and weight update are organized into a serial pipeline. By dividing the critical path through registers, the three different input samples can simultaneously be in the three stages of filter output calculation, error calculation, and weight update in each sampling period, forming an adaptive filtering closed loop.

[0067] The embodiments described above in this application employ a parallel pipelined structure to organize the LMS adaptive filtering output calculation, error calculation, and weight update write-back into a multi-stage pipeline and a continuous closed-loop data path. Compared with the software serial processing method, it can complete the complete adaptive filtering closed-loop processing of a single sampling point within a single sampling period, improve the real-time processing capability of high-density sEMG signals, reduce data processing latency, and ensure that the filtering algorithm runs efficiently, stably, and continuously on the FPGA hardware.

[0068] In some specific embodiments of this application, the LMS adaptive filtering calculation module includes multiple LMS sub-modules configured in parallel.

[0069] The LMS submodules are connected to the noisy sEMG signals output from different sEMG signal input modules. By storing input data, filtered data and weight parameters, the LMS submodules are time-division multiplexed. Each LMS submodule has a multi-stage pipeline formed by filtering output calculation, error calculation and weight update.

[0070] Specifically, refer to Figure 3 As shown, in this application, four RHD2132 chips can acquire data from four channels in parallel within one sampling period. Three of these channels are input noisy sEMG signals, i.e., d(n), and one channel is inherent noise in the acquisition circuit, such as power frequency signal interference and electromyographic drift, i.e., signal X(n). These signals are input in parallel to three LMS modules for parallel adaptive filtering. By storing the input and filtered data along with the weights, time-division multiplexing of the LMS filtering modules can be achieved, greatly reducing the consumption of resources such as DSPs inside the FPGA.

[0071] The embodiments described above in this application improve the real-time performance and resource utilization efficiency of multi-channel electromyography signal processing by parallel acquisition of multi-channel sEMG signals and the introduction of a dedicated noise reference channel, combined with the time-division multiplexing design of the LMS adaptive filtering module. By utilizing the FPGA's internal data storage mechanism to cache the input, filtering results, and weight parameters, time-division multiplexing of a single LMS module across multiple channels is achieved. This ensures parallel filtering capabilities while reducing the consumption of hardware resources such as DSPs in the FPGA, lowering system power consumption and cost, and providing an efficient solution for the embedded implementation of high-density, multi-channel sEMG signal acquisition systems.

[0072] Reference Figure 4 As shown, it should be noted that the noisy electromyography (EMG) signal is acquired through the connection, and the EMG signal is processed by hardware signal processing. Through fixed-point quantization strategy, joint design of order and step size, and parallel pipeline structure, real-time closed-loop operation of adaptive filtering is realized. The signal can be transmitted via USB, and the hardware includes a battery.

[0073] In some specific embodiments of this application, the parallel pipelined structure divides the critical path by registers, so that the multiplication, addition tree and weight update write-back are in different pipeline stages; The parallel pipelined structure uses an enable signal and a valid flag to synchronize sampling, so that the computation triggered by each input sample can complete the filtering output, error calculation and weight update after a predetermined pipeline delay.

[0074] Specifically, this pipeline structure can be divided into five main pipeline stages: the first pipeline stage is the input buffer and delay line update stage, which is used to receive the current sampled data and form the input vectors X(n) and X(n) required for the 7th order filter through shift registers. 1), ..., X(n) 6) The output of this stage is configured with a register to latch the delay line results; the second pipeline stage is a parallel multiplication stage, which uses the FPGA's internal DSP multiplier to calculate in parallel the product of each delay input and its corresponding weight w(k), i.e., X(n). The first stage is the multiplication stage, where the multiplication results are summed using a hierarchical addition tree to obtain the filtered output y(n). Pipeline registers are inserted between each addition stage to reduce accumulation path delay. The second stage is the error calculation stage, where the error signal e(n) = d(n) is calculated using a subtractor. y(n), and set the register buffer error signal at the end of this stage; the fifth pipeline stage is the weight update stage, which completes the weight update operation according to the LMS update relationship, that is, w(k)(n+1) = w(k)(n) + μ·e(n)·X(n) k), where μ is the step size parameter. This stage also processes multiplication and addition update operations in stages, and latches the result in the register before writing the update result back to the weight register. By setting pipeline registers between the above operation stages, the original long combination path of "multiplication - multi-stage accumulation - error calculation - weight update" is divided into multiple shorter calculation stages, so that each pipeline stage contains only a limited number of arithmetic operation units, thereby significantly reducing critical path latency, increasing the highest achievable operating frequency of the system, and ensuring that the 7th order LMS filter can achieve stable real-time processing on the FPGA platform.

[0075] In software serial filtering, each input sample must complete all multiplication, addition, and weight update operations sequentially before the next sample can be processed. This results in significant waiting and idle time during the computation, causing the overall latency to increase linearly with the filter order and the number of channels. In contrast, hardware parallel pipelined filtering divides the filtering computation into multiple processing stages and introduces pipeline registers between these stages, allowing different sampled data to proceed simultaneously in different processing stages, achieving overlapping data flow execution. This architecture can significantly improve system throughput while maintaining limited single-cycle computation latency, making it more suitable for online processing of multi-channel, high real-time surface electromyography (EMG) signals.

[0076] The embodiments described above in this application reduce the combinational logic depth and increase the system's maximum operating frequency by dividing the critical path in timing using registers, so that multiplication, addition trees, and update write-back are in different pipeline stages. In terms of data flow, sampling synchronization is achieved through enable signals and valid flags, ensuring that the calculation triggered by each input sample completes the corresponding y(n), e(n) output and w(n+1) write-back after a predetermined pipeline delay, ultimately realizing a "sampling-driven real-time closed-loop adaptive filtering" in a strict sense.

[0077] Reference Figure 8 As shown, in another embodiment of this application, a high-density surface electromyography (EMG) signal hardware filtering method based on FPGA is provided, which is implemented using the high-density surface EMG signal hardware filtering device based on FPGA in any of the above embodiments, specifically including: S100, through the sEMG signal input module, synchronously acquires multi-channel noisy surface electromyography signals d(n) and at least one reference noise signal X(n); S200: Receives noisy surface electromyography signal d(n) and at least one reference noise signal X(n) through the LMS adaptive filtering calculation module, and filters the received signals. The S300 and FPGA main control modules control the LMS adaptive filtering calculation module, which uses a fixed-point arithmetic system to process the acquired data and executes the LMS adaptive filtering algorithm through a parallel pipelined structure, and outputs the filtered error signal. The S400 buffers the filtered sEMG signal through the data buffer and output interface module and outputs it to an external processing device or host computer system.

[0078] This application addresses the characteristics of surface electromyography (sEMG) signals, such as weak amplitude, complex noise types, and high real-time requirements. It deploys the LMS adaptive filtering algorithm on an FPGA platform via a hardware data path. Through fixed-point quantization strategy, joint design of order and step size, and parallel pipeline structure, it achieves real-time closed-loop operation of adaptive filtering, thereby obtaining low-latency, configurable, and scalable sEMG adaptive filtering processing capabilities without relying on software computation of general-purpose processors.

[0079] Reference Figures 5 to 7 As shown, the sEMG signal output by the program on the host computer after hardware filtering is clearly visible. The sEMG signal without filtering has a lot of noise and the sEMG signal is not visible. The surface electromyography signal output after hardware filtering is buffered and organized, and the data is framed according to system requirements. The filtered surface electromyography signal is output to an external processing device or host computer system through an interface to realize subsequent analysis, display or storage.

[0080] Compared with traditional software-based filtering schemes, the above embodiments of this application leverage the advantages of FPGA in parallel processing and data flow control. This allows the system to simultaneously process 128 channels of signals. By utilizing fixed-point quantization and time-division multiplexing techniques, it ensures real-time performance while fully utilizing the FPGA's hardware resources for adaptive filtering calculations. Especially in sEMG multi-channel real-time monitoring, the proposed LMS adaptive filter not only exhibits high accuracy and stability but also maintains high filtering performance even in complex electromagnetic interference and low signal-to-noise ratio environments, ensuring signal validity and reliability.

[0081] The preferred features in the above embodiments can be used individually in any embodiment, or in any combination thereof, provided they do not conflict with each other. Furthermore, parts not described in detail in the embodiments can be implemented using existing technologies.

[0082] The foregoing has described some specific embodiments of this application. It should be understood that this application is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this application. The above-described preferred features can be used in any combination without conflict.

Claims

1. A high-density surface electromyography (EMG) signal hardware filtering device based on FPGA, characterized in that, include: The sEMG signal input module acquires multi-channel noisy surface electromyography signals and at least one reference noise signal. The LMS adaptive filtering calculation module is connected to the output of the sEMG signal input module. It is used to receive the noisy surface electromyography signal and the reference noise signal, and executes the LMS adaptive filtering algorithm through a fixed-point number arithmetic system and a parallel pipelined structure to output the filtered error signal. The data caching and output interface module is connected to the LMS adaptive filtering calculation module and is used to cache and output the surface electromyography signal filtered by the LMS adaptive filtering calculation module. The FPGA main control module is connected to the sEMG signal input module, the LMS adaptive filtering calculation module, and the data buffer and output interface module, and is used to control the operation of each module.

2. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 1, characterized in that, The sEMG signal input module includes multiple high-precision analog-to-digital converters, forming a multi-channel data acquisition array; In this configuration, at least one acquisition channel is configured to acquire the inherent noise of the acquisition circuit as the reference noise signal X(n), while the remaining channels acquire the noisy surface electromyography signal d(n).

3. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 1, characterized in that, The LMS adaptive filtering calculation module includes: an input processing module, a filtering calculation module, an error calculation module, and a weight update module; The input processing unit is connected to the output terminal of the sEMG signal input module, receives the digitized noisy surface electromyography signal d(n) and the reference noise signal X(n), and after sign expansion and amplitude normalization processing, outputs the processed signals to the filtering calculation unit, the error calculation unit and the weight update unit respectively. The filtering calculation unit receives the reference noise signal output by the input processing unit, calculates the filtered output y(n), and outputs it to the error calculation unit. The error calculation unit simultaneously receives the noisy surface electromyography signal output by the input processing unit and y(n) output by the filtering calculation unit, calculates the error signal e(n) and outputs it to the weight update unit. The weight update unit receives e(n) output by the error calculation unit and the reference noise signal output by the input processing unit, updates the weight coefficients, and then feeds them back to the filter calculation unit to form an adaptive filter closed-loop connection.

4. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 3, characterized in that, The LMS adaptive filtering calculation module adopts a fixed-point arithmetic system, and sets bit width control and quantization strategies at the input end, multiply-accumulate end and weight update end respectively; Specifically, the input processing unit performs symbol expansion and amplitude normalization on the digitized signal, ensuring that the normalized input samples meet the following requirements: ; In the filtering calculation unit, the weight coefficients are stored in a 32-bit signed fixed-point format, and the input sample and the weight coefficients are multiplied and accumulated to form an extended-width product; The bit width of the wide-width bit product is greater than the sum of the bit widths of the input sample and the weight coefficients; In the weight update unit, the weight coefficients are updated using the error signal and the step size factor. It adopts a 16-bit signed fixed-point format and is in negative power of 2 form, with an initial value of ; The weight update unit achieves the same result as the arithmetic shift operation. The multiplication operation can be adjusted in stages according to the convergence speed and steady-state error requirements.

5. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 4, characterized in that, In the weight update unit, the error signal e(n) and the weight update amount Δw(k) = μ e(n) X (n k), using extended bit-width operations; In the formula, X(n) is the step size parameter; k) is the reference noise signal at the nth time. Input sample at time k.

6. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 3, characterized in that, The filtering calculation unit uses a 7th-order adaptive FIR structure as a finite impulse response structure to model the interference noise channel in the surface electromyography signal. The 7th-order adaptive FIR structure operates based on the fixed-point arithmetic system. During the accumulation process, an accumulator structure with guard bits is used, and the multiplication and addition results are truncated and quantized before output, retaining the high significant bits and discarding the low decimal places.

7. A high-density surface electromyography signal hardware filtering device based on FPGA according to any one of claims 1-6, characterized in that, The LMS adaptive filtering calculation module adopts a parallel pipelined structure, which is a multi-channel parallel and single-channel multi-stage serial pipelined approach. Specifically, the filter output calculation, error calculation, and weight update are organized into a single-channel multi-stage pipeline, forming an adaptive filter closed loop within one sampling period. This loop allows for continuous data path processing of a single input sampling point, including filter output calculation, error calculation, weight update, and write-back.

8. The FPGA-based high-density surface electromyography signal hardware filtering device according to claim 7, characterized in that, The LMS adaptive filtering calculation module includes multiple LMS sub-modules configured in parallel. The LMS submodules are respectively connected to the noisy sEMG signals output by different sEMG signal input modules. The LMS submodules are time-division multiplexed by storing input data, filtered data and weight parameters. Each LMS submodule has a multi-stage pipeline formed by the filter output calculation, error calculation, and weight update.

9. A high-density surface electromyography signal hardware filtering device based on FPGA according to claim 7, characterized in that, The parallel pipelined structure divides the critical path using registers, so that multiplication, addition trees, and weight update write-back are in different pipeline stages. The parallel pipelined structure uses an enable signal and a valid flag to synchronize sampling, so that the computation triggered by each input sample completes filtering output, error calculation, and weight update after a predetermined pipeline delay.

10. A hardware filtering method for high-density surface electromyography (EMG) signals based on FPGA, employing the hardware filtering device for high-density surface EMG signals based on FPGA as described in any one of claims 1-9, characterized in that, include: Multi-channel noisy surface electromyography signals d(n) and at least one reference noise signal X(n) are simultaneously acquired through the sEMG signal input module. The LMS adaptive filtering calculation module receives a noisy surface electromyography signal d(n) and at least one reference noise signal X(n), and filters the received signals. The FPGA main control module controls the LMS adaptive filtering calculation module, which uses a fixed-point arithmetic system to process the acquired data and executes the LMS adaptive filtering algorithm through a parallel pipelined structure, and outputs the filtered error signal. The filtered sEMG signal is buffered through the data buffer and output interface module and then output to an external processing device or host computer system.

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