A variable sampling rate-based high-speed wideband signal playback method and device
By using a signal playback method based on variable sampling rate, interpolation, filtering, and digital up-conversion are performed using CPU and FPGA, which solves the problem of data adaptation at different sampling rates and achieves high-fidelity signal playback and hardware resource optimization.
Patent Information
- Application Number
- CN202610409726.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-10
AI Technical Summary
Existing signal playback equipment is difficult to adapt to data with different sampling rates, resulting in distortion of the playback signal waveform, and has high hardware computing resource requirements.
A variable sampling rate-based approach is adopted, which uses CPU to configure parameters and FPGA to perform interpolation, filtering and digital up-conversion to convert multiple low-rate data into parallel processing. Combined with multiple filter technologies, stable variable sampling rate operation is achieved.
It achieves high-fidelity signal playback, reduces the demand for hardware resources, and adapts to the playback needs of data with different sampling rates.
Smart Images
Figure CN122371990A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of signal playback technology, and more specifically, to a high-speed broadband signal playback method and device based on variable sampling rate. Background Technology
[0002] To enable the migration of electromagnetic environments in specific scenarios, electromagnetic wave signals in the environment can be collected and stored, and then the electromagnetic environment can be reproduced in other areas through signal playback technology, which greatly facilitates the testing of the working functions and performance of electronic information equipment in specific environments.
[0003] Since the sampling rates of data acquisition devices and signal playback devices may differ, the signal playback device needs to process the data according to the sampling rate of the data acquisition device to ensure that the played-back electromagnetic signal waveform is not distorted. Currently, there are many models of signal acquisition devices, with varying sampling frequencies and signal bandwidth capabilities. Users increasingly urgently need to reproduce electromagnetic environments using a unified playback device for electromagnetic signal data acquired from various devices. Therefore, researching a high-speed broadband signal playback method based on variable sampling rates is crucial for the high-fidelity construction of diverse and complex electromagnetic environments. Summary of the Invention
[0004] To address the challenge of adapting single signal playback devices to data with different sampling rates, improve the waveform fidelity of the playback signal, and reduce the hardware computing resource requirements for high-speed waveform data playback, this invention provides a high-speed broadband signal playback method and device based on variable sampling rate. This allows for flexible processing of digital waveform data with different sampling rates, enabling high-fidelity playback of generated radio frequency signals.
[0005] In a first aspect, the present invention provides a high-speed broadband signal playback method based on variable sampling rate, comprising: Configuration parameters; the configuration parameters include interpolation factor, filter parameters, and frequency code, etc. The original signal is interpolated based on the interpolation factor; The interpolated data is converted from serial to parallel to obtain multiple alternating parallel intermediate frequency data. Each intermediate frequency (IF) data stream is input into a multinomial filter, which filters the IF data according to the configured filter parameters. The filtered intermediate frequency data is digitally up-converted according to the configured frequency code; The data from each digital up-conversion circuit is converted into a playback radio frequency signal via parallel-to-serial conversion.
[0006] In a preferred embodiment, the CPU performs sampling rate matching and obtains the data interpolation factor L based on the ratio of the operating frequency of the target DAC chip to the sampling rate of the original signal.
[0007] In a preferred embodiment, the number of terms in the multi-term filter is selected according to the output mode configured in the DAC chip, and the coefficients of each term in the multi-term filter are determined based on the center frequency of the intermediate frequency data of the input multi-term filter.
[0008] In a preferred embodiment, the frequency code is determined based on the operating frequency of the target DAC chip.
[0009] In a preferred embodiment, the interpolation of the original signal according to the interpolation factor is: If the sampling rate is increased by a factor of L based on the interpolation factor L, then L-1 zeros will be inserted after each sample of the original signal.
[0010] In a preferred embodiment, the specific operation of the multiple filters filtering the intermediate frequency data according to the configuration parameters is as follows: The interpolated intermediate frequency data is grouped by phase, and only non-zero samples are retained. The non-zero samples of the corresponding phase are processed by the impulse response of each multiphase branch of the multi-phase filter, and finally the processing results of all multiphase branches are combined as the filtered intermediate frequency data.
[0011] In a preferred embodiment, the step of digitally up-converting the filtered intermediate frequency data according to the configured frequency code includes: Based on the configured frequency code, the filtered intermediate frequency data is digitally mixed with the carrier data generated by direct digital frequency synthesis, and then up-converted to the operating frequency of the target DAC chip.
[0012] In a preferred embodiment, the original signal is buffered using a first-in-first-out (FIFO) mechanism.
[0013] Secondly, the present invention provides a high-speed broadband signal playback device based on variable sampling rate, including a CPU and an FPGA; The CPU is used to configure parameters for the FPGA; the configuration parameters include interpolation factors, filter parameters, and frequency codes, etc. The FPGA includes: The interpolation module is used to interpolate the original signal according to the interpolation factor; The parallel-to-serial conversion module is used to convert the interpolated data into serial-to-parallel data to obtain multiple alternating parallel intermediate frequency data. Multiple multinomial filter modules are used to input each intermediate frequency (IF) data into a multinomial filter, and the multinomial filter filters the IF data according to the configured filter parameters; Multiple digital upconversion modules are used to digitally upconvert the filtered intermediate frequency data according to the configured frequency code; The parallel-to-serial conversion module is used to convert the digital up-converted data of each channel into a playback radio frequency signal via parallel-to-serial conversion.
[0014] In a preferred embodiment, the FPGA further includes: The FIFO module is used to buffer the raw signal using a first-in-first-out (FIFO) mechanism.
[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: This invention addresses the problem of playback waveform distortion caused by the inconsistency between waveform data sampling rate and playback sampling rate in traditional technical solutions. It transforms the variable sampling rate operation of single-channel high sampling rate data into parallel processing of multiple low-rate data, and then combines multiple filter technologies to achieve stable variable sampling rate operation inside the FPGA, thereby achieving the effect of realistically restoring digital waveforms to radio frequency signals.
[0016] Compared to traditional solutions, this invention utilizes the advantages of multiple filters to filter multiple low-rate data streams, so that data playback is no longer limited by the sampling data rate and the internal computing speed of the FPGA. It is more versatile and has lower requirements for hardware resources. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a high-speed broadband signal playback method and device based on variable sampling rate, provided in an embodiment of the present invention.
[0018] Figure 2 This is a flowchart of a high-speed broadband signal playback method based on variable sampling rate, provided for an embodiment of the present invention.
[0019] Figure 3 This is a schematic diagram of multiple filters in an embodiment of the present invention.
[0020] Figure 4 This is a playback signal test result diagram of an application example in an embodiment of the present invention. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0022] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0023] To ensure distortion-free playback waveforms, variable sampling rate processing is required for digital waveform data with different sampling rates. Based on the sampling rates of different signal acquisition devices, the CPU of the signal playback device calculates parameters such as interpolation factors, filter parameters, and frequency codes, and then sends the calculated parameters to the FPGA (Field Programmable Gate Array) for data processing. Simultaneously, under limited computing resources, the signal playback device must be capable of playing back high sampling rate (gigahertz and above) waveform data. This invention transforms the variable sampling rate operation of a single high sampling rate data stream into parallel processing of multiple low-rate data streams, combining multiple filter technologies to achieve stable variable sampling rate operation within the FPGA.
[0024] Therefore, for application scenarios where the waveform data sampling rate is lower than the playback sampling rate, in order to achieve data flow matching between lower-frequency data processing chips and higher-frequency ADC (analog-to-digital converter) and DAC (digital-to-analog converter) chips, such as... Figure 1-2 As shown, this embodiment of the invention provides a high-speed broadband signal playback method based on variable sampling rate, comprising the following steps: Step 1: Configure parameters; The configuration parameters include interpolation factors, filter parameters, and frequency codes, etc.; specifically: The CPU performs sampling rate matching and obtains the data interpolation factor L based on the ratio of the target DAC chip's operating frequency to the original signal's sampling rate. The number of terms in the multi-term filter is selected according to the output mode configured in the DAC chip, and the coefficients of each term in the multi-term filter are determined according to the center frequency of the intermediate frequency data of the input multi-term filter. The frequency code is determined based on the operating frequency of the target DAC chip.
[0025] Step 2: Interpolate the original signal according to the interpolation factor; Interpolation can increase the sampling rate of the data stream. If the sampling rate is increased by a factor of L based on the interpolation factor L, then L-1 zeros are inserted after each sample of the original signal. Therefore, the expression for the original signal is: The interpolated data expression is:
[0026] in, This is the interpolated data. The original signal is buffered using a First In First Out (FIFO) mechanism.
[0027] Step 3: Perform serial-to-parallel conversion on the interpolated data to obtain multiple alternating parallel intermediate frequency data; The above interpolation operation will compress the spectrum of the original signal and generate mirror frequency components. In order to reduce the pressure on the FPGA caused by high-speed data operation with a single high sampling rate, the present invention converts the interpolated single-channel sampled data into multiple alternating parallel intermediate frequency data, thereby reducing the required operation speed.
[0028] Step 4: Input each intermediate frequency (IF) data stream into a multinomial filter, which filters the IF data according to the configured filter parameters.
[0029] like Figure 3 As shown, based on the configured number of filter terms and filter coefficients, the multinomial filter is represented as:
[0030] in: It is the first multinomial filter. Impulse response of a multiphase branch.
[0031] It is a tap index for multi-phase branches.
[0032] The specific operation of the multiple filters filtering the intermediate frequency data according to the configuration parameters is as follows: Interpolated intermediate frequency data Group by phase, retaining only non-zero samples; Using the impulse response of each multiphase branch of a multinomial filter The non-zero samples of the corresponding phases are processed, and finally the processing results of all multi-phase branches are merged as the filtered intermediate frequency data, represented as:
[0033] in, This is the intermediate frequency data after filtering by multiple filters.
[0034] Compared to traditional interpolation filters, the multi-function filter designed in this embodiment of the invention reduces the number of multiplications and improves the operating efficiency of hardware resources through parallel computation of L multi-phase branches.
[0035] Step 5: Perform digital upconversion (DUC) on the filtered intermediate frequency data according to the configured frequency code. Specifically, Based on the configured frequency code, the filtered intermediate frequency data is digitally mixed with the carrier data generated by Direct Digital Frequency Synthesis (DDS) and up-converted to the operating frequency of the target DAC chip.
[0036] Step 6: Convert the digital up-converted data of each channel into a playback RF signal by passing it in parallel and serial.
[0037] Therefore, the intermediate frequency data after multi-channel filtering and digital up-conversion at low speed is converted into single-channel high-speed data through parallel-serial conversion, matching the operating frequency of the target DAC chip, thereby generating a high-fidelity playback RF signal.
[0038] Based on the above steps, the method of this invention fully utilizes the characteristics and capabilities of FPGA parallel processing, converting the variable sampling rate operation of a single-channel high-sampling-rate data into parallel processing of multiple-channel low-rate data. Then, interpolation, filtering, and digital up-conversion are performed on each of the multiple parallel data channels, employing multiple filters for filtering. Finally, the data stream with the changed sampling rate is transmitted to the DAC chip for waveform playback via parallel-to-serial conversion. Therefore, by converting the variable sampling rate operation of a single-channel high-sampling-rate data into parallel processing of multiple-channel low-rate data, combined with multiple filter technology, stable variable sampling rate operation can be achieved within the FPGA, adapting to the needs of playing back data with different sampling rates.
[0039] Here is an application example: The DAC chip is used to play back the linear frequency modulated signal waveform data (original signal center frequency is 1.2GHz, bandwidth is 20MHz) pre-acquired by the ADC chip. The DAC chip operates at a frequency of 4.5GHz and the ADC chip has a sampling rate of 500MHz.
[0040] According to an embodiment of the present invention, a high-speed broadband signal playback method based on variable sampling rate is provided, and its specific implementation process is as follows: (1) The CPU calculates the interpolation factor, filter parameters, and frequency code.
[0041] (2) The FPGA receives pre-collected digital waveform data through the SRIO switching chip. The data sampling rate is 500MHz, and the data is buffered through the FIFO module.
[0042] (3) Perform a 9-fold interpolation operation on the digital waveform data to meet the number of effective data points required by the signal at a rate of 4.5 GHz.
[0043] (4) The interpolated data is converted from serial to parallel. One 4.5GHz data channel is split into 16 alternating parallel 281.25MHz intermediate frequency data channels. While keeping the data rate required for the DAC chip output unchanged, the clock rate requirement for FPGA operation is reduced.
[0044] (5) Convolve the 16 intermediate frequency data with the constructed 16 filters to obtain the interpolated filtered data, thus eliminating the data waveform distortion introduced by interpolation.
[0045] (6) Mix the filtered 16-channel intermediate frequency data with the carrier data generated by 16 channels of DDS, and shift the spectrum to the original signal frequency through digital upconversion.
[0046] (7) By converting the 16 channels of 281.25MHz intermediate frequency data into 1 channel of 4.5GHz intermediate frequency data, the DAC chip is output to achieve playback of the original signal at a sampling rate of 4.5GHz.
[0047] The method of this invention has been applied to a certain type of equipment. The test and verification results of the radio frequency signal playback using the method of this invention are as follows: Figure 4 As shown, the implementation example verifies the correctness and engineering feasibility of the high-speed broadband signal playback method based on variable sampling rate.
[0048] Based on the same technological concept, such as Figure 1 As shown, this embodiment of the invention also provides a high-speed broadband signal playback device based on variable sampling rate, including a CPU and an FPGA; The CPU is used to configure parameters for the FPGA; the configuration parameters include interpolation factors, filter parameters, and frequency codes, etc. The FPGA includes: The interpolation module is used to interpolate the original signal according to the interpolation factor; the original signal is buffered using a first-in-first-out (FIFO) mechanism through the FIFO module. The parallel-to-serial conversion module is used to convert the interpolated data into serial-to-parallel data to obtain multiple alternating parallel intermediate frequency data. Multiple multinomial filter modules are used to input each intermediate frequency (IF) data into a multinomial filter, and the multinomial filter filters the IF data according to the configured filter parameters; Multiple digital upconversion modules are used to digitally upconvert the filtered intermediate frequency data according to the configured frequency code; The parallel-to-serial conversion module is used to convert the digital up-converted data of each channel into a playback radio frequency signal via parallel-to-serial conversion.
[0049] The working principles of the CPU, FPGA and their functional modules in the above-mentioned device can be referred to the description in the foregoing method embodiments, and will not be repeated here.
[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A high-speed broadband signal playback method based on variable sampling rate, characterized in that, include: Configuration parameters; the configuration parameters include interpolation factor, filter parameters, and frequency code, etc. The original signal is interpolated based on the interpolation factor; The interpolated data is converted from serial to parallel to obtain multiple alternating parallel intermediate frequency data. Each intermediate frequency (IF) data stream is input into a multinomial filter, which filters the IF data according to the configured filter parameters. The filtered intermediate frequency data is digitally up-converted according to the configured frequency code; The data from each digital up-conversion circuit is converted into a playback radio frequency signal via parallel-to-serial conversion.
2. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The CPU performs sampling rate matching and obtains the data interpolation factor L based on the ratio of the target DAC chip's operating frequency to the original signal's sampling rate.
3. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The number of terms in the multi-term filter is selected according to the output mode configured in the DAC chip, and the coefficients of each term in the multi-term filter are determined according to the center frequency of the intermediate frequency data of the input multi-term filter.
4. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The frequency code is determined based on the operating frequency of the target DAC chip.
5. The high-speed broadband signal playback method based on variable sampling rate according to claim 2, characterized in that, The interpolation of the original signal based on the interpolation factor is: If the sampling rate is increased by a factor of L based on the interpolation factor L, then L-1 zeros will be inserted after each sample of the original signal.
6. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The specific operation of the multiple filters filtering the intermediate frequency data according to the configuration parameters is as follows: The interpolated intermediate frequency data is grouped by phase, and only non-zero samples are retained. The non-zero samples of the corresponding phase are processed by the impulse response of each multiphase branch of the multi-phase filter, and finally the processing results of all multiphase branches are combined as the filtered intermediate frequency data.
7. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The step of digitally up-converting the filtered intermediate frequency data according to the configured frequency code includes: Based on the configured frequency code, the filtered intermediate frequency data is digitally mixed with the carrier data generated by direct digital frequency synthesis, and then up-converted to the operating frequency of the target DAC chip.
8. The high-speed broadband signal playback method based on variable sampling rate according to claim 1, characterized in that, The original signal is buffered using a first-in-first-out (FIFO) mechanism.
9. A high-speed broadband signal playback device based on variable sampling rate, characterized in that, Including CPU and FPGA; The CPU is used to configure parameters for the FPGA; the configuration parameters include interpolation factors, filter parameters, and frequency codes, etc. The FPGA includes: The interpolation module is used to interpolate the original signal according to the interpolation factor; The parallel-to-serial conversion module is used to convert the interpolated data into serial-to-parallel data to obtain multiple alternating parallel intermediate frequency data. Multiple multinomial filter modules are used to input each intermediate frequency (IF) data into a multinomial filter, and the multinomial filter filters the IF data according to the configured filter parameters; Multiple digital upconversion modules are used to digitally upconvert the filtered intermediate frequency data according to the configured frequency code; The parallel-to-serial conversion module is used to convert the digital up-converted data of each channel into a playback radio frequency signal via parallel-to-serial conversion.
10. The high-speed broadband signal playback device based on variable sampling rate according to claim 9, characterized in that, The FPGA also includes: The FIFO module is used to buffer the raw signal using a first-in-first-out (FIFO) mechanism.