Trench power field effect transistor assembly and method of manufacturing the same

Abstract

The present application provides a trench power MOSFET assembly and a manufacturing method thereof. The trench power MOSFET assembly includes a substrate, an epitaxial layer, a buffer region, a first type of trench MOSFET, a second type of trench MOSFET, and a trench capacitor. The epitaxial layer is disposed on the substrate, and the buffer region is formed in the epitaxial layer. The first type of trench MOSFET includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is located in the epitaxial layer, the first source electrode is located on a top surface of the epitaxial layer, and the first drain electrode is located on a bottom surface of the substrate. The second type of trench MOSFET includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is located in the epitaxial layer, the second source electrode and the second drain electrode are both located on the top surface of the epitaxial layer, the first gate electrode is electrically connected to the second drain electrode, and the first source electrode is electrically connected to the second source electrode. The two ends of the trench capacitor are electrically connected to the first drain electrode and the second gate electrode, respectively.

Description

Technical Field

[0001] This invention relates to a field-effect transistor (FET) assembly and its manufacturing method, and more particularly to a trench-type power FET assembly and its manufacturing method. Background Technology

[0002] Generally, trench MOSFETs have low on-state voltage and are commonly used in high-frequency, low-voltage power devices. However, trench MOSFETs only have a single drain terminal voltage on the back of the chip, making it difficult to separate different drain terminals for two or more different trench MOSFETs to be used in different circuits on the same chip, thus limiting application flexibility. Furthermore, trench MOSFETs are susceptible to the Miller effect during switching, which can lead to false turn-on. This can result in a large voltage being injected into the drain when the transistor turns on, potentially damaging the device and affecting its reliability. Therefore, improving the applicability and reliability of trench MOSFETs is a problem that needs to be solved. Summary of the Invention

[0003] This invention relates to a trench-type power MOSFET assembly and its manufacturing method, which improves application flexibility and reliability, and has a simplified manufacturing process to reduce manufacturing costs.

[0004] According to an embodiment of the present invention, a trench power field-effect transistor (FET) assembly includes a substrate, an epitaxial layer, a buffer, a first type trench field-effect transistor (FET), a second type trench field-effect transistor (FET), and a trench capacitor. The epitaxial layer is disposed on the substrate and has a first conductivity type. The buffer is formed in the epitaxial layer and has a second conductivity type, the second conductivity type being the opposite of the first conductivity type. The first type trench field-effect transistor includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is located in the epitaxial layer, the first source electrode is located on the top surface of the epitaxial layer, and the first drain electrode is located on the bottom surface of the substrate. The second type trench field-effect transistor includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is located in the epitaxial layer, the second source electrode and the second drain electrode are both located on the top surface of the epitaxial layer, the first gate electrode and the second drain electrode are electrically connected, and the first source electrode and the second source electrode are electrically connected. The two ends of the trench capacitor are electrically connected to the first drain electrode and the second gate electrode, respectively. The buffer is configured to electrically isolate the first drain electrode and the second drain electrode.

[0005] According to an embodiment of the present invention, a method for manufacturing a trench power field-effect transistor (FET) assembly includes the following steps: An epitaxial layer is formed on a substrate, wherein the epitaxial layer has a first conductivity type and has a first region, a second region, and a third region. A buffer zone is formed in the second region of the epitaxial layer, wherein the buffer zone has a second conductivity type, the second conductivity type being opposite to the first conductivity type. A first trench is formed in the first region, a second trench is formed in the second region, and a third trench is formed in the third region. A first gate electrode of a first-type trench field-effect transistor is formed in the first trench. A second gate electrode of a second-type trench field-effect transistor is formed in the second trench. A first electrode of a trench capacitor is formed in the third trench. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0007] Figure 1A This is a top view schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0008] Figure 1B This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0009] Figure 1C This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0010] Figure 2 This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0011] Figure 3 This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0012] Figure 4A This is a top view schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0013] Figure 4B This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention;

[0014] Figures 5A to 5J This is a cross-sectional schematic diagram of the manufacturing process of a trench power MOSFET assembly according to an embodiment of the present invention.

[0015] Explanation of icon numbers

[0016] 10, 20, 30, 40: Trench power MOSFET assembly; 100: Substrate; 100b: Bottom surface; 110: Epitaxial layer; 110t: Top surface; 112: Buffer zone; 114: Drift region; 115a, 115b: Body region; 116a, 116b: Source doped region; 117: Drain doped region; 120, 121a, 121b, 122a, 122b, 124a, 124b, 1 29, 140: Dielectric layer; 126a, 126b: Gate dielectric layer; 128: Insulating layer; 130: Conductive material; 132a, 132b: Conductive layer; 139: Fill layer; 152b: Gate plug; 154a, 154b: Source plug; 156: Drain plug; 158: Conductive plug; 162: Conductive interconnect layer; A-A', B-B', C-C': Section lines; D1: First drain electrode;

[0017] D2: Second drain electrode; FET1: Type I trench field-effect transistor; FET2: Type II trench field-effect transistor; E1: First electrode; E2: Second electrode; G1: First gate electrode; G2: Second gate electrode; PR1: Patterned photoresist layer; PS: Protective structure; R1: First region; R2: Second region; R3: Third region; S1: First source electrode; S2: Second source electrode; SG1, SG2: Shielded gate; T1: First trench; T1', T2', T2”: Trench; T2: Second trench; T3: Third trench; TC: Trench capacitor; TS1, TS2: Termination structure; tk1, tk2: Width; x, y: Direction. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0019] In this article, terms such as “comprising,” “including,” “containing,” and “having” are open-ended terms, meaning “including but not limited to.”

[0020] When terms such as "first" and "second" are used to describe elements, they are used only to distinguish elements and do not limit the order or importance of the devices. Therefore, in some cases, a first element may also be referred to as a second element, and a second element may also be referred to as a first element, which does not exceed the scope of this invention.

[0021] Figure 1A This is a top view schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention; Figure 1B This is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention; Figure 1CThis is a cross-sectional schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention. Figure 1B It can include along Figure 1A A cross-sectional schematic diagram of one embodiment of the cutting along section lines A-A' and B-B'. Figure 1C It can be along Figure 1A A cross-sectional schematic diagram of one embodiment of the section line C-C' cut.

[0022] Please refer to Figure 1A , Figure 1B and Figure 1CThe trench power MOSFET assembly 10 includes a substrate 100, an epitaxial layer 110, a buffer zone 112, a first-type trench field-effect transistor (FET1), a second-type trench field-effect transistor (FET2), and a trench capacitor TC. The epitaxial layer 110 is disposed on the substrate 100 and has a first conductivity type. The epitaxial layer 110 may have a first region R1, a second region R2, and a third region R3. The buffer zone 112 is disposed in the second region R2 of the epitaxial layer 110 and has a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. A first-type trench field-effect transistor (FET1) includes a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. FET1 is a vertical field-effect transistor, with its first gate electrode G1 located in the first region R1 of the epitaxial layer 110, its first source electrode S1 located above the top surface 110t of the epitaxial layer 110, and its first drain electrode D1 located on the bottom surface 100b of the substrate 100. A second-type trench field-effect transistor (FET2) includes a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. FET2 is a lateral field-effect transistor, with its second gate electrode G2 located in the second region R2 of the epitaxial layer 110, and its second source electrode S2 and second drain electrode D2 both located above the top surface 110t of the epitaxial layer 110. A trench capacitor TC is located in the third region R3 of the epitaxial layer 110. The first gate electrode G1 of the first type trench field-effect transistor FET1 is electrically connected to the second drain electrode D2 of the second type trench field-effect transistor FET2. The first source electrode S1 of the first type trench field-effect transistor FET1 is electrically connected to the second source electrode S2 of the second type trench field-effect transistor FET2. Furthermore, the two ends (or the two electrodes E1 and E2) of the trench capacitor TC are electrically connected to the first drain electrode D1 of the first type trench field-effect transistor FET1 and the second gate electrode G2 of the second type trench field-effect transistor FET2, respectively. In this way, the vertical field-effect transistor (i.e., the first type trench field-effect transistor FET1), the lateral field-effect transistor (i.e., the second type trench field-effect transistor FET2), and the trench capacitor TC can be integrated onto the same chip, creating an integrated circuit. This reduces the possibility of false conduction of the trench power field-effect transistor assembly 10 due to the Miller effect, thereby improving its reliability.

[0023] In some embodiments, the substrate 100 is a semiconductor substrate, such as a silicon substrate or other suitable semiconductor substrate. In some embodiments, the substrate 100 has a first conductivity type and is electrically connected to a first drain electrode D1. That is, the substrate 100 can be regarded as the drain doped region of a first type trench field-effect transistor FET1, which can extend on the bottom surface 110b of the first region R1, the second region R2 and the third region R3 of the epitaxial layer 110.

[0024] In some embodiments, the buffer 112 is configured to electrically isolate the first drain electrode D1 from the second drain electrode D2. The second-type trench field-effect transistor FET2 is located within the buffer 112 and is electrically isolated from the first drain electrode D1. This allows for easy integration of different trench field-effect transistors on the same chip to meet the needs of different circuit designs, thereby increasing the application flexibility of the trench power MOSFET assembly 10.

[0025] In some embodiments, substrate 100 may be an N+ substrate, epitaxial layer 110 may be an N- epitaxial layer, buffer layer 112 may be a P- buffer, and first trench field-effect transistor FET1 and second trench field-effect transistor FET2 may be N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs). In other embodiments, second trench field-effect transistor FET2 may be a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET), but the present invention is not limited thereto.

[0026] In some embodiments, the trench power MOSFET assembly 10 further includes a dielectric layer 140 disposed on the epitaxial layer 110 and located between the epitaxial layer 110 and the first source electrode S1, between the epitaxial layer 110 and the second source electrode S2, and between the epitaxial layer 110 and the second drain electrode D2.

[0027] In some embodiments, the second region R2 is located between the first region R1 and the third region R3, and the second type trench field-effect transistor FET2 is located between the first type trench field-effect transistor FET1 and the trench capacitor TC.

[0028] In some embodiments, the first region R1 of the epitaxial layer 110 has a first trench T1, and the first gate electrode G1 of the first type trench field-effect transistor FET1 is located in the first trench T1. In some embodiments, there are multiple first trenches T1 arranged in the y-direction and extending in the x-direction, such as... Figure 1A As shown.

[0029] In some embodiments, the first type trench field-effect transistor FET1 further includes a shielding gate SG1 disposed in the first trench T1 and located below the first gate electrode G1 to provide charge balance for the epitaxial layer 110.

[0030] In some embodiments, the first-type trench field-effect transistor FET1 further includes a body region 115a and a source-doped region 116a. The body region 115a is formed in the first region R1 of the epitaxial layer 110 and is located between adjacent first trenches T1, while the source-doped region 116a is formed in the body region 115a and is close to the top surface 110t of the epitaxial layer 110. In some embodiments, the body region 115a is substantially located on both sides of the first gate electrode G1, and its depth does not exceed the bottom surface of the first gate electrode G1, thereby allowing the channel of the first-type trench field-effect transistor FET1 to be formed in the body region 115a. In some embodiments, the first source electrode S1 can be electrically connected to the source-doped region 116a through a source plug 154a passing through the dielectric layer 140.

[0031] In some embodiments, the body region 115a has, for example, a second conductivity type (e.g., P-type), and the source doped region 116a has, for example, a first conductivity type (e.g., N-type). In some embodiments, the source doped region 116a may be an N+ doped region.

[0032] In some embodiments, dielectric layer 122a may be disposed in the first trench T1 and located between shielding gate SG1 and epitaxial layer 110 to electrically isolate shielding gate SG1 from epitaxial layer 110. Dielectric layer 124a may be disposed in the first trench T1 and located between shielding gate SG1 and first gate electrode G1 to electrically isolate shielding gate SG1 from first gate electrode G1. Gate dielectric layer 126a may be disposed in the first trench T1 and located between first gate electrode G1 and epitaxial layer 110 (or body region 115a) to electrically isolate first gate electrode G1 from body region 115a.

[0033] In some embodiments, the gate dielectric layer 126a has a substantially uniform thickness, and the thickness of the gate dielectric layer 126a is less than the thickness of the dielectric layer 122a.

[0034] In some embodiments, the second region R2 of the epitaxial layer 110 has a second trench T2, and the second gate electrode G2 of the second type trench field-effect transistor FET2 is located in the second trench T2. In some embodiments, the second trench T2 extends along the y-direction and is located in the buffer zone 112.

[0035] In some embodiments, the second type trench field-effect transistor FET2 further includes a shielding gate SG2 disposed in the second trench T2 and located below the second gate electrode G2 to provide charge balance for the epitaxial layer 110.

[0036] In some embodiments, the second-type trench field-effect transistor FET2 further includes a body region 115b, a source doped region 116b, and a drain doped region 117. The body region 115b is formed in the buffer zone 112 and is located on one side of the second trench T2. The source doped region 116b is formed in the body region 115b and is close to the top surface 110t of the epitaxial layer 110. The drain doped region 117 is formed in the buffer zone 112 and is close to the top surface 110t of the epitaxial layer 110 and the other side of the second trench T2, opposite to the body region 115b and the source doped region 116b. That is, the source doped region 116b and the drain doped region 117 are located in the epitaxial layer 110 on both sides of the second trench T2 (or the second gate electrode G2).

[0037] In some embodiments, the drain doped region 117 may be located between the first type trench field-effect transistor FET1 and the second gate electrode G2, and the source doped region 116b may be located between the trench capacitor TC and the second gate electrode G2.

[0038] In some embodiments, the body region 115b is substantially located on one side of the second gate electrode G2, and its depth does not exceed the bottom surface of the second gate electrode G2, thereby allowing the channel of the second type trench field-effect transistor FET2 to be formed in the body region 115b. In some embodiments, the second source electrode S2 can be electrically connected to the source doped region 116b through the source plug 154b passing through the dielectric layer 140, and the second drain electrode D2 can be electrically connected to the drain doped region 117 through the drain plug 156 passing through the dielectric layer 140. That is, the drain doped region 117 can be located in the epitaxial layer 110 between the second drain electrode D2 and the second gate electrode G2.

[0039] In some embodiments, the body region 115b has, for example, a second conductivity type (e.g., P-type), and the source doped region 116b and the drain doped region 117 have, for example, a first conductivity type (e.g., N-type). In some embodiments, the source doped region 116b and the drain doped region 117 may be N+ doped regions.

[0040] In some embodiments, the second-type trench field-effect transistor FET2 further includes a drift region 114 formed in a buffer zone 112 and surrounding the second trench T2. The drift region 114 has, for example, a first conductivity type (e.g., N-type). In some embodiments, the drift region 114 may be an N-doped region.

[0041] In some embodiments, dielectric layer 122b may be disposed in the second trench T2 and located between shielding gate SG2 and epitaxial layer 110 to electrically isolate shielding gate SG2 from epitaxial layer 110. Dielectric layer 124b may be disposed in the second trench T2 and located between shielding gate SG2 and second gate electrode G2 to electrically isolate shielding gate SG2 from second gate electrode G2. Gate dielectric layer 126b may be disposed in the second trench T2 and located between second gate electrode G2 and epitaxial layer 110 (or body region 115b) to electrically isolate second gate electrode G2 from epitaxial layer 110 (or body region 115b).

[0042] In some embodiments, the gate dielectric layer 126b has a substantially uniform thickness, and the thickness of the gate dielectric layer 126b is less than the thickness of the dielectric layer 122b. However, the invention is not limited thereto, and in other embodiments, the gate dielectric layer 126b may have a non-uniform thickness.

[0043] In some embodiments, the third region R3 of the epitaxial layer 110 has a third trench T3. The first electrode E1 of the trench capacitor TC is located in the third trench T3, the second electrode E2 of the trench capacitor TC may be formed by a portion of the epitaxial layer 110, and the insulating layer 128 of the trench capacitor TC is disposed in the third trench T3 and located between the first electrode E1 and the epitaxial layer 110 to form a capacitor in the third region R3 of the epitaxial layer 110. In some embodiments, the third trench T3 extends along the y-direction and is aligned with the second trench T2 in the x-direction.

[0044] In some embodiments, the second drain electrode D2 of the second-type trench field-effect transistor FET2 can extend from the second region R2 to the first region R1, and is electrically connected to the first gate electrode G1 of the first-type trench field-effect transistor FET1 through the gate plug 152a passing through the dielectric layer 140. Therefore, the portion of the second drain electrode D2 extending into the first region R1 and electrically connected to the first gate electrode G1 can also be regarded as the conductive connection layer of the first gate electrode G1.

[0045] In some embodiments, the trench power MOSFET assembly 10 further includes a conductive connection layer 162 disposed on the dielectric layer 140 and spanning the second region R2 and the third region R3. The conductive connection layer 162 electrically connects the second gate electrode G2 of the second-type trench field-effect transistor FET2 to the first electrode E1 of the trench capacitor TC via a gate plug 152b and a conductive plug 158. Specifically, the gate plug 152b passes through the dielectric layer 140 to electrically connect the conductive connection layer 162 to the second gate electrode G2, and the conductive plug 158 passes through the dielectric layer 140 to electrically connect the conductive connection layer 162 to the first electrode E1.

[0046] In some embodiments, the trench power MOSFET assembly 10 further includes a termination structure TS1 located in a first region R1 of the epitaxial layer 110 and a termination structure TS2 located in a second region R2 of the epitaxial layer 110. The termination structure TS1 may be disposed in the first region R1 on the side of the first type trench field-effect transistor FET1 near the second region R2 or the second type trench field-effect transistor FET2 (i.e., on the outside of the first type trench field-effect transistor FET1). The termination structure TS2 may be disposed in the second region R2 on the side of the second type trench field-effect transistor FET2 near the third region R3 or the trench capacitor TC.

[0047] In some embodiments, the first region R1 of the epitaxial layer 110 further includes a trench T1' extending in the x-direction and aligned with the first trench T1 in the y-direction. A termination structure TS1 is disposed in the trench T1'. In some embodiments, the termination structure TS1 includes a dielectric layer 121a and a conductive layer 132a disposed in the trench T1', wherein the dielectric layer 121a is located between the conductive layer 132a and the epitaxial layer 110.

[0048] In some embodiments, the second region R2 of the epitaxial layer 110 further includes a trench T2' extending in the y-direction and aligned with the second trench T2 in the x-direction. A termination structure TS2 is disposed in the trench T2'. In some embodiments, the termination structure TS2 includes a dielectric layer 121b and a conductive layer 132b disposed in the trench T2', wherein the dielectric layer 121b is located between the conductive layer 132b and the epitaxial layer 110.

[0049] In some embodiments, the trench T2' or the terminal structure TS2 is located in the drift region 114, that is, the drift region 114 surrounds the second gate electrode G2 and the terminal structure TS2.

[0050] In some embodiments, a termination structure TS1 is disposed between a first type trench field-effect transistor FET1 and a second type trench field-effect transistor FET2. A termination structure TS2 is disposed between the second type trench field-effect transistor FET2 and a trench capacitor TC.

[0051] Figure 2 This is a cross-sectional schematic diagram of a trench-type power MOSFET assembly according to an embodiment of the present invention. It must be noted that... Figure 2 The embodiments follow Figure 1A-1C The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figure 2 It can be along Figure 1A A cross-sectional view of another embodiment of the second zone R2 partially cut by section line B-B'.

[0052] Please refer to Figure 2 The main difference between the trench power MOSFET assembly 20 and the trench power MOSFET assembly 10 is that the second type trench field-effect transistor FET2 of the trench power MOSFET assembly 20 is a PMOSFET. The trench power MOSFET assembly 20 does not have a drift region, so the second trench T2 and trench T2' are located in the buffer 112. That is to say, the second gate electrode G2 and the termination structure TS2 are surrounded by the buffer 112.

[0053] In this embodiment, the body region 115b has a first conductivity type (e.g., N-type), and the source doped region 116b and the drain doped region 117 have a second conductivity type (e.g., P-type). In some embodiments, the source doped region 116b and the drain doped region 117 may be P+ doped regions.

[0054] Figure 3 This is a cross-sectional schematic diagram of a trench-type power MOSFET assembly according to an embodiment of the present invention. It must be noted that... Figure 3 The embodiments follow Figure 1A-1C The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figure 3 It can include along Figure 1A A cross-sectional view of another embodiment of the section cut by section lines A-A' and B-B'.

[0055] Please refer to Figure 3 The main difference between the trench power MOSFET assembly 30 and the trench power MOSFET assembly 10 is that, in the trench power MOSFET assembly 30, the gate dielectric layer 126b on both sides of the second gate electrode G2 of the second type trench field-effect transistor FET2 has different thicknesses. The width tk1 of the gate dielectric layer 126b on the side closer to the second drain electrode D2 (or drain doped region 117) is greater than the width tk2 of the gate dielectric layer 126b on the side farther from the second drain electrode D2 (or drain doped region 117). In other words, the width tk2 of the gate dielectric layer 126b on the side closer to the source doped region 116b is less than the width tk1 of the gate dielectric layer 126b on the side closer to the drain doped region 117. This increases the breakdown voltage of the drain side of the second type trench field-effect transistor FET2, thereby improving the breakdown voltage of the second type trench field-effect transistor FET2.

[0056] Figure 4A This is a top view schematic diagram of a trench power MOSFET assembly according to an embodiment of the present invention; Figure 4BThis is a cross-sectional schematic diagram of a trench-type power MOSFET assembly according to an embodiment of the present invention. It must be noted that... Figures 4A-4B The embodiments follow Figure 1A-1C The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figure 4B It can include along Figure 4A A cross-sectional view of another embodiment of the section cut by section lines A-A' and D-D'.

[0057] Please refer to Figure 4A and Figure 4B The main difference between the trench power MOSFET assembly 40 and the trench power MOSFET assembly 10 is that the trench power MOSFET assembly 40 also includes a protection structure PS, which is disposed in the second region R2 of the epitaxial layer 110 and located on the side of the second trench T2 near the second drain electrode D2 (or drain doped region 117). That is, the protection structure PS can be disposed in the epitaxial layer 110 between the second gate electrode G2 and the second drain electrode D2 of the second type trench field-effect transistor FET2, or it can be disposed between the second gate electrode G2 of the first type trench field-effect transistor FET1 and the second type trench field-effect transistor FET2. This increases the breakdown voltage of the drain side of the second type trench field-effect transistor FET2, thereby improving its breakdown voltage.

[0058] In some embodiments, the second region R2 of the epitaxial layer 110 further has a trench T2”, which extends in the y-direction and is aligned with the second trench T2 in the x-direction. A protective structure PS is disposed in the trench T2”. In some embodiments, the protective structure PS includes a dielectric layer 129 and a filler layer 139 disposed in the trench T2”, wherein the dielectric layer 129 is located between the filler layer 139 and the epitaxial layer 110. In some embodiments, the filler layer 139 may be an insulating material or a conductive material, and the present invention is not limited thereto.

[0059] Figures 5A to 5J This is a cross-sectional schematic diagram illustrating the manufacturing process of a trench-type power MOSFET assembly according to an embodiment of the present invention. It must be noted that... Figures 5A to 5J The embodiments follow Figure 1A-1C The component reference numerals and partial content of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here. Figures 5A to 5J It can be along Figure 1A A cross-sectional view diagram showing the section cut along section lines A-A' and B-B'.

[0060] Please refer to Figure 5A An epitaxial layer 110 is formed on a substrate 100, wherein the epitaxial layer 110 has a first region R1, a second region R2, and a third region R3, with the second region R2 located between the first region R1 and the third region R3. The epitaxial layer 110 can be formed by an epitaxial growth process. In some embodiments, a dopant having a first conductivity type (e.g., N-type) may be introduced during the epitaxial growth process to give the epitaxial layer 110 the first conductivity type. In some embodiments, the N-type dopant may include phosphorus, arsenic, antimony, or the like.

[0061] Then, a buffer zone 112 is formed in the second region R2 of the epitaxial layer 110. The buffer zone 112 can be formed by implanting a dopant having a second conductivity type (e.g., P-type) through an ion implantation process. In some embodiments, the P-type dopant may include boron, aluminum, gallium, or the like.

[0062] Please refer to Figure 5B A drift region 114 is formed in buffer 112. The drift region 114 can be formed by implanting a dopant having a first conductivity type (e.g., N-type) using an ion implantation process. In other embodiments, the drift region 114 may not be formed in buffer 112, such as... Figure 2 As shown.

[0063] Please refer to Figure 5C A first trench T1 is formed in a first region R1 of the epitaxial layer 110, a second trench T2 is formed in a second region R2 of the epitaxial layer 110, and a third trench T3 is formed in a third region R3 of the epitaxial layer 110. For example, a mask layer (not shown, such as a hard mask layer and / or a photoresist layer) can be formed on the epitaxial layer 110 first, then the surfaces of the epitaxial layer 110 to be formed (the first trench T1, the second trench T2, and the third trench T3) can be exposed using photolithography and etching processes. Subsequently, the mask layer is used as an etching mask to etch the epitaxial layer 110 (e.g., anisotropic etching) to form the first trench T1, the second trench T2, and the third trench T3. The mask layer is then removed.

[0064] In some embodiments, a first trench T1 is configured to form a first type trench field-effect transistor FET1, a second trench T2 is configured to form a second type trench field-effect transistor FET2, and a third trench T3 is configured to form a trench capacitor TC.

[0065] In some embodiments, trenches T1' may be formed in the first region R1 of the epitaxial layer 110, and trenches T2' may be formed in the second region R2 of the epitaxial layer 110, wherein trenches T1' and T2' are respectively configured to form terminal structures TS1 and TS2. The method for forming trenches T1' and T2' may be the same as the method for forming the first trench T1, the second trench T2, and the third trench T3, and may be formed under the same manufacturing steps as the first trench T1, the second trench T2, and the third trench T3.

[0066] In some embodiments, a trench T2" (not shown, but to be referenced) may also be formed in the second region R2 of the epitaxial layer 110. Figure 4B The groove T2” is configured to form the protective structure PS. The method of forming the groove T2” is the same as the method of forming the first groove T1, the second groove T2 and the third groove T3, and can be formed in the same manufacturing steps as the first groove T1, the second groove T2 and the third groove T3.

[0067] Please refer to Figure 5D A dielectric layer 120 is formed on the epitaxial layer 110. For example, the dielectric layer 120 may be conformally deposited on the surface of a plurality of trenches (including a first trench T1, a second trench T2, a third trench T3, trench T1', trench T2', and trench T2 (if any)) and on the top surface of the epitaxial layer 110 by a deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.). In some embodiments, the dielectric layer 120 comprises silicon oxide or other suitable dielectric material.

[0068] Then, conductive material 130 is formed in multiple trenches (including first trench T1, second trench T2, third trench T3, trench T1', trench T2', and trench T2 (if any)). For example, conductive material 130 can be deposited in the multiple trenches and on the top surface of epitaxial layer 110 by a deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.), and then the conductive material 130 on the top surface of epitaxial layer 110 can be removed using a planarization process. In some embodiments, the material of conductive material 130 may include polysilicon or other suitable conductive materials.

[0069] Please refer to Figure 5EA patterned photoresist layer PR1 is formed on the epitaxial layer 110, covering the third trench T3, trench T1', and trench T2' (and trench T2, if any), and exposing the first trench T1 and the second trench T2. The conductive material 130 exposed by the patterned photoresist layer PR1 is etched to remove a portion of the conductive material 130 located in the first trench T1 and the second trench T2. The conductive material 130 remaining in the first trench T1 forms a shielding gate SG1, and the conductive material 130 remaining in the second trench T2 forms a shielding gate SG2. In addition, the conductive material 130 located in trench T1' forms the filling layer 132a of the terminal structure TS1, the conductive material 130 located in trench T2' forms the filling layer 132b of the terminal structure TS2, and the conductive material 130 located in the third trench T3 forms the first electrode E1 of the trench capacitor TC. Since the first electrode E1 of the trench capacitor TC can share the manufacturing process with the first type trench field-effect transistor FET1 and the second type trench field-effect transistor FET2, no additional manufacturing process is required to form the trench capacitor TC, thus simplifying the process and reducing manufacturing costs.

[0070] In embodiments where the epitaxial layer 110 has a trench T2", the conductive material 130 located in the trench T2" can be formed as a filling layer 139 (not shown, but refer to) of the protective structure PS. Figure 4B However, the present invention is not limited thereto. In other embodiments, the dielectric layer 120 may fill the trench T2” without filling the conductive material 130, such that the filling layer 139 of the protective structure PS may be composed of the dielectric layer 120 located in the trench T2”.

[0071] Please refer to Figure 5F Additional dielectric material is deposited in the first trench T1 and the second trench T2 to form a dielectric layer 124a on the surface of the shielding gate SG1 and a dielectric layer 124b on the surface of the shielding gate SG2. The dielectric layer 120 exposed on the sidewalls of the first trench T1 and the second trench T2 and on the top surface 110t of the epitaxial layer 110 is then removed by an etching process to expose portions of the sidewalls of the first trench T1 and the second trench T2 and the top surface 110t of the epitaxial layer 110. In some embodiments, dielectric layers 124a and 124b may comprise silicon oxide or other suitable dielectric materials.

[0072] In some embodiments, the dielectric layer 120 remaining in the first trench T1 is formed as the dielectric layer 122a of a first-type trench field-effect transistor FET1, and the dielectric layer 120 remaining in the second trench T2 is formed as the dielectric layer 122b of a second-type trench field-effect transistor FET2. Furthermore, the dielectric layer 120 located in trench T1' can be formed as the dielectric layer 121a of a termination structure TS1, the dielectric layer 120 located in trench T2' can be formed as the dielectric layer 121b of a termination structure TS2, and the dielectric layer 120 located in the third trench T3 can be formed as the insulating layer 128 of a trench capacitor TC. In embodiments where the epitaxial layer 110 has a trench T2', the dielectric layer 120 located in trench T2' can be formed as the dielectric layer 129 (not shown, but refer to) of a protective structure PS. Figure 4B ).

[0073] Please refer to Figure 5G A gate dielectric layer 126a is formed on the exposed first trench T1, and a gate dielectric layer 126b is formed on the sidewall of the exposed second trench T2. For example, the gate dielectric layer 126a and gate dielectric layer 126b can be formed using a thermal oxidation process. In some embodiments, the gate dielectric layer 126a may extend from the sidewall of the first trench T1 to the exposed top surface 110t of the first region R1 of the epitaxial layer 110, and the gate dielectric layer 126b may extend from the sidewall of the second trench T2 to the exposed top surface 110t of the second region R2 of the epitaxial layer 110. In some embodiments, the gate dielectric layer 126a and gate dielectric layer 126b may comprise silicon oxide or other suitable dielectric materials.

[0074] Please refer to Figure 5H Conductive material can be deposited in a first trench T1 and a second trench T2 using a deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.) to form the first gate electrode G1 of a first-type trench field-effect transistor (FET1) in the first trench T1 and the second gate electrode G2 of a second-type trench field-effect transistor (FET2) in the second trench T2. In some embodiments, the materials of the first gate electrode G1 and the second gate electrode G2 may include polysilicon or other suitable conductive materials.

[0075] In some embodiments, a patterned photoresist layer (not shown) may be formed on the epitaxial layer 110 to cover the first region R1, the third region R3, and a portion of the second gate electrode G2, thereby exposing the portion of the second gate electrode G2 near the predetermined drain doped region (i.e., the drain doped region 117 described later). The second gate electrode G2 not covered by the patterned photoresist layer can then be removed by an etching process to form an opening (not shown) that exposes a portion of the second gate dielectric layer 126b and dielectric layer 124b located in the second trench T2. Subsequently, an additional dielectric layer is formed in the opening to thicken the portion of the second gate dielectric layer 126b near the predetermined drain doped region, such as... Figure 3 As shown.

[0076] Please refer to Figure 5I A body region 115a is formed in the first region R1 of the epitaxial layer 110, and a body region 115b is formed in the second region R2 of the epitaxial layer 110. Body regions 115a and 115b are formed in different process steps, and there is no restriction on their formation order. Body regions 115a can be formed first and then 115b can be formed, or vice versa.

[0077] For example, a patterned photoresist layer (not shown) can be formed on the epitaxial layer 110 using a first photomask (not shown) to cover the second region R2 and the third region R3 of the epitaxial layer 110 and expose the location of the predetermined body region 115a in the first region R1 of the epitaxial layer 110. Then, a dopant of a second conductivity type, such as P-type, is implanted into the top surface of the epitaxial layer 110 that is not covered by the patterned photoresist layer by an ion implantation process to form the body region 115a in the epitaxial layer between adjacent first trenches T1.

[0078] Alternatively, a patterned photoresist layer (not shown) can be formed on the epitaxial layer 110 using a second photomask (not shown) to cover the first region R1 and the third region R3 of the epitaxial layer 110 and expose the predetermined location of the body region 115b in the second region R2 of the epitaxial layer 110. Then, a dopant of a second conductivity type, such as P-type, is implanted into the top surface of the epitaxial layer 110 that is not covered by the patterned photoresist layer by an ion implantation process to form the body region 115b in the epitaxial layer on one side of the second trench T2 (e.g., the side near the third region R3).

[0079] In embodiments where no drift region is formed in the second region R2, the body region 115b can be formed by implanting a dopant having a first conductivity type (e.g., N-type) into the epitaxial layer 110.

[0080] Please refer to Figure 5JA source doped region 116a is formed in body region 115a, a source doped region 116b is formed in body region 115b, and a drain doped region 117 is formed in drift region 114. The source doped regions 116a, 116b, and 117 can be formed in the same process step. For example, a patterned photoresist layer (not shown) can be formed on the epitaxial layer 110 using a photomask (not shown) to expose the locations where the source doped regions 116a, 116b, and 117 are to be formed. Then, a dopant of a first conductivity type, such as N-type, is implanted into the top surface of the epitaxial layer 110, which is not covered by the patterned photoresist layer, via ion implantation to form the source doped region 116a in body region 115a, the source doped region 116b in body region 115b, and the drain doped region 117 in drift region 114.

[0081] In embodiments where no drift region is formed in the second region R2, the source doped region 116a, source doped region 116b, and drain doped region 117 are formed under different process steps. The source doped region 116b and drain doped region 117 can be formed by implanting a dopant with a second conductivity type (e.g., P-type) into the second region R2 through another ion implantation process.

[0082] Next, please refer to Figure 1B and Figure 1C A dielectric layer 140 is formed on the epitaxial layer 110. Source plugs 154a and 154b, gate plugs 152a and 152b, drain plug 156, and conductive plug 158 are formed in the dielectric layer 140 through photolithography, etching, and deposition processes. Subsequently, a first source electrode S1, a second source electrode S2, a second drain electrode D2, and a conductive connection layer 162 are formed on the dielectric layer 140 through deposition, photolithography, and etching processes. The first source electrode S1 is physically and electrically connected to the source plug 154a, the second source electrode S2 is physically and electrically connected to the source plug 154b, the second drain electrode D2 is physically and electrically connected to the drain plug 156 and the gate plug 152a, and the conductive connection layer 162 is physically and electrically connected to the conductive plug 158 and the gate plug 152b.

[0083] In some embodiments, source plug 154a passes through dielectric layer 140 and the source doped region 116a and a portion of body region 115a below it. Source plug 154b passes through dielectric layer 140 and the source doped region 116b and a portion of body region 115b below it. Gate plug 152a passes through dielectric layer 140 and a portion of first gate electrode G1 below it. Gate plug 152b passes through dielectric layer 140 and a portion of second gate electrode G2 below it. Drain plug 156 passes through dielectric layer 140 and a portion of drain doped region 117 below it. Conductive plug 158 passes through dielectric layer 140 and a portion of first electrode E1 below it.

[0084] In some embodiments, the dielectric layer 140 may include silicon oxide or other suitable dielectric materials. In some embodiments, the source plugs 154a, 154b, gate plugs 152a, 152b, drain plug 156, conductive plug 158, first source electrode S1, second source electrode S2, second drain electrode D2, and conductive interconnect layer 162 may be made of metals (e.g., copper, aluminum, tungsten, titanium, silver, alloys thereof, combinations thereof, etc.) or other suitable conductive materials.

[0085] Based on this, the manufacturing of the trench power MOSFET assembly 10 can be roughly completed.

[0086] Based on the above, the trench power MOSFET assembly of the present invention integrates a first-type trench MOSFET, a second-type trench MOSFET, and a trench capacitor onto a single chip to form an integrated circuit, thereby improving the application flexibility and reliability of the trench power MOSFET assembly. Furthermore, the trench capacitor can share the manufacturing process with both the first-type and second-type trench MOSFETs, thus eliminating the need for additional manufacturing processes to form the trench capacitor, simplifying the process and reducing manufacturing costs.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A trench-type power MOSFET assembly, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate and has a first region, a second region, a third region, and a first conductivity type; A buffer is formed in the second region of the epitaxial layer and has a second conductivity type, which is opposite to the first conductivity type. A first type of trench field-effect transistor includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is located in the first region of the epitaxial layer, the first source electrode is located on the top surface of the epitaxial layer, and the first drain electrode is located on the bottom surface of the substrate. A second type of trench field-effect transistor includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is located in the buffer zone, the second source electrode and the second drain electrode are both located on the top surface of the epitaxial layer, the first gate electrode and the second drain electrode are electrically connected, and the first source electrode and the second source electrode are electrically connected; and A trench capacitor is located in the third region of the epitaxial layer, with its two ends electrically connected to the first drain electrode and the second gate electrode, respectively. The buffer is configured to electrically isolate the first drain electrode from the second drain electrode.

2. The trench-type power MOSFET assembly according to claim 1, characterized in that, The second type of trench field-effect transistor is located between the first type of trench field-effect transistor and the trench capacitor.

3. The trench-type power MOSFET assembly according to claim 1, characterized in that, It also includes a terminal structure disposed between the second type of trench field-effect transistor and the trench capacitor.

4. The trench-type power MOSFET assembly according to claim 3, characterized in that, The second type of trench field-effect transistor further includes a drift region formed in the buffer and surrounding the second gate electrode and the termination structure, wherein the drift region has a first conductivity type.

5. The trench-type power MOSFET assembly according to claim 1, characterized in that, The second type of trench field-effect transistor further includes a drain doped region formed in the buffer zone and located in the epitaxial layer between the second drain electrode and the second gate electrode, and the drain doped region is electrically connected to the second drain electrode.

6. The trench power MOSFET assembly according to claim 1, characterized in that, It also includes a protective structure disposed in the epitaxial layer between the second gate electrode and the second drain electrode of the second type trench field-effect transistor.

7. The trench power MOSFET assembly according to claim 1, characterized in that, The second gate electrode is disposed in the trench of the epitaxial layer, wherein the second type trench field-effect transistor further includes: A shielding gate is disposed in the trench of the epitaxial layer and located below the second gate electrode.

8. The trench power MOSFET assembly according to claim 1, characterized in that, The second gate electrode is disposed in the trench of the epitaxial layer, wherein the second type trench field-effect transistor further includes: A gate dielectric layer is disposed in the trench and located between the second gate electrode and the epitaxial layer, wherein the width of the gate dielectric layer on the side closer to the second drain electrode is greater than the width of the gate dielectric layer on the side farther from the second drain electrode.

9. A method for manufacturing a trench-type power MOSFET assembly, characterized in that, include: An epitaxial layer is formed on a substrate, wherein the epitaxial layer has a first conductivity type and the epitaxial layer has a first region, a second region and a third region; A buffer is formed in the second region of the epitaxial layer, wherein the buffer has a second conductivity type that is opposite to the first conductivity type; A first trench is formed in the first region, a second trench is formed in the second region, and a third trench is formed in the third region; The first gate electrode of a first type of trench field-effect transistor is formed in the first trench. The second gate electrode of the second type trench field-effect transistor is formed in the second trench; as well as The first electrode of a trench capacitor is formed in the third trench.

10. The method for manufacturing a trench-type power MOSFET assembly according to claim 9, characterized in that, Also includes: A drift region is formed in the buffer zone of the epitaxial layer, wherein the drift region has a first conductivity type, and wherein a second trench is formed in the drift region.

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