A BMC reset method, a BMC, and a BMC reset system

Abstract

The application provides a BMC reset method, a BMC and a BMC reset system. The method comprises the following steps: in response to receiving a reset instruction, resetting a reset flag bit of a reset flag register to zero; performing a logical AND operation on the reset reset flag bit and a target bit of a command register of a PCIe endpoint device to clear the target bit, and the target bit being zero is used to make the PCIe endpoint device intercept a host access request; and in response to completion of the logical AND operation, performing a reset. The application adds a reset flag register, resets a reset flag bit of the reset flag register to zero before resetting the BMC, and performs a logical AND operation on the reset flag bit and a target bit of a command register of a PCIe endpoint device to forcibly clear the target bit, so that all access requests of the host are intercepted during the reset, and problems such as a host read request timeout, a device being mistakenly removed or a system hanging due to BMC memory initialization are avoided, and the stability and reliability of a server system are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a BMC reset method, a BMC, and a BMC reset system. Background Technology

[0002] The Baseboard Management Controller (BMC) is a critical management component in a server system. It monitors temperature, power supply voltage, and power consumption; logs events such as fan errors, power supply errors, and system errors; and performs functions such as fan adjustment and system throttling control. Furthermore, the BMC also handles the server's display functionality. Since servers have relatively low display requirements, the display capabilities provided by the BMC chip are sufficient, eliminating the need for an external dedicated graphics card and saving server space.

[0003] In scenarios where the BMC (Browser Memory Management) is used for display functionality, the server uses a portion of the BMC chip's memory as video memory. The host transmits video memory data to the BMC via a high-speed Peripheral Component Interconnect Express (PCIe) channel. When the BMC restarts, its memory needs to be reinitialized, and the video memory data is cleared, resulting in a black screen. Before the memory is fully initialized, the BMC cannot process read / write video memory requests sent by the host. Failure to write video memory requests will prevent the display from updating, and failure to read video memory requests will cause PCIe request timeouts on the host side. If there are a large number of read video memory requests from the host during the BMC restart, multiple timeout errors may cause the host software to misjudge a PCIe link failure, leading to the removal of the current PCIe device, resulting in the display function not recovering even after the BMC restarts. Furthermore, a large number of timeout errors may also directly cause the host system to hang, affecting the normal operation of the server. Summary of the Invention

[0004] This application provides a BMC reset method, a BMC, and a BMC reset system to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this application, a BMC reset method is provided, the method comprising: In response to receiving a reset command, the reset flag bit in the reset flag register is reset to zero; The reset restart flag is logically ANDed with the target bit of the command register of the PCIe endpoint device to clear the target bit to zero. The target bit being zero is used to enable the PCIe endpoint device to intercept host access requests. Upon completion of the aforementioned logic and operation, a reset is performed.

[0006] In one possible implementation, the method further includes: The system receives a hard reset signal sent by a complex programmable logic device (CPLD); wherein, when the CPLD detects an abnormal operation of the BMC, it resets the restart flag bit of the restart flag register to zero, performs a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device, and then sends out the hard reset signal. In response to the hard reset signal, a reset is performed.

[0007] In one possible implementation, performing a logical AND operation between the reset restart flag and the target bit of the command register of the PCIe endpoint device includes: The reset restart flag and the set instruction are sent to the PCIe endpoint device so that the PCIe endpoint device responds to the set instruction by performing a logical AND operation between the target bit in the command register and the reset restart flag.

[0008] In one possible implementation, performing a logical AND operation between the reset restart flag and the target bit of the command register of the PCIe endpoint device includes: The reset restart flag is sent to the PCIe endpoint device so that the PCIe endpoint device performs a logical AND operation between the target bit of the command register and the reset restart flag according to the fixed setting logic.

[0009] In one embodiment, the target bit includes a memory space enable bit and an input / output space enable bit; the memory space enable bit is used to control the host's read / write access requests to the memory space, and the input / output space enable bit is used to control the host's read / write access requests to the input / output space.

[0010] In one possible implementation, the resetting process includes: Reset will be performed after a preset time.

[0011] In one possible implementation, the resetting process includes: A soft reset signal is output so that the receiving end of the soft reset signal receives the soft reset signal and performs a reset. The receiving end includes a double data rate synchronous dynamic random access memory, a video graphics array module, a PCIe endpoint device, and a hardware module associated with the BMC.

[0012] In one possible implementation, the method further includes: In response to the completion of the reset, the restart flag is set to one, and the set restart flag is logically ANDed with the target bit in the command register of the PCIe endpoint device to keep the target bit at its default value. The default value of the target bit is used to enable the PCIe endpoint device to resume normal reception of access requests from the host.

[0013] According to a second aspect of this application, a BMC is provided, including a processor and a double-rate synchronous dynamic random access memory, a video graphics array module, and a PCIe endpoint device respectively connected to the processor; wherein the processor is used to execute the methods described in this application.

[0014] According to a third aspect of this application, a BMC reset system is provided, comprising: The aforementioned BMC; The CPLD, connected to the BMC, is used to trigger a reset operation of the BMC in response to the detection of an abnormal operation of the BMC.

[0015] According to a fourth aspect of this application, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0016] According to a fifth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0017] The BMC reset method, BMC, and BMC reset system of this application, in response to receiving a reset command, reset the restart flag bit of the restart flag register to zero; perform a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device to clear the target bit to zero, the target bit being zero is used to enable the PCIe endpoint device to intercept host access requests; in response to the completion of the logical AND operation, a reset is performed. By adding a restart flag register and resetting its restart flag bit to zero before BMC reset, and performing a logical AND operation between this flag bit and the target bit of the command register of the PCIe endpoint device to forcibly clear the target bit, all host access requests are intercepted during the reset period, avoiding problems such as host read request timeouts, accidental removal of PCIe devices, or system hangs caused by BMC memory initialization, thus improving the stability and reliability of the server system.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0019] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0020] Figure 1 This diagram illustrates the hardware principle block diagram of a general-purpose server implementing display functionality using a BMC. Figure 2 A schematic diagram illustrating the implementation flow of the BMC reset method provided in an embodiment of this application is shown; Figure 3 A schematic diagram of the composition structure of the BMC reset system provided in an embodiment of this application is shown; Figure 4 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0021] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Figure 1 This diagram illustrates the hardware principle block diagram of a general-purpose server implementing display functionality using a BMC. Figure 1As shown, the architecture of the BMC that implements the display function includes a central processing unit (CPU), a complex programmable logic device (CPLD), and the BMC. The BMC integrates an advanced RISC machine (ARM) processor, a PCIe peripheral component interconnect express end point (PCIe EP), a video graphics array (VGA) module, double data rate synchronous dynamic random access memory (DDR), and two logical AND gates.

[0023] Specifically, the CPLD outputs the BMC hardware reset signal BMC_RST_N and the power-on reset signal PWR_ON_RST_N; the ARM outputs the soft reset signal SOFT_RST_N; and the CPU outputs the PCIe reset signal PERST_N. Figure 1 The inputs of the right-hand AND gate are connected to BMC_RST_N, PWR_ON_RST_N, and SOFT_RST_N, and the outputs are connected to the reset pins rst_n of the ARM, VGA, and DDR, respectively. The inputs of the left-hand AND gate are connected to PWR_ON_RST_N and PERST_N, and the outputs are connected to the reset pins rst_n of the PCIe EP. The CPU communicates with the PCIe EP through the PCIe bus. The PCIe EP is bidirectionally connected to the VGA module, and the VGA module is bidirectionally connected to the DDR.

[0024] The host CPU transmits display data to the BMC via the PCIe bus. The PCIe EP in the BMC receives the display data and transmits it to the VGA module. The VGA module processes the data, writes it to DDR, and reads the data from DDR to achieve local or remote display. The PCIe EP and VGA module are decoupled from the BMC's ARM processor; their operation requires no configuration or interaction from the ARM. The PCIe EP is only controlled by the output signals of the left-hand AND gate, responding only to PWR_ON_RST_N and the CPU's PERST_N output. The VGA module, DDR, and ARM processor are only controlled by the output signals of the right-hand AND gate, responding to BMC_RST_N, PWR_ON_RST_N, and SOFT_RST_N. DDR serves as both the running memory of the ARM processor in the BMC and a portion of its space is used as host video memory.

[0025] Based on the aforementioned hardware architecture, the BMC's ARM processor runs an operating system independent of the host CPU. During ARM operation, it can output SOFT_RST_N, triggering a synchronous reset of the ARM processor, DDR, and VGA module via a right-hand AND gate. The PCIeEP, however, is unaffected by this soft reset signal and continues normal operation during the ARM reset and restart process. At this time, the host CPU can continuously interact with the DDR memory area via the PCIe bus and VGA module. However, it cannot respond to requests from the CPU until the DDR has completed its reinitialization. For CPU-issued memory write requests, the DDR cannot update data, and the display cannot refresh; for CPU-issued memory read requests, the DDR cannot return data, resulting in timeout errors on the CPU side. A large number of consecutive timeout errors will cause the CPU-side system software to determine the PCIe... If the VGA link fails, to avoid interference with other business applications, the CPU-side software may directly remove the PCIe VGA virtual device from the BMC. Even if the BMC subsequently resets and restarts, and the DDR returns to normal operation, the display function cannot be automatically restored. Furthermore, different CPU architectures or operating systems have varying tolerances for timeout errors. A large number of timeout errors occurring in a short period can also cause the host system to crash, severely impacting the stable operation of other core server services.

[0026] Therefore, to address the aforementioned deficiencies, this application provides a BMC reset method, a BMC, and a BMC reset system. This method can be executed by an ARM processor within the BMC, or by an electronic device with a deployed BMC.

[0027] Figure 2 A schematic diagram illustrating the implementation flow of the BMC reset method provided in this application embodiment is shown.

[0028] refer to Figure 2 This application provides a BMC reset method, the method comprising: Operation 101: In response to receiving a reset command, the reset flag bit of the reset flag register is reset to zero.

[0029] When the BMC's operating system or firmware detects a scenario requiring a reboot, such as receiving a firmware upgrade request, experiencing a recoverable anomaly in system operation, or an administrator issuing a proactive reboot command through the management interface, the system kernel or service process will generate a software reset instruction, which will notify the BMC's ARM processor by writing to registers or calling a reset function.

[0030] After receiving a reset command, the ARM processor triggers pre-reboot preparation operations by configuring the reboot flag bit in the reboot flag register to zero (logic 0). The reboot flag register is a hardware register added in this application to control PCIe endpoint device access permissions and avoid host access anomalies during reset. It is deployed inside the BMC, and its output is connected to the command register pin of the PCIe endpoint device, allowing it to output level signals for logical operations.

[0031] Operation 102 performs a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device to clear the target bit to zero. A target bit of zero is used to enable the PCIe endpoint device to intercept host access requests.

[0032] The BMC's ARM processor communicates with the PCIe endpoint device. The reset flag outputs a level signal, which performs a logical AND operation with the target bit in the PCIe endpoint device's command register. The target bit controls the PCIe endpoint device's access rights to and responses to access requests from the host CPU. When the target bit is 0, the host access request is intercepted; when the target bit is a default value, such as 1, the host access request is responded to normally. The logical AND operation is a hardware-level bitwise operation implemented using hardware AND gates, and the reset flag level directly participates in the output control of the target bit.

[0033] Operation 103, in response to the completion of the logical AND operation, executes a reset.

[0034] After the target bit is cleared, the BMC triggers an internal reset operation. At this time, the target bit of the PCIe endpoint device is in a cleared state. Access requests sent by the host CPU to the BMC, such as video memory read / write requests and I / O access requests, will be uniformly intercepted or responded to by the PCIe endpoint device according to the PCIe protocol specification. There will be no situation where no response is given after the request is sent, completely avoiding link timeout errors caused by the CPU waiting for a long time without a response. After the reset action is executed, the hardware modules inside the BMC (such as PCIe EP, VGA module, DDR) complete hardware initialization, register configuration and link restoration in sequence. After all the controlled hardware modules of the BMC have completed initialization, the BMC reset and restart process officially ends.

[0035] Thus, this embodiment of the application adds a restart flag register and resets its restart flag to zero before BMC reset. This flag is then logically ANDed with the target bit of the PCIe endpoint device command register to force the target bit to be cleared. This intercepts all access requests from the host during the reset period, avoiding problems such as host read request timeouts, accidental removal of PCIe devices, or system hangs caused by BMC memory initialization, thereby improving the stability and reliability of the server system.

[0036] In one embodiment of this application, the BMC reset method further includes: receiving a hard reset signal sent by a complex programmable logic device (CPLD); wherein, when the CPLD detects an abnormal operation of the BMC, it resets the restart flag bit of the restart flag register to zero, performs a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device, and then sends a hard reset signal; and performs a reset in response to the hard reset signal.

[0037] The aforementioned implementation applies to scenarios where the BMC operating system is not yet hangable, in which case the BMC's ARM processor can actively configure the restart flag register. However, when the BMC experiences a system hang, the ARM cannot perform any software configuration operations and requires external hardware for reset. In server systems, the BMC typically continuously outputs a heartbeat signal to the CPLD. The CPLD monitors this heartbeat signal to determine if the BMC is operating normally. If the CPLD detects an abnormal heartbeat signal (e.g., the signal does not toggle for a long time), it considers the BMC to have experienced a software hang. In this case, the CPLD does not immediately reset the BMC, but instead actively sets the restart flag bit in the BMC's internal restart flag register to zero through interfaces such as general purpose input / output (GPIO) ports or general purpose asynchronous transceiver (UART), and ensures that this zero value is logically ANDed with the target bit of the PCIe endpoint device command register. This operation can be performed by the CPLD directly writing to the register or by configuring the BMC's internal hardware logic through the interface.

[0038] After completing the above configuration, the CPLD generates a hard reset signal and sends it to the BMC. Upon receiving the hard reset signal, the BMC performs a reset operation. Since the restart flag has been cleared before the reset, the PCIe endpoint device is already in a state of blocking host access requests. Therefore, even if the BMC is stuck and unable to configure itself, a timeout error on the host side can still be avoided during the reset process. This implementation achieves a safe reset in the event that the BMC is completely unresponsive.

[0039] In one embodiment of this application, performing a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device includes: sending the reset restart flag bit and a set instruction to the PCIe endpoint device, so that the PCIe endpoint device responds to the set instruction by performing a logical AND operation between the target bit in the command register and the reset restart flag bit.

[0040] Specifically, in this embodiment, a software-configurable logical AND operation can be used to clear the target bit. The BMC's ARM processor is connected to the configuration space of the PCIe endpoint device via an internal bus. When the ARM needs to perform a logical AND operation, it first writes the reset reset flag bit to a temporary register or directly uses it as an operand, and simultaneously sends a specific "set instruction" to the PCIe endpoint device. This instruction can be a write operation to the PCIe endpoint device's internal command register to trigger the execution of the logical AND operation. After receiving the instruction, the PCIe endpoint device actively reads the target bit in the command register, performs a logical AND operation with it and the reset flag bit sent by the ARM, and writes the result back to the target bit. Since the reset flag bit is 0, the result of the operation must be 0, thus clearing the target bit. The advantage of this method is its high flexibility; the BMC can selectively execute logical AND operations according to different scenarios without requiring continuous hardware occupation of logic gate resources.

[0041] In one embodiment of this application, performing a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device includes: sending the reset restart flag bit to the PCIe endpoint device so that the PCIe endpoint device performs a logical AND operation between the target bit of the command register and the reset restart flag bit according to the fixed setting logic.

[0042] Specifically, in this embodiment, the target bit can also be cleared using hardware-fixed logic and operations. An AND gate or equivalent combinational logic circuit can be pre-designed inside the PCIe endpoint device. The two inputs of this circuit are connected to the target bit output of the command register and the output of the reset flag register, respectively. Its output serves as the actual control signal for whether host access is allowed. The BMC's ARM only needs to write the reset reset flag bit into the reset flag register, and the output level of this register will be directly sent to one input of the AND gate. Since the hardware logic runs continuously in real time, without any instruction trigger, the output of the AND gate immediately becomes 0, equivalent to clearing the target bit. In this method, the value of the target bit in the command register itself is not modified (it remains 1 as previously configured by the host), but after passing through the AND gate, the actual enabled signal is always 0. The advantages of this method are fast response speed, no software delay, and no occupation of bus bandwidth, making it particularly suitable for reset scenarios with high real-time requirements.

[0043] In one embodiment of this application, the target bit includes a memory space enable bit and an input / output space enable bit; the memory space enable bit is used to control the host's read / write access requests to the memory space, and the input / output space enable bit is used to control the host's read / write access requests to the input / output space.

[0044] Specifically, the configuration space of a PCIe endpoint device contains a Command register. The Memory Space Enable and I / O Space Enable bits in this register control the PCIe endpoint device's response behavior to Memory Type (MEM) requests and Input / Output Type (IO) requests initiated by the host, respectively. According to the PCIe protocol specification: when the Memory Space Enable bit is 1, the PCIe endpoint device processes incoming MEM type data packet requests normally (including read and write operations); when this bit is 0, it returns an "Unsupported Request (UR)" response to MEM read requests and discards MEM write requests directly. Similarly, when the I / O Space Enable bit is 1, the endpoint device processes IO type requests normally; when this bit is 0, it returns a UR response to IO requests.

[0045] In this embodiment of the application, the output of the dedicated restart flag register is connected to the Command register logic of the PCIe endpoint device and performs a logical AND operation with the memory space enable bit and the input / output space enable bit therein. Specifically, before the BMC performs a reset, the BMC or CPLD first configures the restart flag register to 0. At this time, the result of the logical AND operation is: (memory space enable bit) AND 0=0, and (input / output space enable bit) AND 0=0, which is equivalent to forcibly clearing the target bit to zero. In this way, utilizing the standard behavior specified in the PCIe protocol when the enable bit is 0—"return UR for read requests, discard for write requests"—the PCIe endpoint device will uniformly intercept or respond to all newly sent memory and I / O access requests from the host, thereby preventing timeout errors. Therefore, even during the BMC's DDR reinitialization, the host will not experience link timeouts or system hangs due to waiting for a response.

[0046] In one embodiment of this application, performing a reset includes: waiting for a preset time before performing a reset.

[0047] Specifically, after clearing the restart flag, the PCIe endpoint device begins to intercept newly arriving host requests, returning a UR or discarding them. However, at this time, there may still be old requests that were received before the restart flag was cleared and have not yet been processed. For example, there may be incomplete video memory write operations or unflushed caches in the PCIe endpoint device, VGA module, and DDR. If the BMC reset is triggered immediately after the restart flag is cleared, these old requests in progress may be forcibly interrupted, resulting in incomplete responses or inconsistent states on the host side. Therefore, this implementation inserts a preset waiting time after the restart flag is cleared and before the actual reset is executed. The length of this preset time should be at least sufficient to complete the normal processing of all previously received requests, including data return, status update, and cache refresh. The preset time can be a fixed empirical value configured according to actual needs, or it can be dynamically configured by the BMC according to the current server system status (such as the depth of the PCIe pending request queue). This application does not make specific limitations on this, as long as the time can ensure that old requests are processed completely.

[0048] In one embodiment of this application, performing a reset includes: outputting a soft reset signal so that a receiving end of the soft reset signal receives the soft reset signal and performs a reset. The receiving end includes a double data rate synchronous dynamic random access memory, a video graphics array module, a PCIe endpoint device, and a hardware module associated with the BMC.

[0049] Specifically, after clearing the aforementioned restart flag and waiting for the preset time, the BMC's ARM processor or reset control logic actively outputs a soft reset signal. This soft reset signal is sent simultaneously or sequentially to key hardware modules within the BMC via the chip's internal reset distribution network, including the DDR, VGA modules, PCIe endpoint devices, and other hardware modules associated with the BMC, such as the clock management unit, interrupt controller, and DMA engine. Upon receiving the soft reset signal, each of these modules executes its internal reset operation, restoring its state machine, configuration registers, cache queues, and incomplete transactions to their initial power-on state. After the reset is complete, each module exits the reset state sequentially, the BMC reloads the firmware, and resumes normal operation, completing the reboot.

[0050] In one embodiment of this application, the BMC reset method further includes: in response to the completion of the reset, setting the restart flag to one, and performing a logical AND operation between the set restart flag and the target bit in the command register of the PCIe endpoint device, so that the target bit is restored to the default value, and the target bit being restored to the default value is used to enable the PCIe endpoint device to resume normal reception of CPU access requests.

[0051] Specifically, after the BMC reset process is completed and all hardware modules have initialized and entered normal working state, it is necessary to restore the host's normal access to the BMC's video memory and I / O space. To do this, the BMC resets the reset flag bit in the reset flag register to 1. Since the internal AND gates of the PCIe endpoint device continuously perform a logical AND operation between this reset flag bit and the target bit in the command register, when the reset flag bit becomes 1, the result of the logical AND operation is restored to: target bit AND 1 = target bit. At this time, the actual value of the target bit is entirely determined by the value set by the host through the PCIe configuration write operation. Typically, the host sets these two enable bits to 1 when enumerating devices to allow normal access. Therefore, the target bit is essentially restored to the default value expected by the host (usually 1), and the PCIe endpoint device resumes normal reception and processing of memory and I / O access requests initiated by the host, including video memory read and write operations. At this point, the BMC reset process is complete, and the display function and other functions relying on PCIe communication are restored to normal.

[0052] Figure 3 A schematic diagram of the composition structure of the BMC reset system provided in an embodiment of this application is shown.

[0053] Based on the above-described BMC reset method, this application provides a BMC including a processor and a double-data-rate synchronous dynamic random access memory, a video graphics array module, and a PCIe endpoint device, all connected to the processor. The processor is an ARM processor used to execute the aforementioned BMC reset method.

[0054] Based on the aforementioned BMC, this application also provides a BMC system, which includes the aforementioned BMC and a CPLD. The CPLD is connected to the BMC and is used to trigger a reset operation of the BMC in response to detecting an abnormal operation of the BMC.

[0055] refer to Figure 3 Compared to existing BMC display function implementation architectures, the system design in this application introduces a reboot flag register (reboot_flag_n) and correspondingly introduces two logical AND gates within the PCIe endpoint device to achieve real-time interaction between the reboot flag bit and the target bit. The upper AND gate receives the I / O space enable bit from the command register and the reboot flag bit (reboot_flag_n) from the reboot flag register; the lower AND gate receives the memory space enable bit from the command register and the reboot flag bit (reboot_flag_n) from the reboot flag register. The outputs of the two AND gates jointly control whether the PCIe endpoint device allows I / O and memory access requests from the host side to pass through.

[0056] The following section provides a detailed explanation of the BMC reset process, which can be divided into two scenarios: BMC normal operation and BMC hang. 1) BMC Normal Operation: After detecting a reset command, the ARM processor first clears the reboot flag register reboot_flag_n (sets it to 0). At this time, the outputs of both AND gates become 0. The PCIe endpoint device begins to intercept all subsequent I / O and memory access requests sent by the host. Read requests return a UR, and write requests are discarded. The ARM processor waits for a preset time to ensure that old requests received before reboot_flag_n is cleared are processed normally. After the wait is over, the ARM processor outputs a soft reset signal r_st_n, which is simultaneously sent to various hardware modules such as the DDR, VGA module, and PCIe endpoint device. Each hardware module performs reset and initialization. After the reset is complete, the software configures reboot_flag_n to 1, the outputs of the two AND gates return to the original values ​​of the target bits, the PCIe endpoint device resumes normal reception of host access, and the display function is restored.

[0057] 2) BMC Hang: The CPLD actively clears the reboot flag register `reboot_flag_n` inside the BMC via GPIO or UART interface. After this clearing operation takes effect, the outputs of the two logical AND gates in the PCIe endpoint device become 0, immediately starting to intercept new access requests initiated by the host. The CPLD waits for a preset time before sending a hard reset signal to the BMC. Upon receiving the hard reset signal, the BMC performs reset and initialization of each hardware module. Since the reboot flag was cleared before the reset, host access is effectively intercepted during the reset period, and no timeout error occurs. After the reset is complete, the BMC starts normally, the software configuration `reboot_flag_n` is set to 1, and normal access is restored.

[0058] The BMC reset system of this application, by adding a restart flag register configuration operation, utilizes the characteristics of the PCIe protocol standard to truncate the PCIe requests sent by the host at the PCIe endpoint device when the BMC is reset. This avoids the timeout problem caused by the DDR being unable to respond normally to the host's read and write video memory requests when the BMC is reset, reduces the impact of the BMC reset on the host side, and improves the stability of the server.

[0059] The description of the BMC or BMC reset system in this application is similar to that in the above method embodiments, and has similar beneficial effects, therefore it will not be repeated. For any technical details not covered in the BMC or BMC reset system provided in this application, please refer to... Figures 1 to 2 The meaning is understood in accordance with the description of any of the accompanying drawings.

[0060] It should be noted that the technical solution of this application is not limited to the VGA display service processing flow in the above embodiments. The technical concept of this application, "intercepting host access requests by performing a logical AND operation between the restart flag bit and the target bit of the PCIe command register before reset," can also be extended to other device designs that use PCIe interfaces, such as solid-state drives (SSDs) and USB controllers. Equivalent substitutions or adaptive adjustments made by those skilled in the art based on the technical principles of this application for different application scenarios are all within the protection scope of this application.

[0061] According to embodiments of this application, this application also provides an electronic device and a readable storage medium. The electronic device includes the aforementioned BMC or is equipped with the aforementioned BMC reset system. The computer-readable storage medium stores a computer program that, when executed by a processor, can implement the aforementioned BMC reset method.

[0062] Figure 4 A schematic block diagram of an example electronic device 200 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0063] like Figure 4 As shown, the electronic device 200 includes a computing unit 201, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 202 or a computer program loaded from a storage unit 208 into a random access memory (RAM) 203. The RAM 203 may also store various programs and data required for the operation of the electronic device 200. The computing unit 201, ROM 202, and RAM 203 are interconnected via a bus 204. An input / output (I / O) interface 205 is also connected to the bus 204.

[0064] Multiple components in electronic device 200 are connected to I / O interface 205, including: input unit 206, such as keyboard, mouse, etc.; output unit 207, such as various types of displays, speakers, etc.; storage unit 208, such as disk, optical disk, etc.; and communication unit 209, such as network card, modem, wireless transceiver, etc. Communication unit 209 allows electronic device 200 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0065] The computing unit 201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 201 performs the various methods and processes described above, such as the BMC reset method. For example, in some embodiments, the BMC reset method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 208. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 200 via ROM 202 and / or communication unit 209. When the computer program is loaded into RAM 203 and executed by the computing unit 201, one or more steps of the BMC reset method described above may be performed. Alternatively, in other embodiments, the computing unit 201 may be configured to perform the BMC reset method by any other suitable means (e.g., by means of firmware).

[0066] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0067] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0068] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0069] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0070] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0071] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0072] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A BMC reset method, characterized in that, The method includes: In response to receiving a reset command, the reset flag bit in the reset flag register is reset to zero; The reset restart flag is logically ANDed with the target bit of the command register of the PCIe endpoint device to clear the target bit to zero. The target bit being zero is used to enable the PCIe endpoint device to intercept host access requests. Upon completion of the aforementioned logic and operation, a reset is performed.

2. The method according to claim 1, characterized in that, The method further includes: The system receives a hard reset signal sent by a complex programmable logic device (CPLD); wherein, when the CPLD detects an abnormal operation of the BMC, it resets the restart flag bit of the restart flag register to zero, performs a logical AND operation between the reset restart flag bit and the target bit of the command register of the PCIe endpoint device, and then sends out the hard reset signal. In response to the hard reset signal, a reset is performed.

3. The method according to claim 1, characterized in that, The step of performing a logical AND operation between the reset restart flag and the target bit of the command register of the PCIe endpoint device includes: The reset restart flag and the set instruction are sent to the PCIe endpoint device so that the PCIe endpoint device responds to the set instruction by performing a logical AND operation between the target bit in the command register and the reset restart flag.

4. The method according to claim 1, characterized in that, The step of performing a logical AND operation between the reset restart flag and the target bit of the command register of the PCIe endpoint device includes: The reset restart flag is sent to the PCIe endpoint device so that the PCIe endpoint device performs a logical AND operation between the target bit of the command register and the reset restart flag according to the fixed setting logic.

5. The method according to claim 1, characterized in that, The target bit includes a memory space enable bit and an input / output space enable bit; the memory space enable bit is used to control the host's read and write access requests to the memory space, and the input / output space enable bit is used to control the host's read and write access requests to the input / output space.

6. The method according to claim 1 or 2, characterized in that, The reset process includes: Reset will be performed after a preset time.

7. The method according to claim 1 or 2, characterized in that, The reset process includes: A soft reset signal is output so that the receiving end of the soft reset signal receives the soft reset signal and performs a reset. The receiving end includes a double data rate synchronous dynamic random access memory, a video graphics array module, a PCIe endpoint device, and a hardware module associated with the BMC.

8. The method according to claim 1, characterized in that, The method further includes: In response to the completion of the reset, the restart flag is set to one, and the set restart flag is logically ANDed with the target bit in the command register of the PCIe endpoint device to keep the target bit at its default value. The default value of the target bit is used to enable the PCIe endpoint device to resume normal reception of access requests from the host.

9. A BMC, characterized in that, It includes a processor and a double-rate synchronous dynamic random access memory, a video graphics array module, and a PCIe endpoint device, all connected to the processor. The processor is used to execute the BMC reset method according to any one of claims 1 to 8.

10. A BMC reset system, characterized in that, include: The BMC as described in claim 9; The CPLD, connected to the BMC, is used to trigger a reset operation of the BMC in response to the detection of an abnormal operation of the BMC.

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