Hardware Trojan detection method based on low activity and low observation node joint analysis

Abstract

The hardware Trojan detection method and system based on low activity and low observation node joint analysis belong to the technical field of integrated circuit security, and solve the problem of how to improve the accuracy of identifying high-concealment hardware Trojan; the gate-level netlist is abstracted into a signal propagation directed graph, the nodes in the low activity candidate trigger node set are taken as the starting nodes, the nodes in the low observation candidate load node set are taken as the target nodes, the effective signal propagation path from the starting node to the target node is searched in the directed graph, and if the effective signal propagation path exists, it is determined as a high-risk hardware Trojan potential link; the application proposes a method for identifying high-concealment hardware Trojan potential signal link based on gate-level netlist static analysis, which does not depend on the golden reference model, and does not need to know the Trojan feature library, and is especially suitable for third-party IP core access security detection, backdoor review and logic credibility verification scenes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit security technology and relates to a hardware Trojan detection method and system based on joint analysis of low-activity and low-observation nodes. Background Technology

[0002] With the globalization and increasing complexity of integrated circuit (IC) design and manufacturing, the widespread application of Third-Party Intellectual Property (3PIP) has become the industry norm. While this highly modular and separated design process improves efficiency, it also introduces serious security risks. Hardware Trojans can be maliciously implanted at any stage of chip design, manufacturing, packaging, or testing.

[0003] Hardware Trojans are malicious modifications to the circuitry hidden inside chips, designed to be highly stealthy. Currently, mainstream hardware Trojan detection technologies are mainly divided into destructive and non-destructive detection. Destructive detection, such as reverse engineering, is accurate but costly and time-consuming.

[0004] Typically, a hardware trojan consists of two parts: a "trigger" and a "payload." To evade traditional detection methods, attackers often employ highly stealthy design strategies, using inactive nodes as the trigger and inactive nodes as the payload. The advantages of this strategy are:

[0005] (1) Rare triggering conditions: The trigger is logically bound to a "low-activity node" in the circuit that rarely undergoes state transitions in normal working mode, so that the Trojan is in a dormant state most of the time and is difficult to be activated through conventional functional testing or logic simulation.

[0006] (2) Concealed load effect: The output of the payload is connected to a "low-observability node" in the circuit where the signal state is difficult to transmit to the main output port. This means that even if the Trojan is activated, its abnormal effects (such as information leakage and performance degradation) are easily masked by system noise or normal logic and cannot be effectively observed outside the chip.

[0007] Existing technologies generally suffer from the following drawbacks when detecting hardware Trojans that utilize a dual strategy of "low-activity triggering" and "low-observation output": traditional functional testing methods suffer from high false negative rates due to their inability to cover rare triggering conditions; bypass channel analysis methods have low signal-to-noise ratios and insufficient detection sensitivity and reliability when faced with weak load effects; and formal verification methods are difficult to apply to large-scale commercial circuits due to their huge computational overhead.

[0008] As can be seen from the above, existing technologies generally suffer from insufficient detection coverage, low signal-to-noise ratio, high computational overhead, or poor scalability when detecting hardware Trojans that employ low-activity triggering and low-observation-output strategies for double concealment. To address these shortcomings, there is an urgent need in this field for an automated detection method capable of efficiently and accurately identifying and locating the potential paths of highly concealed hardware Trojans. Summary of the Invention

[0009] The technical problem to be solved by this invention is how to improve the accuracy of identifying highly stealthy hardware Trojans.

[0010] The present invention solves the above-mentioned technical problems through the following technical solutions: The hardware Trojan detection method based on joint analysis of low-activity and low-observation-nodes includes the following steps: S1. Dynamic functional simulation is performed using the gate-level netlist and test vector set of the circuit under test as input. The number of state transitions of each node is recorded and the activity metric of each node is calculated. A set of low-activity candidate trigger nodes is constructed based on nodes whose activity metric is less than the preset low-activity threshold. S2, perform testability analysis on the gate-level netlist, calculate the combined observability value of each internal node, and form a set of low-observability candidate load nodes based on nodes whose combined observability value is not lower than the preset low observability threshold or whose nodes are ranked in the top of the combined observability value by a preset proportion. S3 abstracts the gate-level netlist into a directed graph of signal propagation. It takes the nodes in the set of low-activity candidate trigger nodes as the starting nodes and the nodes in the set of low-observability candidate payload nodes as the target nodes. It searches for an effective signal propagation path from the starting node to the target node in the directed graph. If an effective signal propagation path exists, it is determined to be a potential link of a high-risk hardware Trojan.

[0011] Furthermore, S1 includes the following: S11: Obtain the gate-level netlist of the circuit under test, apply a preset number of random or pseudo-random test vectors to the gate-level netlist, and perform dynamic functional simulation with the gate-level netlist and test vector set as inputs. S12, extract the number of flips TC of the gate-level netlist node by node, and use the ratio of TC to the total number of excitation vectors or the total simulation cycle as the node activity measure, as shown in the following formula:

[0012] in, Represents a node The number of flips during the entire functional simulation process. This represents the total number of excitation vectors. Represents a node Activity measurement value; S13, compare the activity metrics of all nodes, and determine the nodes with activity values ​​below a preset threshold θ as a set of low-activity candidate trigger nodes, as shown in the following formula:

[0013] Where V represents the set of all nodes in the circuit under test, and θ represents the preset activity threshold. This represents a set of inactive nodes.

[0014] Furthermore, S2 includes the following: S21, convert the gate-level netlist of the circuit under test into a standardized structure description file; S22, calculate the combined observability value of each node based on the testability analysis model; S23, sort all nodes by combined observability values ​​in descending order, and select the nodes with CO values ​​in the top 10% as candidate load nodes with low observability; or, for all nodes by combined observability values, select those that satisfy... The nodes are classified as low-observability nodes, among which This indicates a preset low observability threshold. Represents a node The combined observability values ​​yield the set of low-observability candidate load nodes, as shown in the following equation:

[0015] Where V represents the set of all nodes in the circuit under test. This represents the set of candidate payload nodes with low observability.

[0016] Furthermore, the testability analysis model described in S22 adopts the SCOAP model. The calculation of the combinational observability value starts from the main output node of the circuit and proceeds backwards. The combinational observability value of the main output node is set to 0, and the combinational observability value of the input node is calculated according to the following rules based on the type of logic gate: For AND gates or NAND gates ; For OR gates or NOR gates ; Regarding the NOT gate, ; For XOR gates or XNOR gates ; For the MUX21 2-to-1 multiplexer ; For stem nodes ; in, This represents the combinatorial observability value of node n; This represents the combinational observability value of the current logic gate output; This represents the j-th input node whose observability is to be computed. Indicates except The k-th input node other than the one mentioned above, and k≠j; CC0(x) and CC1(x) represent the minimum controllability cost required to force node x to logic "0" or logic "1" respectively; , , , , Each represents a combination of observability values ​​for the corresponding nodes. The j-th input for a multi-input AND / NAND or OR / NOR gate Used for NOT gate inputs. Input terminal used in XOR / XNOR gates , Data input terminal for a 2-to-1 multiplexer , Used for stem node n, where stem represents a signal node with multiple fan-out branches; This indicates that in an AND / NAND gate, to make the division... The controllability cost that must be considered when other inputs satisfy the non-control value "1". This indicates that in the OR / NOR gate, to make the division... Other than the controllable inputs that satisfy the non-control value "0" must be considered for controllability costs.

[0017] Furthermore, the abstraction of the gate-level netlist into a directed graph of signal propagation described in S3 specifically refers to: Construct a directed signal propagation graph G=(V,E) based on the gate-level netlist of the circuit under test; where the node set V includes the main input node, main output node and intermediate signal node in the circuit under test, and the edge set E represents the directed propagation relationship between the input signal and the output signal of each logic gate; For any logic gate, if its input node If the output node is y, then add a directed edge to the directed graph. For nodes with fan-out relationships, the same node corresponds to multiple outgoing edges.

[0018] Furthermore, the search for an effective signal propagation path from the starting node to the target node in the directed graph, as described in S3, specifically involves: For each pair of starting and target nodes, a reachability search is performed using either depth-first or breadth-first traversal. During the traversal, the sequence of nodes on the current access path is recorded, and visited nodes are marked. If the currently traversed node is equal to the target node, then the current node sequence is recorded as a valid path; if the current node does not have an unvisited successor node, then backtrack to the previous node and continue searching until all paths combining the starting node and the target node are traversed; wherein, the valid path is specifically a directed path in which the starting node s and the target node t are different and the path contains at least one directed edge from the input end of the logic gate to the output end.

[0019] Furthermore, in S3, for any low-activity candidate trigger node s and any low-observability candidate load node t, if s ≠ t, and there exists at least one valid path from s to t with at least one edge in the directed signal propagation graph, then the node pair is determined to be valid. The corresponding path is marked as a high-risk hardware Trojan link.

[0020] Corresponding to the above method, the present invention also provides a hardware Trojan detection system based on joint analysis of low-activity and low-observation nodes, comprising: The simulation and activity analysis module is used to perform dynamic functional simulation with the gate-level netlist and test vector set of the circuit under test as input. It records the number of state transitions of each node and calculates the activity metric of each node. Based on the nodes whose activity metric is less than the preset low activity threshold, a set of low-activity candidate trigger nodes is constructed. The testability analysis module is used to perform testability analysis on the gate-level netlist, calculate the combined observability value of each internal node, and construct a set of low-observability candidate load nodes based on nodes whose combined observability value is less than the set low observability screening criteria. The path discovery and localization module is used to abstract the gate-level netlist into a directed graph of signal propagation. It uses nodes in the set of low-activity candidate trigger nodes as starting nodes and nodes in the set of low-observability candidate payload nodes as target nodes to search for effective signal propagation paths from the starting nodes to the target nodes in the directed graph. If an effective signal propagation path exists, it is identified as a potential link for a high-risk hardware Trojan.

[0021] An electronic device includes a memory and a processor, the memory being used to store a program that supports the processor in executing the above-described hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes, the processor being configured to execute the program stored in the memory.

[0022] A storage medium storing a computer program, which, when executed by a processor, performs the steps of the hardware Trojan detection method based on joint analysis of low-activity and low-observation-nodes described above.

[0023] The advantages of this invention are: (1) This invention starts from the fundamental design concept of hardware Trojans to achieve stealth. By structurally linking low-activity node analysis and low-observation node analysis, it can accurately locate the most difficult-to-detect hardware Trojans that simultaneously utilize both stealth strategies. This invention overcomes the problem of missed detection caused by the inability of traditional functional testing to effectively trigger low-activity nodes, and also solves the problem of low signal-to-noise ratio and difficulty in distinguishing weak load effects in bypass channel analysis, significantly improving the detection accuracy and coverage of highly stealthy Trojans.

[0024] (2) The present invention employs an efficient static and semi-static simulation statistical analysis method, the core function of which is as a powerful "suspicious area filter". Compared with the huge computational burden caused by the explosion of state space in formal verification methods, or the large number of physical measurements and complex signal processing required for bypass channel analysis, the present invention directly reduces the scope of investigation from millions of nodes of the entire chip to a limited number of high-risk signal chains through the traversal algorithm. This greatly reduces the complexity and time cost of subsequent manual review or fine verification, significantly improves detection efficiency and reduces computational overhead, making it possible to detect large-scale circuits.

[0025] (3) The entire testing process of this invention can be fully implemented as an automated software tool and seamlessly integrated into existing electronic design automation (EDA) workflows without the need for expensive dedicated hardware. This method mainly relies on static analysis of the gate-level netlist, and its computational complexity increases polynomially rather than exponentially with the increase of circuit size. Therefore, it has excellent scalability and can be effectively applied to current and future large-scale and very large-scale integrated circuit designs, achieving a high degree of automation and good scalability of the testing process.

[0026] (4) This invention provides a "reference-free" hardware Trojan detection technology, which does not require comparing the circuit under test with an absolutely reliable "golden reference model" or a known Trojan signature database, thus solving the problem of the difficulty in obtaining a golden reference model in scenarios such as using third-party IP cores. At the same time, this invention identifies suspicious logic by analyzing the inherent structural properties of the circuit, thus possessing the ability to detect new and unknown hardware Trojans, with stronger versatility and applicability, especially suitable for scenarios such as third-party IP core access security detection, backdoor review, and logic credibility verification. Attached Figure Description

[0027] Figure 1 This is a flowchart of obtaining low-activity nodes according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of obtaining low observation nodes according to Embodiment 1 of the present invention; Figure 3 This is a flowchart of the hardware Trojan link detection and location in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the high-risk trigger-load propagation link in the reference circuit c2670 of Embodiment 1 of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 Specifically, a hardware Trojan detection method based on joint analysis of low-activity and low-observation-nodes is disclosed, including the following steps: S1, screening for low-activity node sets based on dynamic simulation: Dynamic functional simulation is performed using the gate-level netlist and test vector set of the circuit under test as input. The number of state transitions of each node is recorded and the activity metric of each node is calculated. A set of low-activity candidate trigger nodes is constructed based on nodes whose activity metric values ​​are less than a preset low-activity threshold.

[0030] In this embodiment, step S1 is used to identify nodes in the circuit with abnormally low switching activity as potential Trojan triggering parts. By acquiring the gate-level netlist of the circuit under test and applying a set of high-coverage test vectors to it for dynamic functional simulation, the operating behavior of the circuit under typical application scenarios is simulated. During the functional simulation, the system monitors and records the logic state transition information of each signal node in the circuit to generate node activity data, and calculates an activity metric for each node to characterize its switching frequency. Finally, nodes with activity metric values ​​lower than a predefined low-activity screening threshold are selected to form a low-activity candidate triggering node set. Specifically, step S1 includes the following: S11 performs dynamic functional simulation using gate-level netlists and test vector sets as inputs.

[0031] First, obtain the gate-level netlist of the circuit under test, and use a Python script to generate a testbench file based on the circuit under test. Then, apply a preset number of random or pseudo-random test vectors to the gate-level netlist, and perform dynamic functional simulation with the gate-level netlist and test vector set as input, and output the SAIF activity file.

[0032] S12 records the number of state transitions for each node and calculates the activity metric for each node.

[0033] After completing the functional simulation of the gate-level netlist, the generated SAIF activity file is read, and the state holding time T0, T1 and the number of toggles TC of each node are extracted. Among them, T0 is the cumulative time for the node to hold logic 0, T1 is the cumulative time for the node to hold logic 1, and TC is the total number of toggles from logic 0 to logic 1 or from logic 1 to logic 0 during the entire simulation process.

[0034] The ratio of TC to the total number of excitation vectors or the total simulation cycle is used as a node activity metric to characterize the dynamic switching characteristics of the node under test excitation, as shown in the following formula:

[0035] in, Represents a node The number of flips during the entire functional simulation process. This represents the total number of excitation vectors. Represents a node The activity metric, also known as the node flipping probability.

[0036] S13, construct a set of low-activity candidate trigger nodes based on nodes whose activity metric values ​​are less than a preset low-activity threshold.

[0037] In this embodiment, nodes with low activity metrics indicate that they remain stable for most simulation moments and only flip when a few conditions are met, thus better reflecting the low-probability activation characteristics of hardware Trojan trigger signals. Based on this, this embodiment compares the activity metrics of all nodes and identifies nodes below a preset threshold θ as a set of low-activity candidate trigger nodes, as shown in the following formula:

[0038] Where V represents the set of all nodes in the circuit under test, and θ represents the preset activity threshold. This represents the set of low-activity nodes. Preferably, in this embodiment, the activity threshold θ can be set to 0.1.

[0039] S2, filtering the set of low-observation nodes based on testability analysis: Perform testability analysis on the gate-level netlist, calculate the combined observability value of each internal node, and construct a set of low-observability candidate load nodes based on nodes whose combined observability value is not lower than a preset low observability threshold or whose nodes are ranked at a preset proportion before the combined observability value.

[0040] In this embodiment, step S2 is used to screen nodes with low observability from the circuit under test as potential candidate nodes for Trojan payloads. Since the payloads of hardware Trojans are often hidden in internal nodes that are not easily observed directly from the main output, it is necessary to quantify the observability of each node in the circuit and determine the set of low-observability nodes accordingly. Specifically, firstly, the gate-level netlist of the circuit under test is converted into a standardized structure description file suitable for testability analysis; then, based on a predefined circuit testability analysis model, the circuit topology is traversed backwards from the main output, and a combined observability value is calculated for each internal node to quantify the ease with which its logic state is observed. The higher the value, the more difficult it is for the node's logic state to propagate to the main output; finally, nodes with combined observability values ​​higher than the predefined low-observability screening criteria are selected to construct a set of low-observability candidate payload nodes. Specifically, step S2 includes the following: S21 converts the gate-level netlist into a standardized structure description file.

[0041] The gate-level netlist of the circuit under test is converted into a standardized structure description file suitable for testability analysis, so as to explicitly characterize the logic gate types, input-output relationships, and connection relationships between signal nodes.

[0042] Furthermore, the original gate-level netlist can be flattened into modules, signal names standardized, and logical connections organized to enable unified testability analysis to be performed on all nodes in the future.

[0043] Preferably, the standardized description file is a .bench format file.

[0044] S22, calculate the combined observability value of each node based on the testability analysis model.

[0045] This embodiment uses the SCOAP model as an example for testability analysis. SCOAP (Sandia Controllability / Observability Analysis Program) is a deterministic topology metric method for digital circuit testability analysis. Developed by Sandia National Laboratories in the 1980s, it is used to estimate the controllability and observability of nodes in combinational and sequential circuits to guide test vector generation and fault diagnosis.

[0046] After completing the gate-level netlist format conversion, a testability analysis model is used to calculate the combinational observability of each node in the circuit under test. Starting from the main output node, each internal node is traversed layer by layer in the reverse direction of logic propagation to recursively obtain the combinational observability value CO of each node. The combinational observability of the main output node can be defined as CO(o) = 0. The observability of its predecessor nodes is recursively calculated according to the input-output relationship of different logic gates. The specific recursion rules are shown in Table 1 below. Table 1. Rules for calculating the correlation coefficient of input / output nodes for different logic gate types.

[0047] As shown in Table 1 above, for AND gates or NAND gates, ; For OR gates or NOR gates ; Regarding the NOT gate, ; For XOR gates or XNOR gates ; For a 2-to-1 multiplexer (MUX21). ; For stem nodes .

[0048] in, This represents the combinatorial observability value of node n; This represents the combinational observability value of the current logic gate output; This represents the j-th input node whose observability is to be computed. Indicates except The k-th input node other than the one mentioned above, and k≠j; CC0(x) and CC1(x) represent the minimum controllability cost required to force node x to logic "0" or logic "1" respectively; , , , , Both represent the combined observability values ​​of the corresponding nodes, differing only in the node object pointed to by the subscript and the gate type to which it belongs. The j-th input for a multi-input AND / NAND or OR / NOR gate Used for NOT gate inputs. Input terminal used in XOR / XNOR gates , Data input terminal for a 2-to-1 multiplexer , For stem node n, stem represents a signal node with multiple fan-out branches. For a stem node, if any of its fan-out branches can propagate the node state to the main output, then the node can be observed. Therefore, the minimum value among the combined observability values ​​corresponding to each fan-out branch is taken. This indicates that in an AND / NAND gate, to make the division... The controllability cost that must be considered when other inputs satisfy the non-control value "1". This indicates that in the OR / NOR gate, to make the division... Other than the controllable inputs that satisfy the non-control value "0" must be considered for controllability costs.

[0049] In this embodiment, the combined observability value CO is used to characterize the ease with which the node's logic state propagates to the main output and is observed by external testing. A higher CO value indicates that the logic state of the corresponding node is more difficult to propagate to the main output, resulting in lower node observability. Therefore, this aligns with the characteristics of hardware Trojan payload nodes being highly concealed and difficult to detect. Based on this, the CO values ​​of all nodes are sorted, and a set of low-observability candidate payload nodes is determined according to a preset low-observability screening criterion.

[0050] S23. Based on nodes whose combined observability value is not lower than the set low observability screening standard, or nodes whose combined observability value ranks in the top preset proportion, a low observability candidate load node set is formed.

[0051] In this embodiment, the combined observability values ​​of all nodes are sorted in descending order, and the percentile method is used to select the nodes with CO values ​​in the top 10% as low observability candidate load nodes; or a threshold determination method is used to select nodes that meet the following criteria. The nodes are classified as low-observability nodes, among which This indicates a preset low observability threshold. Represents a node The combined observability values ​​yield the set of low-observability candidate load nodes, as shown in the following equation:

[0052] Where V represents the set of all nodes in the circuit under test. This represents the set of candidate payload nodes with low observability.

[0053] S3, identify and locate high-risk "trigger-load" paths: The gate-level netlist is abstracted into a directed graph of signal propagation. The nodes in the set of low-activity candidate trigger nodes are taken as the starting nodes, and the nodes in the set of low-observability candidate payload nodes are taken as the target nodes. An effective signal propagation path from the starting node to the target node is searched in the directed graph. If an effective signal propagation path exists, it is identified as a potential link of a high-risk hardware Trojan.

[0054] In this embodiment, step S3 locates potential malicious links by associating the two node sets mentioned above. Specifically, firstly, the gate-level netlist of the circuit under test is abstracted into a directed graph model, where the vertices of the graph represent signal nodes in the circuit, and the directed edges represent direct signal propagation relationships between nodes. Next, using any node in the low-activity candidate trigger node set as the search starting point and any node in the low-observability candidate load node set as the search ending point, a graph traversal algorithm is used to search for all existing valid signal propagation paths in the constructed circuit logic topology graph. If there is at least one valid signal propagation path between the starting node and the ending node, the path is identified as a high-risk potential hardware Trojan link, and all identified high-risk paths are summarized to generate a final detection report. Specifically, step S3 includes the following: S31 abstracts the gate-level netlist into a directed graph model.

[0055] Construct a directed signal propagation graph G=(V,E) based on the gate-level netlist of the circuit under test; where the node set V includes the main input node, main output node and intermediate signal node in the circuit under test, and the edge set E represents the directed propagation relationship between the input signal and the output signal of each logic gate.

[0056] For any logic gate, if its input node If the output node is y, then add a directed edge to the directed graph. For nodes with fan-out relationships, multiple outgoing edges are allowed for the same node to represent the situation where the signal of that node propagates to multiple downstream logic gates simultaneously. Thus, the logical connections in the gate-level netlist can be converted into a graph structure that can be used for path search.

[0057] S32 uses a graph traversal algorithm to search for an effective path, starting from a low-activity node and ending at a low-observation node.

[0058] After constructing the directed graph of signal propagation, the set of low-activity candidate triggering nodes obtained in S1 is used as the set of starting nodes, and the set of low-observability candidate payload nodes obtained in S2 is used as the set of target nodes. Path traversal is performed in the directed graph to search for an effective signal propagation path from the starting node to the target node.

[0059] Preferably, this embodiment employs depth-first search or breadth-first search to perform reachability searches on each pair of starting and target nodes. During the traversal, the node sequence on the current access path is recorded, and visited nodes are marked to avoid repeated visits. In this embodiment, a valid signal propagation path refers to a directed path where the starting node s is different from the target node t and the path contains at least one directed edge from the input to the output of a logic gate. If the currently traversed node is equal to the target node, the current node sequence is recorded as a candidate "trigger-load" propagation path and is considered a valid path. If the current node has no unvisited successor node, the search continues back to the previous node until all paths combining starting and target nodes are traversed.

[0060] S33. If a valid path exists, it is identified as a high-risk hardware Trojan link, and all high-risk paths are aggregated to generate a detection report.

[0061] For any low-activity candidate trigger node s and any low-observability candidate payload node t, if s ≠ t, and there exists at least one valid path with at least one edge from s to t in the directed graph of signal propagation, then the node pair is determined to be... High-risk "trigger-payload" node pairs are identified, and the corresponding paths are marked as high-risk hardware Trojan links.

[0062] Furthermore, all high-risk links are aggregated to generate a detection report; the detection report includes at least the starting node, ending node, sequence of intermediate nodes along the path, and path length, thus providing a basis for subsequent manual review or experimental verification.

[0063] like Figure 4 As shown, this embodiment uses the reference circuit C2670 as the circuit under test (DUT), and constructs a representative high-risk trigger-load propagation link in the directed signal propagation graph based on the gate-level netlist of the DUT. Each node in the graph represents a signal node in the gate-level netlist, and each connection represents the direction of signal propagation from the preceding node to the following node under the logic gate-level connection relationship. By jointly analyzing the set of low-activity candidate trigger nodes and the set of low-observability candidate load nodes, and performing path search in the directed signal propagation graph, a reachable propagation path from the candidate trigger node to the candidate load node can be obtained.

[0064] exist Figure 4In the diagram, N1624, N1863, N2632, etc., are internal signal node names or node numbers in the gate-level netlist of the reference circuit c2670, used to uniquely identify signal lines in the netlist. The starting node corresponds to a low-activity candidate trigger node, intermediate nodes correspond to intermediate logic nodes on the signal propagation path, and the terminating node corresponds to a low-observability candidate payload node. This high-risk link originates from a low-activity node, propagates through several intermediate logic nodes, and finally merges into a low-observability node. This path indicates that the low-activity node possesses the potential characteristics of a Trojan trigger, while the low-observability node possesses the potential characteristics of a Trojan payload hiding location; there is a continuous logical propagation relationship between the two, therefore, the corresponding node pair can be identified as a high-risk trigger-payload node pair.

[0065] Figure 4 In addition to the main propagation path, the diagram also shows the relationships between some branches connected to intermediate nodes, used to characterize the local topology formed by the fan-in and fan-out of nodes in the gate-level circuit. This diagram visually illustrates that this embodiment does not merely isolate and screen low-activity or low-observation nodes, but rather, based on the gate-level signal propagation topology, further explores the associated paths between them, thereby achieving the location of high-risk links for potential hardware Trojans.

[0066] Example 2 An apparatus includes a memory and a processor, the memory being used to store a program that supports the processor in executing the hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes as described in Embodiment 1, the processor being configured to execute the program stored in the memory.

[0067] Example 3 A storage medium storing a computer program, which, when executed by a processor, performs the steps of the hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes in Embodiment 1.

[0068] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein can be considered as a ordered list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-based system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0069] For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit a program for use in or in conjunction with an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CD-ROM). Additionally, a computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optical scanning of the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0070] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0071] In the description of this specification, references to terms such as "in a preferred embodiment," "preferred," "in this embodiment," "specific," or "furthermore," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware Trojan detection method based on joint analysis of low activity and low observation nodes, characterized in that, Includes the following steps: S1. Dynamic functional simulation is performed using the gate-level netlist and test vector set of the circuit under test as input. The number of state transitions of each node is recorded and the activity metric of each node is calculated. A set of low-activity candidate trigger nodes is constructed based on nodes whose activity metric is less than the preset low-activity threshold. S2, perform testability analysis on the gate-level netlist, calculate the combined observability value of each internal node, and form a set of low-observability candidate load nodes based on nodes whose combined observability value is not lower than the preset low observability threshold or whose nodes are ranked in the top of the combined observability value by a preset proportion. S3 abstracts the gate-level netlist into a directed graph of signal propagation. It takes the nodes in the set of low-activity candidate trigger nodes as the starting nodes and the nodes in the set of low-observability candidate payload nodes as the target nodes. It searches for an effective signal propagation path from the starting node to the target node in the directed graph. If an effective signal propagation path exists, it is determined to be a potential link of a high-risk hardware Trojan.

2. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 1, characterized in that, S1 includes the following: S11: Obtain the gate-level netlist of the circuit under test, apply a preset number of random or pseudo-random test vectors to the gate-level netlist, and perform dynamic functional simulation with the gate-level netlist and test vector set as inputs. S12, extract the number of flips TC of the gate-level netlist node by node, and use the ratio of TC to the total number of excitation vectors or the total simulation cycle as the node activity measure, as shown in the following formula: in, Represents a node The number of flips during the entire functional simulation process. This represents the total number of excitation vectors. Represents a node Activity measurement value; S13, compare the activity metrics of all nodes, and determine the nodes with activity values ​​below a preset threshold θ as a set of low-activity candidate trigger nodes, as shown in the following formula: Where V represents the set of all nodes in the circuit under test, and θ represents the preset activity threshold. This represents a set of inactive nodes.

3. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 1, characterized in that, S2 includes the following: S21, convert the gate-level netlist of the circuit under test into a standardized structure description file; S22, calculate the combined observability value of each node based on the testability analysis model; S23, sort all nodes by combined observability values ​​in descending order, and select the nodes with CO values ​​in the top 10% as candidate load nodes with low observability; or, for all nodes by combined observability values, select those that satisfy... The nodes are classified as low-observability nodes, among which This indicates a preset low observability threshold. Represents a node The combined observability values ​​yield the set of low-observability candidate load nodes, as shown in the following equation: Where V represents the set of all nodes in the circuit under test. This represents the set of candidate payload nodes with low observability.

4. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 3, characterized in that, The testability analysis model described in S22 adopts the SCOAP model. The calculation of the combinational observability value starts from the main output node of the circuit and proceeds backwards. The combinational observability value of the main output node is set to 0, and the combinational observability value of the input node is calculated according to the following rules based on the type of logic gate: For AND gates or NAND gates ; For OR gates or NOR gates ; Regarding the NOT gate, ; For XOR gates or XNOR gates ; For the MUX21 2-to-1 multiplexer ; For stem nodes ; in, This represents the combinatorial observability value of node n; This represents the combinational observability value of the current logic gate output; This represents the j-th input node whose observability is to be computed. Indicates except The k-th input node other than j, and k≠j; CC0(x) and CC1(x) represent the minimum controllability cost required to force node x to logic "0" or logic "1" respectively; , , , , Each represents a combination of observability values ​​for the corresponding nodes. The j-th input for a multi-input AND / NAND or OR / NOR gate Used for NOT gate inputs. Input terminal used in XOR / XNOR gates , Data input terminal for a 2-to-1 multiplexer , Used for stem node n, where stem represents a signal node with multiple fan-out branches; This indicates that in an AND / NAND gate, to make the division... Other than the controllable inputs satisfying the non-control value "1", the controllability cost to be considered. This indicates that in the OR / NOR gate, to make the division... Other than the controllable inputs that satisfy the non-control value "0" must be considered for controllability costs.

5. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 1, characterized in that, The abstraction of the gate-level netlist into a directed graph of signal propagation, as described in S3, is specifically as follows: Construct a directed signal propagation graph G=(V,E) based on the gate-level netlist of the circuit under test; where the node set V includes the main input node, main output node and intermediate signal node in the circuit under test, and the edge set E represents the directed propagation relationship between the input signal and the output signal of each logic gate; For any logic gate, if its input node If the output node is y, then add a directed edge to the directed graph. For nodes with fan-out relationships, the same node corresponds to multiple outgoing edges.

6. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 5, characterized in that, The search for an effective signal propagation path from the starting node to the target node in a directed graph, as described in S3, is as follows: For each pair of starting and target nodes, a reachability search is performed using either depth-first or breadth-first traversal. During the traversal, the sequence of nodes on the current access path is recorded, and visited nodes are marked. If the currently traversed node is equal to the target node, then the current node sequence is recorded as a valid path; if the current node does not have an unvisited successor node, then backtrack to the previous node and continue searching until all paths combining the starting node and the target node are traversed; wherein, the valid path is specifically a directed path in which the starting node s and the target node t are different and the path contains at least one directed edge from the input end of the logic gate to the output end.

7. The hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes according to claim 6, characterized in that, In step S3, for any low-activity candidate trigger node s and any low-observability candidate load node t, if s ≠ t, and there exists at least one valid path with at least one edge from s to t in the directed signal propagation graph, then the node pair is determined to be... The corresponding path is marked as a high-risk hardware Trojan link.

8. A hardware Trojan detection system based on joint analysis of low activity and low observation nodes, characterized in that, include: The simulation and activity analysis module is used to perform dynamic functional simulation with the gate-level netlist and test vector set of the circuit under test as input. It records the number of state transitions of each node and calculates the activity metric of each node. Based on the nodes whose activity metric is less than the preset low activity threshold, a set of low-activity candidate trigger nodes is constructed. The testability analysis module is used to perform testability analysis on the gate-level netlist, calculate the combined observability value of each internal node, and construct a set of low-observability candidate load nodes based on nodes whose combined observability value is less than the set low observability screening criteria. The path discovery and localization module is used to abstract the gate-level netlist into a directed graph of signal propagation. It uses nodes in the set of low-activity candidate trigger nodes as starting nodes and nodes in the set of low-observability candidate payload nodes as target nodes to search for effective signal propagation paths from the starting nodes to the target nodes in the directed graph. If an effective signal propagation path exists, it is identified as a potential link for a high-risk hardware Trojan.

9. An electronic device, comprising a memory and a processor, characterized in that, The memory is used to store a program that supports the processor in executing the hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes as described in any one of claims 1 to 8, and the processor is configured to execute the program stored in the memory.

10. A storage medium storing a computer program, characterized in that, When the computer program is run by the processor, it executes the steps of the hardware Trojan detection method based on joint analysis of low-activity and low-observation nodes as described in any one of claims 1 to 8.

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