A design method and device of a silicon optical circuit, a storage medium and an electronic device

Abstract

The application discloses a design method and device of a silicon optical circuit, a storage medium and an electronic device. The method comprises the following steps: obtaining an optical design file input by a user and a preset process description file, and analyzing the optical design file and the process description file to obtain design parameters of the silicon optical circuit; generating path parameters meeting a first target dimension constraint condition based on the design parameters through a pre-trained path generation network; wherein the first target dimension at least comprises a geometric dimension, an optical dimension and a process dimension; constructing a path geometric model based on the path parameters, converting the path geometric model into layout data under a target process, and generating an initial layout file of the silicon optical circuit based on the layout data; performing photoelectric consistency verification on the initial layout file, and determining a target layout file corresponding to the initial layout file based on a verification result. Through the technical scheme provided by the application, the layout and wiring of the silicon optical circuit can be optimized to meet the design requirements of the silicon optical circuit.

Description

Technical Field

[0001] This application belongs to the field of circuit design technology, and in particular relates to a design method, apparatus, storage medium and electronic device for silicon photonic circuits. Background Technology

[0002] With the rapid development of AI (Artificial Intelligence) chips, significant breakthroughs have also been achieved in the related process technologies of silicon photonics integrated circuits. Compared with traditional electronic circuits or discrete optoelectronic systems, silicon photonics technology can achieve deep optoelectronic integration at the chip level, and has become a core development direction in fields such as high-performance computing, data centers, and optical AI processors.

[0003] However, existing silicon photonics integrated circuit design flows are insufficient to meet the design requirements of silicon photonics integrated circuits. Therefore, it is necessary to provide an artificial intelligence algorithm-driven design method for optimizing the placement and routing of silicon photonic circuits to meet the corresponding design requirements. Summary of the Invention

[0004] The embodiments of this application provide a design method, apparatus, storage medium, and electronic device for silicon photonics circuits. The path parameters of the silicon photonics circuit can be obtained based on a path generation network implemented by artificial intelligence algorithms, thereby optimizing the layout and routing. Then, the initial layout file generated based on the path parameters is subjected to optoelectronic consistency verification to obtain a target layout file that meets the design requirements of the silicon photonics circuit.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0006] According to a first aspect of the embodiments of this application, a method for designing silicon photonic circuits is provided, comprising:

[0007] The system acquires the user-input optical design file and the preset process description file, and parses the optical design file and the process description file to obtain the design parameters of the silicon photonics circuit. The optical design file includes the initial port information of each optical port, and the process description file is used to characterize the design rule information of the process dimension. A pre-trained path generation network is used to generate path parameters that satisfy the constraints of the first objective dimension based on the design parameters; wherein the first objective dimension includes at least the geometric dimension, the optical dimension, and the process dimension. A path geometry model is constructed based on path parameters, the path geometry model is converted into layout data under the target process, and an initial layout file of silicon photonics circuit is generated based on the layout data; wherein, the target process is used to characterize the process specified by the user. The initial layout file is subjected to photoelectric consistency verification, and the target layout file corresponding to the initial layout file is determined based on the verification results.

[0008] In some embodiments of this application, based on the foregoing scheme, the design parameters include target port information for each optical port, and path parameters satisfying the first target dimension constraint are generated based on the design parameters, including: A first topology graph is constructed based on the target port information of each optical port; wherein, each node in the first topology graph corresponds one-to-one with each optical port; The first topological graph is subjected to feature extraction processing to obtain the node feature matrix and the edge feature matrix; Based on the node feature matrix and edge feature matrix, path parameters that satisfy the first objective dimension constraint are generated.

[0009] In some embodiments of this application, based on the aforementioned scheme, path parameters satisfying the first target dimension constraint are generated based on the node feature matrix and the edge feature matrix, including: Normalize the node features in the node feature matrix and the edge features in the edge feature matrix to obtain the initial topological features. Based on the first target dimension constraint, the initial topological features are updated to obtain the target topological features; The target topological features are mapped to continuous coordinate points to obtain path parameters; the path parameters include the coordinate information and local curvature of each coordinate point.

[0010] In some embodiments of this application, based on the foregoing scheme and the first target dimension constraint, the initial topological features are updated to obtain the target topological features, including: Based on the initial topological features, calculate the weight information of the adjacent nodes corresponding to each target node; For each target node, based on the weight information of the neighboring nodes corresponding to the target node and the first target dimension constraint, the node features of the target node and the node features of the neighboring nodes corresponding to the target node are aggregated to update the node features of the target node. Based on the updated node features of each target node and the initial topology features, target topology features are generated.

[0011] In some embodiments of this application, based on the foregoing scheme, the path generation network is trained through the following steps: Obtain sample design parameters from a pre-built sample library, and perform at least one training operation on the initial path generation network based on the sample design parameters until the training termination condition is met, thus obtaining the trained path generation network. The training operations include: Determine the first path generation network corresponding to the current training operation; generate candidate actions based on the sample design parameters using the first path generation network corresponding to the current training operation; the candidate actions are used to generate the corresponding sample path parameters. By using a constraint engine, candidate actions are modified to obtain the target action; The target loss value is determined based on the target action, and the parameters of the first path generation network corresponding to the current training operation are adjusted based on the target loss value to obtain the first path generation network corresponding to the next training operation; the first path generation network corresponding to the first training operation is the initial path generation network.

[0012] In some embodiments of this application, based on the aforementioned scheme, the candidate action is modified to obtain the target action, including: Determine the state vector corresponding to the candidate action; Obtain the target constraint equation from the pre-built constraint equation library; wherein the constraint equation library includes constraint equations corresponding to the second target dimension respectively, and the second target dimension includes at least the optical dimension, geometric dimension, electrical dimension and thermal dimension; The physical deviation of the state vector is calculated based on the target constraint equation; If the physical deviation is greater than the first preset threshold, the state vector is mapped to the nearest physical boundary to correct the state vector; where the physical boundary is the dimensional boundary corresponding to the target constraint equation. The target action corresponding to the candidate action is determined based on the corrected state vector.

[0013] In some embodiments of this application, based on the foregoing scheme, determining the corresponding target loss value based on the target action includes: The loss values ​​corresponding to the third target dimension are obtained based on the target action; wherein, the third target dimension includes at least the optical dimension, the electrical dimension, and the thermal dimension; The target loss value is obtained by weighting the loss values ​​based on the weight coefficients corresponding to each third objective dimension.

[0014] In some embodiments of this application, after constructing a path geometry model based on path parameters according to the foregoing scheme, the method further includes: The design rule check is performed on the path geometry model based on the process description file to obtain the target check results; the design rule check includes at least line width check, spacing check, bending radius check and layer mismatch check. Based on the target inspection results, the path geometry model is corrected to obtain the corrected path geometry model. Accordingly, the path geometry model is converted into layout data under the target process, including: The corrected path geometry model is converted into layout data for the target process.

[0015] In some embodiments of this application, before performing optoelectronic consistency verification on the initial layout file based on the foregoing scheme, the method further includes: Obtain the electronic design file input by the user, and construct a semantic mapping table based on the initial layout file and the electronic design file; According to the preset conversion template, a photoelectric data model is constructed based on the semantic mapping table; The initial layout file is parsed and processed using an optoelectronic data model to obtain the corresponding electronic macrocell definition; Obtain optical metadata and embed it into the electronic macrocell definition; The electronic design file is updated based on the embedded electronic macrocell definition to obtain the initial electronic file corresponding to the initial layout file.

[0016] In some embodiments of this application, based on the aforementioned scheme, optoelectronic consistency verification is performed on the initial layout file, and the target layout file corresponding to the initial layout file is determined based on the verification results, including: Generate the corresponding layout netlist based on the initial layout file, and generate the corresponding electronic netlist based on the initial electronic file; The map netlist is matched with the electronic netlist to obtain the matching similarity. If the matching similarity is less than the second preset threshold, the photoelectric consistency verification is determined to have failed. In the event of failure of optoelectronic consistency verification, the difference information between the layout netlist and the electronic netlist is recorded, and the initial layout file is corrected based on the difference information to obtain the target layout file.

[0017] In some embodiments of this application, based on the aforementioned scheme, the layout netlist and the electronic netlist are matched to obtain a matching similarity, including: The first optical content in the map netlist is matched with the second optical content in the electronic netlist to obtain the optical matching result; The first electronic content in the map netlist is matched with the second electronic content in the electronic netlist to obtain the electronic matching result; The photoelectric hybrid content in the map netlist is matched with the photoelectric hybrid content in the electronic netlist to obtain the photoelectric hybrid matching result; The matching similarity is calculated based on optical matching results, electronic matching results, and photoelectric hybrid matching results.

[0018] According to a second aspect of the embodiments of this application, a design apparatus for silicon photonic circuits is provided, comprising: The file parsing module is used to obtain the optical design file and the preset process description file input by the user, and to parse the optical design file and the process description file to obtain the design parameters of the silicon photonics circuit. The optical design file includes the initial port information of each optical port, and the process description file is used to characterize the design rule information of the process dimension. The path generation module is used to generate path parameters that satisfy the constraints of the first target dimension based on the design parameters through a pre-trained path generation network; wherein the first target dimension includes at least the geometric dimension, optical dimension and process dimension. The file generation module is used to construct a path geometry model based on path parameters, convert the path geometry model into layout data under the target process, and generate an initial layout file for silicon photonics circuits based on the layout data; wherein, the target process is used to characterize the process specified by the user. The file verification module is used to perform optoelectronic consistency verification on the initial layout file and determine the target layout file corresponding to the initial layout file based on the verification results.

[0019] According to a third aspect of the embodiments of this application, a computer-readable storage medium is provided, which stores computer program instructions that, when loaded and executed by a processor, implement the steps of the silicon photonics circuit design method as described in any of the first aspects.

[0020] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including a processor and a memory, wherein the memory stores computer program instructions that can be executed by the processor, and when the processor executes the computer program instructions, it implements the steps of the silicon photonics circuit design method as described in any of the first aspects.

[0021] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of a silicon photonics circuit design method as described in any of the first aspects.

[0022] In this application, user-input optical design files and preset process description files are obtained and parsed to obtain design parameters for silicon photonic circuits. The optical design files include initial port information for each optical port, and the process description files characterize design rule information for the process dimension. A pre-trained path generation network generates path parameters that satisfy constraints in a first target dimension based on the design parameters. The first target dimension includes at least geometric, optical, and process dimensions. A path geometric model is constructed based on the path parameters, converted into layout data under the target process, and an initial layout file for the silicon photonic circuit is generated based on the layout data. The target process characterizes the process specified by the user. The initial layout file undergoes optoelectronic consistency verification, and the target layout file corresponding to the initial layout file is determined based on the verification results. The technical solution provided in this application allows for the acquisition of path parameters for silicon photonic circuits using a path generation network implemented with artificial intelligence algorithms. This enables optimization of layout and routing, and further, optoelectronic consistency verification of the initial layout file generated based on the path parameters yields a target layout file that meets the design requirements of the silicon photonic circuit.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 The diagram illustrates an application scenario of the silicon photonics circuit design method according to embodiments of this application. Figure 2 A flowchart illustrating the design method of silicon photonic circuits in an embodiment of this application is shown; Figure 3 A flowchart illustrating the generation of path parameters in an embodiment of this application is shown; Figure 4 Another flowchart of generating path parameters in an embodiment of this application is shown; Figure 5 A flowchart illustrating the updating of topological features in an embodiment of this application is shown; Figure 6 A flowchart of a correction candidate action in an embodiment of this application is shown; Figure 7 A flowchart illustrating the determination of the target loss value in an embodiment of this application is shown; Figure 8 A flowchart of the modified path geometry model in an embodiment of this application is shown; Figure 9 A flowchart of photoelectric file conversion in an embodiment of this application is shown; Figure 10 A flowchart of photoelectric consistency verification in an embodiment of this application is shown; Figure 11 A flowchart illustrating the calculation of matching similarity in an embodiment of this application is shown; Figure 12 Another flowchart of the design method of silicon photonic circuit in the embodiments of this application is shown; Figure 13 A block diagram of a silicon photonics circuit design apparatus according to an embodiment of this application is shown; Figure 14 A schematic diagram of the structure of an electronic device in an embodiment of this application is shown. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0028] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0029] To enable those skilled in the art to better understand this application, firstly, in conjunction with Figure 1 A brief description of the application scenarios involved in this application is provided.

[0030] See Figure 1 The diagram illustrates an application scenario of the silicon photonics circuit design method according to embodiments of this application.

[0031] Terminal 102 communicates with server 104 via a network. The data storage system can store data that server 104 needs to process, such as process description documents. The data storage system can be integrated onto server 104, or it can be located in the cloud or on other network servers.

[0032] Specifically, the user inputs an optical design file using terminal 102, enabling server 104 to acquire the user-input optical design file and a preset process description file. Server 104 then parses the optical design file and process description file to obtain the design parameters for the silicon photonics circuit. The optical design file includes initial port information for each optical port, while the process description file represents design rule information for the process dimension. A pre-trained path generation network generates path parameters that satisfy the constraints of a first target dimension based on the design parameters. The first target dimension includes at least geometric, optical, and process dimensions. A path geometric model is constructed based on the path parameters, and this model is converted into layout data under the target process. An initial layout file for the silicon photonics circuit is then generated based on the layout data. The target process represents the process specified by the user. The initial layout file undergoes optoelectronic consistency verification, and the corresponding target layout file is determined based on the verification results. Server 104 then sends the target layout file to terminal 102 for displaying the design results of the silicon photonics circuit on terminal 102.

[0033] Among them, terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices and portable wearable devices, and server 104 can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services.

[0034] In one exemplary embodiment, refer to Figure 2 The flowchart of the silicon photonics circuit design method in the embodiments of this application is shown below in detail: Step 201: Obtain the optical design file and preset process description file input by the user, and parse the optical design file and process description file to obtain the design parameters of the silicon photonics circuit.

[0035] User-input optical design files refer to the optical design drafts provided by the user, including initial port information for each optical port, such as the position coordinates of the optical ports, light propagation direction, mode type, and connection requirements. Position coordinates include, but are not limited to, three-dimensional position coordinates or physical position coordinates within the chip or system; mode type refers to supported optical modes; and connection requirements specify whether a direct connection or a connection via components is required.

[0036] The pre-defined process description file is used to characterize design rule information for process dimensions, including but not limited to waveguide layer thickness, material refractive index, minimum bending radius, and PDK (Process Design Kit). Since the design method provided in this embodiment is applicable to different process scenarios of silicon photonics circuits, the process description files required for different process scenarios may differ. Therefore, process description files for different process scenarios can be pre-defined, allowing the acquisition of the corresponding process description file based on the process specified by the user when designing silicon photonics circuits.

[0037] The optical design documents and process description documents are parsed to extract effective information for designing silicon photonic circuits, forming design parameters for the silicon photonic circuits. For example, parsing the optical design documents can map the position coordinates of the optical ports to a unified coordinate system and the mode types to modes supported by the PDK. Parsing the process description documents can transform the physical constraints of the PDK into standard design rules, and distinguish between hard constraints that must be followed and soft constraints that achieve performance optimization.

[0038] Optionally, the design parameters of the silicon photonics circuit can be obtained by parsing the optical design documents and process description documents, or the design parameters of the silicon photonics circuit can be extracted from the optical design documents and process description documents using regular expressions.

[0039] Optionally, effective information for designing silicon photonic circuits can be extracted from optical design documents and process description documents, and then this effective information can be structured to obtain standard design parameters. The structured design parameters can be directly input into a pre-trained path generation network for data analysis and processing.

[0040] Step 202: Generate path parameters that satisfy the first objective dimension constraint conditions based on the design parameters using a pre-trained path generation network.

[0041] The first objective dimension includes at least geometric, optical, and manufacturing dimensions, each with corresponding constraints. The pre-trained path generation network can learn path geometry (geometric dimension), optical loss and coupling efficiency (optical dimension), and manufacturing feasibility (manufacturing dimension) simultaneously. It should be noted that the constraints in different dimensions are not mutually exclusive; some constraints need to be implemented across dimensions.

[0042] The design parameters of the silicon photonics circuit are taken as input and processed by a path generation network to obtain the output path parameters of the silicon photonics circuit. For example, the path generation network includes multiple layers of message passing units, which can perform feature extraction processing on the design parameters, and then combine the constraints of geometric, optical, and process dimensions to perform message passing and updating on the extracted features to obtain the optimal path parameters.

[0043] Optionally, the port features of each optical port are extracted through a path generation network, the topological relationship between each optical port is determined based on the optical waveguide, the corresponding connection features are extracted, and the various features are transformed into a hidden layer representation that includes geometry, optics and process by nonlinear transformation, thereby optimizing the path parameters of the generated silicon photonic circuit.

[0044] Step 203: Construct a path geometry model based on path parameters, convert the path geometry model into layout data under the target process, and generate an initial layout file for silicon photonics circuits based on the layout data.

[0045] The target process is used to characterize the process specified by the user. The design method provided in this embodiment is applicable to different process scenarios of silicon photonics circuits and can automatically achieve the adaptation of the target process.

[0046] The path parameters are converted into a manufacturing-feasible spline curve, and then adaptive modifications are made based on the spline curve to obtain the corresponding path geometric model. For example, information needed to generate the spline curve, such as the position coordinates of the optical port, curvature parameters, and layer identifiers, is extracted from the path parameters to form a continuous path represented as a spline curve. This continuous path is then segmented and sampled to construct a discrete point set, where each point has corresponding horizontal and vertical coordinates. The path parameters are then modified based on this discrete point set to obtain optimized path parameters. Furthermore, primitive segmentation information is generated to distinguish between straight segments, curved segments, and intersection segments. Combining the optimized path parameters and the primitive segmentation information, the path geometric model is constructed.

[0047] Optionally, a curvature compensation algorithm is used to correct the spline curve, eliminate abrupt changes at corners, and obtain a smooth spline curve. The algorithm automatically detects and corrects violations in line width, spacing, and floor height, resulting in a corrected path geometry model.

[0048] A standard-format layout file, or initial layout file, is generated based on the path geometry model. This standard format can be GDSII format, a binary database file format used to store physical layout information of integrated circuits. For example, the target process is determined, the path geometry model is converted into layout data for the target process, and then the corresponding initial layout file is generated based on this layout data.

[0049] Step 204: Perform optoelectronic consistency verification on the initial layout file, and determine the target layout file corresponding to the initial layout file based on the verification results.

[0050] Based on a pre-defined optoelectronic layer mapping table, the geometry of each layer and its corresponding device instances are identified from the initial layout file to calculate the topological connections between optical ports and generate the corresponding layout netlist. If the initial layout file contains an optical path file, the waveguide connection relationships are resolved, and the distance vectors between nodes are calculated. The optoelectronic layer mapping table characterizes the mapping relationships between optical layers, electronic layers, and optical interface layers, and can decode each layer in the initial layout file to its corresponding logic device or connection type.

[0051] The process involves obtaining the electronic netlist corresponding to the electronic design file, performing port-layer-topology 3D alignment between the layout netlist and the electronic netlist, and verifying the consistency of information such as mode type, number, and transmission path based on waveguide topology and port orientation of optical ports for the optical layer. For the electronic layer, connection consistency verification is performed based on node number and electrical parameters such as capacitance and resistance. For the optoelectronic interface layer, hybrid verification is performed on shared nodes such as optoelectronic modulators to ensure that the optoelectronic interface conforms to contact layer rules. The electronic design file can be a user-input electronic design draft.

[0052] Furthermore, if the consistency verification passes, the initial layout file is directly output as the target layout file; if the consistency verification fails, the initial layout file is corrected, and the corrected initial layout file is output as the target layout file.

[0053] In this application, user-input optical design files and preset process description files are obtained and parsed to obtain design parameters for silicon photonic circuits. The optical design files include initial port information for each optical port, and the process description files characterize design rule information for the process dimension. A pre-trained path generation network generates path parameters that satisfy constraints in a first target dimension based on the design parameters. The first target dimension includes at least geometric, optical, and process dimensions. A path geometric model is constructed based on the path parameters, converted into layout data under the target process, and an initial layout file for the silicon photonic circuit is generated based on the layout data. The target process characterizes the process specified by the user. The initial layout file undergoes optoelectronic consistency verification, and the target layout file corresponding to the initial layout file is determined based on the verification results. The technical solution provided in this application allows for the acquisition of path parameters for silicon photonic circuits using a path generation network implemented with artificial intelligence algorithms. This enables optimization of layout and routing, and further, optoelectronic consistency verification of the initial layout file generated based on the path parameters yields a target layout file that meets the design requirements of the silicon photonic circuit.

[0054] Based on the above embodiments, in an exemplary embodiment, the design parameters include target port information for each optical port, see [link to relevant documentation]. Figure 3 This illustrates the method for generating path parameters in embodiments of this application, specifically including: Step 301: Construct a first topology map based on the target port information of each optical port.

[0055] Based on the target port information of each optical port, a topological undirected graph G(V, E) is constructed, which is the first topological graph. Here, node V represents an optical port or turning point, and edge E represents waveguide connectivity. Each node in the first topological graph corresponds one-to-one with each optical port. Attributes such as position, mode type, and power constraints are added to each node in the first topological graph, and attributes such as geometric distance, relative angle, and material layer characteristics are added to each edge in the first topological graph.

[0056] Step 302: Perform feature extraction processing on the first topological graph to obtain the node feature matrix and the edge feature matrix.

[0057] Feature extraction is performed on the nodes and edges in the first topological graph to obtain node features and edge features for each node. Node features include geometric features that characterize local curvature, line width, and direction vectors, as well as layer features that characterize layer number and medium type. Edge features characterize the connection relationships between adjacent nodes. Node feature matrices and edge feature matrices are formed based on the node features of each node.

[0058] Step 303: Based on the node feature matrix and the edge feature matrix, generate path parameters that satisfy the first objective dimension constraint.

[0059] The node feature matrix and edge feature matrix implement structured feature storage, which facilitates batch processing of features in the matrix and improves processing efficiency. Specifically, batch message passing and updating are performed on each node feature in the node feature matrix and each edge feature in the edge feature matrix to predict the optimal coordinate correction vector for each path segment. Then, the correction vector is superimposed on the original coordinates to obtain the optimal path parameters.

[0060] It should be noted that the pre-trained path generation network can incorporate the first objective dimension constraint during the batch processing of features to ensure that the final output path parameters satisfy the first objective dimension constraint. Optionally, a graph neural network can be embedded in the path generation network, specifically using the graph neural network to perform message passing and updating of the features of each node and each edge.

[0061] In this application, a general waveguide topology generation technology based on a path generation network is implemented, which can cover the field of millimeter-scale chips, automatically generate complex waveguide paths that match the ports, and ensure that the generated waveguide layout is conflict-free.

[0062] See Figure 4 This illustrates an optional approach to step 303 above, which can generate path parameters across processes by normalizing features to cover different process scenarios. The features are then updated based on the first target dimension constraint to improve the rationality and reliability of the path parameters. This approach specifically includes: Step 401: Normalize the node features in the node feature matrix and the edge features in the edge feature matrix to obtain the initial topological features.

[0063] Step 402: Based on the first target dimension constraint, update the initial topological features to obtain the target topological features.

[0064] Step 403: Map the target topological features to continuous coordinate points to obtain path parameters.

[0065] A process difference table is obtained, and based on the scaling parameters in the table, the features of each node and each edge are normalized to obtain the corresponding initial topological features. The initial topological features include the feature vectors corresponding to the features of each node and the feature vectors corresponding to the features of each edge. The initial topological features can ensure that the path generation network has a uniform distribution of input features under different processes (such as different refractive indices and geometric scales).

[0066] Using the first objective dimension constraint as the update rule, the parts of the initial topological features that do not meet the constraints are adjusted, and the target topological features that satisfy the first objective dimension constraint are obtained through the update process.

[0067] The target topological features are converted into continuous path parameters by a nonlinear decoder, where the path parameters include the coordinate information of each coordinate point and the local curvature.

[0068] Optionally, for the geometric dimension, measures whether the bending radius and interlayer spacing exceed the limits; for the optical dimension, measures the difference between the predicted optical loss and the target optical loss; for the process dimension, measures the mode deviation of the optical port, and limits the continuity and manufacturability of the spline curve.

[0069] See Figure 5 This illustrates an optional approach to step 402 above, which can intelligently fuse node features based on weight information to more accurately represent the topology of silicon photonic circuits. This improves the accuracy of generating path parameters using target topology features. Specifically, this approach includes: Step 501: Based on the initial topological features, calculate the weight information of the adjacent nodes corresponding to each target node.

[0070] Step 502: For each target node, based on the weight information of the neighboring nodes corresponding to the target node and the first target dimension constraint, the node features of the target node and the node features of the neighboring nodes corresponding to the target node are aggregated to update the node features of the target node.

[0071] Step 503: Generate target topology features based on the updated node features of each target node and the initial topology features.

[0072] Each target node receives and aggregates the weight information of its neighboring nodes, and updates the node features of the target node in combination with the constraints of the first target dimension.

[0073] Specifically, based on the first topology graph, the adjacent nodes corresponding to each target node are determined. Then, based on the feature vectors corresponding to the features of each node in the initial topology features, the weight information of the adjacent nodes corresponding to each target node is calculated. The weight information is used to characterize the association strength of the adjacent node with the target node.

[0074] For each target node, collect the node features of the target node and the node features of its corresponding neighboring nodes, and perform fusion calculations according to the weight information to obtain the updated node features of the target node.

[0075] The initial topological features also include feature vectors corresponding to each edge feature. The updated node features of each target node are integrated and reconstructed to obtain the target topological features.

[0076] Based on the above embodiments, in an exemplary embodiment, the method of training the path generation network in this application is shown, specifically including: Obtain sample design parameters from a pre-built sample library, and perform at least one training operation on the initial path generation network based on the sample design parameters until the training termination condition is met, thus obtaining the trained path generation network. The training operations include: Determine the first path generation network corresponding to the current training operation; generate candidate actions based on the sample design parameters using the first path generation network corresponding to the current training operation; the candidate actions are used to generate the corresponding sample path parameters. By using a constraint engine, candidate actions are modified to obtain the target action; The target loss value is determined based on the target action, and the parameters of the first path generation network corresponding to the current training operation are adjusted based on the target loss value to obtain the first path generation network corresponding to the next training operation; the first path generation network corresponding to the first training operation is the initial path generation network.

[0077] A sample library is pre-built, and sample design parameters for different processes are stored in this library. When iteratively training the path generation network, these parameters can be directly retrieved from the sample library. Using the sample design parameters, the training operation is repeatedly performed on the first path generation network, iteratively updating the weights until the validation set error is less than a preset threshold. At this point, the training termination condition is met, the network parameters are frozen, and a stable, trained path generation network is obtained.

[0078] The constraint engine can embed analytical physical constraints, such as minimum bending radius and waveguide spacing limits, into the reinforcement learning environment model to ensure that optical wiring conforms to process rules. Specifically, during each training operation, candidate actions are generated based on sample design parameters. The constraint engine then receives the state vectors corresponding to the candidate actions and modifies them based on the state vectors to determine valid target actions that satisfy the constraints. Here, a candidate action refers to the set of all possible actions that can be considered; in this embodiment, it is represented by the movement of the wire end coordinates in the silicon photonics circuit wiring. The state vector is a mathematical representation of the current environmental state; in this embodiment, it is represented by a geometric state vector or an electrical state vector.

[0079] Furthermore, based on the target action, the target loss value is calculated, the reward function is updated, and a penalty term is added to adjust the parameters of the first path generation network to ensure convergence stability. Optionally, when the target loss value is less than a preset threshold, a convergence check is triggered and the parameter adjustment steps are frozen, resulting in the trained path generation network.

[0080] Optionally, runtime data and training parameters can be stored in log files for easy reproduction and retraining.

[0081] In this application, a path generation network was obtained through multiple rounds of training operations. During the optimization iteration, the parameters of the network were continuously adjusted to improve the prediction accuracy of the path generation network and achieve a high-precision level across processes.

[0082] Based on the above embodiments, in an exemplary embodiment, a method for constructing the sample library in this application is shown, specifically including: The system acquires design parameter files and predefined scanning strategies, configures target wavelengths and simulation accuracy requirements, and then generates a task queue corresponding to the design parameter files through the task manager. Each task in the task queue is assigned a unique identifier. Furthermore, a 3D simulation model is constructed, which is divided into spatial discrete meshes. A corresponding script file is created for each spatial discrete mesh to record the simulation area, source type, and boundary conditions.

[0083] Using the task manager, each task in the task queue is assigned to a different simulation solution node corresponding to the spatial discrete grid according to the computational resource load. This allows the simulation solution node to perform electromagnetic field time-domain propagation calculations, obtaining field distribution files and spectrum files. Optionally, during the simulation, the residual curve and Poynting power convergence status can be monitored in real time, and convergence can be achieved early when a corresponding threshold is reached to save computational resources.

[0084] Based on the field distribution file and the spectrum file, characteristic quantities such as optical loss, mode transmittance, reflectance, phase response and intermode coupling coefficient are calculated. By comparing the characteristic quantities corresponding to different design parameter files, the characteristic quantities are smoothed and interpolated. The processed label file is generated according to the predefined template. The label file is used to record the correlation between the design parameter file and the characteristic quantities.

[0085] Based on the sample description standard, the design parameter files and feature quantities are normalized and their integrity is verified, and then stored in the database in the form of key-value pairs to form the sample library required for training the path generation network.

[0086] Optionally, for the sample design parameters in the sample library, the coverage and efficiency are calculated respectively. If the coverage is low, the incremental sampling process is triggered, and the newly sampled data is incorporated into the sample library after simulation and correction, so as to realize the self-updating of the sample library.

[0087] In this application, the design parameter file is obtained by sampling and processed by simulation technology to obtain sample design parameters that meet the standards, thereby constructing a dynamically updated sample library to meet the network training requirements, realize the automated construction from no samples to standard samples, and provide a stable and reliable training data foundation for reinforcement learning algorithms.

[0088] Based on the above embodiments, in an exemplary embodiment, a method for updating the training set in the sample library according to the present application is shown, specifically including: Optical, electrical, and thermal measured data of finished devices, such as optical loss, transmission spectrum, phase, delay time, and maximum temperature rise, are obtained from the experimental measurement platform. Then, the initial measured data are standardized, outlier detected, and noise filtered to obtain the target measured data.

[0089] The optical, electrical, and thermal prediction data of the simulated devices are acquired through simulation. The measured data and predicted data are mapped one-to-one according to the device number to form a matching dataset. For each pair of matched data in the matching dataset, the measured simulation error is calculated, and differentiable mapping functions for physical parameters such as refractive index, thickness, and temperature coefficient are established. The gradient of the error with respect to the physical parameters is calculated, and a correction vector is generated based on the learning rate. This correction vector is used to update the parameters of the 3D simulation model, and the updated 3D simulation model can generate higher-quality sample design parameters in the next simulation.

[0090] Optionally, the calibration log records the adjustment magnitude and corresponding error change curve for each parameter adjustment of the 3D simulation model. Based on the adjustment magnitude and error change curve, a calibration effect report and trend chart are generated for long-term analysis. The calibration effect report includes the error reduction rate before and after calibration, model fit goodness, and parameter convergence stability indicators.

[0091] In this application, data such as optical loss, spectrum, and delay from actual tests are obtained and compared with simulation prediction results. Then, the parameters of the material, thickness, and temperature models are fine-tuned through a gradient backpropagation algorithm, and the training set is updated in real time. Through this mode, the three-dimensional simulation model can continuously converge to the real manufacturing environment and achieve long-term self-calibration.

[0092] See Figure 6 This illustrates an optional method for obtaining the target action based on candidate action correction in the above training steps. This method can correct data that is not allowed by physical laws based on constraint equations, thereby obtaining a suitable target action corresponding to the candidate action and improving network quality. Specifically, this method includes: Step 601: Determine the state vector corresponding to the candidate action.

[0093] Step 602: Obtain the target constraint equation from the pre-built constraint equation library.

[0094] The constraint equation library includes constraint equations corresponding to the second objective dimension, which includes at least optical, geometric, electrical, and thermal dimensions.

[0095] Step 603: Calculate the physical deviation of the state vector based on the target constraint equation.

[0096] Step 604: If the physical deviation is greater than the first preset threshold, the state vector is mapped to the nearest physical boundary to correct the state vector.

[0097] The physical boundary is the dimensional boundary corresponding to the objective constraint equation.

[0098] Step 605: Determine the target action corresponding to the candidate action based on the corrected state vector.

[0099] The constraint equation library stores constraint equations corresponding to different dimensions. The constraint equations corresponding to the optical dimension can be used to characterize mode phase matching equations, critical bending radius constraints, etc. The constraint equations corresponding to the geometric dimension can be used to characterize waveguide spacing, minimum linewidth, etc. The constraint equations corresponding to the electrical dimension can be used to characterize interconnect impedance, capacitance parasitic limits, etc. The constraint equations corresponding to the thermal dimension can be used to characterize thermal resistance networks, maximum temperature distribution limits, etc.

[0100] The process involves calculating the state vector corresponding to a candidate action, then selecting the appropriate constraint equation (target constraint equation) from the constraint equation library. The state vector is then substituted into the target constraint equation to calculate the physical deviation corresponding to the current state. If the physical deviation exceeds a first preset threshold, it indicates that the physical deviation exceeds the allowable range. In this case, a projection function is used to map the state vector to the nearest physical boundary to correct the state vector. Finally, the target action is determined based on the corrected state vector. The nearest physical boundary refers to the range allowed by the physical laws of the second target dimension to which the target constraint equation belongs.

[0101] Optionally, the action space is discretely sampled to determine whether each candidate action violates geometric or material constraints. Candidate actions that do not meet the process rules are masked, and only suitable candidate actions are added to the reinforcement learning update process.

[0102] Optionally, parameters such as waveguide layer thickness, refractive index, refractive index coefficient, temperature drift, resistivity, and material thermal conductivity can be obtained from the simulation database. Based on these parameters, corresponding physical models can be constructed, such as waveguide effective refractive index models, temperature coupling equations, and metal interconnect impedance models. The constructed physical models can be instantiated and associated with specific layer numbers or structure types to form corresponding standardized parameter tables for constructing constraint equation libraries.

[0103] Optionally, the number of constraint violations, average deviation, and projection correction magnitude can be recorded for subsequent analysis and stability verification.

[0104] Optionally, when new process or material parameters need to be imported, the constraint equation library can be automatically updated to achieve cross-process adaptation.

[0105] See Figure 7 This illustrates an optional method for determining the target loss value based on the target action in the above training steps. This method can keep the convergence speed and contribution of the optical, electrical, and thermal dimensions consistent during optimization iterations, avoiding the problem of single-dimensional dominance and coupling imbalance. Specifically, this method includes: Step 701: Obtain the loss values ​​corresponding to the third target dimension based on the target action.

[0106] The third objective dimension includes at least the optical dimension, the electrical dimension, and the thermal dimension.

[0107] Step 702: Based on the weight coefficients corresponding to each third objective dimension, the loss value is weighted and calculated to obtain the target loss value.

[0108] Three surrogate models are pre-built: optical attenuation, electrical delay, and thermal distribution. The optical attenuation surrogate model fits optical loss to mode bandwidth using a multilayer perceptron; the electrical delay surrogate model maps layout to latency and power consumption using a convolutional network; and the thermal distribution surrogate model calculates the maximum junction temperature using a sparse radial basis function network. The parameters of these three surrogate models are stored as a weight file for direct use when performing weighted calculations of the loss values.

[0109] Specifically, the loss values ​​corresponding to the target action are calculated based on the three proxy models mentioned above, resulting in optical loss, electrical loss, and thermal loss values. Then, the weight coefficients corresponding to the three proxy models are called to perform weighted calculations on the optical loss, electrical loss, and thermal loss values ​​to obtain the final target loss value.

[0110] Optionally, for each third objective dimension, the local gradient of that dimension is determined based on the ratio between the loss value of that dimension and the shared design parameter vector. Different dimensions use the same preset shared design parameter vector, and then dynamic normalization is used to scale the local gradients of different dimensions to a uniform scale for comparison. If the contribution of any third objective dimension is too high, the weight coefficient corresponding to that dimension is reduced to avoid training oscillations or single-dimensional dominance. If there are directional conflicts between different third objective dimensions, an angle correction algorithm or a Kalman filter algorithm is used to adjust the direction.

[0111] Optionally, the loss value change curve for each third objective dimension can be recorded, the comprehensive convergence index can be calculated, and then the optimal shared design parameter vector can be obtained based on the comprehensive convergence index satisfying the convergence condition.

[0112] Optionally, a performance report containing optical loss, electrical delay, and maximum temperature can be generated based on the shared design parameter vector, and the percentage contribution of photoelectric and thermal weights can be calculated for subsequent interpretable analysis.

[0113] Electronic and optical layouts often struggle to simultaneously meet requirements for delay, loss, and thermal stability, frequently necessitating repeated manual adjustments, resulting in low design efficiency and a tendency to produce local optima. This application introduces adaptive weight adjustment and normalization mechanisms into the reinforcement learning reward function, constructing a multi-constraint collaborative cost function to achieve simultaneous balanced optimization of optical, electronic, and thermal performance. This allows for comprehensive consideration of electronic delay, optical loss, and thermal disturbance weights during the layout phase, achieving global balanced optimization of both signal paths and significantly improving the overall performance and manufacturability of hybrid integrated chips.

[0114] Based on the above embodiments, in an exemplary embodiment, see [link to example]. Figure 8 This illustrates a method for modifying the path geometry model in an embodiment of this application, specifically including: Step 801: Perform design rule checks on the path geometry model based on the process description file to obtain the target check results.

[0115] The design rule checks include at least line width checks, spacing checks, bending radius checks, and layer mismatch checks.

[0116] Step 802: Based on the target inspection results, the path geometry model is corrected to obtain the corrected path geometry model.

[0117] The process description document defines corresponding design rules. Based on the process description document, multiple checks are performed on the path geometry model constructed based on path parameters to obtain multiple target check results. Among them, linewidth check means that if the linewidth represented in the path geometry model is less than a minimum set value, the linewidth is marked as a violation; spacing check means that the spacing between adjacent waveguides and metal layers is measured, and if the spacing is less than a minimum set value, a violation is recorded; bending radius check means that the path curvature in the path geometry model is calculated, and if the curvature is less than a minimum set value, a risk point is marked in the path; layer mismatch check means that the optical layer and the pad layer are located in the correct stacking structure, and if not, a violation is recorded.

[0118] Furthermore, an inspection report is generated based on the target inspection results, including the coordinates of the violation points and corresponding correction suggestions. Based on the inspection report, local vector smoothing and linewidth expansion operations are performed on the violation areas. For paths with excessively small curvature radii, a polynomial refitting method is used to restore the curvature to a manufacturable range. For layer mismatch violations, the incorrect layer numbers are corrected based on an automatic layer remapping table. Optionally, a local interpolation algorithm is used in the above correction process to avoid affecting the original geometric topology of the path geometric model.

[0119] Accordingly, the corrected path geometry model is converted into layout data under the target process.

[0120] In this application, the path geometry model is checked for design rules from multiple aspects, and any violations are corrected. Based on the corrected path geometry model, the layout data is determined, resulting in more accurate and reasonable layout data, thereby improving the effectiveness and reliability of the layout file.

[0121] Based on the above embodiments, in an exemplary embodiment, see [link to example]. Figure 9 This illustrates the method of photoelectric file conversion in the embodiments of this application, specifically including: Step 901: Obtain the electronic design file input by the user, and construct a semantic mapping table based on the initial layout file and the electronic design file.

[0122] Step 902: Construct an optoelectronic data model based on a semantic mapping table according to a preset conversion template.

[0123] Step 903: The initial layout file is parsed and processed using the optoelectronic data model to obtain the corresponding electronic macrocell definition.

[0124] Step 904: Obtain optical metadata and embed the optical metadata into the electronic macrocell definition.

[0125] Step 905: Update the electronic design file based on the embedded electronic macrocell definition to obtain the initial electronic file corresponding to the initial layout file.

[0126] The electronic design file and the initial layout file are parsed to determine the file hierarchy, unit instances and coordinate system. Then, a semantic mapping table is constructed based on the parsing results. The semantic mapping table is used to define the correspondence between logical ports, optical ports, electronic ports and layer attributes.

[0127] The optoelectronic data model constructed according to the preset conversion template has a corresponding tree structure, which can be used to represent the relationship between layers, units, and ports. Specifically, the optoelectronic data model is constructed based on a semantic mapping table, where layer nodes are used to record layer numbers, material properties, and optical / electrical labels, unit nodes are used to describe unit geometric boundaries and reference relationships, and port nodes are used to store port names, orientations, mode types, and waveguide parameters.

[0128] Optical files are converted to electronic orientation using optoelectronic data models. For example, geometric information in the initial layout file is parsed to generate electronic macrocell definitions required for electronic wiring. Then, optical metadata describing the optical devices is obtained and appended to the electronic macrocell definitions, thereby updating the electronic design file and replacing electronic design files that do not contain optical devices with the initial electronic file containing a complete optoelectronic model.

[0129] Optionally, the electronic file can be converted to an optical orientation using an optoelectronic data model. For example, a layout layer structure can be generated, and extended fields such as aperture identifiers, mode identifiers, and layer labels can be added to the layout file to output a unified optoelectronic layout.

[0130] In this application, in order to perform accurate and efficient optoelectronic consistency verification and establish an equivalent mapping relationship between optics and electronics, the electronic design file is first converted into an initial electronic file based on the specification, realizing the logical and physical synchronization of optoelectronic data, so that optoelectronic modules can be collaboratively optimized and verified in the same environment, which greatly improves the consistency and efficiency of hybrid integrated circuit design.

[0131] Based on the above embodiments, in an exemplary embodiment, see [link to example]. Figure 10 This illustrates the method for photoelectric consistency verification in embodiments of this application, specifically including: Step 1001: Generate the corresponding layout netlist based on the initial layout file, and generate the corresponding electronic netlist based on the initial electronic file.

[0132] Step 1002: Match the map netlist with the electronic netlist to obtain the matching similarity.

[0133] Step 1003: If the matching similarity is less than the second preset threshold, then the photoelectric consistency verification is determined to have failed.

[0134] Step 1004: In the event of failure of photoelectric consistency verification, record the difference information between the layout netlist and the electronic netlist, and correct the initial layout file based on the difference information to obtain the target layout file.

[0135] An electronic netlist is generated based on the initial electronic file. The netlist is then hierarchically parsed to extract the nodes, pins, and interconnection information of electronic components. When generating the initial layout file based on the layout data, a netlist description file is also generated simultaneously. Optical component nodes such as waveguides, couplers, and modulators are identified from the netlist description file. A unified numbering rule is used to identify each node and port, thereby generating a unified node table and connection table.

[0136] Obtain a semantic mapping table based on the initial layout file and electronic design file. Based on the initial layout file and semantic mapping table, determine the geometry of each layer and the corresponding device instances to calculate the topological connection relationship between optical ports and generate the corresponding layout netlist. If the initial layout file contains an optical path file, parse the waveguide connection relationship and calculate the distance vector between nodes.

[0137] Furthermore, the physical netlist and the electronic netlist are aligned in three dimensions: port-layer-topology. Matching is performed according to the corresponding dimensions, and the matching similarity is calculated. If the matching similarity is less than a second preset threshold, the matching between the physical netlist and the electronic netlist is considered too low, and the photoelectric consistency verification fails. In the case of photoelectric consistency verification failure, discrepancy information is determined based on the mismatched areas between the physical netlist and the electronic netlist. Based on this discrepancy information, the initial physical netlist file is corrected accordingly to obtain the final output target physical netlist file.

[0138] Optionally, the discrepancy information includes, but is not limited to, missing nodes, inconsistent port names, connection errors, and cross-layer mismatches. A verification report can be generated based on this discrepancy information. The report includes the error type, relevant node identifiers, layout coordinates, and suggested corrective measures. A graphical discrepancy annotation file can also be generated for layout review.

[0139] In this application, optical ports, coupling regions, and mode connection relationships can be identified, and optoelectronic consistency verification can be performed based on port naming and matching rules, providing a reliable design approval basis for the mass production of hybrid integrated chips and improving the accuracy of verification.

[0140] See Figure 11 This illustrates an optional approach to step 1002 above, which can accurately measure the photoelectric consistency verification results using a data-driven method. This method specifically includes: Step 1101: Match the first optical content in the layout netlist with the second optical content in the electronic netlist to obtain the optical matching result.

[0141] Step 1102: Match the first electronic content in the map netlist with the second electronic content in the electronic netlist to obtain the electronic matching result.

[0142] Step 1103: Match the optoelectronic mixed content in the map netlist with the optoelectronic mixed content in the electronic netlist to obtain the optoelectronic mixed matching result.

[0143] Step 1104: Calculate the matching similarity based on the optical matching results, electronic matching results, and photoelectric hybrid matching results.

[0144] Information such as mode type, number, and transmission path from the physical netlist and electronic netlist is obtained to obtain optical matching results. Node numbers and electrical parameters such as capacitance and resistance from the physical and electronic netlists are obtained to obtain electronic matching results. Shared nodes such as opto-modulators from the physical and electronic netlists are obtained to obtain hybrid opto-modulator matching results. Based on the optical, electronic, and hybrid opto-modulator matching results, the proportion of the matching region in the overall result is calculated to obtain the matching similarity.

[0145] Based on the above embodiments, in an exemplary embodiment, a visualization processing method for network training in this application is shown, specifically including: During the training of the path generation network, training logs, loss curves, and gradient tensors are obtained. Relevant variables and intermediate features are encapsulated into log files, and after adding timestamps to the log files, they are uploaded to the database to form a traceable data trajectory.

[0146] Specifically, attribution analysis is performed on the input features of the path generation network (i.e., the feature extraction results of design parameters, including but not limited to node features and edge features), the importance score of each feature is calculated, a weight distribution map is generated, and the geometric parameters or process variables with the greatest impact on the output are identified in the weight distribution map. The intermediate attention matrix is ​​extracted and mapped to a two-dimensional heatmap to display the node-edge interaction strength. For key input features, local sensitivity calculation can also be performed, using partial derivatives or perturbation analysis to solve for the response change rate, combined with LIME (Local Interpretable Model). AgnosticExplanations (a local interpretability model diagnostic interpretation) generates a local approximate linear model and finally outputs a local interpretation report, which is used to explain the direction and intensity of the impact of changes in specific design parameters on performance indicators such as light loss and power consumption.

[0147] Optionally, the system can display a parameter-target mapping scatter plot, a feature correlation matrix heatmap, and a time-series convergence curve display area to the user. When the user selects a specific parameter area on the visualization interface, they can make manual corrections or weighted adjustments, using the manual input as a reward or penalty signal for optimization.

[0148] In this application, the required data is extracted during the training process of the path generation network. Through feature attribution analysis, attention visualization, and human-computer feedback collaboration mechanism, the transparency and controllability of network training are improved, and the model decisions are interpretable, the parameter optimization is interventionist, and the performance converges to a more stable level.

[0149] Based on the above embodiments, in an exemplary embodiment, see [link to example]. Figure 12 Another flowchart illustrating the design method of silicon photonics circuits in this application is shown below, and is described in detail below: Step 1201: Obtain the optical design file and preset process description file input by the user, and parse the optical design file and process description file to obtain the design parameters of the silicon photonics circuit.

[0150] Step 1202: Using a pre-trained path generation network, a first topology graph is constructed based on design parameters. Feature extraction is performed on the first topology graph to obtain a node feature matrix and an edge feature matrix. The node features in the node feature matrix and the edge features in the edge feature matrix are normalized to obtain initial topology features. Based on the initial topology features, the weight information of the adjacent nodes corresponding to each target node is calculated. For each target node, based on the weight information of the adjacent nodes corresponding to the target node and the first target dimension constraint, the node features of the target node and the node features of the adjacent nodes corresponding to the target node are aggregated to update the node features of the target node. Based on the updated node features of each target node and the initial topology features, target topology features are generated. The target topology features are mapped to continuous coordinate points to obtain path parameters.

[0151] Step 1203: Construct a path geometric model based on path parameters, perform design rule checks on the path geometric model based on the process description file to obtain the target check results, and correct the path geometric model based on the target check results to obtain the corrected path geometric model.

[0152] Step 1204: Convert the corrected path geometry model into layout data under the target process, and generate the initial layout file of the silicon photonics circuit based on the layout data.

[0153] Step 1205: Obtain the electronic design file input by the user, and construct a semantic mapping table based on the initial layout file and the electronic design file. According to the preset conversion template, construct an optoelectronic data model based on the semantic mapping table. Through the optoelectronic data model, parse and process the initial layout file to obtain the corresponding electronic macrocell definition, obtain optical metadata, and embed the optical metadata into the electronic macrocell definition. Update the electronic design file based on the embedded electronic macrocell definition to obtain the initial electronic file corresponding to the initial layout file.

[0154] Step 1206: Generate a corresponding layout netlist based on the initial layout file, and a corresponding electronic netlist based on the initial electronic file. Match the first optical content in the layout netlist with the second optical content in the electronic netlist to obtain an optical matching result. Match the first electronic content in the layout netlist with the second electronic content in the electronic netlist to obtain an electronic matching result. Match the optoelectronic hybrid content in the layout netlist with the optoelectronic hybrid content in the electronic netlist to obtain an optoelectronic hybrid matching result. Calculate the matching similarity based on the optical matching result, the electronic matching result, and the optoelectronic hybrid matching result. If the matching similarity is less than a second preset threshold, the optoelectronic consistency verification is determined to have failed.

[0155] Step 1207: In the event of failure of photoelectric consistency verification, record the difference information between the layout netlist and the electronic netlist, and correct the initial layout file based on the difference information to obtain the target layout file.

[0156] In this application, a path generation network based on artificial intelligence algorithms is used to obtain the path parameters of silicon photonic circuits, thereby optimizing the layout and routing. Then, the initial layout file generated based on the path parameters is subjected to optoelectronic consistency verification to obtain a target layout file that meets the design requirements of silicon photonic circuits.

[0157] The following describes an embodiment of the apparatus described in this application, which can be used to execute the silicon photonics circuit design method described in the above embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the silicon photonics circuit design method described above.

[0158] See Figure 13 A block diagram of a silicon photonics circuit design apparatus 1300 according to an embodiment of this application is shown, specifically including: The file parsing module 1301 is used to obtain the optical design file and the preset process description file input by the user, and to parse the optical design file and the process description file to obtain the design parameters of the silicon photonics circuit. The optical design file includes the initial port information of each optical port, and the process description file is used to characterize the design rule information of the process dimension. The path generation module 1302 is used to generate path parameters that satisfy the first target dimension constraint conditions based on the design parameters through a pre-trained path generation network; wherein the first target dimension includes at least a geometric dimension, an optical dimension and a process dimension. The file generation module 1303 is used to construct a path geometry model based on path parameters, convert the path geometry model into layout data under the target process, and generate an initial layout file of silicon photonics circuit based on the layout data; wherein, the target process is used to characterize the process indicated by the user. The file verification module 1304 is used to perform optoelectronic consistency verification on the initial layout file and determine the target layout file corresponding to the initial layout file based on the verification results.

[0159] In an exemplary embodiment, based on the above embodiments, the design parameters include target port information for each optical port, and the path generation module 1302 includes: The topology graph construction unit is used to construct a first topology graph based on the target port information of each optical port; wherein, each node in the first topology graph corresponds one-to-one with each optical port; The matrix construction unit is used to perform feature extraction processing on the first topological graph to obtain the node feature matrix and the edge feature matrix. The path parameter generation unit is used to generate path parameters that satisfy the first objective dimension constraint based on the node feature matrix and the edge feature matrix.

[0160] In an exemplary embodiment, based on the above embodiments, the path parameter generation unit includes: The normalization processing subunit is used to normalize the node features in the node feature matrix and the edge features in the edge feature matrix to obtain the initial topological features. The feature update subunit is used to update the initial topological features based on the first target dimension constraint to obtain the target topological features; The path parameter generation sub-unit is used to map the target topological features into continuous coordinate points to obtain path parameters; the path parameters include the coordinate information and local curvature of each coordinate point.

[0161] In an exemplary embodiment, based on the above embodiments, the feature update subunit is specifically used to calculate the weight information of the adjacent nodes corresponding to each target node based on the initial topological features; for each target node, based on the weight information of the adjacent nodes corresponding to the target node and the first target dimension constraint, the node features of the target node and the node features of the adjacent nodes corresponding to the target node are aggregated to update the node features of the target node; and based on the updated node features of each target node and the initial topological features, target topological features are generated.

[0162] In an exemplary embodiment, based on the above embodiments, the silicon photonics circuit design apparatus 1300 further includes a network training module, which is used to obtain sample design parameters from a pre-built sample library, and perform at least one training operation on the initial path generation network based on the sample design parameters until the training termination condition is met, thereby obtaining the trained path generation network. The training operations include: Determine the first path generation network corresponding to the current training operation; generate candidate actions based on the sample design parameters using the first path generation network corresponding to the current training operation; the candidate actions are used to generate the corresponding sample path parameters. By using a constraint engine, candidate actions are modified to obtain the target action; The target loss value is determined based on the target action, and the parameters of the first path generation network corresponding to the current training operation are adjusted based on the target loss value to obtain the first path generation network corresponding to the next training operation; the first path generation network corresponding to the first training operation is the initial path generation network.

[0163] In an exemplary embodiment, based on the above embodiments, the network training module includes an action correction unit, used to determine the state vector corresponding to the candidate action; obtain the target constraint equation from a pre-built constraint equation library; wherein the constraint equation library includes constraint equations corresponding to the second target dimension, and the second target dimension includes at least an optical dimension, a geometric dimension, an electrical dimension, and a thermal dimension; calculate the physical deviation of the state vector based on the target constraint equation; if the physical deviation is greater than a first preset threshold, map the state vector to the nearest physical boundary to correct the state vector; wherein the physical boundary is the dimensional boundary corresponding to the target constraint equation; and determine the target action corresponding to the candidate action based on the corrected state vector.

[0164] In an exemplary embodiment, based on the above embodiment, the network training module includes a loss value calculation unit, used to obtain loss values ​​corresponding to the third target dimension based on the target action; wherein, the third target dimension includes at least an optical dimension, an electrical dimension, and a thermal dimension; and the loss values ​​are weighted and calculated based on the weight coefficients corresponding to each third target dimension to obtain the target loss value.

[0165] In an exemplary embodiment, based on the above embodiments, the document generation module 1303 further includes a model correction unit, used to perform design rule checks on the path geometry model based on the process description file to obtain target check results; wherein, the design rule checks include at least line width checks, spacing checks, bending radius checks, and layer mismatch checks; and the path geometry model is corrected based on the target check results to obtain a corrected path geometry model. In an exemplary embodiment, based on the above embodiments, the silicon photonics circuit design apparatus 1300 further includes a data conversion module, used to acquire the electronic design file input by the user, and construct a semantic mapping table based on the initial layout file and the electronic design file; construct an optoelectronic data model based on the semantic mapping table according to a preset conversion template; parse and process the initial layout file through the optoelectronic data model to obtain the corresponding electronic macrocell definition; acquire optical metadata and embed the optical metadata into the electronic macrocell definition; update the electronic design file based on the embedded electronic macrocell definition to obtain the initial electronic file corresponding to the initial layout file.

[0166] In an exemplary embodiment, based on the above embodiments, the document verification module 1304 includes: The netlist extraction unit is used to generate the corresponding layout netlist based on the initial layout file, and to generate the corresponding electronic netlist based on the initial electronic file. The netlist matching unit is used to match the layout netlist with the electronic netlist to obtain the matching similarity. The consistency verification unit is used to determine that the photoelectric consistency verification has failed if the matching similarity is less than a second preset threshold. The layout correction unit is used to record the difference information between the layout netlist and the electronic netlist in the event of failure of photoelectric consistency verification, and to correct the initial layout file based on the difference information to obtain the target layout file.

[0167] In an exemplary embodiment, based on the above embodiments, the netlist matching unit includes: The optical matching subunit is used to match the first optical content in the layout netlist with the second optical content in the electronic netlist to obtain the optical matching result; The electronic matching subunit is used to match the first electronic content in the map netlist with the second electronic content in the electronic netlist to obtain the electronic matching result; The hybrid matching subunit is used to match the optoelectronic hybrid content in the layout netlist with the optoelectronic hybrid content in the electronic netlist to obtain the optoelectronic hybrid matching result; The similarity calculation subunit is used to calculate the matching similarity based on optical matching results, electronic matching results, and photoelectric hybrid matching results.

[0168] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing computer program instructions. When the computer program instructions are loaded and executed by a processor, they implement the steps of the silicon photonics circuit design method described above.

[0169] Based on the same inventive concept, this application provides an electronic device, see [link to relevant documentation]. Figure 14 The diagram shows a schematic of the structure of an electronic device in an embodiment of this application. The electronic device includes one or more memories 1404, one or more processors 1402, and at least one computer program stored in the memory 1404 and executable on the processor 1402. When the processor 1402 executes the computer program, it implements the steps of the silicon photonics circuit design method described above.

[0170] The bus architecture (represented by bus 1400) may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 1402 and memory represented by memory 1404. Bus 1400 may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 1405 provides an interface between bus 1400 and receiver 1401 and transmitter 1403. Receiver 1401 and transmitter 1403 may be the same element, a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 1402 is responsible for managing bus 1400 and general processing, while memory 1404 can be used to store data used by processor 1402 during operation.

[0171] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Furthermore, the functional units may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0172] Based on the same inventive concept, this application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the silicon photonics circuit design method described above.

[0173] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0174] The units described as separate components may or may not be physically separate. Similarly, the components of the control device may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0175] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program instructions, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0176] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A design method for silicon photonic circuits, characterized in that, The method includes: The system acquires the user-input optical design file and the preset process description file, and parses the optical design file and the process description file to obtain the design parameters of the silicon photonics circuit; wherein, the optical design file includes the initial port information of each optical port, and the process description file is used to characterize the design rule information of the process dimension; A pre-trained path generation network is used to generate path parameters that satisfy the first target dimension constraint based on the design parameters; wherein, the first target dimension includes at least the geometric dimension, the optical dimension, and the process dimension. A path geometry model is constructed based on the path parameters, the path geometry model is converted into layout data under the target process, and an initial layout file of the silicon photonics circuit is generated based on the layout data; wherein, the target process is used to characterize the process specified by the user; The initial layout file is subjected to photoelectric consistency verification, and the target layout file corresponding to the initial layout file is determined based on the verification results.

2. The method according to claim 1, characterized in that, The design parameters include target port information for each optical port, and the generation of path parameters that satisfy the first target dimension constraint based on the design parameters includes: A first topology graph is constructed based on the target port information of each optical port; wherein each node in the first topology graph corresponds one-to-one with each optical port; The first topological graph is subjected to feature extraction processing to obtain the node feature matrix and the edge feature matrix; Based on the node feature matrix and the edge feature matrix, path parameters that satisfy the first target dimension constraint are generated.

3. The method according to claim 2, characterized in that, The step of generating path parameters that satisfy the first target dimension constraint based on the node feature matrix and the edge feature matrix includes: Normalize the node features in the node feature matrix and the edge features in the edge feature matrix to obtain the initial topological features; Based on the first target dimension constraint, the initial topological features are updated to obtain the target topological features; The target topological feature is mapped to continuous coordinate points to obtain path parameters; wherein, the path parameters include the coordinate information and local curvature of each coordinate point.

4. The method according to claim 3, characterized in that, The step of updating the initial topological features based on the first target dimension constraint to obtain the target topological features includes: Based on the initial topological features, calculate the weight information of the adjacent nodes corresponding to each target node; For each target node, based on the weight information of the neighboring nodes corresponding to the target node and the first target dimension constraint, the node features of the target node and the node features of the neighboring nodes corresponding to the target node are aggregated to update the node features of the target node. Based on the updated node features of each target node and the initial topology features, target topology features are generated.

5. The method according to claim 1 or 4, characterized in that, The path generation network is trained through the following steps: Obtain sample design parameters from a pre-built sample library, and perform at least one training operation on the initial path generation network based on the sample design parameters until the training termination condition is met, thus obtaining the trained path generation network. The training operations include: Determine the first path generation network corresponding to the current training operation; generate candidate actions based on the sample design parameters using the first path generation network corresponding to the current training operation; the candidate actions are used to generate the corresponding sample path parameters. The candidate actions are modified using a constraint engine to obtain the target action; Based on the target action, a corresponding target loss value is determined, and the parameters of the first path generation network corresponding to the current training operation are adjusted based on the target loss value to obtain the first path generation network corresponding to the next training operation; the first path generation network corresponding to the first training operation is the initial path generation network.

6. The method according to claim 5, characterized in that, The step of modifying the candidate action to obtain the target action includes: Determine the state vector corresponding to the candidate action; Obtain the target constraint equation from a pre-built constraint equation library; wherein the constraint equation library includes constraint equations corresponding to the second target dimension, and the second target dimension includes at least an optical dimension, a geometric dimension, an electrical dimension, and a thermal dimension; The physical deviation of the state vector is calculated based on the target constraint equation; If the physical deviation is greater than a first preset threshold, the state vector is mapped to the nearest physical boundary to correct the state vector; wherein the physical boundary is the dimensional boundary corresponding to the target constraint equation. The target action corresponding to the candidate action is determined based on the corrected state vector.

7. The method according to claim 5, characterized in that, Determining the corresponding target loss value based on the target action includes: Based on the target action, loss values ​​corresponding to the third target dimension are obtained respectively; wherein, the third target dimension includes at least an optical dimension, an electrical dimension, and a thermal dimension; The loss value is calculated by weighting the loss values ​​based on the weight coefficients corresponding to each third objective dimension, thus obtaining the target loss value.

8. The method according to claim 1, characterized in that, After constructing the path geometry model based on the path parameters, the method further includes: The design rule check is performed on the path geometry model based on the process description file to obtain the target check result; wherein, the design rule check includes at least line width check, spacing check, bending radius check and layer mismatch check; Based on the target inspection results, the path geometry model is corrected to obtain the corrected path geometry model; Accordingly, converting the path geometry model into layout data under the target process includes: The corrected path geometry model is converted into layout data for the target process.

9. The method according to claim 1, characterized in that, Before performing photoelectric consistency verification on the initial layout file, the method further includes: Obtain the electronic design file input by the user, and construct a semantic mapping table based on the initial layout file and the electronic design file; According to the preset conversion template, an optoelectronic data model is constructed based on the semantic mapping table; The initial layout file is parsed and processed using the aforementioned photoelectric data model to obtain the corresponding electronic macrocell definition; Obtain optical metadata and embed the optical metadata into the electronic macrocell definition; The electronic design file is updated based on the embedded electronic macrocell definition to obtain the initial electronic file corresponding to the initial layout file.

10. The method according to claim 9, characterized in that, The step of performing photoelectric consistency verification on the initial layout file and determining the target layout file corresponding to the initial layout file based on the verification results includes: Generate a corresponding layout netlist based on the initial layout file, and generate a corresponding electronic netlist based on the initial electronic file; The map netlist is matched with the electronic netlist to obtain the matching similarity. If the matching similarity is less than the second preset threshold, the photoelectric consistency verification is determined to have failed. In the event of failure of photoelectric consistency verification, the difference information between the layout netlist and the electronic netlist is recorded, and the initial layout file is corrected based on the difference information to obtain the target layout file.

11. The method according to claim 10, characterized in that, The step of matching the layout netlist with the electronic netlist to obtain the matching similarity includes: The first optical content in the layout netlist is matched with the second optical content in the electronic netlist to obtain an optical matching result; The first electronic content in the map netlist is matched with the second electronic content in the electronic netlist to obtain the electronic matching result; The photoelectric hybrid content in the layout netlist is matched with the photoelectric hybrid content in the electronic netlist to obtain the photoelectric hybrid matching result; The matching similarity is calculated based on the optical matching result, the electronic matching result, and the photoelectric hybrid matching result.

12. A design apparatus for silicon photonic circuits, characterized in that, The device includes: The file parsing module is used to obtain the optical design file and the preset process description file input by the user, and to parse the optical design file and the process description file to obtain the design parameters of the silicon photonics circuit; wherein, the optical design file includes the initial port information of each optical port, and the process description file is used to characterize the design rule information of the process dimension; The path generation module is used to generate path parameters that satisfy the first target dimension constraint conditions based on the design parameters through a pre-trained path generation network; wherein the first target dimension includes at least the geometric dimension, the optical dimension and the process dimension. The file generation module is used to construct a path geometry model based on the path parameters, convert the path geometry model into layout data under the target process, and generate an initial layout file of the silicon photonics circuit based on the layout data; wherein, the target process is used to characterize the process indicated by the user; The file verification module is used to perform photoelectric consistency verification on the initial layout file and determine the target layout file corresponding to the initial layout file based on the verification results.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when loaded and executed by a processor, perform the operations performed by the method as described in any one of claims 1 to 11.

14. An electronic device comprising a processor and a memory, characterized in that, The memory stores computer program instructions that can be executed by the processor, and when the processor executes the computer program instructions, it performs the operation as described in any one of claims 1 to 11.

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