Mechanical and electrical equipment fault diagnosis system and method based on knowledge graph

Abstract

The application is mechanical and electrical equipment fault diagnosis system and method based on knowledge graph, relates to mechanical and electrical equipment fault diagnosis technical field, and includes: atlas certainty partition module; memory continuity allocation module; boundary edge pruning index module; certainty multi-hop query execution module.In the application, the certainty coding mechanism based on the equipment physical bill of materials tree maps the physical hierarchical assembly relationship of the mechanical and electrical equipment into the binary semantic identification of nodes, and the continuous memory partition and linear storage layout are realized on the basis, the random memory access of the fault diagnosis is completely converted into sequential memory access, the processor hardware prefetch characteristics are fully adapted, and the occurrence probability of cache miss, page table cache invalidation and page fault interruption is reduced.

Description

Technical Field

[0001] This invention relates to the field of electromechanical equipment fault diagnosis technology, and in particular to an electromechanical equipment fault diagnosis system and method based on knowledge graphs. Background Technology

[0002] In industrial production settings, heavy electromechanical equipment such as megawatt-class wind turbines, full-face tunnel boring machines, and large steam turbine generator sets contain tens of thousands of components. These components form complex coupled systems through mechanical, electrical, and hydraulic relationships. A failure in a single component can cascade along the physical connection path, ultimately leading to equipment downtime or even production safety accidents. Therefore, rapid and accurate root cause tracing and diagnosis are core requirements for ensuring the safe and stable operation of industrial equipment.

[0003] Currently, knowledge graph technology is widely used in the field of electromechanical equipment fault diagnosis. By modeling components and fault propagation logic using an entity-relationship graph structure, it enables multi-hop tracing of fault root causes. However, existing technical solutions have the following drawbacks:

[0004] Existing general-purpose graph databases employ a flat, general-purpose graph data structure. Node and edge storage in memory / disk utilizes hash-based random allocation or time-series appending strategies, resulting in tightly coupled components in the physical world being discretely distributed in computer memory addresses. Multi-hop queries for fault diagnosis trigger numerous random memory accesses, frequently causing CPU L1 / L2 / L3 cache misses, TLB misses, and operating system page faults. In extreme conditions with multiple devices triggering concurrent alarms in industrial settings, query latency increases exponentially, failing to meet the real-time requirements of industrial scenarios.

[0005] When handling fault propagation queries across subsystems, the lack of an effective deterministic pruning mechanism leads to blind traversal, which can cause path combination explosion and further exacerbate system performance degradation.

[0006] In summary, existing technologies cannot simultaneously meet the requirements of real-time performance, determinism, and high reliability in fault diagnosis of industrial electromechanical equipment. Therefore, a knowledge graph-based fault diagnosis system and method for electromechanical equipment is proposed to address the aforementioned problems. Summary of the Invention

[0007] The purpose of this invention is to provide a knowledge graph-based fault diagnosis system and method for electromechanical equipment in order to solve the above-mentioned problems.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A knowledge graph-based fault diagnosis system for electromechanical equipment includes:

[0010] The graph deterministic partitioning module is configured to parse the BOM file, generate subsystem identifiers with physical hierarchical semantics for nodes through depth-first search and bitwise operations; perform bitwise XOR operations on the identifiers of connected nodes to mark cross-domain boundary nodes, and instantiate the nodes as 64-byte structures;

[0011] The memory contiguous allocation module is configured to request a large page memory pool, using the high-order prefix of the identifier as the key to divide the corresponding physical subsystem into contiguous physical blocks; write the 64-byte structure and edge data into the contiguous physical blocks in a localized compressed sparse row structure, and replace the virtual pointer with a relative integer offset.

[0012] The boundary edge pruning index module is configured to allocate Bloom filters to cross-domain boundary nodes and generate non-cryptographic hash functions using identifiers as seeds. After post-order traversal, the identifiers of downstream fault root cause nodes are calculated by the hash function and injected into the Bloom filters of the corresponding cross-domain boundary nodes.

[0013] The deterministic multi-hop query execution module is configured to map alarm signals as starting nodes and push them into an unlocked circular buffer, and sequentially traverse the continuous physical blocks. When encountering cross-domain boundary nodes, the target fault type is input into the hash function, the corresponding bit of the Bloom filter is read and a bitwise AND operation is performed. If the result is zero, the node is pruned; if the result is one, the node is traversed across the boundary, and the fault propagation chain is backtracked.

[0014] Preferably, when generating subsystem identifiers, the graph deterministic partitioning module is configured to push the root node of the multi-way tree structure onto the stack and assign an initial all-zero code;

[0015] When popping the top node from the stack in a loop, read the sibling node number of the node at the current level, perform a left shift operation according to the depth level of the node, and perform a bitwise OR operation between the result of the left shift and the subsystem identifier of the node's parent node to obtain the subsystem identifier of the node itself.

[0016] Preferably, the method further includes:

[0017] When identifying cross-domain boundary nodes, the configuration is as follows:

[0018] Read the subsystem identifiers of the start and end nodes of the directed edge, and perform a bitwise XOR operation on them to obtain the intermediate result;

[0019] Perform a bitwise AND operation between the intermediate result and the preset subsystem granularity mask. If the result of the bitwise AND is not equal to zero, it is determined that the starting node and the ending node belong to different physical components, and the starting node and the ending node are marked as cross-domain boundary nodes.

[0020] The structure is divided into contiguous physical blocks, which store the following in sequence: globally unique node identifier, subsystem identifier, cross-domain boundary flag, reserved fields, attribute memory offset, number of out-degree edges, number of in-degree edges, and an absolute memory address pointer to the adjacency list.

[0021] Preferably, the localized compressed sparse row data structure is divided into three linear arrays connected end to end within a continuous physical block: a vertex array, an edge array, and a variable-length attribute array; wherein, the vertex array is used to compactly store the structure, the edge array is used to store the edge structure containing the target node identifier and the edge type encoding, and the variable-length attribute array is used to store unstructured or variable-length attribute data.

[0022] Preferably, the two-pass scan relocation algorithm includes:

[0023] The first scan traverses all nodes and edges in the temporary memory, extracts the subsystem identifier, and performs atomic accumulation in the subsystem memory registry to calculate the absolute byte boundary required for each subsystem block.

[0024] The second scan copies the node structure, edge structure, and attribute strings to the corresponding contiguous physical addresses in the big page memory pool based on absolute byte boundaries, and performs pointer redirection operations to replace virtual pointers with relative integer offsets.

[0025] Preferably, the boundary edge pruning index module is configured as follows when generating a non-cryptographic hash function:

[0026] Perform a circular left shift operation on the subsystem identifier of the cross-domain boundary node, and then perform a bitwise XOR operation with a preset prime number to generate a seed for initializing the non-cryptographic hash function.

[0027] Preferably, the post-order traversal algorithm includes:

[0028] Traverse backwards from the leaf nodes of the graph along the directed edges, maintaining a dynamic set of current path faults during the backtracking process;

[0029] When the pointer in reverse traversal touches a cross-domain boundary node, it traverses each node identifier in the current path fault set, inputs a non-cryptographic hash function to calculate multiple index values, and forces the corresponding binary bits in the Bloom filter to one through bitwise shift and bitwise OR operations.

[0030] Preferably, the lock-free circular buffer consists of a continuous array of unsigned integers and maintains a head pointer and a tail pointer;

[0031] When performing an enqueue operation, the node identifier is written to the index position corresponding to the tail pointer, and the tail pointer is wrapped around using a bitwise AND operation; when performing a dequeue operation, the node identifier is read from the index position corresponding to the head pointer, and the head pointer is wrapped around using a bitwise AND operation.

[0032] Preferably, the deterministic multi-hop query execution module is configured as follows when performing sequential traversal:

[0033] Pop the current node from the unlocked circular buffer, obtain the base address of the continuous physical block where the node is located through the subsystem memory registry; continuously read the target node in the edge array using the hardware prefetch feature; if the cross-domain boundary flag of the target node is true, extract the memory offset of the target node to locate the Bloom filter, and perform a bitwise AND operation to perform deterministic branch prediction.

[0034] Knowledge graph-based fault diagnosis methods for electromechanical equipment include:

[0035] The structured BOM file of electromechanical equipment is parsed as a multi-way tree structure. Subsystem identifiers with physical hierarchical semantics are generated for nodes. Bitwise XOR operations are performed on the subsystem identifiers of connected nodes to mark cross-domain boundary nodes. The nodes are instantiated as fixed-length structures.

[0036] Request a large page memory pool from the operating system, divide the corresponding physical subsystem into continuous physical blocks using the high-order prefix of the subsystem identifier as the key, write the structure and edge data into the continuous physical blocks using a localized compressed sparse row data structure, replace the virtual pointer with a relative integer offset and lock the physical memory.

[0037] Bloom filters are assigned to cross-domain boundary nodes. Non-cryptographic hash functions are generated using subsystem identifiers as seeds. After post-order traversal, the identifiers of downstream potential root cause nodes are calculated using non-cryptographic hash functions and injected into the corresponding Bloom filters.

[0038] Abnormal alarm signals are mapped to starting nodes and pushed into an unlocked circular buffer. Sequential traversal is performed in continuous physical blocks. When a cross-domain boundary node is encountered, the target fault type is input into a non-cryptographic hash function. The corresponding bit of the Bloom filter is read and a bitwise AND operation is performed. If the result is zero, the branch is pruned. If the result is one, the boundary is crossed and traversed. Finally, the fault propagation chain is generated by backtracking.

[0039] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0040] 1. This invention uses a deterministic coding mechanism based on the physical bill of materials tree of equipment to map the physical hierarchical assembly relationship of electromechanical equipment into binary semantic identifiers of nodes. Based on this, it realizes continuous memory partitioning and linearized storage layout, completely transforms random memory access for fault diagnosis into sequential memory access, fully adapts to the prefetch characteristics of processor hardware, and reduces the probability of cache misses, page table cache failures and page faults.

[0041] 2. This invention utilizes a purely mathematical probabilistic data structure and a knowledge injection mechanism based on reverse postorder traversal to achieve extremely rapid and accurate pruning of cross-domain fault paths without reading data from downstream subsystems. This completely solves the path explosion problem in cross-subsystem queries, ensuring full traceability and controllable results throughout the diagnostic process. Simultaneously, through refined management technologies such as underlying large-page memory pre-allocation and memory locking, it eliminates the risks of memory fragmentation and data disk swapping, guaranteeing deterministic responses for long-term continuous system operation and meeting the high reliability and high security requirements of industrial scenarios. Attached Figure Description

[0042] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0043] Figure 1 This is a system structure diagram of the present invention;

[0044] Figure 2 This is a flowchart of the method of the present invention. Detailed Implementation

[0045] Several embodiments of this application will now be described in more detail with reference to the accompanying drawings to enable those skilled in the art to implement this application. This application may be embodied in many different forms and for various purposes and should not be limited to the embodiments set forth herein. These embodiments are provided to make this application thorough and complete, and to fully convey the scope of this application to those skilled in the art. The embodiments described do not limit this application.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] Example 1

[0048] Its specific implementation method is combined with the appendix Figure 1 and attached Figure 2 Please provide a detailed explanation.

[0049] Appendix Figure 1 The diagram below shows the structural block diagram of the electromechanical equipment fault diagnosis system based on knowledge graph provided in the embodiments of the present invention. It illustrates the connection relationship between the knowledge graph deterministic partitioning module and the deterministic multi-hop query execution module, and marks the main functional interaction flow of each module.

[0050] Appendix Figure 2 The flowchart of the knowledge graph-based fault diagnosis method for electromechanical equipment provided in this embodiment of the invention illustrates the complete steps from parsing the structured BOM file of the electromechanical equipment into a multi-branch tree structure to backtracking and generating the fault propagation chain.

[0051] In this embodiment, it includes:

[0052] Module 1: Graph Deterministic Partitioning Module

[0053] The core of this module lies in breaking away from the "flat, black-box" management model of general graph databases that treats all nodes equally, and forcibly introducing the "physical bill of materials tree-like hierarchical structure" of electromechanical equipment as the sole deterministic basis for the memory partitioning of graph nodes. Through a strict depth-first traversal algorithm and bitmask encoding rules, each graph node is marked with a binary imprint with physical topological significance.

[0054] Structured definition and parsing rules for input data:

[0055] The input data for this module is a structured Bill of Materials (BOM) file for electromechanical equipment. To ensure the feasibility of the solution, this invention explicitly stipulates that the BOM file must be parsed into a specific multi-branch tree data structure.

[0056] In this multi-branch tree structure, each node represents a physical level or specific component of the electromechanical equipment. The root node represents the entire equipment (e.g., the tunnel boring machine). The child nodes of the root node represent first-level subsystems (e.g., the cutterhead drive system, slurry circulation system, segment assembly system). The child nodes of the first-level subsystems represent second-level components (e.g., the main bearing, reducer, and variable frequency motor under the cutterhead drive system). Leaf nodes represent the bottom-level non-removable parts or sensors (e.g., temperature sensors, gear shafts, and seals).

[0057] In addition to hierarchical inclusion relationships, BOM files also contain "fault propagation relationships" between components (e.g., gear wear leads to abnormal vibration, and abnormal vibration leads to increased bearing temperature). These propagation relationships constitute the directed edges in the graph.

[0058] The system initializes a parser in memory, reads the aforementioned file, and instantiates it into a raw set of nodes and edges in memory. For subsequent bitwise operations, the system stipulates that the maximum subsystem level depth of the device must not exceed four levels, so as to perfectly compress the level information into a 64-bit unsigned integer.

[0059] Deterministic encoding algorithm for subsystem identifiers based on bitmasks:

[0060] This is the first core algorithm in this module. Its purpose is to generate a 64-bit unsigned integer for each node as its subsystem identifier (Subsystem_ID). This identifier is not only a unique number, but its binary bit distribution strictly maps the spatial topological location of the node in the physical electromechanical equipment.

[0061] The system defines the bit segmentation rules for 64-bit unsigned integers as follows:

[0062] The highest sixteen bits (bits 63 to 48) are used to store the code of the first-level subsystem;

[0063] The next sixteen bits (bits 47 to 32) are used to store the encoding of the secondary components;

[0064] The next sixteen bits (bits 31 to 16) are used to store the encoding of the three-level module;

[0065] The lowest sixteen bits (bits 15 through 0) are used to store the code for the fourth-level part.

[0066] The system initializes a stack data structure in main memory for performing a non-recursive depth-first search (DFS) traversal.

[0067] The first step is for the system to push the root node of the BOM tree onto the stack and assign it an initial 64-bit all-zero code (i.e., 0x0000000000000000 in hexadecimal representation).

[0068] The second step is that the system enters a loop that continues to execute as long as the stack is not empty.

[0069] Third, in each loop, the system pops a current node from the top of the stack. The system reads the index of the sibling node of that node at the current level (for example, if it is the third child of its parent node, then the index is 3).

[0070] Fourth, the system performs a deterministic left shift operation based on the depth level of the current node. If the current node is at the first-level subsystem level, the system converts the sequence number 3 into a 16-bit binary number and shifts it left by 48 bits; if it is at the second-level component level, it shifts it left by 32 bits; and so on.

[0071] Fifth, the system performs a bitwise OR operation between the left-shifted result and the Subsystem_ID of the current node's parent node. The result of this operation is the Subsystem_ID of the current node itself.

[0072] The sixth step is for the system to push all child nodes of the current node onto the stack, in preparation for the next round of the loop.

[0073] Through the pure bitwise operations and stack operations described above, when the loop ends, each node in the BOM tree is assigned a Subsystem_ID with strict physical hierarchy semantics. For example, a node belonging to "Gearbox (Level 2 code 0x0005)" under "Mechanical System (Level 1 code 0x0001)" and then to "Input Shaft (Level 3 code 0x0002)" will inevitably have a Subsystem_ID with a hexadecimal representation of 0x0001000500020000. This encoding method abandons random hashing, ensuring that nodes belonging to the same subsystem in physical structure will have identical high-order prefixes in their Subsystem_IDs. This provides an absolutely reliable mathematical basis for the contiguous memory allocation in Module 2.

[0074] Deterministic identification and labeling algorithm for cross-domain boundary nodes:

[0075] After completing the Subsystem_ID encoding for all nodes, the system needs to identify the "bridge nodes" in the graph that connect different physical subsystems. These nodes are the key hubs for fault propagation across systems and also the physical anchor points for subsequent Module 3 to deploy Bloom filters for query pruning.

[0076] The system iterates through the original set of edges obtained from previous parsing in memory. Each directed edge contains a start pointer and an end pointer.

[0077] The system executes the following strict decision-making logic:

[0078] The first step is for the system to read the Subsystem_ID (denoted as ID_Source) of the starting node and the Subsystem_ID (denoted as ID_Target) of the ending node of the current edge.

[0079] The second step is for the system to determine whether the two nodes belong to the same "core subsystem". To achieve extremely fast determination, the system does not use any string comparisons or complex logical judgments, but directly uses a bitwise XOR operation.

[0080] The third step is for the system to perform a bitwise XOR operation on ID_Source and ID_Target to obtain a 64-bit intermediate result (denoted as Result_XOR).

[0081] The fourth step is to define a "subsystem granularity mask". Assuming the system administrator sets the minimum physical boundary of the memory partition to "secondary components", then the high 32 bits of the mask are all 1s and the low 32 bits are all 0s (i.e., 0xFFFFFFFF00000000 in hexadecimal).

[0082] Fifth, the system performs a bitwise AND operation between Result_XOR and the granularity mask of the above subsystem.

[0083] The sixth step is for the system to determine whether the result of the bitwise AND operation is equal to zero.

[0084] If the result is zero, it means that ID_Source and ID_Target are completely identical in the high 32 bits (i.e., the first-level and second-level subsystem codes), and they belong to nodes within the same physical component. In this case, the system does not perform any special processing on these two nodes and continues to traverse the next edge.

[0085] If the result is not zero, it means that the two nodes belong to different physical components (e.g., the starting point is the output shaft of the mechanical system, and the ending point is the generator rotor of the electrical system). In this case, this edge represents a fault propagation path across subsystems. The system immediately forces the starting and ending nodes of the edge to set a Boolean flag named "Is_Boundary" in the memory structure to True.

[0086] Through this extremely low-level bitwise operation mechanism, the system can complete the boundary scan of a massive electromechanical knowledge graph containing millions of edges within milliseconds. All nodes marked with Is_Boundary=True will be extracted and stored in a dedicated boundary node index array.

[0087] Byte alignment and persistence of node internal data structures:

[0088] To ensure that subsequent modules can utilize the CPU's hardware cache prefetching capabilities, this module must perform rigorous C / C++ language-level byte alignment design on the internal data structure of each entity in the graph after completing the above logical partitioning.

[0089] The system stipulates that each graph node must be instantiated in memory as a fixed-length 64-byte structure. The reason for choosing 64 bytes is that this is precisely the standard size of the L1 cache line for modern mainstream x86 and ARM CPUs. This extremely stringent size constraint is the core feature that distinguishes this invention from all graph databases built using high-level languages ​​such as Java / Python.

[0090] The internal memory layout of this 64-byte structure is strictly divided into the following contiguous physical blocks:

[0091] Bytes 0 to 7 (8 bytes in total): Stores a 64-bit globally unique node identifier (Node_ID).

[0092] Bytes 8 to 15 (8 bytes in total): Stores the 64-bit subsystem identifier (Subsystem_ID) calculated by this module.

[0093] Byte 16 (1 byte total): Stores the cross-domain boundary flag (Is_Boundary) calculated by this module, occupying one byte, with a value of 0x00 or 0x01.

[0094] Bytes 17 to 19 (3 ​​bytes in total): Padding, a reserved field used to meet the four-byte alignment requirement of memory addresses and prevent performance penalties during CPU reads.

[0095] Bytes 20 to 23 (4 bytes in total): Stores the memory offset (PropertyOffset) of the node's own attribute data. Since the length of text attributes such as node names (e.g., "main bearing inner ring") is variable, the system does not store them directly in these 64 bytes, but in a separate string constant area. Here, only a 32-bit unsigned integer is reserved as the offset pointer.

[0096] Bytes 24 to 27 (4 bytes in total): Store the number of out-degree edges (Out-degreeCount) that originate from this node.

[0097] Bytes 28 to 31 (4 bytes in total): Store the number of in-degree edges that this node is the endpoint of (In-degreeCount).

[0098] Bytes 32 to 63 (32 bytes in total): Store a 64-bit absolute memory address pointer to the node's adjacency list, and spinlock status bits for concurrency control.

[0099] At this point, Module 1 has completed the transformation of the disorganized BOM text data of electromechanical equipment into a standardized set of nodes with strict physical topological semantics, bitwise encoding, and perfect compatibility with the underlying CPU hardware characteristics. These nodes are currently temporarily stored in the system's temporary memory heap, awaiting Module 2 to move them and lock them into contiguous physical memory blocks.

[0100] Module 2: Memory Contiguous Allocation Module

[0101] In traditional graph databases, the storage of graph entities relies on the garbage collection (GC) mechanism of high-level languages ​​(such as Java) and the standard memory allocator of the operating system (such as malloc). This mechanism leads to a fatal consequence: logically connected electromechanical components (such as input shafts, intermediate shafts, and output shafts within the same gearbox) have completely random and highly fragmented storage addresses in physical memory (RAM). When diagnostic algorithms traverse the graph between these nodes, the CPU's memory controller must frequently traverse different memory pages, causing massive TLB (Translation Lookaside Buffer) misses and L1 / L2 / L3 cache failures, resulting in diagnostic latency increasing dramatically from microseconds to seconds.

[0102] To address this hardware-level performance bottleneck, this module completely takes over the operating system's underlying memory allocation permissions and proposes an "improved compressed sparse row (CSR) contiguous memory layout and locking algorithm for electromechanical subsystems".

[0103] Deterministic pre-allocation mechanism of operating system-level huge page memory pool:

[0104] During the startup initialization phase, this system does not use the standard 4KB memory pages. Instead, it directly initiates a system call to the host operating system (such as the Linux kernel) to request the allocation of two megabytes (2MB) or one gigabyte (1GB) of physical big page memory.

[0105] The first step is for the system to read the total number of temporary node sets and edge sets generated in Module 1, and then calculate the total absolute physical memory capacity required for the graph using a deterministic mathematical formula. The formula is: Total capacity = (Total number of nodes × 64 bytes) + (Total number of edges × 16 bytes) + (Total length of attribute strings) + Reserved buffer.

[0106] The second step involves the system calling the underlying memory mapping function (such as the `mmap` function in the POSIX standard, and forcibly attaching the `MAP_HUGETLB` and `MAP_ANONYMOUS` flags) to request a completely contiguous virtual memory address space from the operating system kernel that cannot be swapped to disk.

[0107] The third step involves the system instantiating a globally addressable directory named "SubsystemMemoryRegistry" in main memory. This directory is essentially a highly optimized radix tree or prefix hash table. The system extracts the high 32 bits of the Subsystem_ID of all nodes in Module 1 (i.e., the encoding of the primary and secondary physical components) as the key for this registry.

[0108] The fourth step involves the system dividing the allocated large page memory pool into several "contiguous physical chunks" of varying sizes. Each chunk strictly corresponds to a specific high 32-bit Subsystem_ID prefix. For example, all nodes and edges belonging to "0x00010005" (representing the mechanical system - gearbox) will be forcibly confined to the same contiguous physical chunk.

[0109] By pre-allocating large pages of memory as described above, the system eliminates the TLB miss penalty caused by cross-page access during graph lookup at the physical hardware level, laying the hardware foundation for subsequent high-speed graph traversal.

[0110] Improved Compacted Sparse Line (CSR) Physical Layout for Subsystems:

[0111] After allocating dedicated contiguous memory blocks for each electromechanical subsystem, the system needs to relocate the node data residing in the temporary heap memory of Module 1 to these blocks according to a specific physical layout. This invention abandons the "node-edge doubly linked list" structure used in traditional graph databases and designs a "Localized Compressed Sparse Row (LocalizedCSR)" data structure.

[0112] Within each subsystem's contiguous physical block, memory addresses are strictly divided into three linear arrays connected end-to-end:

[0113] The first linear array is the "VertexArray (VA)":

[0114] This array is specifically designed for the 64-byte node structure defined in Compact Storage Module 1. The system sequentially writes all nodes belonging to the subsystem into the vertex array according to the lexicographical order of the lower 32 bits of the Subsystem_ID (i.e., the level 3 and level 4 part codes). Since each node strictly occupies 64 bytes, the system can directly locate the memory starting address of any component in O(1) time complexity using an extremely simple base address plus offset formula (physical address = VA base address + node local index × 64), completely eliminating the overhead of pointer dereferencing.

[0115] The second linear array is the "EdgeArray (EA)":

[0116] In electromechanical fault diagnosis, edges represent the propagation path of a fault (e.g., "caused by" or "belongs to"). The edge array follows the vertex array. Each edge is fixed as a 16-byte structure. The first eight bytes store the globally unique identifier (Node_ID) of the target node; the next four bytes store the edge type code (e.g., 0x01 represents mechanical wear propagation, 0x02 represents electrical short circuit propagation); and the last four bytes store the edge weight or probability of occurrence (represented as a single-precision floating-point number according to the IEEE 754 standard).

[0117] To associate vertices with edges, the system utilizes the "Out-degreeCount" field reserved in the node structure of module one. When writing to the vertex array, the system additionally maintains a hidden "EdgeOffset" accumulator. Assume node A has 3 outgoing edges and node B has 2. Node A's starting offset in the edge array is 0, while node B's starting offset is 3. When querying the fault propagation path of node B, the system only needs to jump directly to the 3rd index position of the edge array and read two consecutive 16-byte edge structures. This design completely transforms graph traversal into a pure sequential array reading.

[0118] The third linear array is a "variable-length array of attributes":

[0119] The nodes of electromechanical equipment contain a large amount of unstructured or variable-length attribute data (such as sensor model, manufacturing date, and long text maintenance records). To avoid disrupting the strict 64-byte alignment of the vertex array, the system appends this variable-length data to the end of the block, i.e., to the variable-length attribute array. The "PropertyOffset" field in the vertex structure directly points to the specific byte position within this array. Strings are separated by double null characters (\0\0) as absolute delimiters.

[0120] Deterministic data migration and memory locking:

[0121] In order to perfectly transform the data from the temporary state to the aforementioned localized CSR layout, the system executes a strict "Two-PassScan" migration algorithm.

[0122] First scan (capacity pre-calculation stage):

[0123] The system traverses all nodes and edges in temporary memory. For each node, the system extracts its Subsystem_ID and finds the corresponding subsystem entry in the "Subsystem Memory Registry". The system performs precise atomic accumulation on the total number of nodes, outgoing edges, and attribute strings within the subsystem. After the first scan, the system accurately determines the absolute byte boundaries of the vertex array, edge array, and attribute array required for each subsystem block.

[0124] Second scan (physical write and pointer redirection phase):

[0125] The system iterates through the temporary data again. This time, based on the absolute boundaries calculated in the first scan, the system copies the node structure, edge structure, and attribute strings byte by byte (e.g., using the underlying `memcpy` instruction) to the corresponding contiguous physical addresses in the large page memory pool.

[0126] During the copying process, the system performs the crucial "pointer swizzling" operation. Originally, in temporary memory, the relationships between nodes depended on virtual memory pointers; after writing contiguous blocks, the system replaces all these virtual pointers with "relative integer offsets" based on the base addresses of the vertex and edge arrays. This relative offset design makes the entire graph memory block "position-independent," allowing it to be directly serialized to disk or transmitted over a network to another diagnostic server, and then executed directly without any deserialization or parsing after loading.

[0127] Memory lock command issued:

[0128] After all the data migration is complete, in order to prevent the operating system from swapping out these carefully laid-out map data to the slow mechanical hard drive or solid-state drive when system memory is low, the system must call the operating system's memory locking system call (such as the `mlock` or `mlockall` function in Linux).

[0129] The system passes the starting address and total length of the large page memory pool containing the entire electromechanical knowledge graph to the `mlock` function. Upon receiving this instruction, the operating system kernel forcibly marks the page table entries of these memory pages as "resident in RAM". This step is the last line of defense ensuring that the industrial-grade electromechanical fault diagnosis system maintains deterministic microsecond-level response latency under any extreme concurrent alarm conditions.

[0130] Deep collaboration mechanism for CPU hardware cache prefetching:

[0131] The reason why this module can achieve an exponential leap in diagnostic performance without using any machine learning model is that its data structure design perfectly matches the microarchitecture characteristics of modern CPUs.

[0132] In the actual operation of electromechanical equipment, the propagation of faults exhibits a strong "spatial locality." For example, when a main bearing breaks, the resulting high temperature and severe vibration will inevitably propagate rapidly along the physical assembly relationship to the tightly connected gearbox input shaft, planetary carrier, and lubrication system.

[0133] Because this module has already assigned similar Subsystem_IDs to these physically closely connected components using the BOM tree and forced them to be written sequentially into the same contiguous "Vertex Array (VA)", when the diagnostic system's query thread locates the "main bearing" node and prepares to query its downstream affected components along the edge array, a miracle occurs inside the CPU's silicon:

[0134] When the CPU's Arithmetic Logic Unit (ALU) issues an instruction to the memory controller to read the "main bearing" node (occupying 64 bytes), the memory controller not only retrieves these 64 bytes, but the modern CPU's built-in Spatial Hardware Prefetcher also detects that the program is performing consecutive memory address accesses. The prefetcher automatically triggers additional memory read transactions in the background, pre-moving the memory data of nodes such as the "input axis" and "planetary carrier" that follow the "main bearing" node from the slow main memory (with a latency of about 100 nanoseconds) to the CPU chip's high-speed L1 data cache (with a latency of about 1 nanosecond) and L2 cache.

[0135] When the diagnostic algorithm's loop enters the next iteration and prepares to process the "input axis" node, the data for that node is already quietly lying in the L1 cache, waiting to be read. This interdisciplinary collaborative design, which transforms the "physical assembly continuity of electromechanical equipment" into the "continuity of computer memory addresses" and thus triggers the "CPU's underlying hardware prefetching mechanism," eliminates the memory access pauses that traditional graph databases inevitably experience during multi-hop queries.

[0136] At this point, Module Two has completed the reconstruction of the underlying physical storage architecture of the knowledge graph. The entire electromechanical knowledge graph has been transformed into a series of highly compressed, perfectly aligned, and tightly locked byte streams in physical memory by the operating system.

[0137] However, despite achieving extremely fast traversal within the subsystem, blindly traversing across blocks can still lead to path explosion when faults propagate across subsystems (e.g., mechanical vibration causing short circuits in electrical sensors). Therefore, the system needs to introduce a low-overhead cross-domain interception mechanism.

[0138] Module 3: Boundary Edge Pruning Index Module

[0139] The core of this module lies in hard-coding a purely mathematical probabilistic data structure, the Bloom filter, into specific physical hubs marked as "cross-domain boundary nodes" in Module 1. Through "post-order traversal knowledge injection" during the graph construction phase, each boundary node can "memorize" in advance all possible root causes of failures downstream with extremely low memory overhead.

[0140] Mathematical definition of boundary node Bloom filters and memory-aligned allocation:

[0141] After completing the contiguous memory allocation for Module 2, the system allocates a separate, strictly aligned contiguous memory region in main memory, named the "Boundary Index Region".

[0142] The first step is to count the total number of nodes in the entire graph whose Is_Boundary flag is True (denoted as N_boundary).

[0143] The second step involves the system assigning a fixed-length Bloom filter to each boundary node. To ensure an extremely low false positive rate (FPR) and avoid wasting memory, the system uses deterministic mathematical formulas to calculate the length m of the bit array and the number k of hash functions.

[0144] The system sets a target false positive rate of P = 0.01 (i.e., one percent). It is assumed that an average of n = 1000 potential root cause nodes are located downstream of a boundary node.

[0145] According to the formula The system calculates the required bit array length. It is approximately 9585 bits. To meet the byte alignment requirements of the computer's underlying system, it is rounded up to 1024 bytes (i.e., 8192 bits, occupying 16 consecutive 64-byte cache lines).

[0146] According to the formula The system calculates the optimal number of hash functions, k=6.

[0147] Third, the system allocates a 1024-byte pure zero memory block for each boundary node in the "boundary index area". At the same time, in the vertex array (VA) of module two, the reserved field (Padding) inside the boundary node structure is rewritten as a 32-bit unsigned integer, which serves as the memory offset pointing to the starting address of its dedicated Bloom filter in the "boundary index area".

[0148] Selection and bitwise operation rules for deterministic non-cryptographic hash functions:

[0149] To ensure optimal performance during queries, this system absolutely does not use computationally intensive cryptographic hash functions such as MD5 or SHA-256. Instead, it hardcodes six independent non-cryptographic hash functions based on variants of the MurmurHash3 algorithm.

[0150] The input to these six hash functions is the 64-bit Node_ID of the target faulty node, but they use different deterministic seeds.

[0151] The system cleverly utilizes the 64-bit Subsystem_ID of the boundary node itself as the base seed.

[0152] For the i-th hash function (i ranges from 1 to 6), the initial seed Seed_i is calculated as follows: Circularly left-shift Subsystem_ID by i×7 bits, and then perform a bitwise XOR operation with a preset 64-bit prime number (e.g., 0x9E3779B97F4A7C15).

[0153] After calculating six 64-bit hash values, the system performs a bitwise AND operation on each hash value with the length mask of the bit array (i.e., 8191, which is 00011111111111111), thereby obtaining six deterministic array index values ​​(Index_1 to Index_6) in the range of 0 to 8191.

[0154] Post-order traversal injection algorithm for fault propagation knowledge:

[0155] During the graph initialization phase, all Bloom filters are initialized to zero, and the system must "inject" downstream fault knowledge into these filters. The system employs a pure algorithmic post-order traversal mechanism.

[0156] The first step is for the system to identify all the "leaf nodes" in the graph (i.e., nodes with an out-degree of zero, which usually represent the specific cause of the fault at the lowest level, such as "excessive lubricating oil particle size").

[0157] The second step is for the system to start from these leaf nodes and perform a reverse traversal along the directed edges (i.e., backtracking upstream along the "caused" relationship).

[0158] Third, during the backtracking process, the system maintains a dynamic "CurrentFaultSet". Each time a normal node is traversed, its Node_ID is added to this set.

[0159] Fourth, when the pointer during reverse traversal touches a "cross-domain boundary node", the system pauses backtracking. The system traverses each Node_ID in the "current path failure set", inputs it into six defined hash functions, and calculates six index values.

[0160] Fifth, based on these six index values, the system directly locates the 1024-byte Bloom filter memory block dedicated to that boundary node. The system uses bitshift and bitwise OR operations to force the binary bits corresponding to these six indices to be 1.

[0161] The specific bit manipulation instruction is: `Filter_Memory[Index / 8]|=(1<<(Index%8))`.

[0162] The sixth step is to clear the "current path fault set" and continue backtracking upstream until the entire electromechanical knowledge graph has been traversed.

[0163] Through this ingenious pure algorithm injection process, each boundary node becomes an "intelligent" physical checkpoint. Although it doesn't know which nodes are downstream (because Bloom filters are irreversible), it can instantly determine with over 99% accuracy whether a specific fault phenomenon might be caused by its downstream subsystem.

[0164] Module 4: Deterministic Multi-Hop Query Execution Module

[0165] This module is the final execution engine of the entire diagnostic system. When a sensor or SCADA system in the industrial field reports an abnormal alarm (e.g., "wind turbine main shaft vibration exceeds limits"), this module will utilize the underlying hardware-level data structure built by the first three modules to perform a high-speed multi-hop graph traversal based on memory pointers and bitwise operations.

[0166] Initialization of a lock-free circular buffer:

[0167] To avoid frequent calls to the operating system's `malloc` and `free` functions to allocate memory during the query process (which can cause serious thread blocking and memory fragmentation), the system pre-allocates a fixed-size lock-free ring buffer for each concurrent query thread at startup, replacing the dynamic queue in the traditional breadth-first search (BFS) algorithm.

[0168] The circular buffer consists of a contiguous array of 64-bit unsigned integers of length 65536, specifically used to store the Node_ID of the nodes to be traversed. The system maintains two 32-bit integer pointers: a head pointer and a tail pointer, both initialized to 0.

[0169] Enqueue operation: Write the Node_ID to the Tail index position of the array, and then execute `Tail=(Tail+1)&65535` (using bitwise AND operation to replace the slow modulo operation to achieve extremely fast pointer wrapping).

[0170] Dequeue operation: Read the Node_ID from the Head index position of the array, and then execute `Head=(Head+1)&65535`.

[0171] When Head equals Tail, the queue is empty, and the query ends. This queue design, which uses pure array bitwise operations, compresses the overhead of a single node scheduling operation to within a few CPU clock cycles.

[0172] Ultra-fast execution of diagnostic queries and hardware-level pruning logic:

[0173] When a "spindle vibration exceeds limits" alarm signal is received, the system first maps the text alarm to a starting node Node_ID (denoted as ID_Start) in the graph using a deterministic hash dictionary, and pushes it into a circular buffer. At the same time, the system receives the "target fault type" input by the user (for example, if the user wants to check whether the fault is related to the "gearbox", the system converts it into the Subsystem_ID prefix of the target subsystem, denoted as Target_Prefix).

[0174] The system enters a high-speed `while(Head!=Tail)` loop, executing the following strict underlying logic:

[0175] Step A (Node Dequeueing and Memory Location):

[0176] The system pops a current node Node_ID from the circular buffer. The system obtains the base address of the contiguous physical block where the node is located in O(1) time through the "subsystem memory registry" established in Module 2, and directly reads the 64-byte structure of the node into the CPU register through the offset.

[0177] Step B (High-speed sequential traversal within the subsystem):

[0178] The system reads the "number of out-degree edges" and "edge offset" from the node structure. The system then jumps directly to the "edge array (EA)" of the block and uses the CPU's hardware prefetch feature to continuously read all target node Node_IDs.

[0179] Step C (Boundary interception and Bloom filter bitwise operation pruning):

[0180] For each target node read, the system first checks the 16th byte (Is_Boundary flag) in its structure.

[0181] If Is_Boundary is 0 (False), it means that the node is still inside the current physical subsystem, and the system directly pushes it into the circular buffer to continue the next round of the loop.

[0182] If Is_Boundary is 1 (True), it means that the physical subsystem boundary is about to be crossed! At this time, the system triggers the core pruning logic of this invention:

[0183] The system extracts the FilterOffset of the boundary node and directly locates the memory starting address of the Bloom filter in the "boundary index area".

[0184] The system takes the Target_Prefix (target fault type) queried by the user as input, runs the six defined MurmurHash3 variant functions, and obtains six index values.

[0185] The system sequentially reads the binary bits corresponding to these six indices from the Bloom filter. The system performs a strict bitwise AND operation: `Result=Bit_1&Bit_2&Bit_3&Bit_4&Bit_5&Bit_6`.

[0186] Deterministic branch prediction:

[0187] If `Result==0`, it means the target fault absolutely cannot exist in a subsystem downstream of this boundary node. The system directly discards the target node without pushing it into the circular buffer. This means that the system instantly prunes a huge fault branch tree that could contain tens of thousands of nodes without reading a single byte of memory from the downstream subsystem!

[0188] If `Result==1`, it indicates that the target fault is highly likely to exist downstream. The system pushes the target node into a circular buffer, allowing the query pointer to cross memory blocks and enter the next subsystem for in-depth investigation.

[0189] Step D (Path Backtracking and Diagnostic Report Generation):

[0190] During the traversal, the system uses a pre-allocated contiguous memory array to record the "parent node pointer (ParentPointer)" of each node. The loop terminates when the query hits the target fault node or when the circular buffer is empty. Starting from the hit target node, the system traces back along the parent node pointer to the starting node ID_Start, and concatenates the names of the nodes along the way (obtained by reading the variable-length attribute array PA in Module 2) into a complete fault propagation chain string (e.g., "spindle vibration exceeds limits -> main bearing inner ring peels off -> lubricating oil film ruptures -> lubrication pump motor phase loss").

[0191] Ultimately, the system outputs the plain text string to the front-end visualization interface, or directly converts it into control commands and sends them to the PLC (Programmable Logic Controller) of the electromechanical equipment to execute an emergency shutdown.

[0192] Example 2

[0193] Please see Figure 2 The knowledge graph-based fault diagnosis method for electromechanical equipment includes the following parts:

[0194] The structured BOM file of electromechanical equipment is parsed as a multi-branch tree structure. Subsystem identifiers with physical hierarchical semantics are generated for nodes through depth-first search and bitwise operations. Bitwise XOR operations are performed on the subsystem identifiers of connected nodes to mark cross-domain boundary nodes. The nodes are instantiated into fixed-length structures.

[0195] Request a large page memory pool from the operating system, divide the corresponding physical subsystem into continuous physical blocks using the high-order prefix of the subsystem identifier as the key, write the structure and edge data into the continuous physical blocks using a localized compressed sparse row data structure, replace the virtual pointer with a relative integer offset and lock the physical memory.

[0196] Bloom filters are assigned to cross-domain boundary nodes. Non-cryptographic hash functions are generated using subsystem identifiers as seeds. After post-order traversal, the identifiers of downstream potential root cause nodes are calculated using non-cryptographic hash functions and injected into the corresponding Bloom filters.

[0197] Abnormal alarm signals are mapped to starting nodes and pushed into an unlocked circular buffer. Sequential traversal is performed in continuous physical blocks. When a cross-domain boundary node is encountered, the target fault type is input into a non-cryptographic hash function. The corresponding bit of the Bloom filter is read and a bitwise AND operation is performed. If the result is zero, the branch is pruned. If the result is one, the boundary is crossed and traversed. Finally, the fault propagation chain is generated by backtracking.

[0198] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

[0199] It should be noted that, in this document, the use of relational terms such as "first" and "second" is merely for distinguishing one entity or operation from another, and does not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0200] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0201] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0202] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0203] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0204] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0205] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0206] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A knowledge graph-based fault diagnosis system for electromechanical equipment, characterized in that, include: The graph deterministic partitioning module is configured to parse the BOM file and generate subsystem identifiers with physical hierarchical semantics for nodes through depth-first search and bit operations. Perform a bitwise XOR operation on the identifiers of connected nodes to mark cross-domain boundary nodes, and instantiate the nodes as 64-byte structures; The memory contiguous allocation module is configured to request a large page memory pool, using the high-order prefix of the identifier as the key to divide the corresponding physical subsystem into contiguous physical blocks; write the 64-byte structure and edge data into the contiguous physical blocks in a localized compressed sparse row structure, and replace the virtual pointer with a relative integer offset. The boundary edge pruning index module is configured to allocate Bloom filters to cross-domain boundary nodes and generate non-cryptographic hash functions using identifiers as seeds. After post-order traversal, the identifiers of downstream fault root cause nodes are calculated by the hash function and injected into the Bloom filters of the corresponding cross-domain boundary nodes. The deterministic multi-hop query execution module is configured to map alarm signals as starting nodes and push them into an unlocked circular buffer, and sequentially traverse the continuous physical blocks. When encountering cross-domain boundary nodes, the target fault type is input into the hash function, the corresponding bit of the Bloom filter is read and a bitwise AND operation is performed. If the result is zero, the node is pruned; if the result is one, the node is traversed across the boundary, and the fault propagation chain is backtracked.

2. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 1, characterized in that, When generating subsystem identifiers, the graph deterministic partitioning module is configured to push the root node of the multi-way tree structure onto the stack and assign an initial all-zero code. When popping the top node from the stack in a loop, read the sibling node number of the node at the current level, perform a left shift operation according to the depth level of the node, and perform a bitwise OR operation between the result of the left shift and the subsystem identifier of the node's parent node to obtain the subsystem identifier of the node itself.

3. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 2, characterized in that, Also includes: When identifying cross-domain boundary nodes, the configuration is as follows: Read the subsystem identifiers of the start and end nodes of the directed edge, and perform a bitwise XOR operation on them to obtain the intermediate result; Perform a bitwise AND operation between the intermediate result and the preset subsystem granularity mask. If the result of the bitwise AND is not equal to zero, it is determined that the starting node and the ending node belong to different physical components, and the starting node and the ending node are marked as cross-domain boundary nodes. The structure is divided into contiguous physical blocks, which store the following in sequence: globally unique node identifier, subsystem identifier, cross-domain boundary flag, reserved fields, attribute memory offset, number of out-degree edges, number of in-degree edges, and an absolute memory address pointer to the adjacency list.

4. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 1, characterized in that, The localized compressed sparse row data structure is divided into three linear arrays connected end to end within a continuous physical block: vertex array, edge array, and variable-length attribute array. The vertex array is used to compactly store the structure, the edge array is used to store the edge structure containing the target node identifier and the edge type encoding, and the variable-length attribute array is used to store unstructured or variable-length attribute data.

5. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 4, characterized in that, The two-pass relocation algorithm includes: The first scan traverses all nodes and edges in the temporary memory, extracts the subsystem identifier, and performs atomic accumulation in the subsystem memory registry to calculate the absolute byte boundary required for each subsystem block. The second scan copies the node structure, edge structure, and attribute strings to the corresponding contiguous physical addresses in the big page memory pool based on absolute byte boundaries, and performs pointer redirection operations to replace virtual pointers with relative integer offsets.

6. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 1, characterized in that, The boundary edge pruning index module is configured as follows when generating non-cryptographic hash functions: Perform a circular left shift operation on the subsystem identifier of the cross-domain boundary node, and then perform a bitwise XOR operation with a preset prime number to generate a seed for initializing the non-cryptographic hash function.

7. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 6, characterized in that, Postorder traversal algorithms include: Traverse backwards from the leaf nodes of the graph along the directed edges, maintaining a dynamic set of current path faults during the backtracking process; When the pointer in reverse traversal touches a cross-domain boundary node, it traverses each node identifier in the current path fault set, inputs a non-cryptographic hash function to calculate multiple index values, and forces the corresponding binary bits in the Bloom filter to one through bitwise shift and bitwise OR operations.

8. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 1, characterized in that, An unlocked circular buffer consists of a contiguous array of unsigned integers and maintains a head pointer and a tail pointer. When performing the enqueue operation, the node identifier is written to the index position corresponding to the tail pointer, and the tail pointer is wrapped around using a bitwise AND operation. When performing a dequeue operation, the node identifier is read from the index position corresponding to the head pointer, and the head pointer is wrapped around using a bitwise AND operation.

9. The knowledge graph-based electromechanical equipment fault diagnosis system according to claim 1, characterized in that, The deterministic multi-hop query execution module is configured as follows when performing sequential traversal: Pop the current node from the unlocked circular buffer, obtain the base address of the continuous physical block where the node is located through the subsystem memory registry; continuously read the target node in the edge array using the hardware prefetch feature; if the cross-domain boundary flag of the target node is true, extract the memory offset of the target node to locate the Bloom filter, and perform a bitwise AND operation to perform deterministic branch prediction.

10. A knowledge graph-based method for diagnosing electromechanical equipment faults, and a knowledge graph-based electromechanical equipment fault diagnosis system according to any one of claims 1-9, characterized in that, include: The structured BOM file of electromechanical equipment is parsed as a multi-way tree structure. Subsystem identifiers with physical hierarchical semantics are generated for nodes. Bitwise XOR operations are performed on the subsystem identifiers of connected nodes to mark cross-domain boundary nodes. The nodes are instantiated as fixed-length structures. Request a large page memory pool from the operating system, divide the corresponding physical subsystem into continuous physical blocks using the high-order prefix of the subsystem identifier as the key, write the structure and edge data into the continuous physical blocks using a localized compressed sparse row data structure, replace the virtual pointer with a relative integer offset and lock the physical memory. Bloom filters are assigned to cross-domain boundary nodes. Non-cryptographic hash functions are generated using subsystem identifiers as seeds. After post-order traversal, the identifiers of downstream potential root cause nodes are calculated using non-cryptographic hash functions and injected into the corresponding Bloom filters. Abnormal alarm signals are mapped to starting nodes and pushed into an unlocked circular buffer. Sequential traversal is performed in continuous physical blocks. When a cross-domain boundary node is encountered, the target fault type is input into a non-cryptographic hash function. The corresponding bit of the Bloom filter is read and a bitwise AND operation is performed. If the result is zero, the branch is pruned. If the result is one, the boundary is crossed and traversed. Finally, the fault propagation chain is generated by backtracking.

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