Timing constraint checking method and apparatus, and electronic device

Abstract

The application discloses a timing constraint checking method and device and electronic equipment, and belongs to the technical field of computer data. The method comprises the following steps: acquiring structural information used for representing a connection relationship of a digital circuit and constraint information used for representing a timing constraint rule; acquiring at least one unconstrained path from the structural information based on the constraint information; performing feature extraction on the unconstrained path to obtain path feature information; and obtaining timing anomaly information corresponding to the path feature information based on the path feature information. According to the application, the unconstrained path is automatically identified based on the structural information and the constraint information, and the feature extraction is further performed on the unconstrained path to obtain the timing anomaly information, so that a complete automatic link from original data (i.e. the structural information) to a diagnosis result (i.e. the timing anomaly information) is formed. The operation is simple, the timing anomaly information of the unconstrained path is quickly obtained, and the repair rate for the unconstrained path in the subsequent process is improved.

Description

Technical Field

[0001] This application relates to the field of computer data processing technology, specifically to timing constraint checking methods, apparatus, and electronic equipment. Background Technology

[0002] In digital circuit design, static timing analysis (STA) is a crucial method for verifying whether the chip's timing meets requirements. Currently, in related technologies, after the digital circuit design is completed, the entry-level netlist and timing constraint file are read, and static timing analysis tools are called to traverse all timing paths in the digital circuit, thereby filtering out paths not covered by constraints and forming a list of unconstrained paths.

[0003] However, in the aforementioned technologies, only unconstrained paths are screened out. Subsequently, manual detection and analysis of the unconstrained paths are required to determine the cause of the anomalies. The process of obtaining the cause of the anomalies is cumbersome, which leads to the excessive time required to repair the unconstrained paths. Summary of the Invention

[0004] In view of this, this application provides a timing constraint checking method, apparatus and electronic device to solve the problem of cumbersome operation in checking the abnormal causes of unconstrained paths.

[0005] Firstly, this application provides a timing constraint checking method, the method comprising: Obtain structural information to characterize the connection relationships of digital circuits, and constraint information to characterize timing constraint rules; wherein, the digital circuits include multiple timing paths; Based on the constraint information, at least one unconstrained path is obtained from the structure information; wherein, the unconstrained path refers to a path not covered by temporal constraints; Feature extraction is performed on the unconstrained path to obtain path feature information; Based on the path feature information, the time-series anomaly information corresponding to the path feature information is obtained.

[0006] Secondly, this application provides a timing constraint checking device, the device comprising: The information acquisition module is used to acquire structural information characterizing the connection relationship of digital circuits, and constraint information characterizing timing constraint rules; wherein, the digital circuit includes multiple timing paths; The path acquisition module is used to acquire at least one unconstrained path from the structure information based on the constraint information; wherein, the unconstrained path refers to a path not covered by temporal constraints; The feature extraction module is used to extract features from the unconstrained path to obtain path feature information; The anomaly acquisition module is used to obtain the timing anomaly information corresponding to the path feature information based on the path feature information.

[0007] Thirdly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the timing constraint checking method of the first aspect or any corresponding embodiment described above.

[0008] Fourthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the timing constraint checking method of the first aspect or any corresponding embodiment described above.

[0009] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the timing constraint checking method of the first aspect or any corresponding embodiment described above.

[0010] The timing constraint checking method provided in this application automatically identifies unconstrained paths through structural and constraint information, and further extracts features from the unconstrained paths to obtain timing anomaly information, forming a complete automated link from raw data (i.e., structural information) to diagnostic results (i.e., timing anomaly information). It is easy to operate, and the rapid acquisition of timing anomaly information of unconstrained paths is beneficial to improving the subsequent repair rate of unconstrained paths. Attached Figure Description To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a timing constraint checking method according to an embodiment of this application; Figure 2 An exemplary schematic diagram illustrates a method for obtaining timing anomaly information; Figure 3 This is another flowchart illustrating the timing constraint checking method according to an embodiment of this application; Figure 4 This is another flowchart illustrating the timing constraint checking method according to an embodiment of this application; Figure 5 This is a structural block diagram of a timing constraint checking device according to an embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] It should be noted that the information (including but not limited to user input information, such as information entered by the user into input boxes), data (including but not limited to data used for analysis, stored data, and displayed data, such as context code, all code of the current project, the service pressure corresponding to operations performed on all code of the current project, and the code development status of the current project), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with relevant laws, regulations, and standards. For example, the context code, operations performed on all code of the current project, the corresponding service pressure, and the code development status involved in this application were all obtained with full authorization.

[0014] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0015] According to an embodiment of this application, a timing constraint checking method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0016] This embodiment provides a timing constraint checking method, which can be used in electronic devices such as backend servers, server clusters, distributed systems, cloud servers, or PCs (Personal Computers). Figure 1 This is a flowchart of a timing constraint checking method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps: Step S101: Obtain structural information for characterizing the connection relationship of digital circuits, and constraint information for characterizing timing constraint rules.

[0017] In this embodiment of the application, during timing constraint checks, the electronic device acquires structural information characterizing the connection relationships of digital circuits, as well as constraint information characterizing timing constraint rules. The digital circuits include multiple timing paths.

[0018] For example, the structural information is the gate-level netlist after logic synthesis, the constraint information is the SDC (Synopsys DesignConstraints) constraint file, and the timing path is used to characterize the circuit connection route that the signal travels from the starting point to the ending point.

[0019] Step S102: Based on the constraint information, obtain at least one unconstrained path from the structural information.

[0020] In this embodiment, after obtaining the aforementioned constraint information and structural information, the electronic device obtains at least one unconstrained path from the structural information based on the constraint information. An unconstrained path refers to a path not covered by temporal constraints.

[0021] For example, the electronic device calls the STA or logic synthesis tool engine to traverse all timing paths in the structure information, thereby obtaining at least one unconstrained path.

[0022] Step S103: Extract features from the unconstrained path to obtain path feature information.

[0023] In this embodiment of the application, after obtaining the above-mentioned unconstrained path, the electronic device performs feature extraction on the unconstrained path to obtain path feature information.

[0024] For example, for an unconstrained path, the electronic device performs feature extraction on the unconstrained path based on the above structural information and the above constraint information to obtain path feature information.

[0025] For example, the path feature information includes static topology features and dynamic clock tracing features. Static topology features characterize the structural properties of the unconstrained path itself, while dynamic clock tracing features characterize the clock propagation integrity of the start and / or end points of the unconstrained path upstream of the clock network.

[0026] Step S104: Based on the path feature information, obtain the time-series anomaly information corresponding to the path feature information.

[0027] In this embodiment, after obtaining the aforementioned path feature information, the electronic device obtains timing anomaly information corresponding to the path feature information based on the path feature information. The timing anomaly information is used to characterize the cause of timing anomalies in unconstrained paths.

[0028] In one possible implementation, the electronic device matches the path feature information with a variety of preset timing anomaly causes to obtain the timing anomaly information corresponding to the path feature information. For details, please refer to the description of step S104 below, which will not be repeated here.

[0029] In another possible implementation, the electronic device inputs path feature information into a machine learning model, which is trained based on historically labeled unconstrained path samples; further, it obtains temporal anomaly information output by the machine learning model.

[0030] The timing constraint inspection method provided in this embodiment automatically identifies unconstrained paths through structural and constraint information, and further extracts features from the unconstrained paths to obtain timing anomaly information. This forms a complete automated link from raw data (i.e., structural information) to diagnostic results (i.e., timing anomaly information). The method is easy to operate, and the rapid acquisition of timing anomaly information of unconstrained paths is beneficial to improving the subsequent repair rate of unconstrained paths.

[0031] In an exemplary embodiment, the path feature information in this application includes static topology features and dynamic clock tracing features. Step S103 above includes: Step S1031: Obtain the first structural data of the unconstrained path from the structural information.

[0032] In this embodiment of the application, after obtaining the aforementioned unconstrained path, the first structural data of the unconstrained path is obtained from the aforementioned structural information. The first structural data is used to characterize the path start point, path end point, and circuit connection information between the path start point and path end point of the unconstrained path.

[0033] Step S1032: Based on the constraint information, perform static topology analysis on the first structural data to obtain the static topology features of the unconstrained path.

[0034] In this embodiment of the application, after obtaining the first structural data, the electronic device performs static topology analysis on the first structural data based on constraint information to obtain the static topology features of the unconstrained path.

[0035] For example, the electronic device invokes the STA analysis tool to perform static topology analysis on the first structural data based on constraint information, and obtains the static topology features of the unconstrained path.

[0036] For example, in the embodiments of this application, static topology features include, but are not limited to, at least one of the following: the type of the path start point, the type of the path end point, the clock pin connected to the path start point, the clock pin connected to the path end point, the physical layer information traversed by the unconstrained path, the clock domain relationship of the unconstrained path, the setting information of the path start point, the setting information of the path end point, and other setting information.

[0037] For example, the type of the path start point can be any one of an input port, a register, or a clock pin. Similarly, the type of the path end point can be any one of an output port, a register, or a clock pin.

[0038] For example, the physical layer information traversed by an unconstrained path is used to characterize whether the unconstrained path travels from one module to another. For instance, an unconstrained path enters a submodule from the top-level module.

[0039] For example, the clock domain relationship of an unconstrained path includes any one of synchronous, asynchronous, same-source, and different-source.

[0040] For example, the settings for the starting point of a path include the maximum delay setting (max_delay), the minimum delay setting (min_delay), and a special value setting (case_value). Similarly, the settings for the ending point of a path include the maximum delay setting (max_delay), the minimum delay setting (min_delay), and a special value setting (case_value).

[0041] For example, other settings include the maximum delay setting (max_delay), minimum delay setting (min_delay), and special value setting (case_value) on timing units or pins other than the start and end points in the unconstrained path.

[0042] Step S1033: Based on static topological features, obtain the second structural data of the unconstrained path from the structural information.

[0043] In this embodiment, after obtaining the aforementioned static topology features, the electronic device obtains second structural data of the unconstrained path from the structural information based on the static topology features. The second structural data is used to characterize upstream node information associated with the path's starting point on the clock network, and upstream node information associated with the path's ending point on the clock network.

[0044] For example, the electronic device traces the origin of the path and the destination of the path based on the path origin information and the path destination information contained in the static topology features, and obtains the second structural data by combining the structural information on the clock network.

[0045] Step S1034: Based on the constraint information, perform dynamic clock tracing on the second structure data to obtain the dynamic clock tracing features of the unconstrained path.

[0046] In this embodiment of the application, after acquiring the second structural data, the electronic device performs dynamic clock tracing on the second structural data based on constraint information to obtain the dynamic clock tracing features of the unconstrained path.

[0047] For example, in the embodiments of this application, the dynamic clock tracing features include, but are not limited to, at least one of the following: missing clock definition, broken clock source path, and incorrect clock gating configuration.

[0048] For example, if a clock definition is missing, the electronic device, based on constraint information and combined with the second structure data, traces upwards to the root node of the clock tree to check whether the clock definition is missing.

[0049] For example, if the clock source path is broken, the electronic device uses constraint information and second structural data to trace back to check whether the clock path is complete.

[0050] For example, for clock gating configuration, the electronic device obtains the clock input pin of the clock gating unit traversed by the unconstrained path based on constraint information and combined with the second structure data, and checks whether the clock input pin has clock attributes; if the clock input pin does not have clock attributes, it further checks whether the enable signal of the clock gating unit is fixed to an invalid value or whether clock propagation is prohibited; if any of the above abnormalities exist, it is determined that the clock gating configuration is incorrect.

[0051] In an exemplary embodiment, step S104 includes: Step S1041: Match the path feature information with multiple preset time-series anomaly causes to obtain at least one candidate anomaly cause.

[0052] In this embodiment of the application, after obtaining the above-mentioned path feature information, the electronic device matches the path feature information with a variety of preset timing anomaly causes to obtain at least one candidate anomaly cause.

[0053] For example, timing anomalies may be caused by at least one of the following: missing clock definition, abnormal clock propagation, abnormal clock gating check, missing input delay constraints, missing output delay constraints, missing asynchronous cross-clock domain constraints, missing maximum delay constraints for asynchronous paths, missing spurious asynchronous paths, and missing maximum delay constraints for synchronous paths.

[0054] For example, different timing anomaly causes correspond to different matching conditions. The electronic device uses path feature information as a benchmark. If the path feature information meets the target matching conditions, then the timing anomaly cause corresponding to the target matching conditions is determined as a candidate anomaly cause.

[0055] For example, the matching condition for a missing clock definition is: both the path start point and the path end point are registers and there is no clock defined at the path start point or the path end point.

[0056] For example, the matching condition corresponding to the abnormal propagation of the generated clock is: the path between the generated clock and the source clock is incomplete or the generated clock constraint is not set after passing through the frequency division logic.

[0057] For example, the matching conditions corresponding to the clock gating check anomaly are: no clock propagation in the clock gating unit, the clock gating unit enable signal is set to a fixed value, and the clock gating unit is prohibited from clock propagation.

[0058] For example, the matching condition corresponding to the missing input delay constraint is: the path starting point is the input port, no input delay constraint is set or the virtual clock definition is missing.

[0059] For example, the matching condition corresponding to the missing output delay constraint is: the path endpoint is the output port, and no output delay constraint is set.

[0060] For example, the matching conditions corresponding to the lack of asynchronous cross-clock domain constraints are: the path start point and the path end point are in different clock domains, there is no synchronizer structure, and no asynchronous clock group constraints are set.

[0061] For example, the matching condition corresponding to the lack of maximum delay constraint for asynchronous paths is: the path start point and the path end point are in different clock domains, there is a synchronizer, the frequency difference between the two clock domains is large, and no maximum delay constraint is set.

[0062] For example, the matching conditions for the asynchronous path false path omission are: the path start and path end are in different clock domains, there is a synchronizer on the path, and the path has no actual data interaction in terms of logical function.

[0063] For example, the matching condition corresponding to the maximum delay constraint of the synchronization path is: the path start point and the path end point are in the same clock domain, there is a maximum delay setting at the path start point or the timing path, and the clock cannot propagate normally.

[0064] Step S1042: Based on the basic confidence parameters of the candidate anomaly causes, obtain the confidence level of the candidate anomaly causes.

[0065] In this embodiment of the application, after obtaining the above-mentioned candidate abnormal causes, the electronic device obtains the confidence level of the candidate abnormal causes based on the basic confidence parameters of the candidate abnormal causes.

[0066] For example, the basic confidence parameter is a preset parameter, which can be flexibly set and adjusted according to the actual situation. For instance, the basic confidence parameter for missing clock definition is 0.95, the basic confidence parameter for abnormal clock propagation is 0.75, the basic confidence parameter for abnormal clock gating check is 0.75, the basic confidence parameter for missing input delay constraint is 0.85, the basic confidence parameter for missing output delay constraint is 0.85, the basic confidence parameter for missing asynchronous cross-clock domain constraint is 0.92, the basic confidence parameter for missing maximum delay constraint of asynchronous path is 0.70, the basic confidence parameter for missing spurious path of asynchronous path is 0.70, and the basic confidence parameter for maximum delay constraint of synchronous path is 0.80.

[0067] Specifically, step S1042 includes: Step S1042a: Obtain the basic confidence level based on the basic confidence parameters.

[0068] For example, the electronic device obtains a basic confidence level based on a basic confidence parameter and a first preset weight. For instance, the electronic device determines the basic confidence level by multiplying the basic confidence parameter by the first preset weight. The first preset weight can be any value and can be flexibly set and adjusted according to actual circumstances.

[0069] Step S1042b: From the historical path data, obtain at least one similar path that satisfies the second preset condition in terms of similarity to the unconstrained path.

[0070] In one possible implementation, the second preset condition is that the similarity is greater than the first preset target value. For example, the electronic device obtains the similarity between each historical path and an unconstrained path from historical path data; further, historical paths with a similarity greater than the first preset target value are identified as similar paths. The first preset target value can be any value and can be flexibly set and adjusted according to actual circumstances.

[0071] In another possible implementation, the second preset condition is n similar paths. For example, the electronic device obtains the similarity between each historical path and an unconstrained path from historical path data; further, it determines the n historical paths with the highest similarity as similar paths. Here, n is a positive integer, and its value can be flexibly set and adjusted according to actual circumstances.

[0072] For example, similar paths are generally unconstrained paths.

[0073] Step S1042c: Based on the attribution accuracy of similar paths, obtain the historical confidence parameters.

[0074] Attribution accuracy is used to characterize the proportion of target similar paths relative to the total number of similar paths. Target similar paths refer to similar paths whose corresponding causes of target anomalies are correct.

[0075] For example, after the time-series inspection of similar paths to the target has been performed to obtain the cause of the target anomaly, the correctness of the cause of the target anomaly is determined by the human, and the correct cause of the target anomaly is assigned the correct label so as to obtain the attribution accuracy in the future.

[0076] Step S1042d: Based on the historical confidence parameters, obtain the historical confidence level.

[0077] For example, the electronic device obtains the historical confidence level based on historical confidence parameters and a second preset weight. For instance, the electronic device determines the historical confidence level by multiplying the historical confidence parameters by the second preset weight. The second preset weight can be any value and can be flexibly set and adjusted according to actual circumstances.

[0078] For example, the sum of the first preset weight and the second preset weight is 1. For instance, the first preset weight is 0.7 and the second preset weight is 0.3.

[0079] Step S1042e: Based on the basic confidence level and historical confidence level, obtain the confidence level of the candidate anomaly cause.

[0080] For example, the electronic device determines the confidence level of a candidate cause of an anomaly by summing the base confidence level and the historical confidence level.

[0081] For example, the formula for calculating the confidence score Ctotal for a candidate cause of anomaly is: Ctotal=α Cbase+γ Ccase; Where Cbase refers to the basic confidence parameter, α refers to the first preset weight, Ccase refers to the historical confidence parameter, and γ refers to the second preset weight.

[0082] Step S1043: Select the candidate anomaly cause whose confidence level meets the first preset condition as the target anomaly cause.

[0083] In this embodiment of the application, after obtaining the aforementioned confidence level, the electronic device uses the candidate abnormal cause whose confidence level meets the first preset condition as the target abnormal cause.

[0084] In one possible implementation, the first preset condition is that the confidence level is greater than a second preset target value. For example, the electronic device uses candidate anomaly causes with a confidence level greater than the second preset target value as target anomaly causes. The second preset target value can be any value and can be flexibly set and adjusted according to actual circumstances.

[0085] In another possible implementation, the first preset condition is the m candidate anomaly causes with the highest confidence level. For example, the electronic device uses the m candidate anomaly causes with the highest confidence level as the target anomaly cause. Here, m is a positive integer, and its value can be flexibly set and adjusted according to actual circumstances, such as 1, 2, 3, etc.

[0086] For example, after obtaining the cause of the target anomaly, the cause of the target anomaly can be manually detected to determine whether the cause of the target anomaly is correct, and the correct cause of the target anomaly can be assigned the correct label so that when performing time series checks on other unconstrained paths, the attribution accuracy can be obtained after the unconstrained path becomes a similar path in the historical path data.

[0087] Step S1044: Obtain repair suggestions for the cause of the target anomaly.

[0088] In this embodiment of the application, after obtaining the cause of the target anomaly, the electronic device obtains repair suggestions for the cause of the target anomaly.

[0089] For example, the electronic device obtains repair suggestions corresponding to the target anomaly cause based on a preset cause-suggestion mapping relationship. For instance, the repair suggestion for a missing clock definition is: define a clock; the repair suggestion for a clock propagation anomaly is: check the clock generation definition; the repair suggestion for a clock gating check anomaly is: check the gating settings; the repair suggestion for a missing input delay constraint is: define a virtual clock and set input delay constraints; the repair suggestion for a missing output delay constraint is: define a virtual clock and set output delay constraints; the repair suggestion for a missing asynchronous cross-clock domain constraint is: define a clock group; the repair suggestion for a missing asynchronous path maximum delay constraint is: set the maximum delay constraint; the repair suggestion for an asynchronous path dummy path omission is: set a dummy path; and the repair suggestion for a synchronous path maximum delay constraint is: check if the maximum delay constraint is set correctly.

[0090] In this embodiment of the application, the timing anomaly information includes the cause of the target anomaly, the confidence level of the cause of the target anomaly, and remediation suggestions. For example, as shown... Figure 2As shown, after acquiring path feature information, the electronic device obtains candidate anomaly causes and basic confidence parameters through rule matching; further, it evaluates the confidence of the basic confidence parameters to obtain the confidence of the candidate anomaly causes; further, it obtains the target anomaly cause based on the confidence of the candidate anomaly causes; further, it matches repair suggestions to the target anomaly cause to obtain repair suggestions for the target anomaly cause.

[0091] The temporal constraint inspection method provided in this embodiment obtains the cause of the target anomaly by matching the path feature mapping through a matching mechanism, thereby automating the attribution. The introduction of confidence makes the cause of the target anomaly quantifiable and credible, and the automatic repair suggestions improve the repair efficiency of unconstrained paths. In addition, the historical confidence of candidate anomaly causes is obtained by using the attribution accuracy of similar paths in historical path data. Combined with the basic confidence of the basic confidence parameters, the basic confidence reflects the reliability of the candidate anomaly cause itself (e.g., the typicality of a candidate anomaly cause in a general scenario). The historical confidence realizes the reuse of experience knowledge through similar paths. As historical path data continues to accumulate, the statistical basis of historical confidence becomes more and more reliable, the attribution accuracy continues to improve, and the accuracy of confidence gradually increases.

[0092] This embodiment provides a timing constraint checking method, which can be used in electronic devices such as backend servers, server clusters, distributed systems, cloud servers, or PCs (Personal Computers). Figure 3 This is a flowchart of a timing constraint checking method according to an embodiment of this application, such as... Figure 3 As shown, the process includes the following steps: Step S301: Obtain structural information for characterizing the connection relationship of digital circuits, and constraint information for characterizing timing constraint rules.

[0093] Step S302: Based on the constraint information, obtain at least one unconstrained path from the structural information.

[0094] Step S303: Extract features from the unconstrained path to obtain path feature information.

[0095] Step S304: Based on the path feature information, obtain the time-series anomaly information corresponding to the path feature information.

[0096] The above steps S301-304 and Figure 1 Steps S101-105 in the embodiment are similar; see details below. Figure 1 Examples are not described in detail here.

[0097] Step S305: Display the timing path diagram of the unconstrained path.

[0098] In this embodiment of the application, after obtaining the above-mentioned unconstrained path, the electronic device displays the timing path diagram of the unconstrained path.

[0099] Step S306: Based on the timing anomaly information, display breakpoint markers in the timing path diagram. In this embodiment, after obtaining the aforementioned timing anomaly information, the electronic device displays breakpoint markers in the timing path diagram. These breakpoint markers indicate critical circuit nodes that cause unconstrained paths to be outside the coverage of timing constraints. Exemplarily, these critical circuit nodes include, but are not limited to, at least one of the following: clock source missing nodes, clock generation break nodes, clock gating anomaly nodes, asynchronous clock domain boundary nodes, etc.

[0100] Step S307: In response to the operation on the breakpoint marker, display the cause of the target exception corresponding to the breakpoint marker.

[0101] In this embodiment of the application, after the breakpoint marker is displayed, the electronic device responds to the operation on the breakpoint marker by displaying the target abnormality cause corresponding to the breakpoint marker.

[0102] For example, the operation can be a click operation, a swipe operation, a corresponding key press operation, etc.

[0103] The timing constraint checking method provided in this embodiment displays the timing path diagram of the unconstrained path, displays breakpoint markers in the path diagram based on timing anomaly information, and displays the corresponding target anomaly cause in response to the operation of the breakpoint marker, making the display of the target anomaly cause more intuitive.

[0104] This embodiment provides a timing constraint checking method, which can be used in electronic devices such as backend servers, server clusters, distributed systems, cloud servers, or PCs (Personal Computers). Figure 4 This is a flowchart of a timing constraint checking method according to an embodiment of this application, such as... Figure 4 As shown, the process includes the following steps: Step S401: Obtain structural information for characterizing the connection relationship of digital circuits, and constraint information for characterizing timing constraint rules.

[0105] Step S402: Based on the constraint information, obtain at least one unconstrained path from the structural information.

[0106] Step S403: Extract features from the unconstrained path to obtain path feature information.

[0107] Step S404: Based on the path feature information, obtain the time-series anomaly information corresponding to the path feature information.

[0108] The above steps S401-404 and Figure 1 Steps S101-105 in the embodiment are similar; see details below. Figure 1 Examples are not described in detail here.

[0109] Step S405: For digital circuits, statistical analysis is performed on the timing anomaly information of each unconstrained path, and the first analysis report and the second analysis report are displayed.

[0110] The first analysis report is used to characterize the timing constraint detection status of each path in the digital circuit, while the second analysis report is used to characterize the timing anomaly distribution and repair priority in the digital circuit.

[0111] For example, timing constraint detection includes, but is not limited to, at least one of the following: path identifier, path start type, path end type, path start clock, path end clock, whether the path crosses clock domains, whether the path crosses modules, and the cause of the path's target exception.

[0112] The temporal constraint checking method provided in this embodiment performs cluster statistics on unconstrained paths, generating a first analysis report and a second analysis report. The temporal detection results are more intuitive, further reducing the burden of manual operation. This embodiment also provides a timing constraint checking device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0113] This embodiment provides a timing constraint checking device, such as... Figure 5 As shown, it includes: The information acquisition module 501 is used to acquire structural information that characterizes the connection relationship of digital circuits, and constraint information that characterizes timing constraint rules; wherein, the digital circuit includes multiple timing paths; The path acquisition module 502 is used to acquire at least one unconstrained path from the structure information based on the constraint information; wherein, the unconstrained path refers to a path not covered by temporal constraints; Feature extraction module 503 is used to extract features from the unconstrained path to obtain path feature information; The anomaly acquisition module 504 is used to obtain the timing anomaly information corresponding to the path feature information based on the path feature information.

[0114] In an exemplary embodiment, the feature extraction module 503 is used for: The first structural data of the unconstrained path is obtained from the structural information; wherein the first structural data is used to characterize the path start point, the path end point, and the circuit connection information between the path start point and the path end point of the unconstrained path. Based on the constraint information, static topology analysis is performed on the first structural data to obtain the static topology features of the unconstrained path; Based on the static topology features, second structural data of the unconstrained path is obtained from the structural information; wherein, the second structural data is used to characterize upstream node information associated with the starting point of the path on the clock network, and upstream node information associated with the ending point of the path on the clock network. Based on the constraint information, dynamic clock tracing is performed on the second structure data to obtain the dynamic clock tracing characteristics of the unconstrained path; The path feature information includes the static topology features and the dynamic clock tracing features.

[0115] In an exemplary embodiment, the static topology features include at least one of the following: the type of the path start point, the type of the path end point, the clock pin connected to the path start point, the clock pin connected to the path end point, the physical layer information traversed by the unconstrained path, the clock domain relationship of the unconstrained path, the setting information of the path start point, the setting information of the path end point, and other setting information.

[0116] In an exemplary embodiment, the dynamic clock tracing feature includes at least one of the following: missing clock definition, broken clock source path, and incorrect clock gating configuration.

[0117] In an exemplary embodiment, the exception acquisition module 504 includes: The cause matching unit is used to match the path feature information with multiple preset time-series anomaly causes to obtain at least one candidate anomaly cause. The confidence acquisition unit is used to acquire the confidence level of the candidate anomaly cause based on the basic confidence parameters of the candidate anomaly cause; The target acquisition unit is used to select candidate anomaly causes whose confidence level meets the first preset condition as target anomaly causes. The suggestion acquisition unit is used to acquire repair suggestions for the cause of the target anomaly; The time-series anomaly information includes the cause of the target anomaly, the confidence level of the cause of the target anomaly, and the repair suggestions.

[0118] In an exemplary embodiment, the confidence acquisition unit is configured to: Based on the aforementioned basic confidence parameters, the basic confidence level is obtained; From historical path data, obtain at least one similar path whose similarity to the unconstrained path meets the second preset condition; Based on the attribution accuracy of the similar paths, historical confidence parameters are obtained; wherein, the attribution accuracy is used to characterize the proportion of the target similar path relative to the total number of similar paths, and the target similar path refers to the similar path whose corresponding target anomaly cause is correct; Based on the historical confidence parameters, the historical confidence level is obtained; Based on the baseline confidence level and the historical confidence level, the confidence level of the candidate anomaly cause is obtained.

[0119] In an exemplary embodiment, the apparatus further includes: The path display module is used to display the time-series path diagram of the unconstrained path; A marker display module is used to display breakpoint markers in the timing path diagram based on the timing anomaly information. The cause display module is used to display the target exception cause corresponding to the breakpoint mark in response to the operation on the breakpoint mark.

[0120] In an exemplary embodiment, the apparatus further includes: The report display module is used to statistically analyze the timing anomaly information of each of the unconstrained paths of the digital circuit and display a first analysis report and a second analysis report. The first analysis report is used to characterize the timing constraint detection status of each path in the digital circuit, and the second analysis report is used to characterize the timing anomaly distribution and repair priority in the digital circuit.

[0121] The timing constraint checking apparatus provided in this application can execute the timing constraint checking method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the method execution. Further functional descriptions of the various modules and units described above are the same as in the corresponding embodiments described above, and will not be repeated here.

[0122] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0123] The following is a detailed reference. Figure 6The diagram illustrates a structural schematic suitable for implementing the electronic device described in the embodiments of this application. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 606 is also connected to the bus 604.

[0124] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0125] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the timing constraint checking method of embodiments of this application.

[0126] Figure 6 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0127] This application also provides a computer-readable storage medium. The methods described above according to this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the timing constraint checking method shown in the above embodiments is implemented.

[0128] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0129] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for checking timing constraints, characterized in that, The method includes: Obtain structural information to characterize the connection relationships of digital circuits, and constraint information to characterize timing constraint rules; wherein, the digital circuits include multiple timing paths; Based on the constraint information, at least one unconstrained path is obtained from the structure information; wherein, the unconstrained path refers to a path not covered by temporal constraints; Feature extraction is performed on the unconstrained path to obtain path feature information; Based on the path feature information, the time-series anomaly information corresponding to the path feature information is obtained.

2. The method according to claim 1, characterized in that, The step of extracting features from the unconstrained path to obtain path feature information includes: The first structural data of the unconstrained path is obtained from the structural information; wherein the first structural data is used to characterize the path start point, the path end point, and the circuit connection information between the path start point and the path end point of the unconstrained path. Based on the constraint information, static topology analysis is performed on the first structural data to obtain the static topology features of the unconstrained path; Based on the static topology features, second structural data of the unconstrained path is obtained from the structural information; wherein, the second structural data is used to characterize upstream node information associated with the starting point of the path on the clock network, and upstream node information associated with the ending point of the path on the clock network. Based on the constraint information, dynamic clock tracing is performed on the second structure data to obtain the dynamic clock tracing characteristics of the unconstrained path; The path feature information includes the static topology features and the dynamic clock tracing features.

3. The method according to claim 2, characterized in that, The static topology features include at least one of the following: the type of the path start point, the type of the path end point, the clock pin connected to the path start point, the clock pin connected to the path end point, the physical layer information traversed by the unconstrained path, the clock domain relationship of the unconstrained path, the setting information of the path start point, the setting information of the path end point, and other setting information.

4. The method according to claim 2, characterized in that, The dynamic clock tracing features include at least one of the following: missing clock definition, broken clock source path, or incorrect clock gating configuration.

5. The method according to claim 1, characterized in that, The step of obtaining the time-series anomaly information corresponding to the path feature information based on the path feature information includes: The path feature information is matched with multiple preset time-series anomaly causes to obtain at least one candidate anomaly cause; Based on the basic confidence parameters of the candidate anomaly causes, the confidence level of the candidate anomaly causes is obtained; Candidate anomalies whose confidence levels meet the first preset condition are selected as target anomalies. Obtain repair suggestions for the cause of the target anomaly; The time-series anomaly information includes the cause of the target anomaly, the confidence level of the cause of the target anomaly, and the repair suggestions.

6. The method according to claim 5, characterized in that, The step of obtaining the confidence level of the candidate anomaly cause based on the basic confidence parameters of the candidate anomaly cause includes: Based on the aforementioned basic confidence parameters, the basic confidence level is obtained; From historical path data, obtain at least one similar path whose similarity to the unconstrained path meets the second preset condition; Based on the attribution accuracy of the similar paths, historical confidence parameters are obtained; wherein, the attribution accuracy is used to characterize the proportion of the target similar path relative to the total number of similar paths, and the target similar path refers to the similar path whose corresponding target anomaly cause is correct; Based on the historical confidence parameters, the historical confidence level is obtained; Based on the baseline confidence level and the historical confidence level, the confidence level of the candidate anomaly cause is obtained.

7. The method according to claim 1, characterized in that, The method further includes: Display the timing path diagram of the unconstrained path; Based on the timing anomaly information, breakpoint markers are displayed in the timing path diagram; In response to an operation on the breakpoint marker, the cause of the target exception corresponding to the breakpoint marker is displayed.

8. The method according to claim 1, characterized in that, The method further includes: For the digital circuit, the timing anomaly information of each of the unconstrained paths is statistically analyzed, and a first analysis report and a second analysis report are displayed. The first analysis report is used to characterize the timing constraint detection status of each path in the digital circuit, and the second analysis report is used to characterize the timing anomaly distribution and repair priority in the digital circuit.

9. A timing constraint checking device, characterized in that, The device includes: The information acquisition module is used to acquire structural information characterizing the connection relationship of digital circuits, and constraint information characterizing timing constraint rules; wherein, the digital circuit includes multiple timing paths; The path acquisition module is used to acquire at least one unconstrained path from the structure information based on the constraint information; wherein, the unconstrained path refers to a path not covered by temporal constraints; The feature extraction module is used to extract features from the unconstrained path to obtain path feature information; The anomaly acquisition module is used to obtain the timing anomaly information corresponding to the path feature information based on the path feature information.

10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the timing constraint checking method of any one of claims 1 to 8 by executing the computer instructions.

Images