Semiconductor device

Abstract

A semiconductor device includes a substrate; a bit line and a word line extending on the substrate in directions intersecting each other; a semiconductor pattern connected to the bit line and adjacent to the word line; and a plurality of data storage devices connected to the semiconductor pattern, wherein the data storage device includes a first electrode positioned in a direction perpendicular to the substrate; a plurality of second electrodes positioned in a direction parallel to the substrate; and a dielectric layer provided between the first electrode and the second electrode, a planar area of the first electrode in the direction parallel to the substrate increases as the first electrode moves away from the substrate, and a thickness of each of the second electrodes in the direction perpendicular to the substrate increases as the second electrode becomes closer to the substrate.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0009031, filed with the Korean Intellectual Property Office on January 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] Technologies are being developed to increase the integration density of semiconductor devices. In the case of two-dimensional semiconductor devices, the degree of integration is primarily determined by the area occupied by a single memory cell, and this aspect of integration can be influenced by the level of fine patterning technology.

[0004] However, the fine patterning technology requires expensive equipment, so the integration density of two-dimensional semiconductor devices is increasing, but still limited. Therefore, three-dimensional semiconductor memory devices that include memory cells arranged in three dimensions are being proposed. Summary of the Invention

[0005] Some aspects of this disclosure provide semiconductor devices with improved sensing margin and operating characteristics.

[0006] Some aspects of this disclosure provide a semiconductor device comprising: a substrate; bit lines and word lines extending on the substrate in directions intersecting each other; a semiconductor pattern connected to and adjacent to the bit lines; and a plurality of data storage devices connected to the semiconductor pattern, wherein the data storage devices include: a first electrode positioned in a direction perpendicular to the substrate; a plurality of second electrodes positioned in a direction parallel to the substrate; and a dielectric layer disposed between the first electrode and the second electrodes, wherein the planar area of ​​the first electrode in the direction parallel to the substrate increases as the first electrode moves away from the substrate, and the thickness of each of the second electrodes in the direction perpendicular to the substrate increases as the second electrode moves closer to the substrate.

[0007] Some aspects of this disclosure provide a semiconductor device comprising: a substrate; bit lines and word lines extending on the substrate in directions intersecting each other; a semiconductor pattern connected to and adjacent to the bit lines; and a plurality of data storage devices connected to the semiconductor pattern, wherein the data storage devices include: a first electrode positioned in a direction perpendicular to the substrate; a plurality of second electrodes positioned in a direction parallel to the substrate; and a dielectric layer disposed between the first electrode and the second electrodes, wherein the planar area of ​​the first electrode in the direction parallel to the substrate increases as the first electrode moves away from the substrate, and the second electrodes include a first group having a first thickness and a second group having a second thickness, the first thickness being greater than the second thickness, and the first group being positioned closer to the substrate than the second group.

[0008] Some aspects of this disclosure provide a semiconductor device comprising: a substrate; bit lines and word lines extending on the substrate in directions intersecting each other; a semiconductor pattern connected to and adjacent to the bit lines; and a plurality of data storage devices connected to the semiconductor pattern, wherein the data storage devices include: a first electrode positioned in a direction perpendicular to the substrate; a plurality of second electrodes positioned in a direction parallel to the substrate; and a dielectric layer disposed between the first electrode and the second electrodes, wherein the planar area of ​​the first electrode at its lower surface closest to the substrate in the direction parallel to the substrate is smaller than the planar area of ​​the first electrode at its upper surface furthest from the substrate in the direction parallel to the substrate, and the thickness of the second electrode among the plurality of second electrodes positioned closest to the substrate in the direction perpendicular to the substrate is greater than the thickness of the second electrode among the second electrodes positioned furthest from the substrate in the direction perpendicular to the substrate.

[0009] Some aspects of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming bit lines and word lines extending in intersecting directions on a substrate, and semiconductor patterns connected to and adjacent to the bit lines and word lines; alternately stacking a sacrificial layer and an interlayer insulating layer on the substrate; forming a hole by etching the sacrificial layer and the interlayer insulating layer; and forming a second electrode, a dielectric layer, and a first electrode within the hole, wherein the first electrode is formed in a direction perpendicular to the substrate, the second electrode is formed in a space in a direction parallel to the substrate in which the sacrificial layer is positioned, and the thickness of the sacrificial layer in the direction perpendicular to the substrate increases as the sacrificial layer becomes closer to the substrate.

[0010] The thickness of the second electrode in the direction perpendicular to the substrate can increase as the second electrode gets closer to the substrate.

[0011] In the step of forming the hole by etching the sacrificial layer and the interlayer insulating layer, the planar area of ​​the hole in the direction parallel to the substrate may decrease as the hole gets closer to the substrate.

[0012] The diameter of the lower surface of the first electrode closest to the substrate can be smaller than the diameter of the upper surface of the first electrode furthest from the substrate.

[0013] The sacrificial layer and interlayer insulation can be made of different materials.

[0014] After forming the hole by etching the sacrificial layer and the interlayer insulating layer, selective etching of the sacrificial layer may also be included.

[0015] The first electrode may include a first portion positioned in a direction perpendicular to the substrate and a second portion protruding from the first portion in a direction parallel to the substrate.

[0016] The first and second electrodes may comprise metals with different work functions.

[0017] In a plan view, the second electrode may surround the first electrode.

[0018] The second electrode may include a portion in the plan view that is separate from the first electrode and does not surround the first electrode.

[0019] Therefore, semiconductor devices with improved sensing margin and operating characteristics can be provided. Attached Figure Description

[0020] Figure 1 This is a top plan view of an example of a semiconductor device.

[0021] Figure 2 It is along Figure 1 The sectional view taken from line II-II'.

[0022] Figure 3 and Figure 4 This is a diagram showing a capacitor in a semiconductor device in which the thickness of the second electrode is uniform.

[0023] Figure 5 and Figure 6 This is a diagram showing a capacitor in a semiconductor device in which the thickness of the second electrode varies depending on the region.

[0024] Figure 7 It is along Figure 1 A cross-sectional view of an example semiconductor device taken by line II-II'.

[0025] Figure 8 This is a cross-sectional view showing an example of a semiconductor device.

[0026] Figure 9 This is a cross-sectional view showing an example of a semiconductor device.

[0027] Figure 10 This is a cross-sectional view showing an example of a semiconductor device.

[0028] Figure 11 This is a schematic cross-sectional view showing an example of a capacitor, including the first electrode, the dielectric layer, and the second electrode.

[0029] Figure 12 This is another example of a semiconductor device. Figure 11 The corresponding sectional view.

[0030] Figure 13 This is another example of a semiconductor device. Figure 11 The corresponding sectional view.

[0031] Figure 14 This is another example of a semiconductor device. Figure 1 The corresponding floor plan.

[0032] Figure 15 This is another example of a semiconductor device. Figure 1 The corresponding floor plan.

[0033] Figures 16 to 45 This is a process diagram illustrating an example of the manufacturing process for a semiconductor device. Detailed Implementation

[0034] The present disclosure will be described more fully below with reference to the accompanying drawings, in which specific examples are shown. As those skilled in the art will recognize, the described examples may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0035] For clarity, some parts that are not directly related to the description have been omitted, and throughout the specification, the same reference numerals denote the same or similar components.

[0036] Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. For example, the thickness of layers, regions, films, panels, areas, etc., may be exaggerated in the drawings for clarity.

[0037] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on that other element, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" another element, no intermediate element is present. Furthermore, in the specification, the terms "on" or "above" refer to relative positions and do not necessarily mean that the element is positioned on its upper side based on the direction of gravity.

[0038] Furthermore, unless explicitly stated otherwise, the words “including” and variations such as “contains” or “comprising” will be understood to imply inclusion of the stated elements but not exclusion of any other elements.

[0039] Furthermore, throughout the instruction manual, the phrase "in a plan view" means when viewing the target portion from above, and the phrase "in a sectional view" means when viewing a section taken by vertically cutting the target portion from the side.

[0040] Figure 1 A top plan view showing an example of a semiconductor device. Figure 2 Show along Figure 1 The sectional view taken from line II-II'.

[0041] Reference Figure 1 and Figure 2 The semiconductor device may include a substrate 110, bit lines BL and word lines WL extending on the substrate 110 in intersecting directions, a semiconductor pattern 150 connected (e.g., electrically connected) to the bit lines BL and adjacent to the word lines WL, and a plurality of capacitors 300 connected to the semiconductor pattern 150. The capacitors 300 may be used as a data storage device.

[0042] A semiconductor device may include multiple memory cells. Each memory cell may include a semiconductor pattern 150, a bit line BL connected to the semiconductor pattern 150, a word line WL adjacent to the semiconductor pattern 150, and a data storage device (capacitor 300) connected to the semiconductor pattern 150. The memory cells may be stacked on a third direction DR3 perpendicular to the upper surface of the substrate 110. The memory cells may be arranged in the same layer along a first direction DR1 and a second direction DR2 parallel to the upper surface of the substrate 110. For example, the semiconductor device may include three-dimensionally stacked memory cells.

[0043] Each memory cell may include a transistor and multiple data storage devices connected to the transistor. Depending on the material of the dielectric layer included in the data storage devices, the semiconductor device may be dynamic random access memory (DRAM), ferroelectric RAM (FeRAM), or antiferroelectric RAM (AFeRAM). Although Figure 1 and Figure 2 A transistor and a plurality of capacitors connected to the transistor are shown, but the semiconductor device is not limited to this configuration and may include, for example, two transistors and a plurality of capacitors connected to the two transistors.

[0044] The substrate 110 may include semiconductor materials. For example, the substrate 110 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, the substrate 110 may include semiconductors (such as Si or Ge) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, or InP). For example, the substrate 110 may be a single-crystal epitaxial layer grown on a single-crystal silicon substrate. However, the materials included in the substrate 110 are not limited to these and may be varied.

[0045] The first insulating layer 120 may be positioned on the substrate 110. The first insulating layer 120 may be positioned on the upper surface of the substrate 110. The first insulating layer 120 may cover the upper surface of the substrate 110.

[0046] The first insulating layer 120 may include an insulating material. For example, the first insulating layer 120 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x (or combinations thereof), but this disclosure is not limited thereto.

[0047] The bit line BL can be positioned on the first insulating layer 120. (See also...) Figure 1 and Figure 2 Multiple bit lines BL can be extended and positioned along the first direction DR1. In addition, the bit lines BL can be arranged spaced apart from each other in the second direction DR2.

[0048] Bit lines BL may include conductive materials. Bit lines BL may include, for example, doped semiconductor materials, conductive metal nitrides, metals, metal-semiconductor compounds, or combinations thereof, but this disclosure is not limited thereto.

[0049] Semiconductor pattern 150 can be positioned to contact bit line BL. (Refer to...) Figure 2 The semiconductor pattern 150 can be positioned superimposed on the first electrode 310 on the third direction DR3. Therefore, the semiconductor pattern 150 can be positioned below the first electrode 310. Multiple semiconductor patterns 150 can be positioned at multiple locations spaced apart from each other along the first direction DR1 and the second direction DR2. (See also...) Figure 1 and Figure 2 The semiconductor pattern 150 can be positioned at the intersection of the word line WL and the bit line BL (e.g., at a position on the first direction DR1 and the second direction DR2). Figure 2 As shown, the first end of the semiconductor pattern 150 may contact the bit line BL.

[0050] Semiconductor pattern 150 may include semiconductor materials. For example, semiconductor pattern 150 may include silicon, germanium, or silicon-germanium. For example, semiconductor pattern 150 may include monocrystalline silicon or polycrystalline silicon. However, one or more materials are not limited thereto. For example, semiconductor pattern 150 may include oxide semiconductor materials (such as indium gallium zinc oxide (IGZO)). For example, semiconductor pattern 150 may include oxide semiconductor materials (such as IGZO, Sn-IGZO, IWO, CuS2, WSe2, IZO, ZTO, YZO, or MIZO). As another example, semiconductor pattern 150 may include two-dimensional semiconductor materials. For example, semiconductor pattern 150 may include two-dimensional semiconductor materials (such as MoS2, MoSe2, or WS2).

[0051] Reference Figure 2 The word line WL can be positioned to insulate it from the bit line BL. A second insulating layer 122 can be positioned between the bit line BL and the word line WL. The second insulating layer 122 may include an insulating material. For example, the second insulating layer 122 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiON) x (or combinations thereof), but this disclosure is not limited thereto.

[0052] In some implementations, the semiconductor device may include multiple word lines (WL). See also... Figure 1 and Figure 2 The word lines WL can extend and be positioned along the second direction DR2. Furthermore, the word lines WL can be arranged spaced apart from each other along the first direction DR1.

[0053] The letter line WL can be adjacent to the semiconductor pattern 150. (See reference...) Figure 1 and Figure 2 The letter line WL can be positioned to surround the semiconductor pattern 150.

[0054] The semiconductor device may include a gate insulating layer Gox positioned between a word line WL and a semiconductor pattern 150. The word line WL may be separated from the semiconductor pattern 150 by the gate insulating layer Gox.

[0055] The word line (WL) may include a conductive material. The word line (WL) may include, for example, a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or a combination thereof, but this disclosure is not limited thereto.

[0056] The gate insulating layer Gox may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0057] The second insulating layer 122 can be positioned on the word line WL. Figure 2 In the diagram, the insulating layer positioned between the word line WL and the bit line BL, and on the word line WL, is shown as a single second insulating layer 122. However, this is only an example, and the insulating layer positioned between the word line WL and the bit line BL and the insulating layer positioned on the word line WL may be different.

[0058] Reference Figure 1 and Figure 2 The first electrode 310 may be positioned (e.g., along a third direction DR3) to overlap with the semiconductor pattern 150. The first electrode 310 may be positioned to extend along the third direction DR3. Figure 1 and Figure 2 As shown, the first electrode 310 may have a cylindrical shape extending in the third direction DR3. However, this shape of the first electrode 310 is merely an example, and this disclosure is not limited thereto. In some embodiments, the planar cross-section of the first electrode 310 may be quadrilateral, and the first electrode 310 may have a prism shape. Furthermore, in some embodiments, the first electrode 310 may include a vertical portion extending in the third direction DR3 and an extension extending in a direction intersecting the vertical portion. Other examples of the shape of the first electrode 310 will be described later.

[0059] like Figure 2 As shown, the first electrode 310 can be positioned to extend on the third-direction DR3. (As will be discussed regarding...) Figures 16 to 45 As described, during the process of forming the first electrode 310, a hole can be formed on the third-party DR3, and then the hole can be filled with a conductive material to form the first electrode 310. The upper and lower diameters of the hole formed at this time can be different. This is derived from the shape of the etching process used to form the hole. Therefore, the diameter R2 at the uppermost part of the first electrode 310 and the diameter R1 at the lowermost part of the first electrode 310 can also be different. Figure 1 As shown, the diameter R2 at the uppermost part of the first electrode 310 may be larger than the diameter R1 at the lowermost part of the first electrode 310. In some embodiments, the width of the lower surface of the first electrode 310 in the first direction DR1 may be smaller than the width of the upper surface of the first electrode 310 in the first direction DR1. For example, the diameter of the first electrode 310 in a direction parallel to the substrate 110 (e.g., the upper surface of the substrate 110) may vary depending on the region. Figure 2 As shown, the diameter (or planar area) of the first electrode 310 in a direction parallel to the substrate 110 (e.g., the upper surface of the substrate 110) may gradually increase as it moves away from the substrate 110. In some embodiments, as will be described later, at least based on the variation in the diameter of the first electrode 310 according to the layer, the capacitance of the capacitor including the first electrode 310 may also vary according to the region.

[0060] The first end of the first electrode 310 may be in contact with the semiconductor pattern 150. For example, the first electrode 310 may be electrically connected to the semiconductor pattern 150. The first electrode 310 may include a conductive material. The first electrode 310 may include at least one of, for example, a metal material, a conductive metal nitride, and a doped semiconductor material.

[0061] Referring to Figure 2 , the dielectric layer 320 may be positioned along the periphery of the first electrode 310. Referring together to Figure 1 and Figure 2 , the dielectric layer 320 may be positioned to surround the first electrode 310. For example, the dielectric layer 320 may be positioned between the first electrode 310 and the plurality of second electrodes 330. The dielectric layer 320 may include at least one of a high dielectric constant material, a ferroelectric material, and an antiferroelectric material. In some embodiments, the high dielectric constant material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the ferroelectric material may include a Hf compound. The Hf compound may be, for example, a hafnium-based oxide. The hafnium-based oxide may further include at least one impurity selected from Zr, Si, Al, Y, Gd, La, Sc, and Sr. The ferroelectric material may include, for example, HfO2, HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof. In some embodiments, the antiferroelectric material may include at least one selected from hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide (Hf x Zr 1-x O2, where 0 < x < 1), PbZrO3, PbHfO3, and a combination thereof. In addition, the dielectric layer 320 may have a multilayer structure. In addition, the conductive layer 350 ( Figure 13 shown in) may be positioned between the dielectric layer 320 and the first electrode 310 or the second electrode 330. Various examples of the dielectric layer 320 will be described later with reference to the drawings.

[0062] Referring to Figure 1 and Figure 2 , the plurality of second electrodes 330 may be positioned to extend in a direction parallel to the substrate 110 (e.g., the upper surface of the substrate 110). Referring to Figure 1 , the plurality of second electrodes 330 may be positioned to extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. In addition, referring to Figure 2The second electrode 330 may be positioned spaced apart on the third-direction DR3. An interlayer insulating layer 130 may be positioned between adjacent second electrodes 330. The interlayer insulating layer 130 may include an insulating material. The interlayer insulating layer 130 may include silicon oxide and / or silicon nitride, but the scope of this disclosure is not limited thereto.

[0063] Each second electrode 330, dielectric layer 320, and first electrode 310 can constitute a capacitor 300. For example, a second electrode 330, dielectric layer 320, and first electrode 310 spaced apart on a third-direction DR3 can constitute a capacitor 300, and as... Figure 2 As shown, the semiconductor device may have multiple capacitors 300 stacked on the third-direction DR3. These capacitors 300 may constitute a data storage device.

[0064] The second electrode 330 may include a conductive material. The second electrode 330 may include at least one of, for example, a metallic material, a conductive metal nitride, and a doped semiconductor material.

[0065] In some embodiments, the first electrode 310 and the second electrode 330 may comprise the same material, but this disclosure is not limited thereto. For example, the first electrode 310 and the second electrode 330 may comprise different materials. For example, the first electrode 310 and the second electrode 330 may comprise materials with different work functions. When the first electrode 310 and the second electrode 330 comprise materials with different work functions and the dielectric layer 320 comprises a ferroelectric material, the hysteresis curve (or hysteresis curve) of the dielectric layer 320 may be shifted. In this case, the write voltage and read voltage of the ferroelectric memory may be set differently, and the read voltage may be reduced.

[0066] Reference Figure 2 The thickness of the second electrode 330, which is positioned spaced apart on the third-party DR3, can be different. For example... Figure 2 As shown, the thickness H1 of the second electrode 330 closest to the substrate 110 may be greater than the thickness H2 of the second electrode 330 in the layer directly above it.

[0067] exist Figure 2 In the diagram, the second electrode 330 of the tenth layer is shown on top of the third-direction DR3. However, this is an example for better understanding and ease of description, and the number of stacked second electrodes 330 may differ from ten.

[0068] In some embodiments, when the thickness of the second electrode 330 located in the nth layer is Hn, Hn can decrease as n increases. For example, as Figure 2As shown, the thicknesses of the second electrode 330 positioned in each layer can have the following relationship: H1>H2>H3>H4>H5>H6>H7>H8>H9>H10. Figure 2 For ease of description, only 10 layers are shown, but even when the second electrodes 330 are stacked in N layers, the thickness of each second electrode 330 can follow the relationship: H1>H2>H3>H4……>Hn. For example, the thickness of the second electrode 330 can become thinner as it moves away from the substrate 110.

[0069] As described above, this configuration improves capacitance variation and sensing margin for each capacitor because the area of ​​the first electrode 310 becomes narrower as the first electrode 310 gets closer to the substrate 110. For example, the variation in thickness of the second electrode 330 can compensate for the effect of the variation in the area of ​​the first electrode 310 on the third-direction DR3.

[0070] The following text will describe in detail examples of the effects of semiconductor devices. Figure 3 and Figure 4 The regions of the various capacitors in the semiconductor device are shown, in which the thickness of the second electrode 330 is uniform. Figure 3 A three-dimensional view of the first electrode 310 and dielectric layer 320 in each capacitor is shown, while Figure 4 Show Figure 3 The figure depicts a cross-sectional view of a capacitor, which includes a first electrode 310, a dielectric layer 320, and a second electrode 330.

[0071] Reference Figure 3 and Figure 4 As described above, in the hole-forming process used to form the first electrode 310, the area of ​​the first electrode 310 can be formed differently for each region due to the etching distribution. Therefore, when the thickness of the second electrode 330 is formed to be the same (H1=H2=H3), the area of ​​the capacitor can vary for each layer, which can lead to differences in sensing margin. Furthermore, as... Figure 4 As shown, the length of the second electrode 330 connected to the contact electrode 700 is different for each layer, so RC delay may occur.

[0072] Figure 5 and Figure 6 The diagram shows regions of various capacitors in a semiconductor device, where the thickness of the second electrode 330 varies depending on the region (e.g., as shown regarding...). Figure 2 (As described). Figure 5 A three-dimensional view of the first electrode 310 and dielectric layer 320 in each capacitor is shown, while Figure 6 A cross-sectional view is shown, including a first electrode 310, a dielectric layer 320, and a second electrode 330.

[0073] Reference Figure 5 and Figure 6 The thickness of the second electrode 330 can vary depending on the region. For example, in the capacitor with the smallest area of ​​the first electrode 310, the thickness H1 of the second electrode 330 can be the thickest, and in the capacitor with the largest area of ​​the first electrode 310, the thickness H3 of the second electrode 330 can be the thinnest. Therefore, the reduction in capacitor area caused by the small area of ​​the first electrode 310 can be compensated for by increasing the thickness of the second electrode 330. Thus, the areas of the capacitors located in each layer can be similar, minimizing differences in sensing margin. Furthermore, as... Figure 6 As shown, although the length of the second electrode 330 connected to the contact electrode 700 is different for each layer, the resistance difference caused by these length variations can be compensated by forming the second electrode 330 with different thicknesses, thereby reducing the RC delay difference between layers.

[0074] exist Figure 2 In the figure, the thickness of the second electrode 330 located in each layer is shown to be completely different for each second electrode 330, but in some embodiments, the thickness of the second electrode 330 may vary according to a particular group, while being uniform within the same group.

[0075] For example, Figure 7 Another example of a semiconductor device is shown. Figure 2 The region corresponding to the region. (Refer to...) Figure 7 The thickness of the second electrode 330 can vary for each group. (Refer to...) Figure 7 The second electrode 330 positioned in the first group 3301 may have a first thickness H1, and the second electrode 330 included in the second group 3302 may have a second thickness H2. Figure 7 The diagram shows a configuration in which five second electrodes 330 are included in a group; however, this is merely an example, and the number of second electrodes 330 included in a group can vary. Furthermore, in Figure 7 In the illustration, for ease of description, ten second electrodes 330 and two groups are shown, but this is only an example, and the number of second electrodes 330 and groups to be stacked can vary.

[0076] In some implementations, such as Figure 7 As shown, the thickness H1 of the second electrode 330 of the first group 3301, which is closest to the substrate 110, can be greater than the thickness H2 of the second electrode 330 of the second group 3302, which is further away from the substrate 110. Therefore, as in Figure 2 In the example, the difference in sensing margin caused by the difference in the area of ​​the first electrode 310 in each region can be compensated. Figure 2In the example, a process is used to form a second electrode 330 positioned in each layer with different thicknesses, but in Figure 7 In the example with Figure 2 Compared to the previous example, the process can be simplified by dividing the second electrode 330 into groups and forming groups using different thicknesses.

[0077] In addition, Figure 2 and Figure 7 In the diagram, the first electrode 310 is shown as having a cylindrical shape extending in a third direction DR3, and the dielectric layer 320 is positioned along the periphery of the first electrode 310, but the shapes of the first electrode 310 and the dielectric layer 320 may vary.

[0078] For example, Figure 8 Another example of a semiconductor device is shown. Figure 2 The part indicated by A in [the document / reference](link). Figure 8 The semiconductor device may include a first electrode 310 having a first portion 311 extending in a third direction DR3 and a second portion 312 protruding in a first direction DR1. In this case, the second portion 312 may be positioned adjacent to the second electrode 330. For example, the second portion 312 may be positioned parallel to (or stacked on) the second electrode 330 in the first direction DR1, and the second portion 312 may not be positioned within the unpositioned portion of the second electrode 330. Furthermore, a dielectric layer 320 may be positioned along the edge of the first electrode 310. For example, the dielectric layer 320 may extend along the first portion 311 and the second portion 312. Therefore, in Figure 8 In the cross-section shown, the dielectric layer 320 may include a protrusion projecting in the first direction DR1. For a semiconductor device having this shape, the capacitance of the capacitor can be increased by increasing the area of ​​the capacitor.

[0079] Figure 9 This illustrates another example of a semiconductor device. Figure 8 The cross-section corresponding to the cross-section. (Refer to...) Figure 9 In addition to the first electrode 310, it includes a ratio Figure 8 In addition to the second part 312 of the middle part, semiconductor devices and Figure 8 The semiconductor devices are similar to or equivalent to these. Detailed descriptions of identical components will be omitted below. See reference... Figure 8 The first electrode 310 may have a first portion (or vertical portion) 311 extending in the third direction DR3 and a second portion 312 protruding in the first direction DR1. (Refer to...) Figure 9 The second portion 312 can also be positioned in the portion adjacent to the second electrode 330 in the first direction DR1 and in the portion adjacent to the interlayer insulating layer 130 in the first direction DR1. Figure 8In the example, the second portion 312 is located on the same layer as the second electrode 330, but in Figure 9 In the example, the second portion 312 may be positioned on the same layer as the second electrode 330 and also on the same layer as the interlayer insulating layer 130. For example, a portion of the second portion 312 may overlap with the second electrode 330 in the first direction DR1, and another portion of the second portion 312 may not overlap with the second electrode 330. Figure 9 The semiconductor device may include more Figure 8 The example includes the second part 312 (e.g., each capacitor). In Figure 9 In the example, dielectric layer 320 can be positioned along the edge of first electrode 310. Therefore, in Figure 9 In the cross-section shown, the dielectric layer 320 may include a dielectric layer that is more than... Figure 8 The example shows many protrusions (e.g., each capacitor). For semiconductor devices with this shape and similar shapes, the capacitance of the capacitor can be increased by increasing the area of ​​the capacitor.

[0080] Figure 10 This illustrates another example of a semiconductor device. Figure 8 The cross-section corresponding to the cross-section. (Refer to...) Figure 10 The semiconductor device may include a first electrode 310 having a vertical portion 311 and a recessed portion 313, wherein the width of the first electrode 310 in the recessed portion 313 changes (e.g., narrows) in a third direction DR3. For example, the planar area of ​​the recessed portion 313 parallel to the surface of the substrate 110 may change with increasing distance from the substrate 110.

[0081] Each recessed portion 313 may be positioned adjacent to the second electrode 330. Each recessed portion 313 may be positioned parallel to or overlapping the second electrode 330 in the first direction DR1. The second electrode 330 may be positioned extending in the first direction DR1 within the region where the recessed portion 313 of the first electrode 310 is located. Figure 10 As shown, the recessed portion 313 may include a curved surface. The dielectric layer 320 may also be positioned along the edge of the first electrode 310. Figure 2 In contrast, dielectric layer 320 can be formed along the surface of recessed portion 313 to increase the area of ​​the capacitor and increase its capacitance. Figure 8 and Figure 9 In some embodiments, the planar area of ​​the first electrode 310 increases as the capacitance of the capacitor increases. Figure 10 In some embodiments, the capacitance of the capacitor can be increased without increasing the planar area of ​​the first electrode 310.

[0082] In the preceding description, the capacitor is briefly described as having a structure including a first electrode 310, a dielectric layer 320, and a second electrode 330, but the structure of the capacitor may differ in some embodiments.

[0083] Figure 11 A schematic diagram (e.g., cross-sectional view) illustrating an example of a capacitor is shown. (See reference...) Figure 11 The first electrode 310 and the second electrode 330 may comprise the same material, or they may comprise materials with different work functions. When the first electrode 310 and the second electrode 330 comprise materials with different work functions and the dielectric layer 320 comprises a ferroelectric material, the hysteresis curve of the dielectric layer 320 may be shifted. In this case, the write voltage and read voltage of the ferroelectric memory may be set differently, and the read voltage may be reduced.

[0084] Figure 12 Another example of capacitors is shown. Figure 11 The cross-section corresponding to the cross-section. (Refer to...) Figure 12 The dielectric layer 320 can have a multilayer structure. (Refer to...) Figure 12 The dielectric layer 320 may have a structure in which a first layer 321 and a second layer 322 are stacked alternately. For example, the first layer 321 may include a ferroelectric material, and the second layer 322 may include a high dielectric constant material.

[0085] Figure 13 Another example of capacitors is shown. Figure 11 The cross-section corresponding to the cross-section. (Refer to...) Figure 13 The capacitor may include a conductive layer 350 positioned between the dielectric layer 320 and the second electrode 330. The conductive layer 350 may include, for example, IGZO, but this disclosure is not limited thereto. In this way, when the conductive layer 350 is positioned on a first side of the dielectric layer 320 and the dielectric layer 320 comprises a ferroelectric material, the hysteresis curve of the dielectric layer 320 may be shifted. In this case, the write voltage and read voltage of the ferroelectric memory may be set differently, and the read voltage may be reduced.

[0086] In relation to Figure 1 and Figure 2 In some embodiments of the described semiconductor device, the second electrode 330 surrounding the first electrode 310 is not separate; however, in some embodiments according to this disclosure, the second electrode 330, positioned adjacent to the first electrode 310, may be positioned separately. For example, Figure 14 This illustrates another example of a semiconductor device. Figure 1 The floor plan corresponding to the floor plan. (Refer to...) Figure 14 Except for the first electrode 310 and the adjacent second electrode 330 being separated in the first direction DR1, the semiconductor device and Figure 1 Examples are similar or equivalent. Detailed descriptions of identical components will be omitted. In some embodiments, each of the plurality of second electrodes 330 may include two or more portions spaced apart from each other.

[0087] Furthermore, although the configuration in which the dielectric layer 320 is positioned along the edge of the first electrode 310 has been previously described, in some embodiments the dielectric layer 320 may be positioned along the edge of the second electrode 330.

[0088] Furthermore, although the configuration in which the planar shape of the first electrode 310 is circular has been previously described, this is merely an example, and the planar shape of the first electrode 310 can be quadrilateral or other shapes. For example, Figure 15 This illustrates another example of a semiconductor device. Figure 1 The floor plan corresponding to the floor plan. (Refer to...) Figure 15 Except that the planar shape of the first electrode 310 is quadrilateral, the second electrode 330 adjacent to the first electrode 310 is separated from the first electrode 310 in the first direction DR1, and the dielectric layer 320 is positioned along the first side surface of the second electrode 330, the semiconductor device and Figure 1 Examples are similar or equivalent. Detailed descriptions of identical components will be omitted.

[0089] The following section will describe examples of manufacturing methods for semiconductor devices. Below, a method having the following characteristics will be described: Figure 9 The method of manufacturing a semiconductor device of the shape shown is merely an example, and this disclosure is not limited thereto. For example, it will be understood that aspects of the manufacturing method are applicable to other examples of semiconductor devices described herein.

[0090] Figures 16 to 45 This is a process diagram illustrating an example of a manufacturing process used for semiconductor devices. Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 40 , Figure 42 and Figure 44 It is a floor plan, and Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33, Figure 35 , Figure 37 , Figure 39 , Figure 41 , Figure 43 and Figure 45 They are along Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 , Figure 38 , Figure 40 , Figure 42 and Figure 44 The sectional view taken by line B-B'.

[0091] Reference Figure 16 and Figure 17 First, a bit line BL extending along a first direction DR1 and a word line WL intersecting the bit line BL and extending along a second direction DR2 can be formed on the substrate 110. A first insulating layer 120 can be positioned between the bit line BL and the substrate 110, and a second insulating layer 122 can be positioned between the bit line BL and the word line WL. A semiconductor pattern 150 can be formed at the intersection of the bit line BL and the word line WL. The semiconductor pattern 150 can be positioned to be surrounded by the word line WL, and a gate insulating layer Gox can be positioned between the semiconductor pattern 150 and the word line WL. The descriptions of the substrate 110, bit line BL, word line WL, semiconductor pattern 150, gate insulating layer Gox, first insulating layer 120, and second insulating layer 122 are the same as those provided above and are therefore omitted here.

[0092] Next, refer to Figure 18 and Figure 19 Interlayer insulating layer 130 and sacrificial layer 400 may be stacked alternately. Interlayer insulating layer 130 may include silicon oxide and / or silicon nitride, but this disclosure is not limited thereto. Sacrificial layer 400 and interlayer insulating layer 130 may include different materials. Sacrificial layer 400 and interlayer insulating layer 130 may include materials with etch selectivity, so that sacrificial layer 400 may be selectively etched in subsequent processes.

[0093] The sacrificial layer 400 can be the region where the second electrode 330 will subsequently be formed, and the thickness of the sacrificial layer 400 can vary between layers. Figure 19 As shown, the thickness H1 of the sacrificial layer 400 located in the first layer closest to the substrate 110 can be the thickest, and the thickness of the sacrificial layer 400 can become thinner as the sacrificial layer 400 moves away from the substrate 110. For ease of illustration, Figure 19The diagram shows three sacrificial layers 400, and... Figure 19 The thickness of the sacrificial layer 400 can be such that H1 > H2 > H3. In some embodiments, when the sacrificial layers 400 are stacked as N layers, the thickness of each sacrificial layer can be such that H1 > H2 > H3 ... > HN. However, this is only an example, and for example, in some embodiments, as described above, the sacrificial layers can include multiple groups, and the thickness of the sacrificial layers can be different for each group. In some embodiments (e.g., even when multiple groups with a common thickness are included), the thickness of the sacrificial layer included in the group located closest to the substrate 110 can be the thickest, and the thickness of the sacrificial layer included in the group located furthest from the substrate 110 can be the thinnest.

[0094] Next, refer to Figure 20 and Figure 21 The first via OP1 can be formed as a stack extending through the interlayer insulating layer 130 and the sacrificial layer 400. The first via OP1 can be formed as a stack on the third-direction DR3 with the semiconductor pattern 150, and by forming the first via OP1, the stack of the interlayer insulating layer 130 and the sacrificial layer 400 located on the upper surface of the semiconductor pattern 150 can be removed, thereby exposing the semiconductor pattern 150. As previously described, during the formation process of the first via OP1, the etching process can cause a difference between the diameter R2 at the upper surface farther from the substrate 110 and the diameter R1 at the lower surface adjacent to the substrate 110. For example, the diameter R2 at the upper surface farthest from the substrate 110 can be larger than the diameter R1 at the lower surface adjacent to the substrate 110.

[0095] Next, refer to the following: Figure 22 and Figure 23 A portion of the etchable sacrificial layer 400. Figure 22 In the image, the etched sacrificial layer 400 is shown by dashed lines, which also indicate the recessed portion that extends inward into the interlayer insulating layer 130. (See image for details.) Figure 23 As shown, a portion of the sacrificial layer 400 can be etched to form void spaces between the interlayer insulating layers 130. In this case, an etchant with etch selectivity for the sacrificial layer 400 can be used to perform the etching. Therefore, the interlayer insulating layer 130 can be left unetched in this operation.

[0096] Next, refer to Figure 24 and Figure 25 A second electrode 330 can be formed. The second electrode 330 can be positioned on the bottom and side surfaces of the first hole OP1, and on the upper surface of the stack of the interlayer insulating layer 130 and the sacrificial layer 400. For example... Figure 25As shown, the second electrode 330 can be used to cover the side surfaces of the interlayer insulating layer 130 and the sacrificial layer 400. The second electrode 330 may include a conductive material. The second electrode 330 may include at least one of, for example, a metallic material, a conductive metal nitride, and a doped semiconductor material.

[0097] Next, refer to Figure 26 and Figure 27 The second electrode 330, positioned on the uppermost surface of the stack of interlayer insulating layer 130 and sacrificial layer 400, is removed, and a sacrificial pattern 410 is formed in the empty space between the interlayer insulating layer 130. The sacrificial pattern 410 may be formed to fill a portion of the space where the sacrificial layer 400 was previously etched. The sacrificial pattern 410 may include an insulating material. For example, the sacrificial pattern 410 may include silicon nitride or silicon oxide. Figure 27 As shown, by forming a sacrificial pattern 410, a portion of the second electrode 330 can be covered by the sacrificial pattern 410.

[0098] Next, refer to Figure 28 and Figure 29 The second electrode 330, positioned on the side and bottom surfaces of the first hole OP1, can be removed. However, the second electrode 330 formed in the space between the interlayer insulating layers 130 can be covered by the sacrificial pattern 410 and may not be removed during this operation. Therefore, as Figure 29 As shown, the second electrode 330 can be divided into multiple sections along the first direction DR1 and the third direction DR3. This can then be used to construct each capacitor.

[0099] Next, refer to Figure 30 and Figure 31 This can remove the sacrifice pattern 410. Figure 30 In the middle, the area where the sacrificial pattern 410 is removed and an empty space is formed is shown by dashed lines.

[0100] Next, refer to Figure 32 and Figure 33 The interlayer insulating layer 130 can be partially etched. In this case, refer to... Figure 33 The previously formed second electrode 330 can be exposed by etching the interlayer insulating layer 130. By etching the interlayer insulating layer 130 in this operation, the edges of the interlayer insulating layer 130 and the edges of the sacrificial layer 400 can be aligned.

[0101] Next, refer to Figure 34 and Figure 35 A dielectric layer 320 can be formed. The dielectric layer 320 may include at least one of a high-dielectric material, a ferroelectric material, and an antiferroelectric material. The dielectric layer 320 may be formed along the side surface of the first hole OP1. For example... Figure 34As shown, the dielectric layer 320 may be formed to cover the side surface of the interlayer insulating layer 130 and the second electrode 330. In previous operations, the second electrode 330 may include a portion protruding in the first direction DR1, and the dielectric layer 320 may also be formed to cover the front surface of the protruding second electrode 330.

[0102] Next, refer to Figure 36 and Figure 37 A first electrode 310 may be formed inside the first hole OP1. The first electrode 310 may be formed to completely fill the interior of the first hole OP1. The first electrode 310 may include a conductive material. The first electrode 310 may include at least one of, for example, a metallic material, a conductive metal nitride, and a doped semiconductor material.

[0103] Next, refer to Figure 38 and Figure 39 The second hole OP2 can be formed as a stack extending through the interlayer insulating layer 130 and the sacrificial layer 400. In this case, the second hole OP2 can be formed in a region that does not overlap with the semiconductor pattern 150. The side surfaces of the interlayer insulating layer 130 and the sacrificial layer 400 can be exposed by forming the second hole OP2.

[0104] Next, refer to Figure 40 and Figure 41 The sacrificial layer 400 can be removed through the second hole OP2. As described above, the sacrificial layer 400 and the interlayer insulating layer 130 have etch selectivity, so only the sacrificial layer 400 can be selectively removed. Therefore, as Figure 41 As shown, empty spaces can be formed between the interlayer insulating layers 130. The second electrode 330 formed in the previous operation can be exposed by removing the sacrificial layer 400.

[0105] Reference Figure 42 and Figure 43 A second electrode 330 is formed in the space where the sacrificial layer 400 has been removed. In some embodiments, the second electrode 330 formed in this operation comprises the same material as the second electrode 330 formed in the previous operation, so that the boundary between the second electrode 330 formed in this operation and the second electrode 330 formed in the previous operation may not be identifiable.

[0106] Reference Figure 44 and Figure 45The second hole OP2 can be filled with the same material as the interlayer insulating layer 130 formed in the previous operation. When the material filling the second hole OP2 includes the same material as the interlayer insulating layer 130 formed in the previous operation, the boundary between the interlayer insulating layer 130 filling the second hole OP2 and the interlayer insulating layer 130 formed in the previous operation may not be visible. However, this is only an example, and when the material filling the second hole OP2 is a different material from the interlayer insulating layer 130, the boundary can be identified.

[0107] While this disclosure contains numerous details of specific implementations, these details should not be construed as limiting the scope of the claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, in some cases one or more features from the combination may be removed from that combination, and the combination may involve sub-combinations or variations thereof.

[0108] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Base; Bit lines and word lines extend on the base in their respective intersecting directions; Semiconductor patterns are electrically connected to bit lines; A first electrode extends in a first direction perpendicular to the surface of the substrate, wherein the first electrode is electrically connected to a semiconductor pattern. Multiple second electrodes, spaced apart along a first direction; and A dielectric layer is located between the first electrode and the plurality of second electrodes. The first electrode, the plurality of second electrodes, and the dielectric layer are configured to form a plurality of data storage devices. The area of ​​the plane parallel to the surface of the substrate of the first electrode increases with the distance from the substrate. The plurality of second electrodes includes a lower electrode and an upper electrode. The distance between the upper electrode and the substrate is greater than the distance between the lower electrode and the substrate. The thickness of the lower electrode in the first direction is greater than that of the upper electrode in the first direction.

2. The semiconductor device according to claim 1, wherein, The width of the lower surface of the first electrode in a second direction parallel to the surface of the substrate is smaller than the width of the upper surface of the first electrode in the second direction, and The distance between the lower surface of the first electrode and the substrate is smaller than the distance between the upper surface of the first electrode and the substrate.

3. The semiconductor device according to claim 1, wherein, The first electrode includes: The first part extends in the first direction; and Multiple second portions protrude from the first portion in a second direction parallel to the surface of the substrate. The dielectric layer extends along the first portion and the plurality of second portions.

4. The semiconductor device according to claim 3, wherein, The plurality of second portions are respectively stacked with the plurality of second electrodes along the second direction.

5. The semiconductor device according to claim 3, wherein: The first group of the plurality of second parts is stacked with one group of the plurality of second electrodes along the second direction, and The second group of the plurality of second parts does not overlap with the plurality of second electrodes.

6. The semiconductor device according to claim 1, wherein: The first electrode includes a recessed portion, wherein the planar area of ​​the recessed portion parallel to the surface of the substrate changes with increasing distance from the substrate, and The recessed portion is positioned adjacent to one of the plurality of second electrodes.

7. The semiconductor device according to claim 1, wherein, The first electrode comprises a first material. The plurality of second electrodes include a second material, and The first material and the second material have different work functions.

8. The semiconductor device according to claim 1, further comprising: A conductive layer is positioned between the first electrode and the dielectric layer.

9. The semiconductor device according to claim 1, wherein, The dielectric layer has a multilayer structure comprising ferroelectric materials and high dielectric constant materials, wherein the ferroelectric materials and high dielectric constant materials are alternately stacked in the dielectric layer.

10. The semiconductor device according to claim 1, wherein, The plurality of second electrodes surround the first electrode in the plan view.

11. The semiconductor device according to claim 1, wherein, Each of the plurality of second electrodes includes: Part One, and The second part is separated from the first part.

12. A semiconductor device, comprising: Base; Bit lines and word lines extend on the base in their respective intersecting directions; Semiconductor patterns are electrically connected to bit lines; The first electrode extends in a first direction perpendicular to the surface of the substrate; Multiple second electrodes are spaced apart along a first direction; as well as A dielectric layer is located between the first electrode and the plurality of second electrodes. The first electrode, the plurality of second electrodes, and the dielectric layer are configured to form a plurality of data storage devices. The area of ​​the plane parallel to the surface of the substrate of the first electrode increases with the distance from the substrate. The plurality of second electrodes include: The first group of second electrodes has a first thickness in a first direction; and The second group of second electrodes has a second thickness in the first direction. The first thickness is greater than the second thickness, and The first group of second electrodes is positioned closer to the substrate than the second group of second electrodes.

13. The semiconductor device according to claim 12, wherein, The width of the lower surface of the first electrode in a second direction parallel to the surface of the substrate is smaller than the width of the upper surface of the first electrode in the second direction, and The distance between the lower surface of the first electrode and the substrate is smaller than the distance between the upper surface of the first electrode and the substrate.

14. The semiconductor device according to claim 12, wherein, The first electrode includes: The first part extends in the first direction; and Multiple second portions protrude from the first portion in a second direction parallel to the surface of the substrate. The dielectric layer extends along the first portion and the plurality of second portions.

15. The semiconductor device according to claim 12, wherein: The first electrode includes a recessed portion, wherein the planar area of ​​the recessed portion parallel to the surface of the substrate changes with increasing distance from the substrate, and The recessed portion is positioned adjacent to one of the plurality of second electrodes.

16. The semiconductor device according to claim 12, wherein, The first electrode comprises a first material. The plurality of second electrodes include a second material, and The first material and the second material have different work functions.

17. The semiconductor device according to claim 12, wherein, The dielectric layer has a multilayer structure comprising ferroelectric materials and high dielectric constant materials, wherein the ferroelectric materials and high dielectric constant materials are alternately stacked in the dielectric layer.

18. A semiconductor device, comprising: Base; Bit lines and word lines extend on the base in their respective intersecting directions; Semiconductor patterns are electrically connected to bit lines; The first electrode extends in a first direction perpendicular to the surface of the substrate; Multiple second electrodes are spaced apart along a first direction; as well as A dielectric layer is located between the first electrode and the plurality of second electrodes. The first electrode, the plurality of second electrodes, and the dielectric layer are configured to form a plurality of data storage devices. Wherein, the width of the lower surface of the first electrode in a second direction parallel to the surface of the substrate is smaller than the width of the upper surface of the first electrode in the second direction. Wherein, the distance between the lower surface of the first electrode and the substrate is smaller than the distance between the upper surface of the first electrode and the substrate, and The thickness of the second electrode closest to the substrate among the plurality of second electrodes is greater than the thickness of the second electrode furthest from the substrate among the plurality of second electrodes.

19. The semiconductor device according to claim 18, wherein, The area of ​​the plane parallel to the surface of the substrate of the first electrode increases with the distance from the substrate.

20. The semiconductor device according to claim 18, wherein, The thickness of each of the plurality of second electrodes in the first direction increases as the distance of the second electrode from the substrate decreases.

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