A solid state disk fault-aware read optimization and code length adaptation method and device

Abstract

The application belongs to the technical field of solid-state storage, and specifically discloses a solid-state disk fault-aware reading optimization and code length self-adaption method and device, which comprises the following steps: a fault-aware re-reading mechanism is constructed, a code word that fails to be decoded in a primary decoding round is marked, and only the marked failed code word is transmitted in a subsequent re-reading round; based on the fault-aware re-reading mechanism, the delay of hard-decision decoding and the delay of soft-decision decoding are analyzed and combined to obtain a fault-aware reading delay model; the fault-aware reading delay model comprises a default reading operation delay model and a soft-decision reading operation delay model; when reading data, a reading mode determination result is obtained based on the fault-aware reading delay model; when writing data, a target code length in the case of the shortest reading delay is obtained based on the fault-aware reading delay model; and the target code length is used to write data. Through the application, the reading performance of an SSD can be improved under the condition that the code rate remains unchanged.

Description

Technical Field

[0001] This application belongs to the field of solid-state storage technology, and more specifically, relates to a method and apparatus for solid-state hard disk fault detection reading optimization and code length adaptation. Background Technology

[0002] Flash-based solid-state drives (SSDs) have become widely used in various scenarios such as mobile devices, laptops, storage servers, and data centers due to their advantages of low latency, high energy efficiency, and small size. To further improve storage density, modern SSDs generally adopt advanced technologies such as multi-layer cell design and 3D stacking, but these technologies also lead to a significant increase in the raw bit error rate (RBER). To ensure storage reliability, SSDs need to use error-correcting codes (ECC), which add redundant parity bits to the user data and generate codewords at a fixed code rate (i.e., the ratio of user data bits to the total number of bits in each codeword) to correct a limited number of bit errors.

[0003] In practical applications, the Regression Percentage (RBER) of SSDs fluctuates due to various factors: repeated programming / erasing gradually wears down flash memory cells, causing the RBER to increase with usage time; simultaneously, there are differences in RBER between different pages and between vertical layers of 3D NAND flash memory. To cope with dynamically changing RBER and ensure reliability, existing solutions mainly fall into two categories: one is to reserve sufficient parity bits to cope with high RBER in the worst case, but this solution suffers from excessive storage overhead; the other is to adopt an adaptive bitrate adjustment strategy, using high bitrate encoding in low RBER scenarios, but this requires reserving excessive storage space and incurs high cross-page access overhead.

[0004] Improving SSD read performance while maintaining the same bitrate is a pressing technical problem that needs to be solved in this field. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of this application is to improve the read performance of SSD without changing the bit rate.

[0006] To achieve the above objectives, in a first aspect, this application provides a solid-state drive fault-aware read optimization and code length adaptive method, the method comprising: Construct a fault-aware rereading mechanism: Based on all the codewords in the solid-state drive page, mark the codewords that failed to be decoded in the initial decoding round and transmit only the marked failed codewords in subsequent rereading rounds; Based on the fault-aware rereading mechanism, the latency of hard-decision decoding and soft-decision decoding are analyzed and combined to obtain a fault-aware read latency model. This model includes a default read operation latency model and a soft-decision read operation latency model. The default read operation, when using the fault-aware rereading mechanism, first performs hard-decision decoding; if hard-decision decoding fails, then the soft-decision decoding read operation is performed. The soft-decision read operation, when using the fault-aware rereading mechanism, skips hard-decision decoding and only performs the soft-decision decoding read operation. The default read operation latency model is used to estimate the page read latency corresponding to the default read operation, and the soft-decision read operation latency model is used to estimate the page read latency corresponding to the soft-decision read operation. When reading data, based on the fault-aware read latency model, the read mode determination result is obtained by comparing the page read latency corresponding to the default read operation under the raw bit error rate (RBER) of the current page with the page read latency corresponding to the soft decision read operation. When writing data, the target code length is obtained based on the fault-aware read latency model, which minimizes the read latency. The target code length is used to write the data—the user data is encoded with low-density parity-check code (LDPC) using the generator matrix corresponding to the target code length and then written to the solid-state drive page.

[0007] In one possible implementation, the aforementioned fault-aware rereading mechanism includes: In the initial decoding round, all codewords on the solid-state drive page are transmitted to the (fault-aware) decoder and decoded; successfully decoded codewords are cached, and codewords that fail to decode are marked. In subsequent rereading rounds, only the marked failed codewords are transmitted to the (fault-aware) decoder and decoded, until all codewords are successfully decoded.

[0008] In one possible implementation, the default read operation latency model described above obtains the page read latency corresponding to the default read operation, i.e., the default read operation latency, through the following steps: Based on the data read latency, data transmission latency, and data decoding latency of hard-decision decoding, the overall latency of a single hard-decision decoding is obtained by pipelined modeling of codeword transmission and decoding, and is expressed as: ; Where: RBER represents the raw bit error rate; This indicates the overall delay of a single hard-decision decoding; This indicates the data read latency of hard decision reads; This indicates the number of characters on the page; Indicates the data transmission latency of a single codeword read in a hard decision; This represents the data decoding latency of a single codeword read in a hard-decision read; It means exactly makes The critical value of RBER at that time; Based on the overall latency of a single hard-decision decoding and the (expected) latency of soft-decision decoding for each failed codeword, the default read operation latency (the page read latency corresponding to the default read operation) is obtained by summing the two, and is expressed as: ; in: Indicates the default read operation latency; express After hard decoding, the codeword exactly has The probability of codeword decoding failure; express The delay in soft-decision decoding of each codeword.

[0009] In one possible implementation, the above soft-decision read operation latency model obtains the page read latency corresponding to the soft-decision read operation, i.e., the soft-decision read operation latency, through the following steps: Based on the data read latency, data transmission latency, and data decoding latency of soft-decision reads, the soft-decision read operation latency (the page read latency corresponding to the soft-decision read operation) is obtained by pipelined modeling of codeword transmission and codeword decoding, and is expressed as: ; in: RBER represents the latency of the soft-decision read operation; RBER represents the raw bit error rate. This indicates the number of characters on the page; This indicates the data read latency of soft-decision reads; Indicates the data transmission latency of a single codeword read by a soft decision; This represents the data decoding latency of a single codeword read in a soft-decision read; It means exactly makes The critical value of RBER at that time.

[0010] In one possible implementation, the above-mentioned determination of the reading method includes: If the page read latency corresponding to the default read operation is not greater than the page read latency corresponding to the soft-decision read operation, the read method determination result is to use the default read operation to read data; otherwise, the read method determination result is to use the soft-decision read operation to read data.

[0011] In one possible implementation, the above-mentioned target code length for the shortest read latency case based on the fault-aware read latency model includes: Based on the fault-aware read latency model, the target code length with the shortest read latency is obtained by estimating and sorting the page read latency corresponding to each candidate code length under the original bit error rate of the current page.

[0012] Secondly, this application also provides a solid-state drive fault-aware read optimization and code length adaptive device, comprising: The reread mechanism construction module is used to build a fault-aware reread mechanism: based on all the codewords on the solid-state drive page, the codewords that failed to be decoded in the initial decoding round are marked and only the marked failed codewords are transmitted in subsequent reread rounds; The latency model acquisition module is used to analyze and jointly perform the latency of hard-decision decoding and soft-decision decoding based on the fault-aware rereading mechanism to obtain a fault-aware read latency model. The fault-aware read latency model includes a default read operation latency model and a soft-decision read operation latency model. The default read operation, when using the fault-aware rereading mechanism, first performs hard-decision decoding; if hard-decision decoding fails, then the soft-decision decoding read operation is performed. The soft-decision read operation, when using the fault-aware rereading mechanism, directly skips hard-decision decoding and only performs the soft-decision decoding read operation. The default read operation latency model is used to estimate the page read latency corresponding to the default read operation, and the soft-decision read operation latency model is used to estimate the page read latency corresponding to the soft-decision read operation. The reading module is used to obtain the reading method determination result by comparing the page reading delay corresponding to the default reading operation and the page reading delay corresponding to the soft decision reading operation under the original bit error rate of the current page, based on the fault-aware reading delay model. The write module is used to obtain the target code length with the shortest read latency based on the fault-aware read latency model when writing data; and to write data using the target code length.

[0013] Thirdly, this application provides an electronic device, including: a memory and one or more processors; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions; the one or more processors invoke the computer instructions to cause the electronic device to perform the method described in the first aspect or any possible implementation of the first aspect.

[0014] Fourthly, this application provides a computer-readable storage medium including instructions that, when executed on an electronic device, cause the electronic device to perform the method described in the first aspect or any possible implementation thereof.

[0015] Fifthly, this application provides a computer program product, including a computer program or instructions that, when run on an electronic device, cause the electronic device to perform the method described in the first aspect or any possible implementation thereof.

[0016] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: Under a fixed code rate, there is an inherent trade-off between error correction capability and read latency for low-density parity-check codes (LDPC) of different code lengths—the longer the code length, the stronger the error correction capability but the higher the read latency; the shorter the code length, the lower the read latency but the relatively limited error correction capability. In the write phase, this method predicts the expected read latency for each candidate codeword based on the raw bit error rate (RBER) of the current SSD page using a fault-aware read latency model, and selects the target codeword with the lowest latency for LDPC encoding and writing. This prioritizes short codewords for low-latency reads in low-RBER scenarios and switches to long codewords to ensure error correction reliability in high-RBER scenarios. The entire process only changes the codeword length, not the code rate, thus maintaining the same storage redundancy, requiring no additional reserved storage space, and avoiding cross-page access overhead. In the read phase, a fault-aware reread mechanism transmits only codewords that failed to decode in each reread round, rather than all codewords, effectively reducing unnecessary data transfer and decoding overhead. It can also dynamically determine whether to skip hard-decision decoding and directly enter soft-decision decoding based on a comparison between the page read latency corresponding to the default read operation and the page read latency corresponding to the soft-decision read operation, avoiding the latency caused by high-failure-rate hard-decision decoding in high-error-rate scenarios. The coordinated optimization of the above two paths of read and write together achieves an improvement in SSD read performance under the conditions of fixed code rate and unchanged storage redundancy. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the solid-state drive fault-aware reading optimization and code length adaptive method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the fault perception rereading mechanism provided in the embodiments of this application; Figure 3 This is a schematic diagram of pipelined modeling of a single decoding operation provided in an embodiment of this application; Figure 4 This is a graph showing the relationship between the number of decoding iterations and RBER for hard-decision decoding and soft-decision decoding provided in the embodiments of this application; Figure 5 This is a graph showing the relationship between the fault perception reading latency model and RBER provided in the embodiments of this application; Figure 6This is an example diagram provided in this application embodiment of integrating LDPC code encoding and decoding, fault perception mechanism and fault perception read delay model into the SSD simulator MQSim; Figure 7 This is a schematic diagram of the solid-state drive fault detection, read optimization, and code length adaptive device provided in this application embodiment; Figure 8 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0018] To facilitate a clearer understanding of the various embodiments of this application, some relevant background knowledge will be introduced as follows.

[0019] In LDPC (Low-Density Parity-Check) based SSD controllers, user data needs to be LDPC encoded during the write process, and all data on a single SSD page needs to be hard-decision decoded and soft-decision decoded for error correction during the read process. Existing ECC designs designed for the worst-case RBER of SSDs introduce significant redundancy overhead, while ECC designs with adaptive bitrate adjustment require additional storage space and incur cross-page access overhead, leading to increased redundant data overhead and latency.

[0020] Research has found that, under a fixed code rate, there is a trade-off between read performance and error correction capability for ECC with different code lengths (i.e., the total number of user data and parity bits per codeword): longer codewords provide higher reliability, while shorter codewords achieve lower read latency. This means that in low RBER scenarios, short codewords can be used to pursue high performance, while when the RBER increases due to increased SSD usage time, a switch to longer codewords can be made to ensure reliability. Based on this finding, this application proposes an adaptive code length conversion framework, which dynamically optimizes the read scheme and code length for a single SSD page to achieve low-latency reads while maintaining reliability and fixed storage overhead.

[0021] The purpose of this application is to provide a method and apparatus for solid-state drive (SSD) fault-aware read optimization and code length adaptation. Through a dual mechanism of read strategy optimization and write strategy optimization, the code length is changed while keeping the code rate constant, thus maintaining redundancy and reliability, which can effectively improve the read performance of SSD.

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0025] The embodiments of this application are described below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, the overall architecture of the fault-aware read optimization and code length adaptive scheme proposed in this application includes three core mechanisms: fault-aware reread mechanism, fault-aware decoding mechanism, and adaptive code length selection mechanism. These three mechanisms are deployed in concert in the SSD controller to achieve systematic optimization of read latency.

[0027] On the read path, the fault-aware reread mechanism is responsible for transmitting all codewords of the page to the fault-aware decoder and performing decoding in the initial decoding round of each page read. It then caches successfully decoded codewords and marks those that failed. In subsequent reread rounds, it still detects all codewords of pages that failed to decode, but only transmits the marked failed codewords to the decoder and performs decoding, thus effectively reducing unnecessary data transfer and decoding overhead during rereads. The fault-aware decoding mechanism, based on the raw bit error rate (RBER) of the current SSD page, calls the fault-aware read latency model to determine if a threshold is exceeded: if the threshold is not exceeded, a regular read is used (hard-decision decoding is performed first, and soft-decision decoding is performed after hard-decision decoding fails); if the threshold is exceeded, a bypass read is used (hard-decision decoding is skipped directly, and soft-decision decoding is performed for rereading), thus avoiding the time consumed by invalid hard-decision decoding.

[0028] On the write path, the adaptive code length selection mechanism, before data writing, calls the fault-aware read latency model based on the current SSD page's RBER to predict the expected read latency of each candidate code length (including 1-KiB, 2-KiB, 4-KiB, and 8-KiB, etc.) on that page. It then selects the optimal code length according to the principle of minimizing read latency, guiding the latency-aware encoder to use the corresponding generator matrix to perform LDPC encoding on the user data before writing it to the SSD page. This achieves low latency in subsequent page read stages while maintaining a fixed code rate and unchanged storage redundancy. The above three mechanisms were simulated and verified in the SSD simulator MQSim by integrating an LDPC code encoder and decoder, an error injector, and pipelined encoding and decoding operations.

[0029] The goal of the fault-aware rereading mechanism proposed in this application is to reduce unnecessary data transmission and decoding delays during page data reading.

[0030] like Figure 2 As shown, taking four 4KiB codewords (4KiB in length) on a 16KiB page as an example, the fault-aware rereading mechanism includes the following steps: The controller issues a command to read all four code characters on the page; Perceive all data on the page; Transmit 4 codewords to the fault detection decoder; Decode 4 codewords; Based on the decoding results, cache the 3 codewords that were successfully decoded and mark the 1 codeword that failed to be decoded; The controller issues a command to read the codeword that was marked as failing; Perceive all data on the page; Transmit one codeword of the transmission tag to the fault-aware decoder; Decode one codeword; Based on the decoding result, retrieve the successfully decoded codeword and end the reading operation.

[0031] This application models the read operation after adopting the fault-aware reread mechanism, and the specific steps are as follows.

[0032] Step 1: Establish a read latency model.

[0033] For a capacity of A single SSD page, if using Then the number of characters on the page . This indicates the number of bits (i.e., code length) of a single codeword in the page. This indicates the number of parity bits for a single codeword on the page. ECC stands for Error Correction Code. The latency of a single page read consists of three parts: (1) Data read delay: the time required to sense the original data by applying a reference voltage to the storage unit; (2) Data transmission delay, the time required for raw data to be transmitted from the storage chip to the decoder; (3) Data decoding delay: the time required for the decoder to perform the decoding algorithm on the original data.

[0034] Step 1.1: Establish a latency model for hard-decision read operations (or hard-decision decoding). The data read latency of hard-decision reads is determined by... This indicates that the data transmission delay of a single codeword read by a hard decision is caused by... This indicates that the data decoding latency of a single codeword read by a hard decision is due to It indicates. Among them. It increases with the increase of RBER. Considering the pipelined design of codeword transmission and codeword decoding, the overall latency is as follows: Figure 3 As shown, there are two possible scenarios: Scenario 1: When At this time, the data decoding delay is lower than the data transmission delay, and the overall delay variation is determined by the sequential transmission time of the codewords; Scenario 2: When At this time, the data decoding delay is higher than the data transmission delay, and the overall delay variation is determined by the sequential decoding time of the codewords.

[0035] make To just make Given the RBER value at that time, the latency of a single hard-decision decoding (including data read latency, data transmission latency, and data hard decoding latency) can be expressed as: (1); in: The overall delay of a single hard-decision decoding; Data read latency for hard decision reads; The number of characters on the page; The data transmission latency of a single codeword read by hard decision; : Data decoding latency of a single codeword read by hard decision (increases with RBER); Just enough to make The critical value of RBER at that time.

[0036] Step 1.2: Determine the critical point (1) In the formula Depend on and Decide. It is obtained by multiplying the average number of iterations by the decoding delay of a single iteration of data read by hard decision. The channel throughput is determined by the hardware configuration. The average number of iterations mentioned above, obtained from actual hard-decision decoding tests, is related to the RBER as follows: Figure 4 The curve shown on the left side of the middle (1) represents the hard-decision decoding data, involving lengths of 1-KiB, 2-KiB, 4-KiB, and 8-KiB (code length). The single-iteration data decoding latency of the above hard-decision reads is determined by the hardware configuration.

[0037] Step 1.3: Establish a delay model for the soft-decision read operation (or soft-decision decoding). After the hard-decision read, the number of codewords that need to be processed in the soft-decision read stage is reduced from... This indicates that the data read latency for soft-decision reads is due to... This indicates that the data transmission delay of a single codeword read by soft decision is caused by... This indicates that the data decoding latency of a single codeword read by the soft decision is due to This indicates that, similar to hard-decision decoding, it allows... To just make Given the RBER value at that time, the latency of a single soft-decision decoding (including data read latency, data transmission latency, and data soft decoding latency) can be expressed as: (2); in: The overall delay of a single soft-decision decoding; The number of codewords that need to be processed in the soft decision reading stage after hard decision reading ( ); Data read latency for soft-decision reads; The data transmission delay of a single codeword read by soft decision; The data decoding latency of a single codeword read by soft decision; Just enough to make The critical value of RBER at that time.

[0038] Step 1.4: Determine the critical point (2) In the formula Depend on and Decide. It is obtained by multiplying the average number of iterations by the decoding delay of a single iteration of data read by the soft decision. The channel throughput is determined by the hardware configuration. The average number of iterations mentioned above, obtained from actual soft-decision decoding tests, is related to the RBER as follows: Figure 4 The curve shown on the right side of (2) represents the soft-decision decoding data, involving lengths of 1-KiB, 2-KiB, 4-KiB, and 8-KiB (code length). The single-iteration data decoding delay of the aforementioned soft-decision reads is determined by the hardware configuration.

[0039] Step 2: Establish a fault-aware read latency model. The fault-aware read latency model of this application consists of two parts: Part 1, the default read operation latency model, which first performs hard-decision decoding, and if the hard-decision decoding fails, it performs soft-decision decoding; Part 2, the soft-decision read operation latency model, which only performs soft-decision decoding, that is, it directly skips the hard-decision decoding process.

[0040] Step 2.1: Establish the default read operation latency model. After hard-decision decoding of n codewords, there are... The probability of codeword decoding failure is determined by This indicates that (in the case of a fault-aware rereading mechanism, only the decoding failure is retransmitted) (If there are n codewords, the existing retransmission mechanism retransmits n codewords). Therefore, the default read operation latency is obtained by adding the latency of hard-decision decoding to the expected latency of soft-decision decoding of codewords that failed hard-decision decoding. It can be represented as: (3); in: : Default read operation latency (expected total latency of hard-decision decoding followed by soft-decision decoding if it fails). : Overall delay of single hard decision decoding (calculated by equation (1)); After hard-decoding n codewords, exactly one of them has The probability of codeword decoding failure; : The delay of soft decision decoding of each codeword (calculated by equation (2)).

[0041] Step 2.2: Combine the default read operation latency model with the aforementioned soft-decision read operation latency model (only performing soft-decision decoding). The latency model that only performs soft-decision decoding can be directly derived from... Indicate. Order To just make The RBER value at that time indicates the read operation latency of the jointly optimized fault-aware read latency model. It can be represented as: (4); in: Fault-aware read latency model (jointly optimized read latency); : Default read operation latency (calculated by equation (3)); The delay is only for performing soft-decision decoding operations; Just enough to make The RBER threshold (the threshold that determines whether to skip hard-decision decoding).

[0042] Step 2.3: Determine the critical point First, estimate based on the binomial distribution. The value is represented as Where f is obtained from the actual hard-decision decoding test and its relationship with RBER, such as Figure 5 As shown. This probability is used to calculate ,therefore Depend on and The intersection point is used to determine this.

[0043] This application uses a read latency model optimized by a fault-aware rereading mechanism (i.e., the aforementioned fault-aware read latency model) to perform fault-aware decoding manipulation and optimal code length selection operations. The implementation process of each module is as follows: Figure 6 As shown, the delay-aware encoder calls the delay model and error model before writing data and selects the optimal code length for encoding; the fault-aware decoder calls the delay model and error model before reading data to determine whether to skip hard decoding and directly perform soft decoding, and caches successfully decoded codewords after data decoding, and marks failed decoded codewords for the next round of reading; the error injector calls the error model to inject noise data into the original data before the data is read to the fault-aware decoder, simulating the original bit errors in the flash memory. Figure 6 In the text, COLA stands for Code Length Adaptation, and FTL stands for Flash Translation Layer.

[0044] The specific steps include: RBER prediction, read delay prediction, execution of read commands, write operations, and selection of optimal code length based on the results determined in the aforementioned steps (whether to skip the hard decision decoding process).

[0045] RBER prediction. Based on the physical address of the page being written to / read from, the error model is invoked to calculate the RBER size.

[0046] This application integrates a code length conversion encoder, a fault-aware decoder, and an error injector for simulating errors into the SSD simulator MQSim to simulate real SSD read and write operations.

[0047] Error Injector (used to simulate error generation): Used to simulate errors in the raw data read from the flash memory chip. It generates errors based on existing error models and an additive white Gaussian noise (AWGN) model. It predicts the Restricted Bit Rate (RBER) based on SSD statistics and halves the RBER on each retry. The error model is as follows (A represents the number of P / E cycles, B represents the data retention time, and C represents the number of reads): (5); in: Raw bit error rate; : Basic error rate constant; : P / E Cycles Influence Coefficient; : Number of P / E Cycles; The exponential parameter of P / E Cycles; : Data retention time impact coefficient; Data retention time; , : The exponential parameter of P / E Cycles and the data retention time term; : Influence coefficient of the number of reads; Number of reads; , : The exponential parameter of P / E Cycles and the number of reads; , , , , , , , All of these are preset parameters.

[0048] Read latency prediction. If it is a read command, the read latency under the default read operation is calculated based on the RBER size, and the latency under the soft-decision read operation is calculated and compared to determine whether to skip the hard-decision decoding stage; if it is a write command, the fault-aware read latency model is called to calculate the read latency of each candidate code length under the current RBER based on the RBER size, sort them, and determine the code length with the smallest read latency as the optimal one. The read latency is calculated by the above formula (4).

[0049] Execute the read command based on the result determined in the aforementioned steps (whether to skip the hard decision decoding step).

[0050] For data queried from the backend, errors are first simulated using an error injector, and then the generated raw data is sent to the fault-aware decoder for error correction. Under normal circumstances, if hard-decision decoding is successful, the corrected user data will be cached in the data cache manager and returned to the host interface; otherwise, soft-decision decoding will be performed. After fault-aware rereading, the conversion node will be determined using the above formula (4), and the reading method will be selected.

[0051] Write operations and optimal code length selection. Before data transmission begins, write requests are redirected to the delay-aware encoder. The encoder adjusts the data size and, based on the optimal code length, selects the appropriate parity check matrix to obtain the generator matrix. It then expands the information bits into codewords containing parity bits before data transmission begins.

[0052] This application significantly reduces read latency by introducing a fault-aware read and decode scheme during the SSD read and write operations, and by combining it with a designed joint read latency model to adaptively adjust the encoding code length and decoding method. This scheme offers advantages such as high portability and strong hardware deployability, and can be widely applied in high-density NAND Flash SSD systems.

[0053] In summary, the solid-state drive fault detection reading optimization and code length adaptive method and apparatus provided in this application have the following beneficial effects.

[0054] By employing fault-aware rereading and fault-aware decoding mechanisms, the latency of single SSD page reads is effectively reduced.

[0055] By introducing a fault-aware read latency model, the page read latency of each ECC code length is accurately predicted, and the optimal code length with the lowest latency is selected, thus achieving the optimal balance between error correction performance and read latency.

[0056] By implementing an adaptive encoding strategy that keeps the bitrate constant but changes the bit length, low storage redundancy and no cross-page access overhead are maintained.

[0057] This solution can be integrated into a general-purpose SSD simulator with low overhead, significantly improving the I / O performance of large-capacity SSDs.

[0058] The solid-state drive fault detection read optimization and code length adaptation device provided in this application is described below. The solid-state drive fault detection read optimization and code length adaptation device described below can be referred to in correspondence with the solid-state drive fault detection read optimization and code length adaptation method described above.

[0059] like Figure 7 As shown, the device includes: a reread mechanism construction module 10, a latency model acquisition module 20, a reading module 30, and a writing module 40.

[0060] The reread mechanism construction module 10 is used to construct a fault-aware reread mechanism: based on all the codewords in the solid-state drive page, the codewords that failed to be decoded in the initial decoding round are marked, and only the marked failed codewords are transmitted in subsequent reread rounds.

[0061] The latency model acquisition module 20 is used to analyze and jointly perform the latency of hard-decision decoding and soft-decision decoding based on the fault-aware rereading mechanism to obtain a fault-aware read latency model. The fault-aware read latency model includes a default read operation latency model and a soft-decision read operation latency model. The default read operation, when using the fault-aware rereading mechanism, first performs hard-decision decoding, and only performs soft-decision decoding if hard-decision decoding fails. The soft-decision read operation, when using the fault-aware rereading mechanism, directly skips hard-decision decoding and only performs soft-decision decoding read operations. The default read operation latency model is used to estimate the page read latency corresponding to the default read operation, and the soft-decision read operation latency model is used to estimate the page read latency corresponding to the soft-decision read operation.

[0062] The reading module 30 is used to obtain the reading method determination result when reading data by comparing the page reading delay corresponding to the default reading operation under the original bit error rate of the current page with the page reading delay corresponding to the soft decision reading operation based on the fault-aware reading delay model.

[0063] The writing module 40 is used to obtain the target code length under the condition of shortest read latency based on the fault-aware read latency model when writing data; and to write data using the target code length.

[0064] It is understood that the detailed functional implementation of each of the above units / modules can be found in the description in the aforementioned method embodiments, and will not be repeated here.

[0065] It should be understood that the above-described device is used to execute the methods in the above embodiments. The implementation principle and technical effect of the corresponding program modules in the device are similar to those described in the above methods. The working process of the device can be referred to the corresponding process in the above methods, and will not be repeated here.

[0066] Based on the methods in the above embodiments, this application provides an electronic device, such as... Figure 8 As shown, the electronic device may include a processor 810, a communications interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 can call logical instructions in the memory 830 to execute the methods in the above embodiments.

[0067] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0068] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0069] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0070] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0071] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0072] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0073] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0074] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for optimizing and adapting code length for fault-aware reading of solid-state drives, characterized in that, include: Construct a fault-aware rereading mechanism: Based on all the codewords in the solid-state drive page, mark the codewords that failed to be decoded in the initial decoding round and transmit only the marked failed codewords in subsequent rereading rounds; Based on the fault-aware rereading mechanism, the latency of hard-decision decoding and soft-decision decoding are analyzed and combined to obtain a fault-aware read latency model. This model includes a default read operation latency model and a soft-decision read operation latency model. The default read operation, when using the fault-aware rereading mechanism, first performs hard-decision decoding; if hard-decision decoding fails, then the soft-decision decoding read operation is performed. The soft-decision read operation, when using the fault-aware rereading mechanism, skips hard-decision decoding and only performs the soft-decision decoding read operation. The default read operation latency model is used to estimate the page read latency corresponding to the default read operation, and the soft-decision read operation latency model is used to estimate the page read latency corresponding to the soft-decision read operation. When reading data, based on the fault-aware read latency model, the read mode determination result is obtained by comparing the page read latency corresponding to the default read operation under the original bit error rate of the current page with the page read latency corresponding to the soft decision read operation. When writing data, the target code length is obtained based on the fault-aware read latency model, which minimizes the read latency; the target code length is then used to write the data.

2. The solid-state drive fault-aware reading optimization and code length adaptive method according to claim 1, characterized in that, The fault-aware rereading mechanism includes: In the initial decoding round, all codewords on the solid-state drive page are transmitted to the decoder and decoded; successfully decoded codewords are cached, and codewords that fail to decode are marked. In subsequent rereading rounds, only the marked failed codewords are transmitted to the decoder and decoded, until all codewords are successfully decoded.

3. The solid-state drive fault-aware reading optimization and code length adaptive method according to claim 1, characterized in that, The default read operation latency model is obtained by following these steps: Based on the data read latency, data transmission latency, and data decoding latency of hard-decision decoding, the overall latency of a single hard-decision decoding is obtained by pipelined modeling of codeword transmission and decoding, and is expressed as: ； Where: RBER represents the raw bit error rate; This indicates the overall delay of a single hard-decision decoding; This indicates the data read latency of hard decision reads; This indicates the number of characters on the page; Indicates the data transmission latency of a single codeword read in a hard decision; This represents the data decoding latency of a single codeword read in a hard-decision read; It means exactly makes The critical value of RBER at that time; Based on the overall latency of a single hard-decision decoding and the latency of soft-decision decoding for each failed codeword, the default read operation latency is obtained by summing the two, and is expressed as: ； in: Indicates the default read operation latency; express After hard decoding, the codeword exactly has The probability of codeword decoding failure; express The delay in soft-decision decoding of each codeword.

4. The solid-state drive fault-aware reading optimization and code length adaptive method according to claim 1, characterized in that, The soft-decision read operation latency model obtains the page read latency corresponding to the soft-decision read operation, i.e., the soft-decision read operation latency, through the following steps: Based on the data reading latency, data transmission latency, and data decoding latency of soft-decision reading, the soft-decision reading operation latency is obtained by pipelined modeling of codeword transmission and codeword decoding, and is expressed as: ； in: RBER represents the latency of the soft-decision read operation; RBER represents the raw bit error rate. This indicates the number of characters on the page; This indicates the data read latency of soft-decision reads; Indicates the data transmission latency of a single codeword read by a soft decision; This represents the data decoding latency of a single codeword read in a soft-decision read; It means exactly makes The critical value of RBER at that time.

5. The solid-state drive fault-aware reading optimization and code length adaptive method according to claim 1, characterized in that, The result of obtaining the reading method determination includes: If the page read latency corresponding to the default read operation is not greater than the page read latency corresponding to the soft-decision read operation, the read method determination result is to use the default read operation to read data; otherwise, the read method determination result is to use the soft-decision read operation to read data.

6. The solid-state drive fault-aware reading optimization and code length adaptive method according to claim 1, characterized in that, The method for obtaining the target code length under the condition of minimum read latency based on the fault-aware read latency model includes: Based on the fault-aware read latency model, the target code length with the shortest read latency is obtained by estimating and sorting the page read latency corresponding to each candidate code length under the original bit error rate of the current page.

7. A solid-state drive fault-aware read optimization and code length adaptive device, characterized in that, include: The reread mechanism construction module is used to build a fault-aware reread mechanism: based on all the codewords on the solid-state drive page, the codewords that failed to be decoded in the initial decoding round are marked and only the marked failed codewords are transmitted in subsequent reread rounds; The latency model acquisition module is used to analyze and jointly perform the latency of hard-decision decoding and soft-decision decoding based on the fault-aware rereading mechanism to obtain a fault-aware read latency model. The fault-aware read latency model includes a default read operation latency model and a soft-decision read operation latency model. The default read operation, when using the fault-aware rereading mechanism, first performs hard-decision decoding; if hard-decision decoding fails, then the soft-decision decoding read operation is performed. The soft-decision read operation, when using the fault-aware rereading mechanism, directly skips hard-decision decoding and only performs the soft-decision decoding read operation. The default read operation latency model is used to estimate the page read latency corresponding to the default read operation, and the soft-decision read operation latency model is used to estimate the page read latency corresponding to the soft-decision read operation. The reading module is used to obtain the reading method determination result by comparing the page reading delay corresponding to the default reading operation and the page reading delay corresponding to the soft decision reading operation under the original bit error rate of the current page, based on the fault-aware reading delay model. The write module is used to obtain the target code length with the shortest read latency based on the fault-aware read latency model when writing data; and to write data using the target code length.

8. An electronic device, characterized in that, include: Memory and one or more processors; The memory is coupled to the one or more processors, and the memory is used to store computer program code, the computer program code including computer instructions; The one or more processors invoke the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-6.

9. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-6.

10. A computer program product, comprising a computer program or instructions, characterized in that: When the computer program or instructions are run on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-6.

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