Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of improving image quality by reducing or minimizing voltage fluctuation of a gate electrode of a driving transistor. The display device includes a substrate, a field effect transistor on the substrate, an oxide-based transistor on a different layer from the field effect transistor and connected to the field effect transistor through a contact hole in an insulating layer, and a pixel electrode on the oxide-based transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0040980 filed in the Korean Intellectual Property Office on March 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device capable of improving image quality. Background Art

[0004] An organic light emitting display device includes a display element whose brightness is changed by electric current, for example, an organic light emitting diode. Utility Model Content

[0005] Aspects and features of embodiments of the present disclosure provide a display device capable of improving image quality by reducing or minimizing voltage fluctuations of a gate electrode of a driving transistor.

[0006] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features described herein. By referring to the detailed description of the present disclosure given below, the above and other aspects and features of the embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs.

[0007] According to one or more embodiments of the present disclosure, a display device includes a substrate, a field effect transistor on the substrate, an oxide-based transistor on a different layer from the field effect transistor and connected to the field effect transistor through a contact hole in an insulating layer, and a pixel electrode on the oxide-based transistor.

[0008] In one or more embodiments, the field effect transistor includes a metal oxide semiconductor field effect transistor (MOSFET).

[0009] In one or more embodiments, the substrate includes a silicon substrate.

[0010] In one or more embodiments, the field effect transistor includes a driving transistor including a gate electrode connected to a first node, a source electrode connected to a driving voltage line, and a drain electrode connected to a second node.

[0011] In one or more embodiments, the field effect transistor further includes an emission control transistor including a gate electrode connected to the emission control line, a source electrode connected to the second node, and a drain electrode connected to the pixel electrode.

[0012] In one or more embodiments, the field effect transistor further includes an initialization transistor including a gate electrode connected to the third gate line, a source electrode connected to the pixel electrode, and a drain electrode connected to the ground.

[0013] In one or more embodiments, the oxide-based transistor includes a switching transistor including a gate electrode connected to a first gate line, a drain electrode connected to a data line, and a source electrode connected to a first node.

[0014] In one or more embodiments, the oxide-based transistor further includes a compensation transistor including a gate electrode connected to the second gate line, a drain electrode connected to the first node, and a source electrode connected to the second node.

[0015] In one or more embodiments, the display device further includes a first capacitor connected between the driving voltage line and the first node.

[0016] In one or more embodiments, the display device further includes a second capacitor connected between the source electrode of the switching transistor and the first node.

[0017] In one or more embodiments, the first capacitor and the second capacitor are on an oxide-based transistor.

[0018] In one or more implementations, the drive transistor includes a dual-gate transistor.

[0019] In one or more embodiments, the field effect transistor includes a P-type transistor.

[0020] In one or more embodiments, the oxide-based transistor includes an N-type transistor.

[0021] In one or more embodiments, the active layer of the oxide-based transistor includes indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0022] In one or more embodiments, the oxide-based transistor is positioned further from the substrate than the field effect transistor.

[0023] In one or more embodiments, the pixel electrode is connected to a field effect transistor.

[0024] In one or more embodiments, the field effect transistor is a dual-gate transistor.

[0025] In one or more embodiments, a field effect transistor overlaps with an oxide-based transistor.

[0026] In the display device according to the present disclosure, the switching transistor and the compensation transistor include an oxide-based active layer (or semiconductor layer). Accordingly, the leakage current of the switching transistor and the compensation transistor (e.g., the leakage current in the on state) can be reduced or minimized. Accordingly, the voltage fluctuation of the node to which the gate electrode of the driving transistor, the source electrode of the switching transistor, and the drain electrode of the compensation transistor are commonly connected can be reduced or minimized, so that the image quality of the display device can be improved.

[0027] The effects, aspects, and features of the present disclosure are not limited to the aforementioned effects, aspects, and features, and various other effects, aspects, and features are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0030] Figure 2 is a cross-sectional view showing a display device according to one or more embodiments;

[0031] Figure 3 is a plan view showing a display unit of a display device according to one or more embodiments;

[0032] Figure 4 is a block diagram showing a display panel and a display driver according to one or more embodiments;

[0033] Figure 5 is a circuit diagram of one pixel of a display device according to one or more embodiments;

[0034] Figure 6 yes Figure 5 A timing diagram of a first gate signal, a second gate signal, a third gate signal, an emission control signal and a data signal;

[0035] Figure 7 is a circuit diagram of one pixel of a display device according to one or more embodiments;

[0036] Figure 8 is a plan view of a transistor of a pixel array according to one or more embodiments;

[0037] Fig. 9 shows a first pattern layer of a pixel according to one or more embodiments;

[0038] Fig.10 shows a second pattern layer of a pixel according to one or more embodiments;

[0039] Fig.11 shows a third pattern layer and a first type contact hole of a pixel according to one or more embodiments;

[0040] Fig.12 shows a fourth pattern layer and a second type contact hole of a pixel according to one or more embodiments;

[0041] Fig.13 shows a fifth pattern layer and a third type contact hole of a pixel according to one or more embodiments;

[0042] Fig.14 shows a sixth pattern layer of a pixel according to one or more embodiments;

[0043] Fig.15 shows a seventh pattern layer and a fourth type contact hole of a pixel according to one or more embodiments;

[0044] Fig.16 An eighth pattern layer and a fifth type contact hole of a pixel according to one or more embodiments are shown;

[0045] Fig.17 shows a ninth pattern layer and a sixth type contact hole of a pixel according to one or more embodiments;

[0046] Fig.18 shows a tenth pattern layer and a seventh type contact hole of a pixel according to one or more embodiments;

[0047] Fig.19 An eleventh pattern layer and an eighth type contact hole of a pixel according to one or more embodiments are shown;

[0048] Fig. 20 Shows Fig. 9 The first pattern layer and Fig.10 a second pattern layer;

[0049] Fig.21 Shows Fig. 9 The first pattern layer, Fig.10 The second pattern layer and Fig.11 a third pattern layer and a first type contact hole;

[0050] Fig. 22 Shows Fig. 9 The first pattern layer, Fig.10 The second pattern layer, Fig.11 The third pattern layer and the first type contact hole and Fig.12 a fourth pattern layer and a second type contact hole;

[0051] Fig.23Shows Fig.12 The fourth pattern layer and Fig.13 a fifth pattern layer and a third type contact hole;

[0052] Fig.24 Shows Fig.13 The fifth pattern layer and Fig.14 A sixth pattern layer;

[0053] Fig.25 Shows Fig.14 The sixth pattern layer and Fig.15 The seventh pattern layer;

[0054] Fig.26 Shows Fig.13 The fifth pattern layer, Fig.14 The sixth pattern layer and Fig.15 a seventh pattern layer and a fourth type contact hole;

[0055] Fig. 27 Shows Fig.15 The seventh pattern layer and Fig.16 an eighth pattern layer and a fifth type contact hole;

[0056] Fig.28 Shows Fig.18 The tenth pattern layer and Fig.19 an eleventh pattern layer and an eighth type contact hole;

[0057] Fig.29A and Fig.29B is along Figures 8 to 28 A cross-sectional view taken along line II';

[0058] Fig.30 is a cross-sectional view showing a structure of a display element according to one or more embodiments;

[0059] Figure 31 to Figure 34 is a cross-sectional view showing a structure of a light emitting element according to one or more embodiments;

[0060] Fig.35 It is shown Fig.33 A cross-sectional view of an example of an organic light emitting diode;

[0061] Fig.36 It is shown Fig.34 A cross-sectional view of an example of an organic light emitting diode;

[0062] Fig.37 is a cross-sectional view showing a structure of a pixel of a display device according to one or more embodiments;

[0063] Fig.38is a diagram showing an example of a virtual reality device including a display device according to one or more embodiments; and

[0064] Fig.39 and Fig.40 It is a diagram for explaining the effects of the present disclosure. DETAILED DESCRIPTION

[0065] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0066] Figure 1 is a perspective view showing a display device 10 according to one or more embodiments.

[0067] Reference Figure 1 The display device 10 may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As another example, the display device 10 may be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD).

[0068] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, the display device 10 may have a planar shape similar to a quadrilateral shape having short sides in the first direction DR1 and long sides in the second direction DR2. An angle at which the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be a right angle or rounded to an appropriate curvature (e.g., a predetermined curvature). The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0069] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0070] The display panel 100 may include a main area MA and a sub area SBA.

[0071] The main area MA may include a display area DA including pixels configured to display an image and a non-display area NDA arranged around the display area DA along an edge or periphery of the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element (e.g., referring to Figure 5 The light-emitting element LEL in the device.

[0072] For example, a self-luminous element (e.g., see Figure 5 The light-emitting element LEL) may include at least one of an organic light-emitting diode (organic LED, OLED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0073] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line and a fan-out line connecting the display driver 200 to the display area DA.

[0074] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, and / or rolled. For example, when the sub-area SBA is bent, the sub-area SBA may bendable in the thickness direction (e.g., the third direction DR3, for example, the substrate SUB of the display device 10 (e.g., the reference direction DR4). Figure 2 ) overlaps with the main area MA in the thickness direction of the display area. The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0075] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines DL (eg, Figure 3 ). The display driver 200 may supply a power voltage to the power line, and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, and / or an ultrasonic bonding method. For example, the display driver 200 may be arranged in the sub-area SBA, and may overlap with the main area MA in the thickness direction (third direction DR3) by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0076] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0077] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense a change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having an appropriate frequency (e.g., a predetermined frequency). The touch driver 400 may calculate whether an input is made and input coordinates based on the change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed by an integrated circuit (IC).

[0078] The power supply unit 500 may be arranged on the circuit board 300 to supply a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to be supplied to the driving voltage line VDL (eg, referring to Figure 3 ), and a common voltage may be generated to be supplied to the light emitting elements LEL of a plurality of pixels (eg, referring to Figure 5 ) A common electrode common to the light emitting elements LEL. For example, the driving voltage may be a high potential voltage for driving the light emitting element LEL, and the common voltage may be a low potential voltage for driving the light emitting element LEL.

[0079] Figure 2 is a cross-sectional view showing a display device 10 according to one or more embodiments.

[0080] Reference Figure 2 , the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a transistor layer TRL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0081] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0082] The transistor layer TRL may be arranged on the substrate SUB. The transistor layer TRL may include a plurality of transistors constituting a pixel circuit of a pixel. The transistor layer TRL may also include a gate line, a data line DL (eg, Figure 3 ), power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines DL, and leads connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0083] The transistor layer TRL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The transistor, gate line, data line DL, and power line of each of the pixels of the transistor layer TRL may be arranged in the display area DA. The gate control line and fan-out line of the transistor layer TRL may be arranged in the non-display area NDA. The lead line of the transistor layer TRL may be arranged in the sub-area SBA.

[0084] The light emitting element layer EMTL may be disposed on the transistor layer TRL. The light emitting element layer EMTL may include a plurality of light emitting elements LEL (eg, referring to FIG. 1 ) in which a pixel electrode, a light emitting layer, and a common electrode are sequentially stacked to emit light. Figure 5 ) and a pixel defining layer defining pixels. A plurality of light emitting elements LEL of the light emitting element layer EMTL may be arranged in the display area DA.

[0085] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives an appropriate voltage (e.g., a predetermined voltage) through the transistor of the transistor layer TRL and the common electrode receives a cathode voltage, holes and electrons may be transmitted to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0086] As another example, the plurality of light emitting elements LEL may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0087] The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL.

[0088] The touch sensing unit TSU may be disposed on the encapsulation layer ENC. The touch sensing unit TSU may include a plurality of touch electrodes for capacitively sensing a user's touch and a touch line connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing unit TSU may sense the user's touch by using a mutual capacitance method or a self capacitance method.

[0089] As another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0090] A plurality of touch electrodes of the touch sensing unit TSU may be arranged in a touch sensor area overlapping the display area DA. A touch line of the touch sensing unit TSU may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0091] The color filter layer CFL may be arranged on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and may block or absorb light of a different wavelength. The color filter layer CFL may absorb part of the light from outside the display device 10 to reduce reflected light due to the external light. Accordingly, the color filter layer CFL may prevent color distortion caused by reflection of the external light.

[0092] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0093] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, and / or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include a display driver 200 and a pad unit electrically connected to the circuit board 300.

[0094] When the sub-area SBA is bent, a protection layer may be further disposed on the bent portion of the sub-area SBA.

[0095] Figure 3 is a plan view showing a display unit of a display device according to one or more embodiments. Figure 4 is a block diagram illustrating a display panel 100 and a display driver 200 according to one or more embodiments.

[0096] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0097] The display area DA may include a plurality of pixels PX, a plurality of driving voltage lines VDL connected to the plurality of pixels PX, a plurality of common voltage lines VSL (see Figure 5 ), a plurality of gate lines GL, a plurality of emission control lines EML and a plurality of data lines DL.

[0098] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, an emission control line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the pixels PX may include at least one transistor, a light emitting element LEL (eg, Figure 5 ) and capacitors.

[0099] The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1. The plurality of gate lines GL may be arranged along the second direction DR2. The plurality of gate lines GL may sequentially supply gate signals to the plurality of pixels PX.

[0100] The plurality of emission control lines EML may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The plurality of emission control lines EML may be arranged along the second direction DR2. The plurality of emission control lines EML may transmit the emission control signal EM (eg, Figure 5 ) is sequentially supplied to a plurality of pixels PX.

[0101] The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The plurality of data lines DL may be arranged along the first direction DR1. The plurality of data lines DL may supply data voltages to the plurality of pixels PX. The data voltages may determine the brightness of each of the pixels PX.

[0102] The plurality of driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The plurality of driving voltage lines VDL may be arranged along the first direction DR1. The plurality of driving voltage lines VDL may supply driving voltages to the plurality of pixels PX. The driving voltage may be a high potential voltage for driving the light emitting element LEL of the pixel PX.

[0103] The non-display area NDA may be around (eg, may surround) the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, and first and second gate control lines GSL1 and GSL2.

[0104] The fan-out line FL may extend to the display area DA from the display driver 200. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0105] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0106] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission signal ECS received from the display driver 200 to the emission control driver 620.

[0107] Sub-area SBA (for example, see Figure 1 ) may extend from one side of the non-display area NDA. The sub-area SBA may include the display driver 200 and the pad portion DP. The pad portion DP may be arranged closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 (e.g., refer to FIG. 1 ) through an anisotropic conductive film (ACF). Figure 1 ).

[0108] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0109] The timing controller 210 may receive a data signal DATA and a timing signal of a digital video from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission signal ECS for controlling the operation timing of the emission control driver 620 based on the timing signal. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through a first gate control line GSL1. The timing controller 210 may supply the emission signal ECS to the emission control driver 620 through a second gate control line GSL2. The timing controller 210 may supply the data signal DATA of the digital video and the data control signal DCS to the data driver 220.

[0110] The data driver 220 may convert the data signals DATA of the digital video into analog data voltages and supply them to the data lines DL through the fan-out lines FL. The gate signals of the gate driver 610 may select the pixels PX to which the data voltages are supplied, and the selected pixels PX may receive the data voltages through the data lines DL.

[0111] The power supply unit 500 may be disposed on the circuit board 300 to supply power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply to the driving voltage line VDL and may generate a common voltage to supply to a common electrode common to the light emitting elements LEL of a plurality of pixels PX.

[0112] The gate driver 610 may be arranged at one outer side of the display area DA or at one side of the non-display area NDA. The emission control driver 620 may be arranged at the other outer side of the display area DA or at the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be arranged at either one side or the other side of the non-display area NDA.

[0113] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating the emission control signal EM based on the emission signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed on (or in) the same layer as the transistors of each of the pixels PX. The gate driver 610 may supply the gate signal to the gate line GL, and the emission control driver 620 may supply the emission control signal EM to the emission control line EML.

[0114] Figure 5 is a circuit diagram of one pixel of a display device according to one or more embodiments.

[0115] Pixel PX (for example, see Figure 3 ) may be connected to the first gate line GWL, the second gate line GCL, the third gate line GRL, the emission control line EML, the data line DL, the driving voltage line VDL and the common voltage line VSL. Here, the common voltage line VSL may be connected to the common electrode (e.g., cathode electrode) of the light emitting element LEL.

[0116] The pixel PX may include a pixel circuit PC and a light emitting element LEL. The pixel circuit PC may include a driving transistor TD, a switching transistor TS, a compensation transistor TC, an initialization transistor TI, an emission control transistor TE, a first capacitor C1, and a second capacitor C2.

[0117] The driving transistor TD may include a gate electrode, a source electrode, and a drain electrode. The driving transistor TD may control a source-drain current (hereinafter referred to as a driving current) according to a data voltage applied to the gate electrode. A driving current (e.g., a driving current Isd) flowing through a channel region of the driving transistor TD may be proportional to the square of a difference between a threshold voltage Vth and a voltage Vsg between a source electrode and a gate electrode of the driving transistor TD (Isd=k×(Vsg–Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the driving transistor TD, Vsg is a source-gate voltage of the driving transistor TD, and Vth is a threshold voltage of the driving transistor TD.

[0118] The light emitting element LEL may emit light by receiving the driving current Isd. The emission amount or brightness of the light emitting element LEL may be proportional to the magnitude of the driving current Isd.

[0119] The light emitting element LEL may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode. As another example, the light emitting element LEL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. As another example, the light emitting element LEL may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer arranged between the first electrode and the second electrode. As another example, the light emitting element LEL may be a micro light emitting diode.

[0120] A first electrode of the light emitting element LEL may be electrically connected to a third node N3. The first electrode of the light emitting element LEL may be connected to a drain electrode of the emission control transistor TE and a source electrode of the initialization transistor TI through the third node N3. A second electrode of the light emitting element LEL may be connected to a common voltage line VSL. The second electrode of the light emitting element LEL may receive a common voltage ELVSS (e.g., a low potential voltage) from the common voltage line VSL.

[0121] The switching transistor TS can be turned on by the first gate signal GW of the first gate line GWL to electrically connect the data line DL to the first node N1 which is the gate electrode of the driving transistor TD. As the switching transistor TS is turned on in response to the first gate signal GW, the data voltage Vdat (eg, reference voltage Vdat) of the data line DL is Figure 6 ) may be supplied to the first node N1. A gate electrode of the switching transistor TS may be electrically connected to the first gate line GWL, a drain electrode of the switching transistor TS may be electrically connected to the data line DL, and a source electrode of the switching transistor TS may be electrically connected to the first node N1 through the second capacitor C2. In one or more embodiments, in order to supply the data voltage Vdat to the data line DL, the above-mentioned data driver 220 may generate a data voltage Vdat as an analog voltage based on a data signal DATA of a digital video supplied from the outside, and may supply the generated data voltage Vdat to the data line DL.

[0122] The compensation transistor TC may be turned on by the second gate signal GC of the second gate line GCL to electrically connect the first node N1, which is the gate electrode of the driving transistor TD, to the second node N2, which is the drain electrode of the driving transistor TD. The compensation transistor TC may be connected in series between the first node N1 and the second node N2. The gate electrode of the compensation transistor TC may be electrically connected to the second gate line GCL, the drain electrode of the compensation transistor TC may be electrically connected to the first node N1, and the source electrode of the compensation transistor TC may be electrically connected to the second node N2.

[0123] The initialization transistor TI may be turned on by the third gate signal GR of the third gate line GRL to electrically connect the ground GND to the third node N3 which is the first electrode of the light emitting element LEL. The initialization transistor TI may be connected in series between the ground GND and the third node N3. The gate electrode of the initialization transistor TI may be electrically connected to the third gate line GRL, the drain electrode of the initialization transistor TI may be electrically connected to the ground GND, and the source electrode of the initialization transistor TI may be electrically connected to the third node N3.

[0124] The emission control transistor TE may be turned on by an emission control signal EM of an emission control line EML to electrically connect a second node N2, which is a drain electrode of the drive transistor TD, to a third node N3, which is a first electrode of the light emitting element LEL. A gate electrode of the emission control transistor TE may be electrically connected to the emission control line EML, a source electrode of the emission control transistor TE may be electrically connected to the second node N2, and a drain electrode of the emission control transistor TE may be electrically connected to the third node N3.

[0125] The first capacitor C1 may be connected between a first node N1 which is a gate electrode of the driving transistor TD and a source electrode of the driving transistor TD (or a driving voltage line VDL which supplies a driving voltage ELVDD). A first electrode of the first capacitor C1 may be connected to the first node N1, and a second electrode of the first capacitor C1 may be connected to the source electrode of the driving transistor TD and the driving voltage line VDL. The first capacitor C1 may store, for example, a threshold voltage Vth of the driving transistor TD.

[0126] The second capacitor C2 may be electrically connected between the switching transistor TS and the first node N1 which is the gate electrode of the driving transistor TD. The first electrode of the second capacitor C2 may be electrically connected to the source electrode of the switching transistor TS, and the second electrode of the second capacitor C2 may be electrically connected to the first node N1. The second capacitor C2 may store, for example, a data voltage Vdat supplied from the data line DL through the switching transistor TS.

[0127] When the driving transistor TD and the emission control transistor TE are turned on, the driving current Isd may be supplied to the light emitting element LEL so that the light emitting element LEL may emit light.

[0128] At least one of the driving transistor TD, the switching transistor TS, the compensation transistor TC, the initialization transistor TI and the emission control transistor TE described above may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the driving transistor TD, the initialization transistor TI and the emission control transistor TE may be a P-type MOSFET.

[0129] At least one of the driving transistor TD, the switching transistor TS, the compensation transistor TC, the initialization transistor TI, and the emission control transistor TE may be an oxide-based transistor. For example, each of the switching transistor TS and the compensation transistor TC may be an N-type oxide-based transistor. In other words, each of the switching transistor TS and the compensation transistor TC may include an oxide-based semiconductor material. Since oxide-based semiconductors have high carrier mobility and low leakage current, the voltage drop is not large although the driving time is long. That is, in the case of oxide-based semiconductors, since the color change of the image caused by the voltage drop is not large even during low-frequency driving, low-frequency driving is possible. Accordingly, a display device that prevents the generation of leakage current and has reduced power consumption can be realized by using the switching transistor TS and the compensation transistor TC, each of which contains an oxide-based semiconductor material. In addition, in the case of using an oxide-based semiconductor transistor (i.e., an oxide-based transistor), it is not necessary to form a low-temperature polycrystalline silicon (LTPS) semiconductor transistor by a crystallization process of excimer laser annealing (ELA), and therefore the display panel 100 (for example, referring to Figure 1 ) can be reduced, which is conducive to the realization of large-area display devices.

[0130] Oxide-based semiconductors are sensitive to light, so that fluctuations in the amount of current and similar phenomena may occur due to light from the outside. Accordingly, it can be considered to absorb or reflect light from the outside by positioning a metal layer under the oxide-based semiconductor. The metal layer positioned under the oxide-based semiconductor of each of the switching transistor TS and the compensation transistor TC can be used as a lower gate electrode (e.g., a relative gate electrode). For example, each of the switching transistor TS and the compensation transistor TC can be a dual-gate transistor having two gate electrodes (e.g., a gate electrode and a relative gate electrode). The gate electrode and the relative gate electrode can be arranged to face each other (e.g., relative) on different layers. For example, each of the switching transistor TS and the compensation transistor TC is an N-type oxide-based semiconductor transistor, and the gate electrode and the relative gate electrode of each of the switching transistor TS and the compensation transistor TC can be positioned to face each other (e.g., relative) across the oxide-based semiconductor interposed therebetween.

[0131] Since the aforementioned switching transistor TS and the compensation transistor TC include an oxide-based active layer (or semiconductor layer), the leakage current of the switching transistor TS and the compensation transistor TC (e.g., the leakage current in the on state) can be reduced or minimized. Accordingly, the voltage fluctuation of the gate node (e.g., the first node N1) to which the gate electrode of the driving transistor TD, the source electrode of the switching transistor TS, and the drain electrode of the compensation transistor TC are commonly connected can be reduced or minimized, so that the image quality of the display device can be improved.

[0132] Figure 6 yes Figure 5 1 is a timing diagram of the first gate signal GW, the second gate signal GC and the third gate signal GR, the emission control signal EM and the data signal DATA.

[0133] like Figure 6 In the example shown in FIG. 1 , the display device 10 of the present disclosure (eg, referring to FIG. 1 ) Figure 1 ) may be operated based on an initialization period P1, a threshold voltage detection period P2, a data writing period P3, and an emission period P5. Here, the threshold voltage detection period P2 may refer to a period for detecting a threshold voltage Vth of the driving transistor TD.

[0134] The initialization period P1, the threshold voltage detection period P2, the data writing period P3, the margin period P4 and the emission period P5 may be repeated sequentially and cyclically. For example, the threshold voltage detection period P2 may be performed after the initialization period P1, the data writing period P3 may be performed after the threshold voltage detection period P2, the margin period P4 may be performed after the data writing period P3, the emission period P5 may be performed after the margin period P4, and the initialization period P1 may be performed again after the emission period P5. After the initialization period P1, the previous period may be repeated again.

[0135] The first gate signal GW, the second gate signal GC, the third gate signal GR and the emission control signal EM may have an activation level or an inactivation level for each time period. Here, the activation level of each signal may mean a voltage at a level capable of turning on the corresponding transistor to which the corresponding signal is applied. In other words, the activation level signal may have a value greater than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a P-type transistor, the activation level of each signal may mean a low level. The inactivation level of each signal may mean a voltage at a level capable of turning off the corresponding transistor. In other words, the inactivation level signal may have a value less than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is a P-type transistor, the inactivation level of each signal may mean a high level. When the corresponding transistor is an N-type transistor, the activation level of each signal may mean a high level, and the inactivation level of each signal may mean a low level.

[0136] During the initialization period P1, the first gate signal GW, the second gate signal GC, the third gate signal GR and the emission control signal EM may have an activation level. In the initialization period P1, the data signal DATA may have a level of the initialization voltage Vref. In other words, the data signal DATA of the initialization period P1 may be the initialization voltage Vref. The initialization voltage Vref may have, for example, a value smaller than the common voltage ELVSS.

[0137] Thereafter, during the threshold voltage detection period P2, the first gate signal GW, the second gate signal GC, and the third gate signal GR may have an activation level, and the emission control signal EM may have an inactivation level. In one or more embodiments, during the threshold voltage detection period P2, the data signal DATA may be maintained at the level of the aforementioned initialization voltage Vref.

[0138] Then, during the data writing period P3, the first gate signal GW and the third gate signal GR may have an activation level, and the second gate signal GC and the emission control signal EM may have an inactive level. During the data writing period P3, the data signal DATA may be converted (or changed) to the level of the data voltage Vdat. In other words, the data signal DATA of the data writing period P3 may be a data voltage Vdat having a value corresponding to a specific gray level of an image to be displayed.

[0139] Thereafter, during the margin period P4, the first gate signal GW, the second gate signal GC, the third gate signal GR and the emission control signal EM may all have an inactive level. During the margin period P4, the data signal DATA may be maintained at a level of an initialization voltage (eg, initialization voltage Vref).

[0140] Next, during the emission period P5, the emission control signal EM may have an activation level, and the first gate signal GW, the second gate signal GC, and the third gate signal GR may each have an inactivation level. In the emission period P5, the data signal DATA may be maintained at a level of an initialization voltage (eg, initialization voltage Vref).

[0141] Figure 7 is a circuit diagram of one pixel of a display device according to one or more embodiments.

[0142] according to Figure 7 The pixel PX of the display device 10 of the embodiment shown in FIG. Figure 5 The pixel PX of FIG. 4 is different in that the driving transistor TD is composed of a dual-gate transistor, and therefore, the following description will focus on the difference.

[0143] like Figure 7 In the example shown in , the driving transistor TD may include a first sub-transistor Td1 and a second sub-transistor Td2 connected in series between the second node N2 and the driving voltage line VDL.

[0144] A gate electrode of the first sub-transistor Td1 may be connected to the first node N1 , a source electrode of the first sub-transistor Td1 may be connected to the driving voltage line VDL, and a drain electrode of the first sub-transistor Td1 may be connected to a source electrode of the second sub-transistor Td2 .

[0145] A gate electrode of the second sub-transistor Td2 may be connected to the first node N1, a source electrode of the second sub-transistor Td2 may be connected to the drain electrode of the first sub-transistor Td1, and a drain electrode of the second sub-transistor Td2 may be connected to the second node N2.

[0146] The gate electrode of the first sub-transistor Td1 and the gate electrode of the second sub-transistor Td2 may be integrally formed.

[0147] Figure 8 is a plan view of transistors of a pixel array according to one or more embodiments. Fig. 9 A first pattern layer 101 of a pixel according to one or more embodiments is shown. Fig.10 A second pattern layer 102 of a pixel is shown according to one or more embodiments. Fig.11 A third pattern layer 103 and a first type contact hole CTa of a pixel according to one or more embodiments are shown. Fig.12 A fourth pattern layer 104 and a second type contact hole CTb of a pixel according to one or more embodiments are shown. Fig.13 A fifth pattern layer 105 and a third type contact hole CTc of a pixel according to one or more embodiments are shown. Fig.14 A sixth pattern layer 106 of a pixel according to one or more embodiments is shown. Fig.15 A seventh pattern layer 107 and a fourth type contact hole CTd of a pixel according to one or more embodiments are shown. Fig.16 An eighth pattern layer 108 and a fifth type contact hole CTe of a pixel according to one or more embodiments are shown. Fig.17 A ninth pattern layer 109 and a sixth type contact hole CTf of a pixel according to one or more embodiments are shown. Fig.18 A tenth pattern layer 110 and a seventh type contact hole CTg of a pixel according to one or more embodiments are illustrated. Fig.19 An eleventh pattern layer 111 and an eighth type contact hole CTh of a pixel according to one or more embodiments are illustrated. Fig. 20 Shows Fig. 9 The first pattern layer 101 and Fig.10 The second pattern layer 102 is formed. Fig.21 Shows Fig. 9 The first pattern layer 101, Fig.10 The second pattern layer 102 and Fig.11 The third pattern layer 103 and the first type contact holes CTa. Fig. 22 Shows Fig. 9 The first pattern layer 101, Fig.10 The second pattern layer 102, Fig.11 The third pattern layer 103 and the first type contact hole CTa and Fig.12 The fourth pattern layer 104 and the second type contact holes CTb. Fig.23 Shows Fig.12 The fourth pattern layer 104 and Fig.13 The fifth pattern layer 105 and the third type contact holes CTc. Fig.24 Shows Fig.13 The fifth pattern layer 105 and Fig.14 The sixth pattern layer 106 is formed. Fig.25 Shows Fig.14 The sixth pattern layer 106 and Fig.15 The seventh pattern layer 107 is formed. Fig.26 Shows Fig.13 The fifth pattern layer 105, Fig.14 The sixth pattern layer 106 and Fig.15 The seventh pattern layer 107 and the fourth type contact hole CTd. Fig. 27 Shows Fig.15 The seventh pattern layer 107 and Fig.16 The eighth pattern layer 108 and the fifth type contact holes CTe. Fig.28 Shows Fig.18 The tenth pattern layer 110 and Fig.19 The eleventh pattern layer 111 and the eighth type contact hole CTh. Fig.29A and Fig.29B is along Figures 8 to 28 Here, Fig.29A is along Figures 8 to 28 A cross-sectional view taken along line II' of Fig.29B is along Figures 8 to 28 A cross-sectional view taken along line I'-I".

[0148] like Figure 8 As shown in FIG. , the display device 10 of the present disclosure (for example, referring to FIG. Figure 1 ) may include a driving transistor TD, a switching transistor TS, a compensation transistor TC, an initialization transistor TI, and an emission control transistor TE. Here, the switching transistor TS and the compensation transistor TC may be arranged on a different layer from other transistors (e.g., the driving transistor TD, the initialization transistor TI, and the emission control transistor TE). For example, Fig.28 and Fig.29A As shown in , the switch transistor TS and the compensation transistor TC may be arranged on the drive transistor TD. For example, an N-type transistor including an oxide-based active layer (e.g., the switch transistor TS and the compensation transistor TC) may be arranged on a P-type MOSFET (e.g., the drive transistor TD, the initialization transistor TI, and the emission control transistor TE). In other words, the oxide-based transistor may be arranged farther from the substrate SUB than the MOSFET.

[0149] The oxide-based transistor and the MOSFET may be connected in the third direction DR3 through a plurality of pattern layers. Fig.29A As shown in the figure, the first gate electrode G1 of the driving transistor TD can be connected to the fifth drain region D5 (or the fifth drain electrode) of the compensation transistor TC through the first node electrode NE1, the first lower node connection electrode NCEa1, the first upper node connection electrode NCEb1 and the third drain connection electrode DCE3 arranged along the third direction DR3.

[0150] like Figure 8 , Fig.25 , Fig.26 , Fig.29A and Fig.29B As shown in , the switch transistor TS, which is an oxide-based transistor, may overlap with the initialization transistor TI and the emission control transistor TE, which are MOSFETs, in the third direction DR3. For example, the fourth gate electrode G4 of the switch transistor TS may overlap with the third gate electrode G3, the third source region S3, and the third drain region D3 of the initialization transistor TI. Moreover, the fourth gate electrode G4 of the switch transistor TS may overlap with the second gate electrode G2, the second source region S2, and the second drain region D2 of the emission control transistor TE. The fourth gate electrode G4 of the switch transistor TS may overlap with the first gate electrode G1 of the drive transistor TD.

[0151] like Figure 8 , Fig.25 , Fig.26 , Fig.29A and Fig.29B As shown in FIG, the compensation transistor TC which is an oxide-based transistor may overlap the driving transistor TD which is a MOSFET in the third direction DR3. For example, the fifth gate electrode G5 of the compensation transistor TC may overlap the first gate electrode G1, the first source region S1, and the first drain region D1 of the driving transistor TD.

[0152] Since the oxide-based transistor and the MOSFET overlap in the third direction DR3 as described above, the integration density of the transistor per unit area can be improved.

[0153] like Fig.29A and Fig.29B As shown in , the display device 10 of the present disclosure may include a substrate SUB, a transistor layer TRL, a capacitor layer CPL, a light emitting element layer EMTL, and an encapsulation layer ENC sequentially stacked along a third direction DR3.

[0154] The driving transistor TD, the switching transistor TS, the compensation transistor TC, the initialization transistor TI, and the emission control transistor TE described above may be arranged in the transistor layer TRL. In this case, in the transistor layer TRL, the switching transistor TS and the compensation transistor TC may be arranged on a different layer from other transistors (e.g., the driving transistor TD, the initialization transistor TI, and the emission control transistor TE).

[0155] The capacitor layer CPL may include a plurality of pattern layers for forming the first capacitor C1 and the second capacitor C2.

[0156] Fig.29A and Fig.29B The substrate SUB shown in FIG. 1 may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The substrate SUB may be a substrate doped with first type impurities.

[0157] like Fig. 9 and Fig.21 As shown in FIG. 1 , the first pattern layer 101 may be disposed on (or inside) the substrate SUB. The first pattern layer 101 may include, for example, a first well region W1, a second well region W2, and a third well region W3.

[0158] Each of the first to third well regions W1 to W3 may be a region doped with second type impurities. The second type impurities may be different from the first type impurities. For example, when the first type impurities are p-type impurities, the second type impurities may be n-type impurities. When the first type impurities are n-type impurities, the second type impurities may be p-type impurities.

[0159] In each of the first to third well regions W1 to W3 , a source region, a drain region, and a channel region of a corresponding transistor may be disposed.

[0160] For example, Figure 8 and Fig. 20 As shown in , the first source region S1 (or the first source electrode) and the first drain region D1 (or the first drain electrode) of the driving transistor TD may be arranged in the first well region W1. Each of the first source region S1 and the first drain region D1 may be a region doped with a first type of impurity. The first gate electrode G1 of the driving transistor TD may intersect and overlap with the first well region W1. In a plan view, the first well region W1 intersecting with the first gate electrode G1 may define two parts, and the first source region S1 may be arranged in either of the two parts, and the first drain region D1 may be arranged in the other of the two parts. In other words, in the first well region W1, the first source region S1 and the first drain region D1 may be arranged on both sides of the first gate electrode G1, respectively, with the first gate electrode G1 interposed therebetween. The first channel region CH1 of the driving transistor TD may be arranged in a portion of the first well region W1 overlapping with the first gate electrode G1.

[0161] In addition, if Fig.29A As shown in , the first source region S1 may include a first low-concentration impurity region LDD1 having an impurity concentration relatively lower than that of other portions of the first source region S1. In other words, a portion of the first source region S1 may include a lower concentration of impurities than other portions of the first source region S1. The first drain region D1 may include a second low-concentration impurity region LDD2 having an impurity concentration relatively lower than that of other portions of the first drain region D1. In other words, a portion of the first drain region D1 may include a lower concentration of impurities than other portions of the first drain region D1.

[0162] The first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 may be arranged close to the first channel region CH1 of the driving transistor TD. For example, the first low-concentration impurity region LDD1 may be arranged close to the first channel region CH1 to overlap with the first spacer SW1, and the second low-concentration impurity region LDD2 may be arranged close to the first channel region CH1 to overlap with the second spacer SW2. Thus, the distance between the high-concentration impurity region of the first source region S1 and the high-concentration impurity region of the first drain region D1 may be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, and the length of the first channel region CH1 may be eventually increased due to the increased distance. Accordingly, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0163] like Figure 8 , Fig. 20 and Fig.28 As shown in , the second source region S2 (or the second source electrode) and the second drain region D2 (or the second drain electrode) of the emission control transistor TE may be arranged in the second well region W2.

[0164] Each of the second source region S2 and the second drain region D2 may be a region doped with the aforementioned second type impurities. The second gate electrode G2 of the emission control transistor TE may intersect and overlap with the second well region W2. In a plan view, the second well region W2 intersecting with the second gate electrode G2 may define two parts, and the second source region S2 may be arranged in either of the two parts, and the second drain region D2 may be arranged in the other of the two parts. In other words, in the second well region W2, the second source region S2 and the second drain region D2 may be arranged on both sides of the second gate electrode G2, respectively, with the second gate electrode G2 interposed therebetween. The second channel region CH2 of the emission control transistor TE may be arranged in a portion of the second well region W2 that overlaps with the second gate electrode G2. The second source region S2 and the second drain region D2 may include the aforementioned first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, respectively.

[0165] like Figure 8 and Fig. 20As shown in , the third source region S3 (or the third source electrode) and the third drain region D3 (or the third drain electrode) of the initialization transistor TI may be arranged in the third well region W3. Each of the third source region S3 and the third drain region D3 may be a region doped with the aforementioned second type impurities. The third gate electrode G3 of the initialization transistor TI may intersect and overlap with the third well region W3. In a plan view, the third well region W3 intersecting with the third gate electrode G3 may define two parts, and the third source region S3 may be arranged in either of the two parts, and the third drain region D3 may be arranged in the other of the two parts. In other words, in the third well region W3, the third source region S3 and the third drain region D3 may be arranged on both sides of the third gate electrode G3, respectively, with the third gate electrode G3 interposed therebetween. The third channel region CH3 of the initialization transistor TI may be arranged in the portion of the third well region W3 overlapping with the third gate electrode G3. The third source region S3 and the third drain region D3 may include the aforementioned first and second low-concentration impurity regions LDD1 and LDD2 , respectively.

[0166] like Fig.29A As shown in , the gate insulating layer GTI may be arranged on each of the first to third well regions W1 to W3. For example, the gate insulating layer GTI may be arranged on the first to third channel regions CH1 to CH3 of the first to third well regions W1 to W3. As an example, the gate insulating layer GTI may be arranged on the first channel region CH1 of the drive transistor TD in the first well region W1, and may be arranged on the second channel region CH2 of the emission control transistor TE in the second well region W2.

[0167] The gate insulating layer GTI may be formed of, for example, silicon oxide. The gate insulating layer GTI may be formed by an atomic layer deposition (ALD) method.

[0168] like Fig.10 and Fig.29A As shown in FIG. 1 , the second pattern layer 102 may be disposed on the gate insulating layer GTI. The second pattern layer 102 may include, for example, a first gate electrode G1, a second gate electrode G2, and a third gate electrode G3.

[0169] The first gate electrode G1 may be arranged on the gate insulating layer GTI to overlap a portion of the first well region W1. The first gate electrode G1 may extend on the gate insulating layer GTI in a direction crossing the first well region W1.

[0170] The second gate electrode G2 may be arranged on the gate insulating layer GTI to overlap a portion of the second well region W2. The second gate electrode G2 may extend on the gate insulating layer GTI in a direction crossing the second well region W2.

[0171] The third gate electrode G3 may be arranged on the gate insulating layer GTI to overlap a portion of the third well region W3. The third gate electrode G3 may extend on the gate insulating layer GTI in a direction crossing the third well region W3.

[0172] The first to third gate electrodes G1 to G3 may be formed of, for example, polysilicon or polysilicon doped with first type impurities.

[0173] like Fig.29A As shown in , a first spacer SW1 may be arranged on one side surface of each of the first to third gate electrodes G1 to G3, and a second spacer SW2 may be arranged on the other side surface of each of the first to third gate electrodes G1 to G3. As an example, the first spacer SW1 may be arranged on a first side surface of the first gate electrode G1, and the second spacer SW2 may be arranged on a second side surface of the first gate electrode G1. The first spacer SW1 may be arranged on the first low-concentration impurity region LDD1, and the second spacer SW2 may be arranged on the second low-concentration impurity region LDD2. Each of the first spacer SW1 and the second spacer SW2 may be formed of an oxide layer, a nitride layer, or an oxynitride layer.

[0174] like Fig.29A As shown in , an ohmic contact layer 120 may be arranged on each of the first to third gate electrodes G1 to G3, each of the first to third source regions S1 to S3, and each of the first to third drain regions D1 to D3. As an example, the ohmic contact layer 120 may be arranged on the first gate electrode G1, the first source region S1, and the first drain region D1. In one or more embodiments, the ohmic contact layer 120 may be arranged on the second gate electrode G2, the second source region S2, and the second drain region D2. In this case, the ohmic contact layer 120 may be arranged on a region (e.g., a first high-concentration impurity region) other than the first low-concentration impurity region LDD1 in each of the first to third source regions S1 to S3. In addition, the ohmic contact layer 120 may be arranged on a region (e.g., a second high-concentration impurity region) other than the second low-concentration impurity region LDD2 in each of the first to third drain regions D1 to D3.

[0175] The ohmic contact layer 120 may be formed of, for example, a silicide layer. For example, the silicide layer may be a cobalt silicide layer. The silicide layer may be manufactured by, for example, a self-aligned silicide process.

[0176] like Fig.29A As shown in FIG. 1 , a passivation layer 135 may be disposed on each of the ohmic contact layer 120 and each of the first and second spacers SW1 and SW2. For example, the passivation layer 135 may be disposed on the entire surface of the substrate SUB including the ohmic contact layer 120 and the first and second spacers SW1 and SW2. The passivation layer 135 may be made of, for example, silicon nitride (SiNx ) layer is formed.

[0177] like Fig.29A As shown in FIG. 1 , the first interlayer insulating layer VA1 may be disposed on the passivation layer 135 . The first interlayer insulating layer VA1 may be disposed on the entire surface of the substrate SUB including the passivation layer 135 .

[0178] The first interlayer insulating layer VA1 may be made of, for example, silicon oxide (SiO x ) layer and silicon nitride (SiN x ) layers.

[0179] like Fig.11 , Fig.21 and Fig.29A As shown in FIG. 1 , the third pattern layer 103 (eg, a metal layer) may be disposed on the first interlayer insulating layer VA1. Fig.11 In the example shown in , the third pattern layer 103 may include a first node electrode NE1, a second node electrode NE2, a third node electrode NE3, a first gate connection electrode GCE1, a second gate connection electrode GCE2, a first source connection electrode SCE1, and a first drain connection electrode DCE1. As an example, FIG. 29A to FIG. 29B It is shown that the second node electrode NE2 , the first node electrode NE1 , the first source connection electrode SCE1 , and the third node electrode NE3 are arranged on the first interlayer insulating layer VA1 .

[0180] like Fig.11 and Fig.21 As shown in , the first node electrode NE1 may be connected to the first gate electrode G1 of the driving transistor TD through a first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135. Fig.29A As shown in , the first node electrode NE1 may be connected to the first gate electrode G1 of the driving transistor TD through a second contact hole CT2 penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0181] like Fig.11 and Fig.21 As shown in , the second node electrode NE2 may be connected to the first drain region D1 of the driving transistor TD and the second source region S2 of the emission control transistor TE through the first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135. Fig.29A As shown in , the second node electrode NE2 may be connected to the first drain region D1 of the driving transistor TD through a first contact hole CT1 penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0182] like Fig.11 and Fig.21As shown in , the third node electrode NE3 may be connected to the third source region S3 of the initialization transistor TI and the second drain region D2 of the emission control transistor TE through the first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135. Fig.29B As shown in FIG. 1 , the third node electrode NE3 may be connected to the second drain region D2 of the emission control transistor TE through a sixth contact hole CT6 penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0183] like Fig.11 and Fig.21 As shown in FIG. 1 , the first gate connection electrode GCE1 may be connected to the second gate electrode G2 of the emission control transistor TE through a first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0184] like Fig.11 and Fig.21 As shown in FIG. 1 , the second gate connection electrode GCE2 may be connected to the third gate electrode G3 of the initialization transistor TI through a first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0185] like Fig.11 and Fig.21 As shown in , the first source connection electrode SCE1 may be connected to the first source region S1 of the driving transistor TD through a first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135. FIG. 29A to FIG. 29B As shown in FIG. 1 , the first source connection electrode SCE1 may be connected to the first source region S1 of the driving transistor TD through the third, fourth, and fifth contact holes CT3 , CT4 , and CT5 penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0186] like Fig.11 and Fig.21 As shown in FIG. 1 , the first drain connection electrode DCE1 may be connected to the third drain region D3 of the initialization transistor TI through a first type contact hole CTa penetrating the first interlayer insulating layer VA1 and the passivation layer 135 .

[0187] The first to sixth contact holes CT1 to CT6 mentioned above may belong to the first type contact holes CTa.

[0188] The third pattern layer 103 may be formed of, for example, tungsten (W).

[0189] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the third pattern layer 103 and the inner wall of the first type contact hole CTa. The bonding layer may be used to improve the bonding strength between the third pattern layer 103 and the inner wall of the first type contact hole CTa (e.g., the material of the first interlayer insulating layer VA1). The diffusion barrier layer may be used to prevent diffusion of the third pattern layer 103 (e.g., the metal layer) in the first type contact hole CTa. The bonding layer may be arranged between the inner wall of the first type contact hole CTa and the third pattern layer 103. The diffusion barrier layer may be arranged between the bonding layer and the third pattern layer 103.

[0190] The bonding layer may be formed of, for example, titanium. The diffusion barrier layer may be formed of a titanium nitride layer.

[0191] like FIG. 29A to FIG. 29B As shown in FIG. 1 , the second interlayer insulating layer VA2 may be disposed on the third pattern layer 103. For example, the second interlayer insulating layer VA2 may be disposed on the entire surface of the substrate SUB including the first node electrode NE1, the second node electrode NE2, the third node electrode NE3, the first gate connection electrode GCE1, the second gate connection electrode GCE2, the first source connection electrode SCE1, and the first drain connection electrode DCE1 described above.

[0192] The second interlayer insulating layer VA2 may include the same material as the first interlayer insulating layer VA1 described above.

[0193] like Fig.12 , Fig. 22 and Fig.29A As shown in FIG. 1 , the fourth pattern layer 104 (eg, a metal layer) may be disposed on the second interlayer insulating layer VA2. Fig.12 In the example shown in , the fourth pattern layer 104 may include a first gate line GWL, a second gate line GCL, a third gate line GRL, an emission control line EML, a first driving connection electrode VCE1, a first pixel connection electrode PCE1, a first lower node connection electrode NCEa1, a second lower node connection electrode NCEa2 and a ground GND. As an example, FIG. 29A to FIG. 29B It is shown that a first gate line GWL, a second gate line GCL, a third gate line GRL, a first driving connection electrode VCE1, a first pixel connection electrode PCE1, a first lower node connection electrode NCEa1 and a ground GND are arranged on the second interlayer insulating layer VA2.

[0194] like Fig.21 and Fig. 22 As shown in FIG. 2 , the third gate line GRL may be connected to the second gate connection electrode GCE2 through the second type contact hole CTb penetrating the second interlayer insulating layer VA2 .

[0195] like Fig. 22As shown in FIG, the emission control line EML may be connected to the first gate connection electrode GCE1 through a second type contact hole CTb penetrating the second interlayer insulating layer VA2.

[0196] like Fig. 22 As shown in , the first driving connection electrode VCE1 may be connected to the first source connection electrode SCE1 through the second type contact hole CTb penetrating the second interlayer insulating layer VA2. Fig.29A As shown in FIG. 1 , the first driving link electrode VCE1 may be connected to the first source link electrode SCE1 through an eighth contact hole CT8 penetrating the second interlayer insulating layer VA2 .

[0197] The first pixel connection electrode PCE1 may be connected to the third node electrode NE3 through the second type contact hole CTb penetrating the second interlayer insulating layer VA2. Fig.29B As shown in FIG. 1 , the first pixel connection electrode PCE1 may be connected to the third node electrode NE3 through a ninth contact hole CT9 penetrating the second interlayer insulating layer VA2 .

[0198] The first lower node connection electrode NCEa1 may be connected to the first node electrode NE1 through a second type contact hole CTb penetrating the second interlayer insulating layer VA2. Fig.29A As shown in FIG. 1 , the first lower node connection electrode NCEa1 may be connected to the first node electrode NE1 through a seventh contact hole CT7 penetrating the second interlayer insulating layer VA2 .

[0199] The second lower node connection electrode NCEa2 may be connected to the second node electrode NE2 through a second type contact hole CTb penetrating the second interlayer insulating layer VA2 .

[0200] For example, refer to Figure 11 to Figure 12 , the ground GND may be connected to the first drain connection electrode DCE1 through the second type contact hole CTb penetrating the second interlayer insulating layer VA2.

[0201] The seventh to ninth contact holes CT7 to CT9 mentioned above may belong to the second type contact holes CTb.

[0202] The fourth pattern layer 104 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the fourth pattern layer 104 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0203] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the fourth pattern layer 104 and the inner wall of the second type contact hole CTb. The bonding layer may be used to improve the bonding strength between the fourth pattern layer 104 and the inner wall of the second type contact hole CTb (e.g., the material of the second interlayer insulating layer VA2). The diffusion barrier layer may be used to prevent diffusion of the fourth pattern layer 104 in the second type contact hole CTb. The bonding layer may be arranged between the inner wall of the second type contact hole CTb and the fourth pattern layer 104. The diffusion barrier layer may be arranged between the bonding layer and the fourth pattern layer 104.

[0204] The bonding layer may be formed of, for example, titanium. The diffusion barrier layer may be formed of a titanium nitride layer.

[0205] like FIG. 29A to FIG. 29B As shown in , the third interlayer insulating layer VA3 may be arranged on the fourth pattern layer 104. For example, the third interlayer insulating layer VA3 may be arranged on the entire surface of the substrate SUB including the first gate line GWL, the second gate line GCL, the third gate line GRL, the emission control line EML, the first driving connection electrode VCE1, the first pixel connection electrode PCE1, the first lower node connection electrode NCEa1, the second lower node connection electrode NCEa2 and the ground GND.

[0206] The third interlayer insulating layer VA3 may include the same material as the first interlayer insulating layer VA1 described above.

[0207] like Fig.13 , Fig.23 and FIG. 29A to FIG. 29B As shown in , the fifth pattern layer 105 may be arranged on the third interlayer insulating layer VA3. Fig.13 In the example shown in , the fifth pattern layer 105 may include a first relative gate electrode GB1, a second relative gate electrode GB2, a first upper node connection electrode NCEb1, a second upper node connection electrode NCEb2, a second pixel connection electrode PCE2, and a second driving connection electrode VCE2. As an example, FIG. 29A to FIG. 29B It is shown that the first opposing gate electrode GB1, the second opposing gate electrode GB2, the first upper node connection electrode NCEb1, the second pixel connection electrode PCE2 and the second driving connection electrode VCE2 are arranged on the third interlayer insulating layer VA3.

[0208] like Fig.23 As shown in FIG. 1 , the first counter gate electrode GB1 may be connected to the first gate line GWL through a third type contact hole CTc penetrating the third interlayer insulating layer VA3 .

[0209] like Fig.23 As shown in FIG. 1 , the second counter gate electrode GB2 may be connected to the second gate line GCL through a third type contact hole CTc penetrating the third interlayer insulating layer VA3 .

[0210] like Fig.23 As shown in , the first upper node connection electrode NCEb1 may be connected to the first lower node connection electrode NCEa1 through a third type contact hole CTc penetrating the third interlayer insulating layer VA3. For example, the first upper node connection electrode NCEb1 may be connected to the first lower node connection electrode NCEa1 through an eleventh contact hole CT11 penetrating the third interlayer insulating layer VA3.

[0211] like Figure 22 to Figure 23 As shown in FIG. 4 , the second upper node connection electrode NCEb2 may be connected to the second lower node connection electrode NCEa2 through a third type contact hole CTc penetrating the third interlayer insulating layer VA3 .

[0212] like Fig.23 As shown in , the second pixel connection electrode PCE2 can be connected to the first pixel connection electrode PCE1 through the third type contact hole CTc penetrating the third interlayer insulating layer VA3. Fig.29B As shown in FIG. 1 , the second pixel connection electrode PCE2 may be connected to the first pixel connection electrode PCE1 through a twelfth contact hole CT12 penetrating the third interlayer insulating layer VA3 .

[0213] like Fig.23 As shown in , the second driving connection electrode VCE2 can be connected to the first driving connection electrode VCE1 through the third type contact hole CTc penetrating the third interlayer insulating layer VA3. Fig.29A As shown in FIG. 1 , the second driving link electrode VCE2 may be connected to the first driving link electrode VCE1 through a tenth contact hole CT10 penetrating the third interlayer insulating layer VA3 .

[0214] The aforementioned tenth to twelfth contact holes CT10 to CT12 may belong to the third type contact holes CTc.

[0215] The fifth pattern layer 105 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the fifth pattern layer 105 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0216] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the fifth pattern layer 105 and the inner wall of the third type contact hole CTc. The bonding layer may be used to improve the bonding strength between the fifth pattern layer 105 and the inner wall of the third type contact hole CTc (e.g., the material of the third interlayer insulating layer VA3). The diffusion barrier layer may be used to prevent diffusion of the fifth pattern layer 105 (e.g., the metal layer) in the third type contact hole CTc. The bonding layer may be arranged between the inner wall of the third type contact hole CTc and the fifth pattern layer 105. The diffusion barrier layer may be arranged between the bonding layer and the fifth pattern layer 105.

[0217] The bonding layer may be formed of, for example, titanium. The diffusion barrier layer may be formed of a titanium nitride layer.

[0218] like FIG. 29A to FIG. 29B As shown in FIG. 1 , the fourth interlayer insulating layer VA4 may be arranged on the fifth pattern layer 105. For example, the fourth interlayer insulating layer VA4 may be arranged on the entire surface of the substrate SUB including the first opposing gate electrode GB1, the second opposing gate electrode GB2, the first upper node connection electrode NCEb1, the second upper node connection electrode NCEb2, the second pixel connection electrode PCE2, and the second driving connection electrode VCE2.

[0219] The fourth interlayer insulating layer VA4 may include the same material as the first interlayer insulating layer VA1 described above.

[0220] like Fig.14 , Fig.24 , Fig.29A and Fig.29B As shown in , the sixth pattern layer 106 may be arranged on the fourth interlayer insulating layer VA4. Fig.14 In the example shown in FIG. 1 , the sixth pattern layer 106 may include a first active layer ACT1 and a second active layer ACT2 .

[0221] On the upper side, the first active layer ACT1 may overlap the first opposing gate electrode GB1, the second pixel connection electrode PCE2, and the second driving connection electrode VCE2. Fig.29A and Fig.29B (or Fig.25 ), the first active layer ACT1 may include a fourth source region S4 (or a fourth source electrode), a fourth drain region D4 (or a fourth drain electrode), and a fourth channel region CH4. The fourth channel region CH4 of the switch transistor TS may be formed in a region of the first active layer ACT1 overlapping with the first opposing gate electrode GB1. The first active layer ACT1 may include an oxide. For example, the first active layer ACT1 may be a semiconductor layer including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0222] On the lower side, the second active layer ACT2 may overlap the second opposing gate electrode GB2, the first upper node connection electrode NCEb1, and the second driving connection electrode VCE2. Fig.29A and Fig.29B (or Fig.25), the second active layer ACT2 may include a fifth source region S5 (or a fifth source electrode), a fifth drain region D5 (or a fifth drain electrode), and a fifth channel region CH5. The fifth channel region CH5 of the compensation transistor TC may be formed in a region of the second active layer ACT2 overlapping with the second opposing gate electrode GB2. The second active layer ACT2 may include an oxide. For example, the second active layer ACT2 may be a semiconductor layer including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0223] like Fig.29A and Fig.29B As shown in FIG. 1 , the fifth interlayer insulating layer VA5 may be disposed on the sixth pattern layer 106. For example, the fifth interlayer insulating layer VA5 may be disposed on the entire surface of the substrate SUB including the first and second active layers ACT1 and ACT2 described above.

[0224] The fifth interlayer insulating layer VA5 may include the same material as the first interlayer insulating layer VA1 described above.

[0225] like Fig.15 , Fig.25 , Fig.26 , Fig.29A and Fig.29B As shown in , the seventh pattern layer 107 may be arranged on the fifth interlayer insulating layer VA5. Fig.15 In the example shown in , the seventh pattern layer 107 may include a fourth gate electrode G4, a second source connection electrode SCE2, a second drain connection electrode DCE2, a fifth gate electrode G5, a third source connection electrode SCE3, a third drain connection electrode DCE3, a third pixel connection electrode PCE3 and a third drive connection electrode VCE3. As an example, Fig.29A and Fig.29B It is shown that the third source connection electrode SCE3, the fifth gate electrode G5, the third drain connection electrode DCE3, the third pixel connection electrode PCE3, the second drain connection electrode DCE2 and the fourth gate electrode G4 are arranged on the fifth interlayer insulating layer VA5.

[0226] The fourth gate electrode G4 may overlap the first active layer ACT1 and the first opposite gate electrode GB1. The fourth channel region CH4 of the switching transistor TS may be formed in a region of the first active layer ACT1 overlapping the fourth gate electrode G4. Fig.26 As shown in FIG. 1 , the fourth gate electrode G4 may be connected to the first counter gate electrode GB1 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4 .

[0227] The fifth gate electrode G5 may overlap the second active layer ACT2 and the second opposite gate electrode GB2. The fifth channel region CH5 of the compensation transistor TC may be formed in a region of the second active layer ACT2 overlapping the fifth gate electrode G5. Fig.26 As shown in FIG, the fifth gate electrode G5 may be connected to the second counter gate electrode GB2 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4.

[0228] For example, refer to Figure 25 to Figure 26 , the second source connection electrode SCE2 may overlap with the fourth source region S4 of the first active layer ACT1. Fig.26 As shown in FIG. 5 , the second source connection electrode SCE2 may be connected to the fourth source region S4 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 .

[0229] The second drain connection electrode DCE2 may overlap the fourth drain region D4 of the first active layer ACT1. Fig.26 and Fig.29B As shown in , the second drain connection electrode DCE2 may be connected to the fourth drain region D4 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5. Fig.29B As shown in FIG. 5 , the second drain connection electrode DCE2 may be connected to the fourth drain region D4 through a twentieth contact hole CT20 penetrating the fifth interlayer insulating layer VA5 .

[0230] The third source connection electrode SCE3 may overlap the fifth source region S5 of the second active layer ACT2. Fig.26 As shown in , the third source connection electrode SCE3 may be connected to the fifth source region S5 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5. Fig.29A As shown in , the third source connection electrode SCE3 can be connected to the fifth source region S5 through the thirteenth contact hole CT13 and the fourteenth contact hole CT14 penetrating the fifth interlayer insulating layer VA5. In addition, the third source connection electrode SCE3 can be connected to the second upper node connection electrode NCEb2 through the fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4.

[0231] The third drain connection electrode DCE3 may overlap the fifth drain region D5 of the second active layer ACT2. Fig.26 As shown in , the third drain connection electrode DCE3 can be connected to the fifth drain region D5 through the fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5. In addition, the third drain connection electrode DCE3 can be connected to the first upper node connection electrode NCEb1 through the fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4. For example, as Fig.29A and Fig.29B As shown in FIG. 1 , the third drain connection electrode DCE3 may be connected to the fifth drain region D5 through the fifteenth contact hole CT15, the sixteenth contact hole CT16, and the seventeenth contact hole CT17 penetrating the fifth interlayer insulating layer VA5. In addition, the third drain connection electrode DCE3 may be connected to the first upper node connection electrode NCEb1 through the eighteenth contact hole CT18 penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4.

[0232] like Fig.26 and Fig.29B As shown in , the third pixel connection electrode PCE3 can be connected to the second pixel connection electrode PCE2 through the fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4. Fig.29B As shown in FIG. 1 , the third pixel connection electrode PCE3 may be connected to the second pixel connection electrode PCE2 through a nineteenth contact hole CT19 penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4 .

[0233] like Fig.26 As shown in FIG. 1 , the third driving link electrode VCE3 may be connected to the second driving link electrode VCE2 through a fourth type contact hole CTd penetrating the fifth interlayer insulating layer VA5 and the fourth interlayer insulating layer VA4 .

[0234] The thirteenth to twentieth contact holes CT13 to CT20 may belong to the fourth type contact holes CTd.

[0235] The seventh pattern layer 107 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the seventh pattern layer 107 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0236] A bonding layer and a diffusion barrier layer may also be arranged between the seventh pattern layer 107 and the inner wall of the fourth type contact hole CTd. The bonding layer may be used to improve the bonding strength between the seventh pattern layer 107 and the inner wall of the fourth type contact hole CTd (e.g., the material of the fifth interlayer insulating layer VA5). The diffusion barrier layer may be used to prevent the diffusion of the seventh pattern layer 107 (e.g., the metal layer) in the fourth type contact hole CTd. The bonding layer may be arranged between the inner wall of the fourth type contact hole CTd and the seventh pattern layer 107. The diffusion barrier layer may be arranged between the bonding layer and the seventh pattern layer 107.

[0237] The bonding layer may include, for example, titanium.The diffusion barrier layer may include a titanium nitride layer.

[0238] like Fig.29A and Fig.29BAs shown in , the sixth interlayer insulating layer VA6 may be arranged on the seventh pattern layer 107. For example, the sixth interlayer insulating layer VA6 may be arranged on the entire surface of the substrate SUB including the fourth gate electrode G4, the second source connection electrode SCE2, the second drain connection electrode DCE2, the fifth gate electrode G5, the third source connection electrode SCE3, the third drain connection electrode DCE3, the third pixel connection electrode PCE3 and the third driving connection electrode VCE3 described above.

[0239] The sixth interlayer insulating layer VA6 may include the same material as the first interlayer insulating layer VA1 described above.

[0240] like Fig.16 , Fig. 27 , Fig.29A and Fig.29B As shown in , the eighth pattern layer 108 may be arranged on the sixth interlayer insulating layer VA6. Fig.16 In the example shown in , the eighth pattern layer 108 may include a lower common capacitor electrode CCPEa, a first lower capacitor electrode CPEa1, a second lower capacitor electrode CPEa2, a first data link electrode DLCE1, and a fourth pixel link electrode PCE4. As an example, Fig.29A and Fig.29B It is shown that the first lower capacitor electrode CPEa1 , the lower common capacitor electrode CCPEa, the fourth pixel connection electrode PCE4 , and the second lower capacitor electrode CPEa2 are arranged on the sixth interlayer insulating layer VA6 .

[0241] like Fig. 27 As shown in , the lower common capacitor electrode CCPEa may be connected to the third drain connection electrode DCE3 through a fifth type contact hole CTe penetrating the sixth interlayer insulating layer VA6. Fig.29A and Fig.29B As shown in , the lower common capacitor electrode CCPEa may be connected to the third drain connection electrode DCE3 through the twenty-first contact hole CT21 penetrating the sixth interlayer insulating layer VA6. The lower common capacitor electrode CCPEa may include at least one first extension electrode EXa1 extending in the second direction DR2 and at least one second extension electrode EXa2 extending in the first direction DR1. The second extension electrode EXa2 may have a shape branched from the first extension electrode EXa1. The first extension electrode EXa1 and the second extension electrode EXa2 may be integrally formed.

[0242] like Fig. 27As shown in , the first lower capacitor electrode CPEa1 may be connected to the third driving connection electrode VCE3 through the fifth type contact hole CTe penetrating the sixth interlayer insulating layer VA6. The first lower capacitor electrode CPEa1 may include at least one first extension electrode EXa11 extending in the second direction DR2 and at least one second extension electrode EXa12 extending in the first direction DR1. The second extension electrode EXa12 may have a shape branched from the first extension electrode EXa11. The first extension electrode EXa11 and the second extension electrode EXa12 may be formed integrally.

[0243] The first extension electrode EXa11 of the first lower capacitor electrode CPEa1 may be arranged adjacent to the first extension electrode EXa1 of the lower common capacitor electrode CCPEa. The first capacitor C1 may be formed between the lower common capacitor electrode CCPEa and the first lower capacitor electrode CPEa1. For example, the lower common capacitor electrode CCPEa may include a first electrode of the first capacitor C1, and the first lower capacitor electrode CPEa1 may include a second electrode of the first capacitor C1.

[0244] like Fig. 27 As shown in , the second lower capacitor electrode CPEa2 may be connected to the second source connection electrode SCE2 through a fifth type contact hole CTe penetrating the sixth interlayer insulating layer VA6. The second lower capacitor electrode CPEa2 may include at least one first extension electrode EXa21 extending in the second direction DR2 and at least one second extension electrode EXa22 extending in the first direction DR1. The second extension electrode EXa22 may have a shape branching from the first extension electrode EXa21. The first extension electrode EXa21 and the second extension electrode EXa22 may be formed integrally.

[0245] The first extension electrode EXa21 of the second lower capacitor electrode CPEa2 may be arranged adjacent to the first extension electrode EXa1 of the lower common capacitor electrode CCPEa. The second capacitor C2 may be formed between the lower common capacitor electrode CCPEa and the second lower capacitor electrode CPEa2. For example, the lower common capacitor electrode CCPEa may include the second electrode of the second capacitor C2, and the second lower capacitor electrode CPEa2 may include the first electrode of the second capacitor C2.

[0246] like Fig. 27 As shown in FIG. 5 , the first data link electrode DLCE1 may be connected to the second drain link electrode DCE2 through a fifth type contact hole CTe penetrating the sixth interlayer insulating layer VA6 .

[0247] like Fig. 27 As shown in , the fourth pixel connection electrode PCE4 can be connected to the third pixel connection electrode PCE3 through the fifth type contact hole CTe penetrating the sixth interlayer insulating layer VA6. Fig.29A and Fig.29B As shown in , the fourth pixel connection electrode PCE4 may be connected to the third pixel connection electrode PCE3 through a twenty-second contact hole CT22 penetrating the sixth interlayer insulating layer VA6 .

[0248] The twenty-first and twenty-second contact holes CT21 and CT22 may belong to the fifth type contact holes CTe.

[0249] The eighth pattern layer 108 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the eighth pattern layer 108 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0250] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the eighth pattern layer 108 and the inner wall of the fifth type contact hole CTe. The bonding layer may be used to improve the bonding strength between the eighth pattern layer 108 and the inner wall of the fifth type contact hole CTe (e.g., the material of the sixth interlayer insulating layer VA6). The diffusion barrier layer may be used to prevent the diffusion of the eighth pattern layer 108 (e.g., the metal layer) in the fifth type contact hole CTe. The bonding layer may be arranged between the inner wall of the fifth type contact hole CTe and the eighth pattern layer 108. The diffusion barrier layer may be arranged between the bonding layer and the eighth pattern layer 108.

[0251] The bonding layer may include, for example, titanium.The diffusion barrier layer may include a titanium nitride layer.

[0252] like Fig.29A and Fig.29B , the seventh interlayer insulating layer VA7 may be disposed on the eighth pattern layer 108. For example, the seventh interlayer insulating layer VA7 may be disposed on the entire surface of the substrate SUB including the lower common capacitor electrode CCPEa, the first lower capacitor electrode CPEa1, the second lower capacitor electrode CPEa2, the first data link electrode DLCE1, and the fourth pixel connection electrode PCE4 described above.

[0253] The seventh interlayer insulating layer VA7 may include the same material as the first interlayer insulating layer VA1 described above.

[0254] like Fig.17 , Fig.29A and Fig.29B As shown in , the ninth pattern layer 109 may be arranged on the seventh interlayer insulating layer VA7. Fig.17 In the example shown in , the ninth pattern layer 109 may include an intermediate common capacitor electrode CCPEb, a first intermediate capacitor electrode CPEb1, a second intermediate capacitor electrode CPEb2, a second data link electrode DLCE2, and a fifth pixel link electrode PCE5. As an example, Fig.29A and Fig.29BIt is shown that the first intermediate capacitor electrode CPEb1 , the intermediate common capacitor electrode CCPEb, the fifth pixel connection electrode PCE5 , and the second intermediate capacitor electrode CPEb2 are arranged on the seventh interlayer insulating layer VA7 .

[0255] The first middle capacitor electrode CPEb1 may have the same shape and size as the first lower capacitor electrode CPEa1 (eg, the same size in the first, second, and third directions DR1, DR2, and DR3). The entire first middle capacitor electrode CPEb1 may overlap the entire first lower capacitor electrode CPEa1.

[0256] The middle common capacitor electrode CCPEb may have the same shape and the same size (e.g., the same size in the first direction DR1, the second direction DR2, and the third direction DR3) as the lower common capacitor electrode CCPEa described above. The entire middle common capacitor electrode CCPEb may overlap the entire lower common capacitor electrode CCPEa.

[0257] The second middle capacitor electrode CPEb2 may have the same shape and the same size as the second lower capacitor electrode CPEa2 (e.g., the same size in the first direction DR1, the second direction DR2, and the third direction DR3). The entire second middle capacitor electrode CPEb2 may overlap the entire second lower capacitor electrode CPEa2.

[0258] like Fig.17 As shown in , the middle common capacitor electrode CCPEb can be connected to the lower common capacitor electrode CCPEa through the sixth type contact hole CTf penetrating the seventh interlayer insulating layer VA7. Fig.29A and Fig.29B As shown in FIG. 7 , the middle common capacitor electrode CCPEb may be connected to the lower common capacitor electrode CCPEa through a twenty-ninth contact hole CT29 and a thirtieth contact hole CT30 penetrating the seventh interlayer insulating layer VA7 .

[0259] The middle common capacitor electrode CCPEb may include at least one first extension electrode EXb1 extending in the second direction DR2 and at least one second extension electrode EXb2 extending in the first direction DR1. The second extension electrode EXb2 may have a shape branched from the first extension electrode EXb1. The first extension electrode EXb1 and the second extension electrode EXb2 may be integrally formed.

[0260] like Fig.17As shown in , the first middle capacitor electrode CPEb1 may be connected to the first lower capacitor electrode CPEa1 through a sixth type contact hole CTf penetrating the seventh interlayer insulating layer VA7. Fig.29A and Fig.29B As shown in , the first middle capacitor electrode CPEb1 may be connected to the first lower capacitor electrode CPEa1 through the twenty-third contact hole CT23, the twenty-fourth contact hole CT24, the twenty-fifth contact hole CT25, and the twenty-sixth contact hole CT26 penetrating the seventh interlayer insulating layer VA7. The first middle capacitor electrode CPEb1 may include at least one first extension electrode EXb11 extending in the second direction DR2 and at least one second extension electrode EXb12 extending in the first direction DR1. The second extension electrode EXb12 may have a shape branched from the first extension electrode EXb11. The first extension electrode EXb11 and the second extension electrode EXb12 may be formed integrally.

[0261] The first extension electrode EXb11 of the first intermediate capacitor electrode CPEb1 may be arranged adjacent to the first extension electrode EXb1 of the intermediate common capacitor electrode CCPEb. The first capacitor C1 may be formed between the intermediate common capacitor electrode CCPEb and the first intermediate capacitor electrode CPEb1. For example, the intermediate common capacitor electrode CCPEb may include a first electrode of the first capacitor C1, and the first intermediate capacitor electrode CPEb1 may include a second electrode of the first capacitor C1.

[0262] like Fig.17 As shown in , the second middle capacitor electrode CPEb2 may be connected to the second lower capacitor electrode CPEa2 through a sixth type contact hole CTf penetrating the seventh interlayer insulating layer VA7. The second middle capacitor electrode CPEb2 may include at least one first extension electrode EXb21 extending along the second direction DR2 and at least one second extension electrode EXb22 extending along the first direction DR1. The second extension electrode EXb22 may have a shape branching from the first extension electrode EXb21. The first extension electrode EXb21 and the second extension electrode EXb22 may be formed integrally.

[0263] The first extension electrode EXb21 of the second intermediate capacitor electrode CPEb2 may be arranged adjacent to the first extension electrode EXb1 of the intermediate common capacitor electrode CCPEb. The second capacitor C2 may be formed between the intermediate common capacitor electrode CCPEb and the second intermediate capacitor electrode CPEb2. For example, the intermediate common capacitor electrode CCPEb may include the second electrode of the second capacitor C2, and the second intermediate capacitor electrode CPEb2 may include the first electrode of the second capacitor C2.

[0264] like Fig.17As shown in FIG. 8 , the second data link electrode DLCE2 may be connected to the first data link electrode DLCE1 through a sixth type contact hole CTf penetrating the seventh interlayer insulating layer VA7 .

[0265] like Fig.17 As shown in , the fifth pixel connection electrode PCE5 can be connected to the fourth pixel connection electrode PCE4 through the sixth type contact hole CTf penetrating the seventh interlayer insulating layer VA7. Fig.29A and Fig.29B As shown in , the fifth pixel connection electrode PCE5 may be connected to the fourth pixel connection electrode PCE4 through the twenty-seventh contact hole CT27 and the twenty-eighth contact hole CT28 penetrating the seventh interlayer insulating layer VA7.

[0266] The twenty-third to thirtieth contact holes CT23 to CT30 may belong to the sixth type contact holes CTf.

[0267] The ninth pattern layer 109 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the ninth pattern layer 109 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0268] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the ninth pattern layer 109 and the inner wall of the sixth type contact hole CTf. The bonding layer may be used to improve the bonding strength between the ninth pattern layer 109 and the inner wall of the sixth type contact hole CTf (e.g., the material of the seventh interlayer insulating layer VA7). The diffusion barrier layer may be used to prevent the diffusion of the ninth pattern layer 109 (e.g., the metal layer) in the sixth type contact hole CTf. The bonding layer may be arranged between the inner wall of the sixth type contact hole CTf and the ninth pattern layer 109. The diffusion barrier layer may be arranged between the bonding layer and the ninth pattern layer 109.

[0269] The bonding layer may include, for example, titanium.The diffusion barrier layer may include a titanium nitride layer.

[0270] like Fig.29A and Fig.29B As shown in FIG. 1 , the eighth interlayer insulating layer VA8 may be arranged on the ninth pattern layer 109. For example, the eighth interlayer insulating layer VA8 may be arranged on the entire surface of the substrate SUB including the intermediate common capacitor electrode CCPEb, the first intermediate capacitor electrode CPEb1, the second intermediate capacitor electrode CPEb2, the second data link electrode DLCE2, and the fifth pixel connection electrode PCE5 described above.

[0271] The eighth interlayer insulating layer VA8 may include the same material as the first interlayer insulating layer VA1 described above.

[0272] like Fig.18 , Fig.29A and Fig.29B As shown in , the tenth pattern layer 110 may be arranged on the eighth interlayer insulating layer VA8. Fig.18 In the example shown in , the tenth pattern layer 110 may include an upper common capacitor electrode CCPEc, a first upper capacitor electrode CPEc1, a second upper capacitor electrode CPEc2, a third data link electrode DLCE3, and a sixth pixel link electrode PCE6. As an example, Fig.29A and Fig.29B It is shown that the first upper capacitor electrode CPEc1 , the upper common capacitor electrode CCPEc, the sixth pixel connection electrode PCE6 , and the second upper capacitor electrode CPEc2 are arranged on the eighth interlayer insulating layer VA8 .

[0273] The first upper capacitor electrode CPEc1 may have the same shape and the same size (eg, the same size in the first, second, and third directions DR1, DR2, and DR3) as the first intermediate capacitor electrode CPEb1, and the entire first upper capacitor electrode CPEc1 may overlap the entire first intermediate capacitor electrode CPEb1.

[0274] The upper common capacitor electrode CCPEc may have the same shape and the same size (e.g., the same size in the first direction DR1, the second direction DR2, and the third direction DR3) as the middle common capacitor electrode CCPEb described above. The entire upper common capacitor electrode CCPEc may overlap the entire middle common capacitor electrode CCPEb.

[0275] The second upper capacitor electrode CPEc2 may have the same shape and the same size as the second intermediate capacitor electrode CPEb2 (e.g., the same size in the first direction DR1, the second direction DR2, and the third direction DR3). The entire second upper capacitor electrode CPEc2 may overlap the entire second intermediate capacitor electrode CPEb2.

[0276] like Fig.18 As shown in , the upper common capacitor electrode CCPEc can be connected to the middle common capacitor electrode CCPEb through the seventh type contact hole CTg penetrating the eighth interlayer insulating layer VA8. Fig.29A and Fig.29B As shown in , the upper common capacitor electrode CCPEc may be connected to the middle common capacitor electrode CCPEb through the thirty-seventh and thirty-eighth contact holes CT37 and CT38 penetrating the eighth interlayer insulating layer VA8.

[0277] The upper common capacitor electrode CCPEc may include at least one first extension electrode EXc1 extending in the second direction DR2 and at least one second extension electrode EXc2 extending in the first direction DR1. The second extension electrode EXc2 may have a shape branched from the first extension electrode EXc1. The first extension electrode EXc1 and the second extension electrode EXc2 may be integrally formed.

[0278] like Fig.18 As shown in , the first upper capacitor electrode CPEc1 may be connected to the first middle capacitor electrode CPEb1 through a seventh type contact hole CTg penetrating the eighth interlayer insulating layer VA8. Fig.29A and Fig.29B As shown in , the first upper capacitor electrode CPEc1 may be connected to the first intermediate capacitor electrode CPEb1 through the thirty-first contact hole CT31, the thirty-second contact hole CT32, the thirty-third contact hole CT33, and the thirty-fourth contact hole CT34 penetrating the eighth interlayer insulating layer VA8. The first upper capacitor electrode CPEc1 may include at least one first extension electrode EXc11 extending in the second direction DR2 and at least one second extension electrode EXc12 extending in the first direction DR1. The second extension electrode EXc12 may have a shape branched from the first extension electrode EXc11. The first extension electrode EXc11 and the second extension electrode EXc12 may be formed integrally.

[0279] The first extension electrode EXc11 of the first upper capacitor electrode CPEc1 may be arranged adjacent to the first extension electrode EXc1 of the upper common capacitor electrode CCPEc. The first capacitor C1 may be formed between the upper common capacitor electrode CCPEc and the first upper capacitor electrode CPEc1. For example, the upper common capacitor electrode CCPEc may include a first electrode of the first capacitor C1, and the first upper capacitor electrode CPEc1 may include a second electrode of the first capacitor C1.

[0280] like Fig.18 As shown in , the second upper capacitor electrode CPEc2 may be connected to the second intermediate capacitor electrode CPEb2 through a seventh type contact hole CTg penetrating the eighth interlayer insulating layer VA8. The second upper capacitor electrode CPEc2 may include at least one first extension electrode EXc21 extending in the second direction DR2 and at least one second extension electrode EXc22 extending in the first direction DR1. The second extension electrode EXc22 may have a shape branching from the first extension electrode EXc21. The first extension electrode EXc21 and the second extension electrode EXc22 may be formed integrally.

[0281] The first extension electrode EXc21 of the second upper capacitor electrode CPEc2 may be arranged adjacent to the first extension electrode EXc1 of the upper common capacitor electrode CCPEc. The second capacitor C2 may be formed between the upper common capacitor electrode CCPEc and the second upper capacitor electrode CPEc2. For example, the upper common capacitor electrode CCPEc may include the second electrode of the second capacitor C2, and the second upper capacitor electrode CPEc2 may include the first electrode of the second capacitor C2.

[0282] like Fig.18 As shown in FIG. 8 , the third data link electrode DLCE3 may be connected to the second data link electrode DLCE2 through a seventh type contact hole CTg penetrating the eighth interlayer insulating layer VA8 .

[0283] like Fig.18 As shown in , the sixth pixel connection electrode PCE6 can be connected to the fifth pixel connection electrode PCE5 through the seventh type contact hole CTg penetrating the eighth interlayer insulating layer VA8. Fig.29A and Fig.29B As shown in , the sixth pixel connection electrode PCE6 may be connected to the fifth pixel connection electrode PCE5 through the thirty-fifth contact hole CT35 and the thirty-sixth contact hole CT36 penetrating the eighth interlayer insulating layer VA8.

[0284] The thirty-first to thirty-eighth contact holes CT31 to CT38 may belong to the seventh type contact holes CTg.

[0285] The tenth pattern layer 110 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the tenth pattern layer 110 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0286] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the tenth pattern layer 110 and the inner wall of the seventh type contact hole CTg. The bonding layer may be used to improve the bonding strength between the tenth pattern layer 110 and the inner wall of the seventh type contact hole CTg (e.g., the material of the eighth interlayer insulating layer VA8). The diffusion barrier layer may be used to prevent the diffusion of the tenth pattern layer 110 (e.g., the metal layer) in the seventh type contact hole CTg. The bonding layer may be arranged between the inner wall of the seventh type contact hole CTg and the tenth pattern layer 110. The diffusion barrier layer may be arranged between the bonding layer and the tenth pattern layer 110.

[0287] The bonding layer may include, for example, titanium.The diffusion barrier layer may include a titanium nitride layer.

[0288] In one or more embodiments, all of the eighth pattern layer 108, the ninth pattern layer 109, and the tenth pattern layer 110 described above may have the same shape and the same size. Here, the size may mean a size in at least one of the first direction DR1, the second direction DR2, and the third direction DR3.

[0289] like Fig.29A and Fig.29B As shown in FIG. 1 , the ninth interlayer insulating layer VA9 may be disposed on the tenth pattern layer 110. For example, the ninth interlayer insulating layer VA9 may be disposed on the entire surface of the substrate SUB including the upper common capacitor electrode CCPEc, the first upper capacitor electrode CPEc1, the second upper capacitor electrode CPEc2, the third data link electrode DLCE3, and the sixth pixel connection electrode PCE6 described above.

[0290] The ninth interlayer insulating layer VA9 may include the same material as the first interlayer insulating layer VA1 described above.

[0291] like Fig.19 , Fig.28 , Fig.29A and Fig.29B As shown in , the eleventh pattern layer 111 may be arranged on the ninth interlayer insulating layer VA9. Fig.19 In the example shown in FIG. 1 , the eleventh pattern layer 111 may include a driving voltage line VDL, a data line DL, and a seventh pixel connection electrode PCE7 .

[0292] like Fig.28 As shown in , the driving voltage line VDL may be connected to the first upper capacitor electrode CPEc1 through an eighth type contact hole CTh penetrating the ninth interlayer insulating layer VA9. Fig.29A and Fig.29B As shown in , the driving voltage line VDL may be connected to the first upper capacitor electrode CPEc1 through a thirty-ninth contact hole CT39 penetrating the ninth interlayer insulating layer VA9 .

[0293] like Fig.28 As shown in FIG. 8 , the data line DL may be connected to the third data link electrode DLCE3 through an eighth type contact hole CTh penetrating the ninth interlayer insulating layer VA9 .

[0294] like Fig.28 As shown in , the seventh pixel connection electrode PCE7 can be connected to the sixth pixel connection electrode PCE6 through the eighth type contact hole CTh penetrating the ninth interlayer insulating layer VA9. Fig.29A and Fig.29BAs shown in FIG. 8 , the seventh pixel connection electrode PCE7 may be connected to the sixth pixel connection electrode PCE6 through the fortieth contact hole CT40 and the forty-first contact hole CT41 penetrating the ninth interlayer insulating layer VA9 .

[0295] The thirty-ninth to forty-first contact holes CT39 to CT41 may belong to the eighth type contact holes CTh.

[0296] The eleventh pattern layer 111 may include, for example, titanium (Ti) and / or aluminum (Al). In addition, the eleventh pattern layer 111 may have, for example, a multi-layer structure including titanium and aluminum as described above.

[0297] In one or more embodiments, a bonding layer and a diffusion barrier layer may be further arranged between the eleventh pattern layer 111 and the inner wall of the eighth type contact hole CTh. The bonding layer may be used to improve the bonding strength between the eleventh pattern layer 111 and the inner wall of the eighth type contact hole CTh (e.g., the material of the ninth interlayer insulating layer VA9). The diffusion barrier layer may be used to prevent the diffusion of the eleventh pattern layer 111 (e.g., the metal layer) in the eighth type contact hole CTh. The bonding layer may be arranged between the inner wall of the eighth type contact hole CTh and the eleventh pattern layer 111. The diffusion barrier layer may be arranged between the bonding layer and the eleventh pattern layer 111.

[0298] The bonding layer may include, for example, titanium.The diffusion barrier layer may include a titanium nitride layer.

[0299] like Fig.29A and Fig.29B As shown in FIG. 1 , the tenth interlayer insulating layer VA10 may be disposed on the eleventh pattern layer 111. For example, the tenth interlayer insulating layer VA10 may be disposed on the entire surface of the substrate SUB including the driving voltage line VDL, the data line DL, and the seventh pixel connection electrode PCE7 described above.

[0300] The tenth interlayer insulating layer VA10 may include the same material as the first interlayer insulating layer VA1 described above.

[0301] like Fig.29A and Fig.29B As shown in , the light emitting element layer EMTL including the pixel electrode PE such as the eleventh pattern layer 111 may be arranged on the tenth interlayer insulating layer VA10. The pixel electrode PE may be connected to the seventh pixel connection electrode PCE7 through the ninth type contact hole penetrating the tenth interlayer insulating layer VA10. In other words, the pixel electrode PE may be connected to the seventh pixel connection electrode PCE7 through the forty-second contact hole CT42 penetrating the tenth interlayer insulating layer VA10. The forty-second contact hole CT42 may belong to the ninth type contact hole.

[0302] The light emitting element layer EMTL may include a plurality of light emitting elements LEL having a plurality of pixel electrodes PE and a dam PDL (or pixel defining layer) defining a plurality of emission areas EA.

[0303] The plurality of light emitting elements LEL may include, for example, a first light emitting element (e.g., a first light emitting element LEL), a second light emitting element, and a third light emitting element. The first light emitting element LEL may include a first pixel electrode (e.g., a first pixel electrode PE), a first light emitting layer (e.g., a first light emitting layer EL), and a common electrode CM. The second light emitting element may include a second pixel electrode, a second light emitting layer, and a common electrode CM. The third light emitting element may include a third pixel electrode, a third light emitting layer, and a common electrode CM.

[0304] The first emission region (e.g., first emission region EA) in which the first pixel electrode PE, the first light emitting layer EL, and the common electrode CM are sequentially stacked indicates a region in which holes from the first pixel electrode PE and electrons from the common electrode CM are combined with each other in the first light emitting layer EL to emit light. In this case, the first pixel electrode PE may be an anode electrode of the first light emitting element LEL, and the common electrode CM may be a cathode electrode of the first light emitting element LEL.

[0305] In a top emission structure that emits light toward the common electrode CM relative to the first light emitting layer EL, the first pixel electrode PE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0306] The dam PDL (or pixel defining layer) may define the emission area EA of each pixel PX. To this end, the dam PDL may be arranged to expose, for example, a partial area of ​​each of the first pixel electrode PE, the second pixel electrode, and the third pixel electrode on the tenth interlayer insulating layer VA10. The dam PDL may cover the edge of each of the first pixel electrode PE, the second pixel electrode, and the third pixel electrode. In one or more embodiments, the dam PDL may be arranged in the sixth type contact hole CTf (for example, the twenty-ninth contact hole CT29) penetrating the seventh interlayer insulating layer VA7. Accordingly, the twenty-ninth contact hole CT29 penetrating the seventh interlayer insulating layer VA7 may be filled with the dam PDL. The dam PDL may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, and / or the like.

[0307] like FIG. 29A to FIG. 29BAs shown in , the spacer SPC may be arranged on the dam PDL. The spacer SPC may be used to support a mask during a process of manufacturing a light-emitting layer (e.g., a first light-emitting layer EL). The spacer SPC may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, and / or the like.

[0308] The first light emitting layer EL may be formed on the first pixel electrode PE. The first light emitting layer EL may include an organic material to emit light of a desired color (e.g., a predetermined color). For example, the first light emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a desired light (e.g., a predetermined light), and may be formed using a phosphorescent material or a fluorescent material.

[0309] For example, the organic material layer of the first light-emitting layer EL in the first emission area EA that emits light of a first color (e.g., blue) may include a phosphorescent material including a host material having CBP and / or mCP and a doping material having (4,6-F2ppy)2Irpic or L2BD111, but the present disclosure is not limited thereto.

[0310] The organic material layer of the second light-emitting layer of the second emission region emitting light of a second color (eg, green) may include a host material including CBP and / or mCP and an organic material including Ir(ppy). 3 Alternatively, the organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may include tris(8-hydroxyquinoline)aluminum (Alq 3 ) of the fluorescent material, but the present disclosure is not limited thereto.

[0311] For example, the organic material layer of the third light-emitting layer of the third emission region emitting light of a third color (e.g., red) may be a phosphorescent material including a host material including carbazole biphenyl (CBP) or mCP (1,3-bis(carbazole-9-yl)) and a dopant including at least one selected from the group consisting of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline)iridium) and PtOEP (octaethylporphyrin platinum). Alternatively, the organic material layer of the third light-emitting layer of the third light-emitting region may be a phosphorescent material including PBD:Eu(DBM) 3 The present invention may include fluorescent materials of phenanthracene or perylene, but the present disclosure is not limited thereto.

[0312] The common electrode CM may be arranged on the first light emitting layer EL, the second light emitting layer, and the third light emitting layer. The common electrode CM may be arranged to cover the first light emitting layer EL, the second light emitting layer, and the third light emitting layer. The common electrode CM may be a common layer commonly arranged on the first light emitting layer EL, the second light emitting layer, and the third light emitting layer. A covering layer may be formed on the common electrode CM.

[0313] In the top emission structure, the common electrode CM may be formed of a transparent conductive material (TCO) such as ITO and / or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of the semi-transmissive conductive material, the light emitting efficiency may be increased due to the microcavity effect.

[0314] The encapsulation layer ENC may be formed on the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer (e.g., a first inorganic encapsulation layer TFE1 and a second inorganic encapsulation layer TFE3) to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0315] The first inorganic encapsulation layer TFE1 may be arranged on the common electrode CM, the organic encapsulation layer TFE2 may be arranged on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be arranged on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed by a multilayer in which one or more inorganic layers of silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The organic encapsulation layer TFE2 may be an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, and / or the like.

[0316] In one or more embodiments, reference is made to Figures 30 to 37 Describe the light emitting element LEL (e.g. Fig.29A and Fig.29B Another structure of the first light emitting element LEL).

[0317] Fig.30 is a cross-sectional view showing a structure of a display element according to one or more embodiments, and Figure 31 to Figure 34 is a cross-sectional view showing a structure of a light emitting element LEL according to one or more embodiments.

[0318] Reference Fig.30The light emitting element LEL (eg, organic light emitting diode) according to one or more embodiments may include a pixel electrode 201 , a common electrode 205 , and an intermediate layer 203 between the pixel electrode 201 and the common electrode 205 described above.

[0319] The pixel electrode 201 may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). The pixel electrode 201 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and / or a compound thereof. For example, the pixel electrode 201 may have a three-layer structure of ITO / Ag / ITO.

[0320] The common electrode 205 may be arranged on the intermediate layer 203. The common electrode 205 may include a low work function metal, an alloy, a conductive compound, and / or any combination thereof. For example, the common electrode 205 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, and / or any combination thereof. The common electrode 205 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0321] The intermediate layer 203 may include a high molecular material or a low molecular material emitting light of a desired color (eg, a predetermined color). In addition to various organic materials, the intermediate layer 203 may include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0322] In one or more embodiments, the intermediate layer 203 may include a light-emitting layer and a first functional layer and a second functional layer disposed below and above the light-emitting layer, respectively. The first functional layer may include, for example, a hole transport layer HTL (e.g., see Fig.35 ), or may include a hole transport layer HTL and a hole injection layer HIL (eg, referring to Fig.35 ). The second functional layer is a component disposed on the light emitting layer and is optional. For example, the intermediate layer 203 may include or may not include the second functional layer. The second functional layer may include an electron transport layer ETL (for example, refer to Fig.35 ) and / or an electron injection layer EIL (for example, see Fig.35 ).

[0323] In one or more embodiments, the intermediate layer 203 may include two or more light emitting units sequentially stacked between the pixel electrode 201 and the common electrode 205 and a charge generation layer CGL disposed between the two light emitting units. When the intermediate layer 203 includes the light emitting unit and the charge generation layer CGL, the light emitting element LEL (e.g., an organic light emitting diode) may be a tandem light emitting element. The light emitting element LEL (e.g., an organic light emitting diode) may improve color purity and light emitting efficiency by having a stacked structure of a plurality of light emitting units.

[0324] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer disposed below and above the light-emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The luminous efficiency of an organic light-emitting diode, which is a tandem light-emitting element having a plurality of light-emitting layers, may be further increased by the negative charge generation layer and the positive charge generation layer.

[0325] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0326] In one or more embodiments, Fig.31 As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1 including a first light emitting layer EL1 and a second light emitting unit EU2 including a second light emitting layer EL2, which are sequentially stacked. The charge generation layer CGL may be arranged between the first light emitting unit EU1 and the second light emitting unit EU2. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a charge generation layer CGL, a second light emitting layer EL2, and a common electrode 205, which are sequentially stacked. The first functional layer and the second functional layer may be arranged on and below the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be included below and above the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0327] In one or more embodiments, Fig.32As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1 and a third light emitting unit EU3 including a first light emitting layer EL1, and a second light emitting unit EU2 including a second light emitting layer EL2. The first charge generation layer CGL1 may be arranged between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be arranged between the second light emitting unit EU2 and the third light emitting unit EU3. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generation layer CGL1, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked sequentially. The first functional layer and the second functional layer may be arranged on and below the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be arranged on and below the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0328] In one or more embodiments, in the light emitting element LEL (e.g., an organic light emitting diode), in addition to the second light emitting layer EL2, the second light emitting unit EU2 may further include a third light emitting layer EL3 and / or a fourth light emitting layer EL4 directly contacting the second light emitting layer EL2 below and / or above the second light emitting layer EL2. Here, direct contact may mean that no other layer is arranged between the second light emitting layer EL2 and the third light emitting layer EL3 and / or between the second light emitting layer EL2 and the fourth light emitting layer EL4. The third light emitting layer EL3 may be a red light emitting layer, and the fourth light emitting layer EL4 may be a green light emitting layer.

[0329] For example, Fig.33 As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode 201, a first light emitting layer EL1, a first charge generation layer CGL1, a third light emitting layer EL3, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode 205 stacked sequentially. Alternatively, as Fig.34 As shown in the figure, the light-emitting element LEL (e.g., an organic light-emitting diode) may include a pixel electrode 201, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1 and a common electrode 205 stacked sequentially.

[0330] Fig.35 It is shown Fig.33 A cross-sectional view of an example of an organic light emitting diode, and Fig.36 It is shown Fig.34 A cross-sectional view of an example of an organic light emitting diode.

[0331] Reference Fig.35 , the light emitting element LEL (e.g., an organic light emitting diode) may include a first light emitting unit EU1, a second light emitting unit EU2, and a third light emitting unit EU3 stacked sequentially. The first charge generation layer CGL1 may be arranged between the first light emitting unit EU1 and the second light emitting unit EU2, and the second charge generation layer CGL2 may be arranged between the second light emitting unit EU2 and the third light emitting unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0332] The first light emitting unit EU1 may include a blue light emitting layer BEML. The first light emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 201 and the blue light emitting layer BEML. In one or more embodiments, a p-doped layer may further be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. In one or more embodiments, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer may increase the light emission efficiency of the blue light emitting layer BEML. The blue light auxiliary layer may increase the light emission efficiency of the blue light emitting layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the light emitting layer.

[0333] The second light emitting unit EU2 may include a yellow light emitting layer YEML and a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML. The second light emitting unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may also include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0334] The third light-emitting unit EU3 may include a blue light-emitting layer BEML. The third light-emitting unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light-emitting layer BEML. The third light-emitting unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue light-emitting layer BEML and the common electrode 205. The electron transport layer ETL may have a single layer and / or multiple layers. In one or more embodiments, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may also be included between the blue light-emitting layer BEML and the hole transport layer HTL. At least one of the hole blocking layer and the buffer layer may also be included between the blue light-emitting layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0335] Fig.36 The light emitting element LEL (e.g., organic light emitting diode) shown in FIG. Fig.35 The light emitting element LEL (eg, organic light emitting diode) shown in FIG. 1 is different in the stacking structure of the second light emitting unit EU2, and the other configurations are the same. Fig.36 , the second light emitting unit EU2 may include a green light emitting layer GEML, a red light emitting layer REML directly contacting the green light emitting layer GEML below the green light emitting layer GEML, and a yellow light emitting layer YEML directly contacting the green light emitting layer GEML above the green light emitting layer GEML. The second light emitting unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may also include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0336] Fig.37 is a cross-sectional view illustrating a structure of a pixel of a display device according to one or more embodiments.

[0337] Reference Fig.37 , the display device 10 (for example, referring to Figure 2 ) of the display panel 100 (for example, see Figure 2 ) may include a plurality of pixels. The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode 201, a common electrode 205, and an intermediate layer 203. In one or more embodiments, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0338] The pixel electrode 201 may be independently provided in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0339] The intermediate layer 203 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first light emitting unit EU1 and a second light emitting unit EU2 stacked sequentially and a charge generation layer CGL between the first light emitting unit EU1 and the second light emitting unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0340] The first light emitting unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. The first light emitting unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. The first light emitting unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 201. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first light emitting unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0341] The second light emitting unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second light emitting unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second light emitting unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second light emitting unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In one or more embodiments, in the second light emitting unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3, at least one of a hole blocking layer and a buffer layer may be further included between the light emitting layer and the electron transport layer ETL.

[0342] The thickness H1 of the red light emitting layer REML, the thickness H2 of the green light emitting layer GEML, and the thickness H3 of the blue light emitting layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as the hole transport layer HTL.

[0343] exist Fig.37 In the embodiment, the auxiliary layer AXL may be disposed only in the first pixel PX1, but the present disclosure is not limited thereto. For example, the auxiliary layer AXL may be disposed in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0344] The display panel 100 of the display device 10 may further include a cover layer 207 disposed outside the common electrode 205. The cover layer 207 may be used to improve the light emitting efficiency through the principle of constructive interference. Accordingly, the light extraction efficiency of the light emitting element LEL (e.g., organic light emitting diode) may be increased, so that the light emitting efficiency of the light emitting element LEL (e.g., organic light emitting diode) may be improved.

[0345] Fig.38 is a diagram showing an example of a virtual reality device including a display device according to one or more embodiments. Fig.38 FIG. 1 shows a virtual reality device 1 to which a display device 10_1 according to one or more embodiments is applied. Here, the display device 10_1 may be, for example, a device including the one described above. Figures 1 to 37 A display device of a component.

[0346] Reference Fig.38 The virtual reality device 1 according to one or more embodiments may be a glasses-type device. The virtual reality device 1 according to one or more embodiments may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device memory 50.

[0347] Although Fig.38 The virtual reality device 1 including the temples 30a and 30b is shown, but the virtual reality device 1 according to one or more embodiments may be applied to a head mounted display including a headband wearable on the head instead of the temples 30a and 30b. That is, the virtual reality device 1 according to one or more embodiments is not limited to Fig.38 The virtual reality device 1 shown in FIG. 1 can be applied to various electronic devices in various forms.

[0348] The display device storage 50 may include a display device 10_1 and a reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Accordingly, the user may observe the virtual reality image displayed on the display device 10_1 through the right eye.

[0349] Fig.38 The display device memory 50 is shown to be arranged at the right end of the support frame 20, but the present disclosure is not limited thereto. For example, the display device memory 50 may be arranged at the left end of the support frame 20, and in this case, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the left eye of the user through the left lens 10a. Accordingly, the user may observe the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device memory 50 may be arranged at both the left and right ends of the support frame 20. In that case, the user may observe the virtual reality image displayed on the display device 10_1 through the left eye and the right eye.

[0350] Fig.39 and Fig.40 It is a diagram for explaining the effects of the present disclosure.

[0351] exist Fig.39 and Fig.40 In FIG. 1 , “Ref 60 Hz” on the X-axis refers to a case where the display device is driven at 60 Hz (eg, a first standard). For example, the first standard refers to a retention rate of a driving current (IEL) required when the display device is driven at 60 Hz.

[0352] exist Fig.39 In FIG. 1 , “Ref 10 Hz” on the X-axis refers to a case where the display device is driven at 10 Hz (eg, the second standard). For example, the second standard refers to a retention rate of a driving current required when the display device is driven at 10 Hz.

[0353] exist Fig.40 In FIG. 1 , “Ref 1 Hz” on the X-axis refers to a case where the display device is driven at 1 Hz (eg, the third standard). For example, the third standard refers to a retention rate of a driving current required when the display device is driven at 1 Hz.

[0354] exist Fig.39 In the figure, "①_T2 10Hz" on the X-axis refers to when Figure 5 A case where the display device is driven at 10 Hz when the driving transistor TD, the compensation transistor TC, the emission control transistor TE and the initialization transistor TI include non-oxide semiconductors (e.g., low-temperature polycrystalline silicon (LTPS) semiconductors) and only the switching transistor TS includes an oxide-based semiconductor (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0355] exist Fig.39 In the figure, "①_T3 10Hz" on the X-axis refers to when Figure 5 A case where the display device is driven at 10 Hz when the driving transistor TD, the switching transistor TS, the emission control transistor TE and the initialization transistor TI include non-oxide semiconductors (e.g., low-temperature polycrystalline silicon (LTPS) semiconductors) and only the compensation transistor TC includes an oxide-based semiconductor (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0356] exist Fig.39 In the figure, "①_T4 10Hz" on the X-axis refers to when Figure 5 A case where the display device is driven at 10 Hz when the driving transistor TD, the switching transistor TS, the compensation transistor TC and the initialization transistor TI include non-oxide semiconductors (e.g., low-temperature polycrystalline silicon (LTPS) semiconductors) and only the emission control transistor TE includes an oxide-based semiconductor (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0357] exist Fig.39 In the figure, "①_T5 10Hz" on the X-axis refers to when Figure 5 A case where the display device is driven at 10 Hz when the driving transistor TD, the switching transistor TS, the compensation transistor TC and the emission control transistor TE include non-oxide semiconductors (e.g., low-temperature polycrystalline silicon (LTPS) semiconductors) and only the initialization transistor TI includes an oxide-based semiconductor (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0358] exist Fig.39 In the figure, "①_T2 / 3 10Hz" on the X-axis refers to when Figure 5 A case where the display device is driven at 10 Hz when the driving transistor TD, the emission control transistor TE and the initialization transistor TI include a non-oxide semiconductor (e.g., a low-temperature polycrystalline silicon (LTPS) semiconductor) and the switching transistor TS and the compensation transistor TC include an oxide-based semiconductor (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0359] exist Fig.40 In the figure, "②_T2 / 3 1Hz" on the X-axis refers to when Figure 5A case where the display device is driven at 1 Hz when the driving transistor TD, the emission control transistor TE and the initialization transistor TI include non-oxide semiconductors (e.g., low-temperature polycrystalline silicon (LTPS) semiconductors) and the switching transistor TS and the compensation transistor TC include oxide-based semiconductors (e.g., indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO)).

[0360] In one or more embodiments, Fig.39 and Fig.40 The Y-axis on the left side of FIG. 1 refers to the retention rate of the driving current (IEL) flowing through the light emitting element in each case described above, and Fig.39 The Y-axis on the right side of the diagram refers to the value of the drive current.

[0361] In addition, for example, Fig.39 and Fig.40 The curve corresponding to “@maximum current” in FIG. 1 refers to the retention rate of the driving current and the value of the driving current for each case at a data voltage of 0V.

[0362] In addition, for example, Fig.39 and Fig.40 The curve corresponding to “@38G” in FIG. 1 refers to the retention rate of the driving current and the value of the driving current for each case at a data voltage of 38 gray levels.

[0363] In addition, for example, Fig.39 and Fig.40 The curve corresponding to “white current (A)” in FIG. 1 refers to the retention rate of the driving current and the value of the driving current for each case at the data voltage of the white gray level.

[0364] like Fig.39 As shown in , when the switching transistor TS and the compensation transistor TC each include an oxide-based semiconductor, the retention rate of the driving current of the display device can be substantially similar to the retention rate of the driving current of the first standard (i.e., the display device driven at 60 Hz) despite being driven at 10 Hz. In other words, since the leakage current is reduced when the switching transistor TS and the compensation transistor TC each include an oxide-based semiconductor, the retention rate of the driving current in one frame period is increased even at a low-speed drive of, for example, 10 Hz, so that the image quality can be improved.

[0365] In addition, if Fig.40As shown in , when the switching transistor TS and the compensation transistor TC each include an oxide-based semiconductor, the retention rate of the driving current of the display device can be substantially similar to the retention rate of the driving current of the first standard (i.e., the display device driven at 60 Hz) despite driving at 1 Hz. In other words, since the leakage current is reduced when the switching transistor TS and the compensation transistor TC each include an oxide-based semiconductor, the retention rate of the driving current in one frame period is increased even at a low-speed drive of, for example, 1 Hz, so that the image quality can be improved.

Claims

1. A display device, characterized in that: include: substrate; A field effect transistor, the field effect transistor being on the substrate; an oxide-based transistor on a different layer from the field effect transistor and connected to the field effect transistor through a contact hole in the insulating layer; as well as A pixel electrode is provided on the oxide-based transistor.

2. The display device according to claim 1, wherein: The field effect transistor includes a metal oxide semiconductor field effect transistor.

3. The display device according to claim 1, wherein: The substrate includes a silicon substrate.

4. The display device according to claim 1, wherein: The field effect transistor includes a driving transistor including a gate electrode connected to a first node, a source electrode connected to a driving voltage line, and a drain electrode connected to a second node.

5. The display device according to claim 4, characterized in that The field effect transistor also includes an emission control transistor including a gate electrode connected to an emission control line, a source electrode connected to the second node, and a drain electrode connected to the pixel electrode.

6. The display device according to claim 5, characterized in that The field effect transistor further includes an initialization transistor including a gate electrode connected to the third gate line, a source electrode connected to the pixel electrode, and a drain electrode connected to the ground.

7. The display device according to claim 4, characterized in that The oxide-based transistor includes a switching transistor including a gate electrode connected to a first gate line, a drain electrode connected to a data line, and a source electrode connected to the first node.

8. The display device according to claim 7, characterized in that The oxide-based transistor further includes a compensation transistor including a gate electrode connected to a second gate line, a drain electrode connected to the first node, and a source electrode connected to the second node.

9. The display device according to claim 7, wherein: Also includes: A first capacitor is connected between the driving voltage line and the first node.

10. The display device according to claim 9, characterized in that Also includes: A second capacitor is connected between the source electrode of the switching transistor and the first node.

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