A multi-system, multi-channel digital TR synchronization circuit

Abstract

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

Description

Technical Field

[0001] This utility model belongs to the field of digital TR synchronization technology, specifically a multi-system, multi-channel digital TR synchronization circuit. Background Technology

[0002] In electronic systems such as radar detection, multi-channel digital transmit / receive (TR) technology is increasingly widely used. Multi-channel synchronization, as a core function of digital TR systems, directly affects the system's phase consistency, thus determining beamforming accuracy and signal processing performance. Current technologies face numerous challenges in achieving synchronization within and between multi-channel digital TR boards:

[0003] Traditional hardware synchronization methods are affected by factors such as circuit delays and component differences, resulting in significant phase deviations between channels. This is particularly true for inter-board ADCs (analog-to-digital converters), DACs (digital-to-analog converters), and FPGAs (field-programmable gate arrays), where the startup synchronization accuracy is low, impacting subsequent signal processing quality. Hardware synchronization solutions require complex timing designs, are difficult to implement internally within FPGAs, and necessitate redesigning the hardware architecture when expanding to multiple systems, leading to poor compatibility. Single-system synchronization designs are difficult to directly extend to multi-system scenarios; adding a subsystem requires reconstructing the synchronization reference, resulting in high system integration costs and long development cycles.

[0004] Therefore, there is an urgent need for a multi-system, multi-channel digital TR synchronization scheme that is simple in design, has high synchronization accuracy, and is easy to expand, in order to meet the high-performance signal processing requirements of modern radar systems. Utility Model Content

[0005] The purpose of this invention is to provide a multi-system, multi-channel digital TR synchronization circuit to solve the problems of low accuracy and difficulty in expansion in the existing synchronization technology mentioned in the background art.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0007] A multi-system, multi-channel digital TR synchronization circuit includes a GPS / BD timing module, a system clock source, several multi-channel digital TR boards, and a system lead generation device; wherein, the rubidium clock output port of the GPS / BD timing module is connected to the reference clock input port of the system clock source, and the second pulse output port of the GPS / BD timing module is connected to the synchronization input port of the system lead generation device;

[0008] The sampling system clock output port and the lead clock output port of the system clock source are connected to the sampling clock input port and the lead clock input port of each multi-channel digital TR board, respectively; the lead signal generation port of the system lead generation device is connected to the lead signal input port of each multi-channel digital TR board.

[0009] The system lead clock output port of the system clock source is connected to the lead signal input port of the system lead generator.

[0010] According to the above technical solution, the system clock source includes a sampling system clock and a lead clock; wherein, the sampling system clock is used to provide a unified working clock for other chips; and the lead clock is used to provide a reference clock for the analysis of the lead signal.

[0011] According to the above technical solution, the output port of the sampling system clock is connected to the sampling clock input port of each multi-channel digital TR board, and the lead clock output port is connected to the lead clock input port of each multi-channel digital TR board and the lead clock input port of the system lead generation device, respectively.

[0012] According to the above technical solution, the multi-channel digital TR board includes an ADC chip, a DAC chip, a clock chip, and an FPGA chip; wherein, the sampling system clock is connected to the clock chip; and the lead clock is connected to the FPGA chip of the multi-channel digital TR board.

[0013] According to the above technical solution, the clock chip is connected to the ADC chip, DAC chip and FPGA chip respectively. The clock chip is used to divide the sampling system clock of the system clock source into multiple sampling clocks and distribute clock signals to the ADC chip, DAC chip and FPGA chip.

[0014] According to the above technical solution, the FPGA chip is also connected to the SYNC input interface of the ADC chip and the DAC chip respectively. The FPGA chip is used to analyze the lead signal based on the lead clock to generate a synchronization signal, so as to control the synchronous acquisition of the ADC chip and the synchronous transmission of the DAC chip.

[0015] According to the above technical solution, the system lead generation device generates a periodic lead signal based on the lead clock input from the system clock source and the second pulse input from the GPS / BD timing module. The period of the lead signal matches the frequency of the lead clock and is used to trigger each multi-channel digital TR board to perform synchronization operation.

[0016] According to the above technical solution, the rubidium clock of the GPS / BD timing module is used to provide a high-precision reference clock for the system clock source, ensuring the long-term stability of the sampling system clock and the lead clock output by the system clock source; the second pulse is used to provide a trigger reference for the system lead generation device, ensuring the consistency of the time reference of the lead signal.

[0017] Furthermore, the FPGA chip has a built-in pre-lead synchronization unit for sampling and parsing the pre-lead signal. When the time difference between the pre-lead signal and each multi-channel digital TR board is within the pre-lead clock cycle, the ADC chip and DAC chip are triggered to start synchronously.

[0018] Furthermore, the clock chip, ADC chip, and DAC chip support multi-chip synchronization. The clock signal and pre-signal between the system clock source and each multi-channel digital TR board are designed with equal length to ensure consistent signal transmission delay.

[0019] Furthermore, when a new subsystem is added, the system synchronization reference is expanded by adding a GPS / BD timing module, and the multi-channel digital TR board realizes the synchronization control after the system expansion through the synchronization parsing function of the FPGA chip.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] In this invention, the rubidium clock and second pulse of the GPS / BD timing module are used as the reference, and the accuracy of the leading clock determines the synchronization accuracy (e.g., when the leading clock is 20MHz, the synchronization error can be controlled within 50ns). Multiple systems can be expanded by adding a GPS / BD timing module, and each subsystem uses a unified timing reference without requiring hardware architecture reconstruction. The hardware-software combined synchronization scheme reduces the internal logic complexity of the FPGA, and reduces hardware development costs by relying on the chip's inherent synchronization function and equal-length wiring design. Same-source clock allocation and equal-length signal design avoid clock skew and phase errors, ensuring the stability of multi-channel synchronous operation. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall principle of this utility model;

[0023] Figure 2 This is a block diagram illustrating the internal working principle of the multi-channel digital TR board of this utility model. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0025] Example 1

[0026] like Figure 1 As shown, a multi-system multi-channel digital TR synchronization circuit includes a GPS / BD timing module, a system clock source, several multi-channel digital TR boards, and a system lead generation device; wherein, the rubidium clock output port of the GPS / BD timing module is connected to the reference clock input port of the system clock source, and the second pulse output port of the GPS / BD timing module is connected to the synchronization input port of the system lead generation device.

[0027] The sampling system clock output port and the lead clock output port of the system clock source are connected to the sampling clock input port and the lead clock input port of each multi-channel digital TR board, respectively; the lead signal generation port of the system lead generation device is connected to the lead signal input port of each multi-channel digital TR board.

[0028] The system lead clock output port of the system clock source is connected to the lead signal input port of the system lead generator.

[0029] In this invention, the rubidium clock and second pulse of the GPS / BD timing module are used as the reference, and the accuracy of the leading clock determines the synchronization accuracy (e.g., when the leading clock is 20MHz, the synchronization error can be controlled within 50ns). Multiple systems can be expanded by adding a GPS / BD timing module, and each subsystem uses a unified timing reference without requiring hardware architecture reconstruction. The hardware-software combined synchronization scheme reduces the internal logic complexity of the FPGA, and reduces hardware development costs by relying on the chip's inherent synchronization function and equal-length wiring design. Same-source clock allocation and equal-length signal design avoid clock skew and phase errors, ensuring the stability of multi-channel synchronous operation.

[0030] Example 2

[0031] This embodiment is a further refinement of Embodiment 1.

[0032] In this embodiment, the workflow of the multi-system, multi-channel digital TR synchronization circuit is as follows:

[0033] Timing reference establishment: The rubidium clock output of the GPS / BD timing module is sent to the external reference clock input port of the system clock source to synchronize the lead clock of the system clock source and the sampling system clock with the rubidium clock; the second pulse (PPS) is output to the synchronization input port of the system lead generation device as the trigger reference for the lead signal.

[0034] Clock signal distribution: The sampling system clock of the system clock source is divided into multiple paths by the clock chip and supplied to the ADC chip, DAC chip and FPGA chip respectively; the lead clock is directly input to the FPGA chip as the clock reference for lead signal analysis.

[0035] Lead signal generation and transmission: The system lead generation device generates a lead signal based on the lead clock and second pulse, and sends it to the lead signal input port of each multi-channel digital TR board through equal-length signal lines.

[0036] Synchronous control execution: The FPGA chip samples the lead signal using the lead clock, generates a synchronization signal by parsing the lead synchronization unit, and connects it to the SYNC input interface of the ADC chip and DAC chip to realize synchronous acquisition of the ADC channel and synchronous transmission of the DAC channel.

[0037] Example 3

[0038] This embodiment is a further refinement of Embodiment 2, illustrating the implementation method of multi-chip synchronization:

[0039] The clock chip's synchronization function: It receives the sampling system clock and the leading clock from the system clock source, and through internal frequency division and buffer circuits, provides clock signals of the same source and equal amplitude to the ADC chip, DAC chip and FPGA chip to ensure that the clock phases of the chips are consistent.

[0040] Synchronous Triggering of ADC and DAC: After the FPGA chip parses the preamble signal, the generated synchronization signal simultaneously triggers all acquisition channels of the ADC chip and all transmission channels of the DAC chip, synchronizing all ADC and DAC channels in the entire system. The FPGA uses the preamble signal as a start flag for system applications, ensuring that data processing begins synchronously, thereby achieving synchronous acquisition of all ADC channels and synchronous transmission of all DAC channels, completing the synchronization function of the entire system. Because the clocks are from the same source and the signal transmission delays are consistent, nanosecond-level synchronization between channels is achieved.

[0041] This embodiment is a further refinement of Embodiment 2, illustrating the specific process of system expansion:

[0042] New subsystem access: When a new subsystem needs to be accessed, a GPS / BD timing module 4 is added. Its rubidium clock is synchronized with the reference clock of the original system clock source, and the second pulse is connected to the extended synchronization input port of the system lead generation device.

[0043] FPGA Logic Adaptation: The FPGA chip of the multi-channel digital TR board identifies the characteristics of the lead signals of the newly added subsystems by updating the synchronous parsing program, and realizes the compatible parsing of the lead signals of multiple systems.

[0044] Synchronization accuracy guarantee: The clock signal and preamble signal of the newly added subsystem adopt the same length design as the original system to ensure that the synchronization accuracy of each subsystem is not reduced after expansion.

[0045] Signal length equalization design: The clock signal lines and lead signal lines between the system clock source and the multi-channel digital TR board are routed on the same layer and processed with equal length. Combined with differential signal transmission, the delay deviation is controlled within 1 / 10 of the lead clock cycle.

[0046] FPGA parsing logic: The parsing guide synchronization unit adopts an edge-triggered sampling mechanism to sample the rising or falling edge of the guide signal at high frequency (the sampling frequency is not less than 10 times the guide clock). Through digital filtering and phase compensation algorithms, the synchronization error caused by transmission delay is eliminated.

[0047] Multi-chip synchronization support: The selected ADC chip, DAC chip and clock chip all have built-in synchronization control interfaces (such as SYNC, CLK_IN), which support multi-chip cascading synchronization and can achieve channel expansion without additional logic circuits.

[0048] Through the above-mentioned hardware and software combination design, this utility model realizes high-precision synchronous control of multi-system multi-channel digital TR, meets the stringent requirements of electronic systems such as radar detection for synchronization performance, and at the same time has good system scalability and engineering practicality.

[0049] The modules used in this invention are all existing devices. For example, the GPS / BD timing module uses a version with rubidium clock output (e.g., UM220); the system clock source uses a system frequency synthesizer module; the FPGA chip uses XC7V690T, the ADC chip uses AD9268, the DAC chip uses AD9154, the clock chip uses LMK04828, and the system lead generation device uses a timing generator (e.g., LMK05318).

[0050] In this invention, the GPS / BD timing module connects the reference rubidium clock to the external reference interface of the system clock source module via an RF cable; the GPS / BD timing module connects the pulse-per-second (PPS) to the system lead generation device via an RS422 cable; the system clock source connects the lead clock to the system lead generation device via an RF cable; the system clock source connects the lead clock and the sampling system clock to the multi-channel digital TR board via an RF cable; the system lead generation device connects the lead signal to the multi-channel digital TR board via an RS422 cable; the sampling system clock, after passing through the clock chip LMK04828 on the digital processing board, is further divided by the internal VCO and provided to AD9268 and AD9154 respectively; AD9268 and AD9154 are connected to external signals via RF interfaces.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0052] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A multi-system multi-channel digital TR synchronization circuit, characterized by: It includes a GPS / BD timing module, a system clock source, several multi-channel digital TR boards, and a system lead generation device; wherein, the rubidium clock output port of the GPS / BD timing module is connected to the reference clock input port of the system clock source, and the second pulse output port of the GPS / BD timing module is connected to the synchronization input port of the system lead generation device; The sampling system clock output port and the lead clock output port of the system clock source are connected to the sampling clock input port and the lead clock input port of each multi-channel digital TR board, respectively; the lead signal generation port of the system lead generation device is connected to the lead signal input port of each multi-channel digital TR board. The system lead clock output port of the system clock source is connected to the lead signal input port of the system lead generator.

2. A multi-system multi-channel digital TR synchronization circuit according to claim 1, characterized in that: The system clock source includes a sampling system clock and a lead clock; the sampling system clock is used to provide a unified operating clock for other chips; the lead clock is used to provide a reference clock for lead signal analysis.

3. A multi-system multi-channel digital TR synchronization circuit according to claim 2, characterized in that: The output port of the sampling system clock is connected to the sampling clock input port of each multi-channel digital TR board, and the lead clock output port is connected to the lead clock input port of each multi-channel digital TR board and the lead clock input port of the system lead generation device, respectively.

4. A multi-system multi-channel digital TR synchronization circuit according to claim 2, characterized in that: The multi-channel digital TR board includes an ADC chip, a DAC chip, a clock chip, and an FPGA chip; the sampling system clock is connected to the clock chip; and the lead clock is connected to the FPGA chip of the multi-channel digital TR board.

5. A multi-system, multi-channel digital TR synchronization circuit according to claim 3, characterized in that: The clock chip is connected to the ADC chip, DAC chip and FPGA chip respectively. The clock chip is used to divide the sampling system clock of the system clock source into multiple sampling clocks and distribute clock signals to the ADC chip, DAC chip and FPGA chip.

6. A multi-system multi-channel digital TR synchronization circuit according to claim 5, characterized in that: The FPGA chip is also connected to the SYNC input interface of the ADC chip and the DAC chip respectively. The FPGA chip is used to analyze the lead signal based on the lead clock to generate a synchronization signal, so as to control the synchronous acquisition of the ADC chip and the synchronous transmission of the DAC chip.

7. A multi-system, multi-channel digital TR synchronization circuit according to claim 6, characterized in that: The system lead generation device generates a periodic lead signal based on the lead clock input from the system clock source and the second pulse input from the GPS / BD timing module. The period of the lead signal matches the frequency of the lead clock and is used to trigger each multi-channel digital TR board to perform synchronization operation.

8. A multi-system multi-channel digital TR synchronization circuit according to claim 7, characterized in that: The rubidium clock in the GPS / BD timing module is used to provide a high-precision reference clock for the system clock source, ensuring the long-term stability of the sampling system clock and the lead clock output by the system clock source; the second pulse is used to provide a trigger reference for the system lead generation device, ensuring the consistency of the time reference of the lead signal.

Images