Display device and electronic device including the same

Abstract

This allows testing of the data voltage output by the DEMUX switch element. [Solution] This specification discloses a display device and an electronic device including the same. A display device according to various embodiments of this specification includes a plurality of subpixels, a plurality of data lines electrically connected to the plurality of subpixels, a plurality of data pads electrically connected to the plurality of data lines, a plurality of test pads including a first test pad and a second test pad spaced apart from the plurality of data pads, a first group DEMUX switch element connecting a first group of data lines from the plurality of data lines to the plurality of data pads, a second group DEMUX switch element connecting a second group of data lines from the plurality of data lines to the plurality of data pads, and a first test switch element positioned between a first electrode of any one of the first DEMUX switch elements included in the first group DEMUX switch element and a first test pad.

Description

Technical Field

[0001] This specification relates to a display device and an electronic device including the same.

Background Art

[0002] With the development of the information society, the requirements for display devices for displaying images are becoming increasingly diverse. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation systems, and smart TVs.

[0003] Display devices include light-receiving display devices such as liquid crystal display devices, field emission display devices, and light-emitting display devices, and light-emitting display devices such as organic light-emitting display devices including organic light-emitting elements, inorganic light-emitting display devices including inorganic light-emitting elements such as inorganic semiconductors, and ultra-small light-emitting display devices including ultra-small light-emitting elements.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One problem of this specification is to provide a display device capable of testing a data voltage output by a DEMUX switch element.

[0006] The problems of this specification are not limited to those described above, and other problems not mentioned will be clearly understood by those of ordinary skill in the art from the following description.

Means for Solving the Problems

[0007] Display devices according to various embodiments of this specification include a plurality of subpixels, a plurality of data lines electrically connected to the plurality of subpixels, a plurality of data pads electrically connected to the plurality of data lines, a plurality of test pads including a first test pad and a second test pad separated from the plurality of data pads, a first group DEMUX switch element that connects a first group of data lines from the plurality of data lines to the plurality of data pads, a second group DEMUX switch element that connects a second group of data lines from the plurality of data lines to the plurality of data pads, and a first test switch element disposed between the first electrode of any one of the first DEMUX switch elements included in the first group DEMUX switch element and the first test pad.

[0008] According to various embodiments of this specification, among a plurality of first DEMUX switch elements included in the first group of DEMUX switch elements, the remaining first DEMUX switch elements, excluding any one of the first DEMUX switch elements, can be electrically isolated from the first test switch element.

[0009] According to various embodiments of this specification, a second test switch element may be provided, which is positioned between the first electrode and the second test pad of any one of the second DEMUX switch elements included in the second group of DEMUX switch elements.

[0010] According to various embodiments of this specification, among a plurality of second DEMUX switch elements included in the second group of DEMUX switch elements, the remaining second DEMUX switch elements, with the exception of one of the second DEMUX switch elements, can be electrically isolated from the second test switch element.

[0011] According to various embodiments of this specification, the gate electrode of a first test switch element and a resistor connected to the gate electrode of a second test switch element may be included.

[0012] Various embodiments of this specification may further include a plurality of data pads, a plurality of test pads, and an electrostatic discharge circuit electrically connected to resistors.

[0013] According to various embodiments of this specification, the first group of DEMUX switching elements may include a plurality of transistors connected in parallel.

[0014] According to various embodiments of this specification, the second group of DEMUX switching elements may include a plurality of transistors connected in parallel.

[0015] According to various embodiments of this specification, the first test switch element may include a plurality of transistors connected in series.

[0016] According to various embodiments of this specification, the second test switch element may include a plurality of transistors connected in series.

[0017] According to various embodiments of this specification, the plurality of subpixels include a first group subpixel connected to a first group DEMUX switch element via a first group data line, and a second group subpixel connected to a second group DEMUX switch element via a second group data line, wherein any one of the plurality of first subpixels included in the first group subpixel connected to any one of the first DEMUX switch elements embodies a first color, and any one of the plurality of second subpixels included in the second group subpixel connected to any one of the second DEMUX switch elements embodies a first color.

[0018] According to various embodiments of this specification, any one first subpixel may be connected to a first electrode of any one first DEMUX switch element, and any one second subpixel may be connected to a first electrode of any one second DEMUX switch element.

[0019] Various embodiments of this specification include an electronic device comprising a display module for displaying images, a power supply module for supplying power to the display module, and a processor for transmitting data signals and control signals to the display module, wherein the display module comprises a plurality of subpixels, a plurality of data lines electrically connected to the plurality of subpixels, a plurality of data pads electrically connected to the plurality of data lines, a plurality of test pads including a first test pad and a second test pad separated from the plurality of data pads, a first group DEMUX switch element for connecting a first group of data lines from the plurality of data lines to the plurality of data pads, a second group DEMUX switch element for connecting a second group of data lines from the plurality of data lines to the plurality of data pads, and a first test switch element positioned between the first electrode of any one of the first DEMUX switch elements included in the first group DEMUX switch element and the first test pad.

[0020] According to various embodiments of this specification, the first test switch element further includes a resistive active layer, and the first test switch element includes a first test gate electrode disposed on the first test active layer and a gate insulating film covering the first test active layer, the resistive active layer is electrically connected to the gate electrode of the first test switch element, and the first test active layer may include a first electrode connected to a first electrode of any one of the first DEMUX switch elements, a second electrode connected to a first test pad, and a channel disposed between the first electrode of the first test active layer and the second electrode of the first test active layer.

[0021] According to various embodiments of this specification, the first test active layer and the resistive active layer may be located on the same layer.

[0022] According to various embodiments of the present specification, it further includes a second test switch element disposed between the first electrode of any one of the second DEMUX switch elements included in the second group of DEMUX switch elements and the second test pad. The second test switch element includes a second test gate electrode disposed on a second test active layer and a gate insulating film covering the second test active layer. The resistive active layer is electrically connected to the gate electrode of the second test switch element. The second test active layer may include a first electrode connected to the first electrode of any one of the second DEMUX switch elements, a second electrode connected to the second test pad, and a channel disposed between the first electrode of the second test active layer and the second electrode of the first test active layer.

[0023] According to various embodiments of the present specification, the first electrode of the first test switch element is connected to the first electrode of any one of the first DEMUX switch elements via a second test connection wiring, the second electrode of the first test switch element is connected to the first test pad via a first test connection wiring, the first electrode of the second test switch element is connected to the first electrode of any one of the second DEMUX switch elements via a fourth test connection wiring, the second electrode of the second test switch element is connected to the second test pad via a third test connection wiring, and the second test connection wiring and the fourth test connection wiring may be disposed on the same layer.

[0024] According to various embodiments of the present specification, the first test connection wiring and the third test connection wiring may be disposed on different layers from each other.

[0025] According to various embodiments of the present specification, it further includes a first power supply wiring to which a first power supply voltage is applied. On a plane, the first power supply wiring may be separated from the first test switch element.

[0026] According to various embodiments of the present specification, on a plane, the first power supply wiring may be separated from the resistive active layer.

[0027] According to various embodiments of the present specification, on a plane, the first power supply wiring may overlap with the first group of DEMUX switch elements and the second group of DEMUX switch elements.

[0028] According to various embodiments of the present specification, it may further include a first resistance connection electrode connected to the resistance active layer through a plurality of first group resistance contact holes, and a second resistance connection electrode connected to the resistance active layer through a plurality of second group resistance contact holes.

[0029] According to various embodiments of the present specification, the number of contact holes connecting the first resistance connection electrode and the resistance active layer may be the same as the number of contact holes connecting the second resistance connection electrode and the resistance active layer.

[0030] According to various embodiments of the present specification, the resistance of the resistance active layer may be 1000 Ω or more and 10000 Ω or less.

[0031] According to various embodiments of the present specification, the plurality of data pads include a first data pad and a second data pad, and at least one of the plurality of DEMUX connection wirings connecting the first data pad to the first group of DEMUX switch elements may be disposed on a different layer from at least one of the plurality of DEMUX connection wirings connecting the second data pad to the first group of DEMUX switch elements.

Advantages of the Invention

[0032] According to the present invention, a display device capable of testing the data voltage output by the DEMUX switch element can be provided.

Brief Description of the Drawings

[0033] [Figure 1] It is a perspective view showing a display device according to an embodiment of the present specification. [Figure 2] It is a plan view showing a display device according to an embodiment of the present specification. [Figure 3]This is a schematic diagram illustrating an exemplary display device according to one embodiment of this specification. [Figure 4] This is a partially enlarged view illustrating a magnified portion of section J in Figure 2. [Figure 5a] This is a partially enlarged view illustrating the K portion of Figure 2. [Figure 5b] This is a partially enlarged view illustrating the L portion of Figure 5a. [Figure 5c] This is a partially enlarged view illustrating the M portion of Figure 5a. [Figure 5d] This is a partially enlarged view illustrating the N portion of Figure 5a. [Figure 6] This is an illustrative cross-sectional view of a display device according to an embodiment of this specification, taken along line I-I' in Figure 5a. [Figure 7] This is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line II-II' in Figure 5a. [Figure 8] This is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line III-III' in Figure 5a. [Figure 9] This is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line IV-IV' in Figure 5a. [Figure 10] This is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line II-II' in Figure 5a. [Figure 11] This is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line III-III' in Figure 5a. [Figure 12] This is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line IV-IV' in Figure 5a. [Figure 13] This is an illustrative cross-sectional view of a display device according to an embodiment of this specification, taken along line V-V' in Figure 5a. [Figure 14]This is an illustrative cross-sectional view of a display device according to an embodiment of this specification, taken along the line VI-VI' in Figure 5a. [Figure 15] This is an illustrative cross-sectional view of a display device according to an embodiment of this specification, taken along line VII-VII' in Figure 5a. [Figure 16] This is a block diagram of an electronic device according to one embodiment of this specification. [Figure 17] This is a schematic diagram of an electronic device according to various embodiments described herein. [Modes for carrying out the invention]

[0034] The advantages and features of the embodiments disclosed herein, as well as methods for achieving them, will become clearer with reference to the embodiments described below in detail, along with the accompanying drawings. However, the inventions herein are not limited to the embodiments disclosed below and can be realized in a variety of different forms, and these embodiments are provided merely to complete the disclosure herein and to fully inform those who are ordinary skill in the art to which the inventions herein pertain, and the inventions herein are defined solely by the scope of the claims.

[0035] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or elements are interposed immediately above or between other elements. Throughout this specification, the same reference numerals refer to the same component. The shapes, sizes, proportions, angles, numbers, etc., shown in the drawings illustrating embodiments are illustrative and not limited to those shown herein.

[0036] While terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component mentioned below may, of course, be the second component within the technical concept of the embodiments disclosed herein.

[0037] Each feature of the various embodiments disclosed herein can be combined or linked together, either partially or entirely, enabling a wide range of technical interdependencies and drives, and each embodiment can be implemented independently of or in conjunction with one another.

[0038] The following describes specific embodiments with reference to the attached drawings. Components that perform substantially the same function between embodiments are given the same reference numerals in the drawings, and repeated explanations thereof are omitted.

[0039] Figure 1 is a perspective view showing a display device according to one embodiment of this specification. Figure 2 is a plan view showing a display device according to one embodiment of this specification.

[0040] Referring to Figures 1 and 2, the display device 10 is a device that displays videos and still images, and can be used as a display screen for a variety of products, including not only portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic organizers, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs), but also televisions, laptops, monitors, billboards, and the Internet of Things (IoT).

[0041] The display device 10 may be an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-miniature light-emitting display device using an ultra-miniature light-emitting diode (micro or nano light-emitting diode (micro LED or nano LED)). The following description will focus on the case where the display device 10 is an organic light-emitting display device, but the embodiments described herein are not limited thereto.

[0042] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0043] The display panel 100 can be formed as a rectangular plane having a longer side in a first direction (e.g., the X-axis direction) and a shorter side in a second direction (e.g., the Y-axis direction) that intersects the first direction (e.g., the X-axis direction). The corner where the longer side in the first direction (e.g., the X-axis direction) and the shorter side in the second direction (e.g., the Y-axis direction) intersect can be rounded or right-angled to have a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle and can be formed as other polygons, circles, or ellipses. The display panel 100 is formed flat, but is not limited to this. For example, the display panel 100 may include curved surfaces formed at the left and right edges that have a constant curvature or a changing curvature. The display panel 100 can also be formed flexibly so that it can be bent, curved, folded, or rolled up.

[0044] The display panel 100 may include a display area DA for displaying an image and a non-display area NDA arranged around the display area DA. Alternatively, the display area DA and the non-display area NDA are defined on the substrate of the display panel 100.

[0045] The display area DA occupies most of the area of ​​the display panel 100. The display area DA may be located in the center of the display panel 100. Pixels may be arranged in the display area DA to display an image.

[0046] The hidden area NDA may be located adjacent to the display area DA. The hidden area NDA may be located outside the display area DA. The hidden area NDA may be located surrounding the display area DA. The hidden area NDA may be located at the edge of the display panel 100.

[0047] A pad may be placed in the non-display area (NDA) for connection to the circuit board 300. The pad may be placed on one side edge of the display panel 100. For example, the pad may be placed on the lower edge of the display panel 100.

[0048] The circuit board 300 may be placed on a pad located on one side edge of the display panel 100. The circuit board 300 can be attached to the pad using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste). This allows the circuit board 300 to be electrically connected to the signal wiring of the display panel 100. The display panel 100 can receive inputs such as data voltage, power supply voltage, and scan timing signals through the circuit board 300. The circuit board 300 may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0049] The display driver circuit 200 can generate data voltage, power supply voltage, scan timing signal, etc. The display driver circuit 200 can supply data voltage, power supply voltage, scan timing signal, etc. to the display panel 100 via the circuit board 300.

[0050] Each of the display driver circuits 200 can be formed as an integrated circuit (IC) and attached to the circuit board 300. Alternatively, the display driver circuits 200 can be attached to the display panel 100 using a COG (chip on glass), COP (chip on plastic), or ultrasonic bonding method.

[0051] Figure 3 is a schematic diagram illustrating a display device according to one embodiment of this specification.

[0052] Referring to Figure 3, a display device according to one embodiment of this specification includes a pad, a first group DEMUX switch element GDEMT1, a second group DEMUX switch element GDEMT2, a first test switch element TET1, a second test switch element TET2, a resistor RP, a first group sub-pixel GSP1, and a second group sub-pixel GSP2. Hereinafter, the switch elements disclosed herein may be switching thin film transistors (TFTs), but the embodiments herein are not limited thereto. DEMUX is an abbreviation for demultiplexer.

[0053] The first group subpixel GSP1 and the second group subpixel GSP2 are arranged in the display area, while the remaining components, namely the pads, the first group DEMUX switch element GDEMT1, the second group DEMUX switch element GDEMT2, the first test switch element TET1, the second test switch element TET2, the resistor RP, etc., may be arranged in the non-display area.

[0054] The first group subpixel GSP1 may include a plurality of first subpixels SP11, SP12, SP13. The plurality of first subpixels SP11, SP12, SP13 may include a first subpixel SP11 that embodies a first color, a first subpixel SP12 that embodies a second color, and a first subpixel SP13 that embodies a third color.

[0055] The second group subpixel GSP2 may include multiple second subpixels SP21, SP22, and SP23. These multiple second subpixels SP21, SP22, and SP23 may include a second subpixel SP21 that embodies the first color, a second subpixel SP22 that embodies the second color, and a second subpixel SP23 that embodies the third color.

[0056] In the display device according to the embodiments of this specification, the first group subpixel GSP1 and the second group subpixel GSP2 may be repeatedly arranged in a first direction (e.g., row direction). As shown in the figures, the first group subpixel GSP1 and the second group subpixel GSP2 are sequentially arranged in the first direction, and the first group subpixel GSP1 and the second group subpixel GSP2 may again be repeatedly arranged in the first direction from the second group subpixel GSP2.

[0057] In the first group of subpixels GSP1, a first subpixel SP11 embodying the first color, a first subpixel SP12 embodying the second color, and a first subpixel SP13 embodying the third color may be repeatedly arranged in a second direction (for example, in the column direction).

[0058] In the second group of subpixels GSP2, a second subpixel SP21 embodying the first color, a second subpixel SP22 embodying the second color, and a second subpixel SP23 embodying the third color may be repeatedly arranged in a second direction (e.g., the column direction).

[0059] The first, second, and third colors may be any one of the colors selected from the group consisting of red, green, and blue, without overlapping. For example, the first color may be red, the second color may be green, and the third color may be blue, but the embodiments herein are not limited thereto.

[0060] The pads may include multiple data pads DP1, DP2, DP3, multiple test pads TP1, TP2, test gate pad TGP, multiple clock pads CLP1, CLP2, and multiple gate pads GP.

[0061] Multiple data pads DP1, DP2, and DP3 can supply data voltages to the first group subpixel GSP1 and the second group subpixel GSP2. The multiple data pads DP1, DP2, and DP3 may include the first data pad DP1, the second data pad DP2, and the third data pad DP3.

[0062] The data voltages supplied from the first data pad DP1, the second data pad DP2, and the third data pad DP3 can be applied to a plurality of first subpixels SP11, SP12, SP13 located in the first group subpixel GSP1 and a plurality of second subpixels SP21, SP22, SP23 located in the second group subpixel GSP2, respectively.

[0063] For example, the data voltage supplied from the first data pad DP1 may be applied to the first subpixel SP11 and the second subpixel SP21 that embody the first color. The data voltage supplied from the second data pad DP2 may be applied to the first subpixel SP12 and the second subpixel SP22 that embody the second color. The data voltage supplied from the third data pad DP3 may be applied to the first subpixel SP13 and the second subpixel SP23 that embody the third color. However, the embodiments of this specification are not limited thereto.

[0064] The first group of DEMUX switch elements GDEMT1 includes multiple first DEMUX switch elements, and the second group of DEMUX switch elements GDEMT2 may include multiple second DEMUX switch elements. In the example in Figure 3, the first group of DEMUX switch elements GDEMT1 includes three first DEMUX switch elements DEMT1 corresponding to the first to third data pads DP1 to DP3, and the second group of DEMUX switch elements GDEMT2 includes three second DEMUX switch elements corresponding to the first to third data pads DP1 to DP3.

[0065] The gate electrode of the first group DEMUX switch element GDEMT1 may be connected to the first clock pad CLP1. The first electrodes (which are also the first connection electrodes) of the multiple first DEMUX switch elements included in the first group DEMUX switch element GDEMT1 may be connected to the first subpixel SP11 which embodies the first color, the first subpixel SP12 which embodies the second color, and the first subpixel SP13 which embodies the third color, respectively. The second electrodes (which are also the second connection electrodes) of the multiple first DEMUX switch elements included in the first group DEMUX switch element GDEMT1 may be connected to the first data pad DP1, the second data pad DP2, and the third data pad DP3, respectively. The first group DEMUX switch element GDEMT1 is turned on by a signal applied via the first clock pad CLP1, and can apply data signals transmitted from the first data pad DP1, the second data pad DP2, and the third data pad DP3 to the first subpixel SP11 which embodies the first color, the first subpixel SP12 which embodies the second color, and the first subpixel SP13 which embodies the third color, respectively.

[0066] The gate electrode of the second group DEMUX switch element GDEMT2 may be connected to the second clock pad CLP2. The first electrodes (which are also the first connection electrodes) of the multiple second DEMUX switch elements included in the second group DEMUX switch element GDEMT2 may be connected to the second subpixel SP21 which embodies the first color, the second subpixel SP22 which embodies the second color, and the second subpixel SP23 which embodies the third color, respectively. The second electrodes (which are also the second connection electrodes) of the multiple second DEMUX switch elements included in the second group DEMUX switch element GDEMT2 may be connected to the first data pad DP1, the second data pad DP2, and the third data pad DP3, respectively. The second group DEMUX switch element GDEMT2 is turned on by a signal applied via the second clock pad CLP2, and can apply data signals transmitted from the first data pad DP1, the second data pad DP2, and the third data pad DP3 to the second subpixel SP21 which embodies the first color, the second subpixel SP22 which embodies the second color, and the second subpixel SP23 which embodies the third color, respectively.

[0067] The first data pad DP1 may be connected to a first subpixel SP11 that embodies the first color and a second subpixel SP21 that embodies the first color. A first DEMUX switch element DEMT1 that embodies the first color may be placed between the first subpixel SP11 that embodies the first color and the first data pad DP1. A second DEMUX switch element that embodies the first color may be placed between the second subpixel SP21 that embodies the first color and the first data pad DP1.

[0068] The second data pad DP2 may be connected to the first subpixel SP12 and the second subpixel SP22 that embody the second color. A first DEMUX switch element that embody the second color may be placed between the first subpixel SP12 and the second data pad DP2. A second DEMUX switch element that embody the second color may be placed between the second subpixel SP22 and the second data pad DP2.

[0069] The third data pad DP3 may be connected to a first subpixel SP13 and a second subpixel SP23 that embody the third color. A first DEMUX switch element that embody the third color may be placed between the first subpixel SP13 and the third data pad DP3. A second DEMUX switch element that embody the third color may be placed between the second subpixel SP23 and the third data pad DP3.

[0070] The first and second DEMUX switch elements, which embody the first, second, and third colors, may each include a plurality of sub-DEMUX switch elements DEMT11, DEMT12, DEMT13, and DEMT14 connected in parallel. Referring to an enlarged diagram for illustrative purposes, the first DEMUX switch element DEMT1, which embodys the first color, may include a first sub-DEMUX switch element DEMT11, a second sub-DEMUX switch element DEMT12, a third sub-DEMUX switch element DEMT13, and a fourth sub-DEMUX switch element DEMT14. The first electrodes of each of these may be connected to the same node, and the second electrodes of each of these may also be connected to the same node. By including a plurality of sub-DEMUX switch elements DEMT11, DEMT12, DEMT13, and DEMT14 connected in parallel, a relatively large current can be distributed and processed across multiple sub-DEMUX switch elements, thereby reducing the power consumption of the display device.

[0071] As mentioned above, the first electrode of the first DEMUX switch element DEMT1 that embodies the first color can be connected to the first sub-pixel SP11 that embodies the first color. In addition, the first electrode (which is also the first connection electrode) of the first DEMUX switch element DEMT1 that embodies the first color can also be connected to the first test pad TP1. In other words, the first electrode of the first DEMUX switch element DEMT1 that embodies the first color can be connected not only to the first sub-pixel SP11 that embodies the first color, but also to the first test pad TP1. A first test switch element TET1 can be placed between the first electrode of the first DEMUX switch element DEMT1 that embodies the first color and the first test pad TP1. The gate electrode of the first test switch element TET1 can be connected to the test gate pad TGP. The first electrode of the first test switch element TET1 can be connected to the first electrode of the first DEMUX switch element DEMT1 that embodies the first color. The second electrode of the first test switch element TET1 can be connected to the first test pad TP1.

[0072] As mentioned above, the first connection electrode (which is also the first electrode) of the second DEMUX switch element that embodies the first color can be connected to the second sub-pixel SP21 that embodies the first color. In addition, the first connection electrode of the second DEMUX switch element that embodies the first color can also be connected to the second test pad TP2. In other words, the first connection electrode of the second DEMUX switch element that embodies the first color can be connected not only to the second sub-pixel SP21 that embodies the first color, but also to the second test pad TP2. A second test switch element TET2 can be placed between the first connection electrode of the second DEMUX switch element that embodies the first color and the second test pad TP2. The gate electrode of the second test switch element TET2 can be connected to the test gate pad TGP. The first electrode of the second test switch element TET2 can be connected to the first connection electrode of the second DEMUX switch element that embodies the first color. The second electrode of the second test switch element TET2 can be connected to the second test pad TP2.

[0073] Both the gate electrode of the first test switch element TET1 and the gate electrode of the second test switch element TET2 can be connected to a test gate pad TGP. The first test switch element TET1 and the second test switch element TET2 can be turned on by a signal applied via the test gate pad TGP. The turned-on first test pad TP1 and the second test pad TP2 can receive a supply of data voltages to be applied to the first subpixel SP11 and the second subpixel SP21, respectively, which embody the first color. The implementer can turn on the test switch elements TET1 and TET2 and verify whether the appropriate data voltages are output to multiple subpixels from the first DEMUX switch element (e.g., DEMT1) and the second DEMUX switch element. For example, the first test pad TP1 receives data voltages from the first data pad DP1 via the first DEMUX switch element DEMT1 and the first test switch element TET1. Furthermore, the data voltage from the first data pad DP1 is output to the second test pad TP2 via the second DEMUX switch element and the second test switch element TET2. Therefore, by comparing the data voltage output to the first test pad TP1 and the data voltage output to the second test pad TP2, it is possible to confirm whether the appropriate data voltage is being output to the first sub-pixel SP11 and the second sub-pixel SP21. In addition, the test switch elements can be turned off in situations where measurement of the output data voltage is not necessary, such as for product shipment. This reduces interference with data lines located on the display area side (for example, current leakage or parasitic capacitance).

[0074] The first test switch element TET1 and the second test switch element TET2 may each include a plurality of sub-test switch elements TET11, TET12, TET21, and TET22 connected in series.

[0075] For example, referring to the enlarged diagram, the first test switch element TET1 may include a first sub-test switch element (or eleventh test switch element) TET11 and a second sub-test switch element (or twelfth test switch element) TET12. The first electrode of the first sub-test element may be connected to the second electrode of the second sub-test switch element TET12. The second electrode of the first sub-test switch element TET11 may be connected to the first test pad TP1, and the first electrode of the second sub-test switch element TET12 may be connected to the first electrode of the first DEMUX switch element DEMT1. By including sub-test switch elements connected in series, high voltage processing can be performed smoothly, for example, in a distributed manner, and overheating of individual switch elements can be prevented. Therefore, the reliability of the display device can be improved.

[0076] The second test switch element TET2 may include a third sub-test switch element (or 21st test switch element) TET21 and a fourth sub-test switch element (or 22nd test switch element) TET22. The first electrode of the third sub-test element may be connected to the second electrode of the fourth sub-test switch element TET22. The second electrode of the third sub-test switch element TET21 may be connected to the second test pad TP2, and the first electrode of the fourth sub-test switch element TET22 may be connected to the first electrode of the second DEMUX switch element.

[0077] The display device according to the embodiment may further include a resistor RP positioned between the test gate pad TGP and the first test switch element TET1 (or second test switch element TET2). The resistor RP can serve to protect the test switch elements TET1, TET2, including the first test switch element TET1 and the second test switch element TET2, and the sub-pixels SP11, SP12, SP13, SP21, SP22, SP23 positioned in the display area from static electricity that may be generated from the test gate pad TGP. In the embodiment, the resistor RP may be 1000Ω or more and 10000Ω or less. If the resistor RP is less than 1000Ω, the display device may not be adequately protected from static electricity. If the resistor RP is greater than 10000Ω, the first test switch element TET1 or the second test switch element TET2 may not be properly turned on or turned off, which may result in the test not being performed correctly or the interference described above occurring. Preferably, the resistor RP may be 2000Ω or more and 80000Ω or less. More preferably, the resistance can be 3000Ω or more and 60000Ω or less. Within this range, the first test switch element TET1 and other elements can be turned on and off smoothly, and the display device can be adequately protected from static electricity. In one embodiment, the resistor RP can be omitted.

[0078] The display device according to the embodiments of this specification may further include an electrostatic discharge circuit EDC connected via adjacent wiring to the output sections of a plurality of pads TGP, TP1, TP2, DP1, DP2, DP3. Unlike the resistor RP, this can perform the function of discharging static electricity to the outside of the display device by utilizing ground connection or the like. For example, an electrostatic discharge circuit EDC that discharges static electricity can be placed on the outer casing of the display device. The electrostatic discharge circuit EDC is connected to a plurality of pads, and the resistor RP may be connected to the test gate pad TGP.

[0079] The display device according to the embodiments of this specification includes a plurality of test switch elements TET1, TET2, a plurality of test pads TP1, TP2, and a test gate pad TGP for testing the data voltage output from the DEMUX switch elements. By including these, it is possible to verify whether the first DEMUX switch element DEMT1, which embodies the first color, and the second DEMUX switch element, which embodies the first color, uniformly output the data voltage from the first data pad DP1.

[0080] To verify the uniformity of the output data voltage, etc., the display device according to the embodiments herein connects a first test pad TP1 to any one (or a single) first DEMUX switch element. A first test switch element TET1 may be placed between these first DEMUX switch elements and the first test pad TP1. The first group of DEMUX switch elements GDEMT1 may include a plurality of first DEMUX switch elements. The plurality of first DEMUX switch elements may include any one first DEMUX switch element (e.g., DEMT1) connected to the first test pad TP1 and the remaining first DEMUX switch elements excluding any one first DEMUX switch element (e.g., DEMT1).

[0081] As shown in the diagram, among the first group of DEMUX switch elements GDEMT1, the first DEMUX switch element DEMT1 shown in the enlarged view is the "any one of the first DEMUX switch elements" described above. On the other hand, the remaining first DEMUX switch elements, excluding the "any one of the first DEMUX switch elements," can be electrically isolated from the first test pad TP1.

[0082] Similarly, to verify the uniformity of the output data voltage, etc., the display device according to the embodiments herein connects a second test pad TP2 to any one (or a single) second DEMUX switch element. A second test switch element TET2 may be placed between these second DEMUX switch elements and the second test pad TP2. The second group of DEMUX switch elements GDEMT2 may include a plurality of second DEMUX switch elements. The plurality of second DEMUX switch elements may include any one second DEMUX switch element connected to the second test pad TP2 and the remaining second DEMUX switch elements excluding one of the second DEMUX switch elements. The remaining second DEMUX switch elements of the second group of DEMUX switch elements GDEMT2, excluding one of the second DEMUX switch elements, may be electrically isolated from the second test pad TP2.

[0083] In one embodiment, the color (e.g., the first color) embodied by a subpixel (e.g., a first subpixel SP11 embodying a first color) connected to the first test pad TP1 may be the same as the color (e.g., the first color) embodied by a subpixel (e.g., a second subpixel SP21 embodying a first color) connected to the second test pad TP2. Furthermore, all data pads (e.g., the first data pad DP1) to which the first test switch element TET1 and the second test switch element TET2 are connected may be identical.

[0084] The display device according to the embodiments of this specification connects multiple test pads TP1, TP2 to each of the first electrodes of multiple DEMUX switch elements (e.g., a first DEMUX switch element DEMT1 that embodies a first color and a second DEMUX switch element that embodies a first color) connected to the same data pad (e.g., a first data pad DP1). Therefore, it is possible to verify whether the data voltage supplied from each data pad (e.g., the first data pad DP1, the second data pad DP2) is properly applied to the subpixel after each DEMUX switch element (e.g., the first DEMUX switch element DEMT1, the second DEMUX switch element).

[0085] Figure 4 is an enlarged portion of Figure 2, illustrating the J portion in Figure 2. Figure 5a is an enlarged portion of Figure 2, illustrating the K portion in Figure 2. Figure 5b is an enlarged portion of Figure 5a, illustrating the L portion in Figure 5a. Figure 5c is an enlarged portion of Figure 5a, illustrating the M portion in Figure 5a. Figure 5d is an enlarged portion of Figure 5a, illustrating the N portion in Figure 5a.

[0086] Referring to Figures 2 and 4, the test gate pad TGP may be connected to the resistor connection wiring RPCL. The first test pad TP1 may be connected to the first test connection wiring TECL1, and the second test pad TP2 may be connected to the third test connection wiring TECL3. The first data pad DP1 may be connected to the 13th DEMUX connection wiring DEML13, the second data pad DP2 may be connected to the 23rd DEMUX connection wiring DEML23, and the third data pad DP3 may be connected to the 33rd DEMUX connection wiring DEML33.

[0087] The resistive connection wiring RPCL, the first test connection wiring TECL1, the second test connection wiring TECL2, the 13th DEMUX connection wiring DEML13, the 23rd DEMUX connection wiring DEML23, and the 33rd DEMUX connection wiring DEML33 can all be connected via multiple contact holes to the wiring connected to the electrostatic discharge circuit described above. The wiring connected to the electrostatic discharge circuit is connected via contact holes to multiple cross wirings that connect to each other, and the multiple cross wirings can also be connected via contact holes to each of the resistive connection wiring RPCL, the first test connection wiring TECL1, the second test connection wiring TECL2, the 13th DEMUX connection wiring DEML13, the 23rd DEMUX connection wiring DEML23, and the 33rd DEMUX connection wiring DEML33.

[0088] Referring to Figures 2, 4, and 5a to 5d, the 13th DEMUX connection wiring DEML13 can be connected to the 12th DEMUX connection wiring DEML12 via the 1st DEMUX connection contact hole DEMCT1 (Figure 5d). Multiple 1st DEMUX connection contact holes DEMCT1 can be formed. The description of multiple contact holes can be omitted below.

[0089] As shown in Figure 5d, the 12th DEMUX connection wiring DEML12 may be connected via the 111th DEMUX connection wiring DEML111 and the 11th DEMUX connection contact hole DEMCT11. The 12th DEMUX connection wiring DEML12 may also be connected via the 211th DEMUX connection wiring DEML211 and the 21st DEMUX connection contact hole DEMCT21.

[0090] As shown in Figure 5c, the 111th DEMUX connection wiring DEML111 can be connected to the second connection electrode DEMSD211 of the first DEMUX switch element that embodies the first color via the 11th DEMUX contact hole DECT11.

[0091] As shown in Figure 5c, the second connecting electrode DEMSD211 of the first DEMUX switch element embodying the first color may be connected to the 11th DEMUX active layer DEMACT11 via a contact hole. The 11th DEMUX active layer DEMACT11, together with the 11th DEMUX gate electrode DEMG11, constitutes the first DEMUX switch element embodying the first color. As shown in Figure 5d, the 11th DEMUX gate electrode DEMG11 may be connected to the first clock wiring CL1 via a contact hole CLCT11. The 11th DEMUX active layer DEMACT11 may be connected to the first connecting electrode DEMSD111 of the first DEMUX switch element embodying the first color via a contact hole. As shown in Figure 5c, the first connection electrode DEMSD111 of the first DEMUX switch element that embodies the first color is connected to the 11th data line DL11, and the 11th data line DL11 can apply a data voltage from the first data pad DP1 to the first subpixel SP11 that embodies the first color.

[0092] As shown in Figure 5c, the 211th DEMUX connection wiring DEML211 can be connected to the second connection electrode DEMSD221 of the second DEMUX switch element, which embodies the first color, via the 21st DEMUX contact hole DECT21.

[0093] As shown in Figure 5c, the second connecting electrode DEMSD221 of the second DEMUX switch element embodying the first color may be connected to the 21st DEMUX active layer DEMACT21 via a contact hole. The 21st DEMUX active layer DEMACT21, together with the 21st DEMUX gate electrode DEMG21, constitutes the second DEMUX switch element embodying the first color. As shown in Figure 5d, the 21st DEMUX gate electrode DEMG21 may be connected to the second clock wiring CL2 via a contact hole CLCT21. The 21st DEMUX active layer DEMACT21 may be connected to the first connecting electrode DEMSD121 of the second DEMUX switch element embodying the first color via a contact hole. As shown in Figure 5c, the first connection electrode DEMSD121 of the second DEMUX switch element that embodies the first color is connected to the 21st data line DL21, and the 21st data line DL21 can apply a data voltage from the first data pad DP1 to the second subpixel SP21 that embodies the first color.

[0094] As shown in Figure 5d, the 23rd DEMUX connection wiring DEML23 can be connected to the 22nd DEMUX connection wiring DEML22 via the 2nd DEMUX connection contact hole DEMCT2.

[0095] As shown in Figure 5d, the 22nd DEMUX connection wiring DEML22 may be connected to the 121st DEMUX connection wiring DEML121 via the 12th DEMUX connection contact hole DEMCT12. The 22nd DEMUX connection wiring DEML22 may be connected to the 221st DEMUX connection wiring DEML221 via the 22nd DEMUX connection contact hole DEMCT22.

[0096] As shown in Figure 5c, the 121st DEMUX connection wiring DEML121 can be connected to the second connection electrode DEMSD212 of the first DEMUX switch element, which embodies the second color, via the 12th DEMUX contact hole DECT12.

[0097] As shown in Figure 5c, the second connecting electrode DEMSD212 of the first DEMUX switch element embodying the second color may be connected to the 12th DEMUX active layer DEMACT12 via a contact hole. The 12th DEMUX active layer DEMACT12, together with the 12th DEMUX gate electrode DEMG12, constitutes the first DEMUX switch element embodying the second color. As shown in Figure 5d, the 12th DEMUX gate electrode DEMG12 may be connected to the first clock wiring CL1 via a contact hole CLCT12. The 12th DEMUX active layer DEMACT12 may be connected to the first connecting electrode DEMSD112 of the first DEMUX switch element embodying the second color via a contact hole. As shown in Figure 5c, the first connection electrode DEMSD112 of the first DEMUX switch element that embodies the second color is connected to the 12th data line DL12, and the 12th data line DL12 can apply a data voltage from the second data pad DP2 to the first subpixel SP12 that embodies the second color.

[0098] As shown in Figure 5c, the 221st DEMUX connection wiring DEML221 can be connected to the second connection electrode DEMSD222 of the second DEMUX switch element, which embodies the second color, via the 22nd DEMUX contact hole DECT22.

[0099] As shown in Figure 5c, the second connecting electrode DEMSD222 of the second DEMUX switch element embodying the second color may be connected to the 22nd DEMUX active layer DEMACT22 via a contact hole. The 22nd DEMUX active layer DEMACT22, together with the 22nd DEMUX gate electrode DEMG22, constitutes the second DEMUX switch element embodying the second color. As shown in Figure 5d, the 22nd DEMUX gate electrode DEMG22 may be connected to the second clock wiring CL2 via a contact hole CLCT22. The 22nd DEMUX active layer DEMACT22 may be connected to the first connecting electrode DEMSD122 of the second DEMUX switch element embodying the second color via a contact hole. As shown in Figure 5c, the first connecting electrode DEMSD122 of the second DEMUX switch element that embodies the second color is connected to the 22nd data line DL22, and the 22nd data line DL22 can apply a data voltage from the second data pad DP2 to the second subpixel SP22 that embodies the second color.

[0100] As shown in Figure 5d, the 33rd DEMUX connection wiring DEML33 can be connected to the 32nd DEMUX connection wiring DEML32 via the 3rd DEMUX connection contact hole DEMCT3.

[0101] As shown in Figure 5d, the 32nd DEMUX connection wiring DEML32 may be connected via the 131st DEMUX connection wiring DEML131 and the 13th DEMUX connection contact hole DEMCT13. The 32nd DEMUX connection wiring DEML32 may be connected via the 231st DEMUX connection wiring DEML231 and the 23rd DEMUX connection contact hole DEMCT23.

[0102] As shown in Figure 5c, the 131st DEMUX connection wiring DEML131 can be connected to the second connection electrode DEMSD213 of the first DEMUX switch element, which embodies the third color, via the 13th DEMUX contact hole DECT13.

[0103] As shown in Figure 5c, the second connecting electrode DEMSD213 of the first DEMUX switch element embodying the third color can be connected to the 13th DEMUX active layer DEMACT13 via a contact hole. The 13th DEMUX active layer DEMACT13, together with the 13th DEMUX gate electrode DEMG13, constitutes the first DEMUX switch element embodying the third color. As shown in Figure 5d, the 13th DEMUX gate electrode DEMG13 can be connected to the first clock wiring CL1 via a contact hole CLCT21. The 13th DEMUX active layer DEMACT13 can be connected to the first connecting electrode DEMSD113 of the first DEMUX switch element embodying the third color via a contact hole. As shown in Figure 5c, the first connection electrode DEMSD113 of the first DEMUX switch element that embodies the third color is connected to the 13th data line DL13, and the 13th data line DL13 can apply a data voltage from the third data pad DP3 to the first subpixel SP13 that embodies the third color.

[0104] As shown in Figure 5c, the 231st DEMUX connection wiring DEML231 can be connected to the second connection electrode DEMSD223 of the second DEMUX switch element, which embodies the third color, via the 23rd DEMUX contact hole DECT23.

[0105] As shown in Figure 5c, the second connecting electrode DEMSD223 of the second DEMUX switch element embodying the third color can be connected to the 23rd DEMUX active layer DEMACT23 via a contact hole. The 23rd DEMUX active layer DEMACT23, together with the 23rd DEMUX gate electrode DEMG23, constitutes the second DEMUX switch element embodying the third color. As shown in Figure 5d, the 23rd DEMUX gate electrode DEMG23 can be connected to the second clock wiring CL2 via a contact hole CLCT23. The 23rd DEMUX active layer DEMACT23 can be connected to the first connecting electrode DEMSD123 of the second DEMUX switch element embodying the third color via a contact hole. As shown in Figure 5c, the first connection electrode DEMSD123 of the second DEMUX switch element that embodies the third color is connected to the 23rd data line DL23, which can apply a data voltage from the third data pad DP3 to the second subpixel SP23 that embodies the third color.

[0106] As shown in the figures, the first power supply wiring PSL1 (Figures 5a to 5d) can be superimposed on the first group DEMUX switch elements, the second group DEMUX switch elements, and multiple DEMUX connection wirings.

[0107] The first power supply wiring PSL1 may be separated from the first test switch element TET1, the second test switch element TET2, and the resistor. The resistor may include a resistive active layer RPACT (Figure 5b).

[0108] As shown in Figure 5b, the first test switch element TET1 can be connected to the first test connection electrode TECE1 and the second test connection electrode TECE2. The second test switch element TET2 can be connected to the third test connection electrode TECE3 and the fourth test connection electrode TECE4.

[0109] The first test connection electrode TECE1 can be connected to the first test connection wiring TECL1. The second test connection electrode TECE2 can be connected to the second test connection wiring TECL2. The third test connection electrode TECE3 can be connected to the third test connection wiring TECL3. The fourth test connection electrode TECE4 can be connected to the fourth test connection wiring TECL4.

[0110] As shown in Figure 4, the first test connection wiring TECL1 and the third test connection wiring TECL3 can be connected to the first test pad TP1 and the second test pad TP2, respectively.

[0111] The second test connection wire TECL2 and the fourth test connection wire TECL4 can be connected to the first DEMUX switch element and the second DEMUX switch element. For example, the second test connection wire TECL2 can be connected to the first connection electrode DEMSD121 of the second DEMUX switch element that embodies the first color. The fourth test connection wire TECL4 can be connected to the first connection electrode DEMSD111 of the first DEMUX switch element that embodies the first color.

[0112] The gate electrode of the first test switch element TET1 and the gate electrode of the second test switch element TET2 can be connected to each other. The test gate electrode TEG can be connected to the second resistive connection electrode RPCE2 via a contact hole.

[0113] The second resistive electrode RPCE2 may be connected to the resistive active layer RPACT via contact holes RPCT4, RPCT5, and RPCT6. The resistive active layer RPACT may be connected to the first resistive electrode RPCE1 via contact holes RPCT1, RPCT2, and RPCT3. The first resistive electrode RPCE1 is connected to the resistive wiring RPCL, which may be connected to the test gate pad TGP.

[0114] Figure 6 is an illustrative cross-sectional view of a display device according to an embodiment of this specification, cut along line I-I' in Figure 5a.

[0115] Referring to Figures 5a and 6, these are cross-sectional views showing subpixels according to one embodiment of this specification. Each subpixel SP may include at least one display transistor DT, a capacitor C1, and light-emitting elements 171, 172, 173.

[0116] The substrate SUB is made of an insulating material such as polymer resin or glass. For example, the substrate SUB may contain polyimide. In this case, the substrate SUB may be a flexible substrate that can be bent, folded, and rolled.

[0117] A thin-film transistor layer TFTL containing the display transistor DT and capacitor C1 of each sub-pixel SP is arranged on the substrate SUB. The thin-film transistor layer TFTL may include the display transistor DT, a first anode connection electrode ANDE1, a second anode connection electrode ANDE2, a buffer film BF, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a first planarization film 160, and a second planarization film 180.

[0118] A buffer film BF is placed on the substrate SUB. The buffer film BF can be formed from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0119] A display transistor DT is placed on the buffer film BF. The display transistor DT may include a display active layer DACT, a display gate electrode DG, a first display electrode (or the first electrode of the display transistor DT) DSD1, and a second display electrode (or the second electrode of the display transistor DT) DSD2.

[0120] The display active layer DACT, first display electrode DSD1, and second display electrode DSD2 of the display transistor DT are arranged on the buffer film BF. The display active layer DACT can include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first display electrode DSD1 and the second display electrode DSD2 can be conductive by doping the silicon semiconductor with ions or impurities. The display active layer DACT overlaps with the display gate electrode DG in a third direction (e.g., the Z-axis direction), while the first display electrode DSD1 and the second display electrode DSD2 do not overlap with the display gate electrode DG in a third direction (e.g., the Z-axis direction). The third direction (e.g., the Z-axis direction) can be defined as the thickness direction of the substrate SUB or the thickness direction of the display panel 100. The functional layer including the display active layer DACT can be arranged between the buffer film BF and the gate insulating film 130.

[0121] A gate insulating film 130 is placed on the display active layer DACT, the first display electrode DSD1, and the second display electrode DSD2 of the display transistor DT. The gate insulating film 130 can be formed from an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0122] A display gate electrode DG and a first capacitor electrode CAE1 are arranged on the gate insulating film 130 of the display transistor DT. The display gate electrode DG may be superimposed on the display active layer DACT in a third direction (e.g., the Z-axis direction). The first capacitor electrode CAE1 may be superimposed on the second capacitor electrode CAE2 in a third direction (e.g., the Z-axis direction). The display gate electrode DG and the first capacitor electrode CAE1 can be formed as a single or multilayer from one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The first capacitor electrode CAE1 may contain the same material as the display gate electrode DG. The first gate metal layer, including the display gate electrode DG and the first capacitor electrode CAE1, may be placed between the gate insulating film 130 and the first interlayer insulating film 141.

[0123] A first interlayer insulating film 141 is placed on the indicator gate electrode DG and the first capacitor electrode CAE1. The first interlayer insulating film 141 can be formed from an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0124] A second capacitor electrode CAE2 is placed on the first interlayer insulating film 141. Since the first interlayer insulating film 141 has a predetermined dielectric constant, a capacitor C1 can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the first interlayer insulating film 141 placed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2. The second capacitor electrode CAE2 can be formed as a single or multilayer from one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. A second gate metal layer including the second capacitor electrode CAE2 may be placed between the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0125] A second interlayer insulating film 142 is placed on the second capacitor electrode CAE2. The second interlayer insulating film 142 can be formed from an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0126] A first anode connection electrode ANDE1 is positioned on the second interlayer insulating film 142. The first anode connection electrode ANDE1 can be connected to the second indicator electrode DSD2 via a first anode contact hole ANCT1 that penetrates the first interlayer insulating film 141 and the second interlayer insulating film 142, exposing the second indicator electrode DSD2 of the indicator transistor DT. The first anode connection electrode ANDE1 can be formed as a single or multilayer from one of the following materials or alloys: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0127] A connecting electrode CE is positioned on the second interlayer insulating film 142. The connecting electrode CE may be connected to the first display electrode DSD1 of the display transistor DT via a connecting electrode contact hole CECT that penetrates the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first display electrode DSD1. The connecting electrode CE may be formed as a single or multilayer from one of the following materials or alloys: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). In one embodiment, the connecting electrode CE may contain the same material as the first anode connecting electrode ANDE1. The first data metal layer, including the first anode connecting electrode ANDE1 and the connecting electrode CE, may be positioned between the second interlayer insulating film 142 and the first planarization film 160.

[0128] A first planarization film 160 is placed on the first anode connection electrode ANDE1 for planarization. The first planarization film 160 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0129] A second anode connection electrode ANDE2 is positioned on the first planarization film 160. The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 via a second anode contact hole ANCT2 that penetrates the first planarization film 160 and exposes the first anode connection electrode ANDE1. The second anode connection electrode ANDE2 may be formed as a single or multilayer from one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The second data metal layer containing the second anode connection electrode ANDE2 may be positioned between the second interlayer insulating film 142 and the first planarization film 160.

[0130] A second planarization film 180 is placed on the second anode connection electrode ANDE2 for planarization. The second planarization film 180 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0131] A light-emitting element layer (EML) is placed on the second planarization film 180. The light-emitting element layer (EML) may include light-emitting elements 171, 172, 173 and a bank 190. Each of the light-emitting elements 171, 172, and 173 may include a pixel electrode 171, a light-emitting layer 172, and a common electrode 173. The common electrode 173 may be connected in common to multiple different light-emitting elements.

[0132] The pixel electrode 171 is formed on the second planarization film 180. The pixel electrode 171 can be connected to the second anode connection electrode ANDE2 via a third anode contact hole ANCT3 that penetrates the second planarization film 180 and exposes the second anode connection electrode ANDE2.

[0133] In a top emission structure that emits light in the direction of the common electrode 173 with respect to the light-emitting layer 172, the pixel electrode 171 can be formed from a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0134] Bank 190 is formed on the first planarization film 160 to partition the pixel electrode 171 in order to define the light-emitting region EA. The light-emitting region EA is a region in which the pixel electrode 171, light-emitting layer 172, and common electrode 173 are sequentially stacked, and holes from the pixel electrode 171 and electrons from the common electrode 173 combine with each other in the light-emitting layer 172 to emit light. Bank 190 is formed to cover the edge of the pixel electrode 171. Bank 190 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0135] A light-emitting layer 172 is formed on the pixel electrode 171 and the bank 190. The light-emitting layer 172 contains an organic material and is capable of emitting a predetermined color. For example, the light-emitting layer 172 includes a hole transporting layer, an organic material layer, and an electron transporting layer.

[0136] The common electrode 173 is formed on the light-emitting layer 172. The common electrode 173 is formed so as to cover the light-emitting layer 172. The common electrode 173 may be a common layer formed in common to all light-emitting regions EA, including the illustrated light-emitting region. A capping layer (CPL) may be formed on the common electrode 173.

[0137] In the upper light-emitting structure, the common electrode 173 can be formed from a transparent conductive oxide (TCO) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), or from a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 is formed from a semi-transmissive metallic material, the light emission efficiency is increased by the microcavity.

[0138] A sealing layer TFEL is placed on the common electrode 173. The sealing layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating the light-emitting layer EML. The sealing layer TFEL may also include at least one organic film to protect the light-emitting layer EML from foreign matter such as dust. For example, the sealing layer TFEL may include a first inorganic film TFE1, an organic film TFE2, and a second inorganic film TFE3.

[0139] The first inorganic film TFE1 is placed on the common electrode 173, the organic film TFE2 is placed on the first inorganic film TFE1, and the second inorganic film TFE3 is placed on the organic film TFE2. The first inorganic film TFE1 and the second inorganic film TFE3 can be formed as a multilayer film in which one or more inorganic films from among silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately laminated. The organic film TFE2 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0140] Alternatively, a packing layer, a sealing material, and a sealing substrate may be used instead of the sealing layer TFEL. In this case, the sealing substrate may be an insulating substrate containing an insulating material such as glass or plastic. The packing layer may be, but is not limited to, a vacuum-sealed layer of air. The sealing material may be placed in the non-display area of ​​the display panel 100 and surround the display area DA.

[0141] Figure 7 is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line II-II' of Figure 5a. Figure 8 is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line III-III' of Figure 5a. Figure 9 is an illustrative cross-sectional view of a display device according to the first embodiment of this specification, cut along line IV-IV' of Figure 5a. Components having substantially the same function as those in the embodiments described above are given the same reference numerals, and repeated descriptions thereof are omitted.

[0142] Referring to Figures 5a and 7, the second test connection wiring TECL2 and the fourth test connection wiring TECL4 are placed on the first interlayer insulating film 141. The second gate metal layer, including the second test connection wiring TECL2 and the fourth test connection wiring TECL4, may be placed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 may be placed over the second test connection wiring TECL2 and the fourth test connection wiring TECL4. The second test connection wiring TECL2 and the fourth test connection wiring TECL4 may contain the same material as the second capacitor electrode described above.

[0143] On the second interlayer insulating film 142, the first connection electrode DEMSD111 of the first DEMUX switch element that embodies the first color and the first connection electrode DEMSD121 of the second DEMUX switch element that embodies the first color are arranged. Also on the second interlayer insulating film 142, the first connection electrode DEMSD112 of the first DEMUX switch element that embodies the second color and the first connection electrode DEMSD113 of the first DEMUX switch element that embodies the third color are arranged. The first connection electrode DEMSD112 of the first DEMUX switch element that embodies the second color and the first connection electrode DEMSD113 of the first DEMUX switch element that embodies the third color are arranged between the first electrode of the first DEMUX switch element and the first connection electrode DEMSD121 of the second DEMUX switch element that embodies the first color.

[0144] The first connection electrode DEMSD111 of the first DEMUX switch element that embodies the first color may penetrate the first test contact hole TECT1 formed in the second interlayer insulating film 142. The first connection electrode DEMSD111 of the first DEMUX switch element that embodies the first color may be connected to the fourth test connection wiring TECL4 exposed by the first test contact hole TECT1.

[0145] The first connecting electrode DEMSD121 of the second DEMUX switch element embodying the first color may penetrate the second test contact hole TECT2 formed in the second interlayer insulating film 142. The first connecting electrode DEMSD121 of the second DEMUX switch element embodying the first color may be connected to the second test connection wiring TECL2 exposed by the second test contact hole TECT2, as shown in Figures 5c and 7.

[0146] A first data metal layer, including the first electrode of the first DEMUX switch element, the first connecting electrode DEMSD121 of the second DEMUX switch element embodying the first color, the first connecting electrode DEMSD112 of the first DEMUX switch element embodying the second color, and the first connecting electrode DEMSD113 of the first DEMUX switch element embodying the third color, may be positioned between the second interlayer insulating film 142 and the first planarization film 160. The first planarization film 160 may be positioned covering these. These may contain the same material as the first anode connecting electrode described above.

[0147] A first power supply line PSL1 and a 21st data line DL21 are arranged on the first planarization film 160. The 21st data line DL21 can pass through a 21st data line contact hole DLCT21 formed in the first planarization film 160. The 21st data line DL21 can be connected to a first connection electrode DEMSD121 of a second DEMUX switch element that embodies a first color exposed by the 21st data line contact hole DLCT21.

[0148] The first power supply wiring PSL1 can be superimposed on the first electrode of the first DEMUX switch element, the first connection electrode DEMSD121 of the second DEMUX switch element that embodies the first color, the first connection electrode DEMSD112 of the first DEMUX switch element that embodies the second color, and the first connection electrode DEMSD113 of the first DEMUX switch element that embodies the third color.

[0149] The first power supply wiring PSL1 may be connected to any one of several pads. The first power supply wiring PSL1 may receive a first power supply voltage from the drive circuit via the circuit board. Although not shown, the display device may further include a second power supply wiring. The second power supply wiring may be connected to any one of several pads. The second power supply wiring may receive a second power supply voltage from the drive circuit via the circuit board. In this case, the first power supply voltage may be a voltage with a lower potential than the second power supply voltage. For example, the second power supply voltage may be a high-potential drive voltage, and the first power supply voltage may be a low-potential drive voltage.

[0150] The second data metal layer, which includes the first power wiring PSL1 and the 21st data line DL21, may be positioned between the first planarization film 160 and the second planarization film 180. The second planarization film 180 may be positioned to cover the first power wiring PSL1 and the 21st data line DL21. The first power wiring PSL1 and the 21st data line DL21 may contain the same material as the second anode connection electrode described above.

[0151] Referring to Figures 5a and 8, the first test active layer of the first test switch element TET1 is placed on the buffer film BF. The first test active layer may include the first electrode TESD11 of the first test switch element TET1, the second electrode TESD22 of the first test switch element TET1, and the channels TEACT11 and TEACT12 of the first test switch element TET1 placed between them.

[0152] The first test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode and the second electrode of the first test switch element TET1 may be conductive by doping the silicon semiconductor with ions or impurities. The first test active layer is superimposed on the test gate electrode TEG in a third direction (e.g., the Z-axis direction), while the first electrode and the second electrode of the first test switch element TET1 are not superimposed on the test gate electrode TEG in a third direction (e.g., the Z-axis direction).

[0153] The first test switch element TET1 may include a plurality of transistors connected in series. The first test switch element TET1 may include an eleventh test switch element TET11 and a twelfth test switch element TET12. The eleventh test switch element TET11 may include an eleventh test active layer, and the twelfth test switch element TET12 may include a twelfth test active layer.

[0154] The 11th test active layer may include a first electrode TESD11 of the 11th test switch element TET11, a second electrode TESD12 of the 11th test switch element TET11, and a channel TEACT11 of the 11th test switch element TET11 positioned between them.

[0155] The 11th test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode TESD11 and the second electrode TESD12 of the 11th test switch element TET11 may be conductive by doping the silicon semiconductor with ions or impurities. The 11th test active layer superimposes the 11th test gate electrode TEG11 in a third direction (e.g., the Z-axis direction), while the first electrode TESD11 and the second electrode TESD12 of the 11th test switch element TET11 do not superimpose the 11th test gate electrode TEG11 in a third direction (e.g., the Z-axis direction).

[0156] The 12th test active layer may include a first electrode of the 12th test switch element TET12, a second electrode of the 12th test switch element TET12, and a channel TEACT12 of the 12th test switch element TET12 positioned between them.

[0157] The 12th test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode and the second electrode of the 12th test switch element TET12 may be conductive by doping the silicon semiconductor with ions or impurities. The 12th test active layer is superimposed on the 12th test gate electrode TEG12 in a third direction (e.g., the Z-axis direction), while the first electrode and the second electrode of the 12th test switch element TET12 are not superimposed on the 12th test gate electrode TEG12 in a third direction (e.g., the Z-axis direction).

[0158] When multiple transistors are connected in series, the second electrode TESD12 of the 11th test switch element TET11 may be connected to the first electrode of the 12th test switch element TET12.

[0159] The functional layer, including the first test active layer, may be positioned between the buffer film BF and the gate insulating film 130. The gate insulating film 130 may be positioned covering the first test active layer. The first test active layer may contain the same material as the display active layer described above.

[0160] A test gate electrode TEG is placed on the gate insulating film 130. Multiple test gate electrodes TEGs are formed. For example, a test gate electrode TEG may include an 11th test gate electrode TEG 11 and a 12th test gate electrode TEG 12.

[0161] The first gate metal layer, including the 11th test gate electrode TEG11 and the 12th test gate electrode TEG12, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be positioned to cover the 11th test gate electrode TEG11 and the 12th test gate electrode TEG12. The 11th test gate electrode TEG11 and the 12th test gate electrode TEG12 may contain the same material as the indicated gate electrode described above.

[0162] A first test connection wiring TECL1 and a second test connection wiring TECL2 are placed on the first interlayer insulating film 141. A second gate metal layer, including the first test connection wiring TECL1 and the second test connection wiring TECL2, may be placed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 may be placed over the first test connection wiring TECL1 and the second test connection wiring TECL2. The first test connection wiring TECL1 and the second test connection wiring TECL2 may contain the same material as the second capacitor electrode described above.

[0163] A first test connection electrode TECE1 and a second test connection electrode TECE2 are placed on the second interlayer insulating film 142.

[0164] The first test connection electrode TECE1 may penetrate the 11th test connection contact hole TETCT11 formed in the second interlayer insulating film 142. The first test connection electrode TECE1 may be connected to the first test connection wiring TECL1 exposed by the 11th test connection contact hole TETCT11.

[0165] The first test connection electrode TECE1 can penetrate the 12th test connection contact hole TETCT12 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130. The first test connection electrode TECE1 can be connected to the first test active layer exposed by the 12th test connection contact hole TETCT12.

[0166] The second test connection electrode TECE2 may penetrate the 21st test connection contact hole TETCT21 formed in the second interlayer insulating film 142. The second test connection electrode TECE2 may be connected to the second test connection wiring TECL2 exposed by the 21st test connection contact hole TETCT21.

[0167] The second test connection electrode TECE2 may penetrate the 22nd test connection contact hole TETCT22 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130. The second test connection electrode TECE2 may be connected to the first test active layer exposed by the 22nd test connection contact hole TETCT22.

[0168] Referring to Figures 5a and 9, the second test active layer of the second test switch element TET2 is placed on the buffer film BF. The second test active layer may include the first electrode TESD13 of the second test switch element TET2, the second electrode TESD24 of the second test switch element TET2, and the channels TEACT21 and TEACT22 of the second test switch element TET2 placed between them.

[0169] The second test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode and the second electrode of the second test switch element TET2 may be conductive due to ion or impurity doping of the silicon semiconductor. The second test active layer is superimposed on the test gate electrode TEG in a third direction (e.g., the Z-axis direction), while the first electrode and the second electrode of the second test switch element TET2 are not superimposed on the test gate electrode TEG in a third direction (e.g., the Z-axis direction).

[0170] The second test switch element TET2 may include multiple transistors connected in series. The second test switch element TET2 may include the 21st test switch element TET21 and the 22nd test switch element TET22. The 21st test switch element TET21 may include the 21st test active layer, and the 22nd test switch element TET22 may include the 22nd test active layer.

[0171] The 21st test active layer may include a first electrode of the 21st test switch element TET21, a second electrode of the 21st test switch element TET21, and a channel TEACT21 of the 21st test switch element TET21 positioned between them.

[0172] The 21st test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode and the second electrode of the 21st test switch element TET21 may be conductive by doping the silicon semiconductor with ions or impurities. The 21st test active layer is superimposed on the 21st test gate electrode TEG21 in a third direction (e.g., the Z-axis direction), while the first electrode and the second electrode of the 21st test switch element TET21 are not superimposed on the 21st test gate electrode TEG21 in a third direction (e.g., the Z-axis direction).

[0173] The 22nd test active layer may include a first electrode of the 22nd test switch element TET22, a second electrode of the 22nd test switch element TET22, and a channel TEACT22 of the 22nd test switch element TET22 positioned between them.

[0174] The 22nd test active layer may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first electrode and the second electrode of the 22nd test switch element TET22 may be conductive by doping the silicon semiconductor with ions or impurities. The 22nd test active layer is superimposed on the 22nd test gate electrode TEG22 in a third direction (e.g., the Z-axis direction), while the first electrode and the second electrode of the 22nd test switch element TET22 are not superimposed on the 22nd test gate electrode TEG22 in a third direction (e.g., the Z-axis direction).

[0175] When multiple transistors are connected in series, the second electrode of the 21st test switch element TET21 may be connected to the first electrode of the 22nd test switch element TET22.

[0176] The functional layer, including the second test active layer, may be positioned between the buffer film BF and the gate insulating film 130. The gate insulating film 130 may be positioned covering the second test active layer. The second test active layer may contain the same material as the display active layer described above.

[0177] A third test connection wiring TECL3 and a test gate electrode TEG are arranged on the gate insulating film 130. Multiple test gate electrodes TEGs are formed. For example, a test gate electrode TEG may include a 21st test gate electrode TEG21 and a 22nd test gate electrode TEG22.

[0178] The first gate metal layer, including the third test connection wiring TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be positioned to cover the third test connection wiring TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22. The third test connection wiring TECL3, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22 may contain the same material as the indicated gate electrode described above.

[0179] A fourth test connection wiring TECL4 is placed on the first interlayer insulating film 141. The second gate metal layer, including the fourth test connection wiring TECL4, may be placed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 may be placed over the fourth test connection wiring TECL4. The fourth test connection wiring TECL4 may contain the same material as the second capacitor electrode described above.

[0180] A third test connection electrode TECE3 and a fourth test connection electrode TECE4 are placed on the second interlayer insulating film 142.

[0181] The third test connection electrode TECE3 may penetrate the 31st test connection contact hole TETCT31 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141. The third test connection electrode TECE3 may be connected to the third test connection wiring TECL3 exposed by the 31st test connection contact hole TETCT31.

[0182] The third test connection electrode TECE3 may penetrate the 32nd test connection contact hole TETCT32 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130. The third test connection electrode TECE3 may be connected to the second test active layer exposed by the 32nd test connection contact hole TETCT32.

[0183] The fourth test connection electrode TECE4 may penetrate the 41st test connection contact hole TETCT41 formed in the second interlayer insulating film 142. The fourth test connection electrode TECE4 may be connected to the fourth test connection wiring TECL4 exposed by the 41st test connection contact hole TETCT41.

[0184] The fourth test connection electrode TECE4 may penetrate the 42nd test connection contact hole TETCT42 formed in the second interlayer insulating film 142, the first interlayer insulating film 141, and the gate insulating film 130. The fourth test connection electrode TECE4 may be connected to the second test active layer exposed by the 42nd test connection contact hole TETCT42.

[0185] Referring to Figures 8 and 9, the first test connection wiring TECL1, the second test connection wiring TECL2, and the fourth test connection wiring TECL4 can all be formed on the first interlayer insulating film 141. The third test connection wiring TECL3 can be formed on the gate insulating film 130.

[0186] In one embodiment, the second test connection wiring TECL2 may be formed on the same layer as the fourth test connection wiring TECL4, while the first test connection wiring TECL1 may be formed on a different layer from the third test connection wiring TECL3. The paths for transmitting the data voltage output from the DEMUX switch element to the test switch element are the second test connection wiring TECL2 and the fourth test connection wiring TECL4 (Figure 5b), and these may be formed from the same material to improve test accuracy and reduce skew deviation. The first test connection wiring TECL1 and the third test connection wiring TECL3 may be formed from different materials for advantageous wiring design and placement as shown in the plan view described above.

[0187] Figure 10 is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line II-II' of Figure 5a. Figure 11 is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line III-III' of Figure 5a. Figure 12 is an illustrative cross-sectional view of a display device according to a second embodiment of this specification, cut along line IV-IV' of Figure 5a. Components having substantially the same function as those in the embodiments described above are given the same reference numerals, and repeated descriptions thereof are omitted.

[0188] The first and second embodiments described above differ in that the second test connection wiring TECL2, the third test connection wiring TECL3, and the fourth test connection wiring TECL4 are formed on the gate insulating film 130, while the first test connection wiring TECL1 is formed on the first interlayer insulating film 141. In the first embodiment, the first test connection wiring TECL1, the second test connection wiring TECL2, and the fourth test connection wiring TECL4 are formed on the first interlayer insulating film 141, and the third test connection wiring TECL3 is formed on the gate insulating film 130.

[0189] Referring to Figures 5a and 10, the second test connection wiring TECL2 and the fourth test connection wiring TECL4 are positioned on the gate insulating film 130. The first gate metal layer, including the second test connection wiring TECL2 and the fourth test connection wiring TECL4, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be positioned to cover the second test connection wiring TECL2 and the fourth test connection wiring TECL4. The second test connection wiring TECL2 and the fourth test connection wiring TECL4 may contain the same material as the indicator gate electrode described above.

[0190] The first connecting electrode DEMSD111 of the first DEMUX switch element that embodies the first color can penetrate the first test contact hole TECT1 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0191] The first connecting electrode DEMSD121 of the second DEMUX switch element that embodies the first color can penetrate the second test contact hole TECT2 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0192] Referring to Figures 5a and 11, the test gate electrode TEG and the second test connection wiring TECL2 are placed on the gate insulating film 130.

[0193] The first gate metal layer, including the 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection wiring TECL2, may be placed between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be placed over the 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection wiring TECL2. The 11th test gate electrode TEG11, the 12th test gate electrode TEG12, and the second test connection wiring TECL2 may contain the same material as the indicated gate electrode described above.

[0194] The first test connection wiring TECL1 is placed on the first interlayer insulating film 141.

[0195] A first test connection electrode TECE1 and a second test connection electrode TECE2 are placed on the second interlayer insulating film 142.

[0196] The second test connection electrode TECE2 may penetrate the 21st test connection contact hole TETCT21 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141. The second test connection electrode TECE2 may be connected to the second test connection wiring TECL2 exposed by the 21st test connection contact hole TETCT21.

[0197] Referring to Figures 5a and 12, the third test connection wiring TECL3, the fourth test connection wiring TECL4, and the test gate electrode TEG are arranged on the gate insulating film 130.

[0198] The first gate metal layer, including the third test connection wiring TECL3, the fourth test connection wiring TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be positioned to cover the third test connection wiring TECL3, the fourth test connection wiring TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22. The third test connection wiring TECL3, the fourth test connection wiring TECL4, the 21st test gate electrode TEG21, and the 22nd test gate electrode TEG22 may contain the same material as the indicated gate electrode described above.

[0199] A third test connection electrode TECE3 and a fourth test connection electrode TECE4 are placed on the second interlayer insulating film 142.

[0200] The fourth test connection electrode TECE4 may penetrate the 41st test connection contact hole TETCT41 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141. The fourth test connection electrode TECE4 may be connected to the fourth test connection wiring TECL4 exposed by the 41st test connection contact hole TETCT41.

[0201] Referring to Figures 11 and 12, the second test connection wiring TECL2, the third test connection wiring TECL3, and the fourth test connection wiring TECL4 can all be formed on the gate insulating film 130. The first test connection wiring TECL1 can be formed on the first interlayer insulating film 141.

[0202] Figure 13 is an illustrative cross-sectional view of a display device according to an embodiment of this specification, cut along line V-V' in Figure 5a.

[0203] Referring to Figures 5a and 13, a resistive active layer RPACT may be formed on a buffer film BF. The resistive active layer RPACT may have a first resistive connection electrode RPCE1 and a second resistive connection electrode RPCE2 superimposed on it, and at least a portion of them. The functional layer including the resistive active layer RPACT may be positioned between the buffer film BF and the gate insulating film 130. The gate insulating film 130 may be positioned covering the resistive active layer RPACT. The resistive active layer RPACT may contain the same material as the display active layer described above, but the embodiments herein are not limited thereto.

[0204] A first resistive connection electrode RPCE1 and a second resistive connection electrode RPCE2 are arranged on the second interlayer insulating film 142. The first resistive connection electrode RPCE1 can penetrate the first group resistive contact holes RPCT1, RPCT2, and RPCT3 formed in the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130. The first resistive connection electrode RPCE1 can be connected to the resistive active layer RPACT exposed by the first group resistive contact holes RPCT1, RPCT2, and RPCT3.

[0205] The second resistive connection electrode RPCE2 may penetrate the second group resistive contact holes RPCT4, RPCT5, and RPCT6 formed in the first interlayer insulating film 141, the second interlayer insulating film 142, and the gate insulating film 130. The second resistive connection electrode RPCE2 may be connected to the resistive active layer RPACT exposed by the second group resistive contact holes RPCT4, RPCT5, and RPCT6.

[0206] The first group of resistive contact holes RPCT1, RPCT2, RPCT3 and the second group of resistive contact holes RPCT4, RPCT5, RPCT6 may each contain multiple resistive contact holes, and the number of contact holes in the first group of resistive contact holes RPCT1, RPCT2, RPCT3 may be the same as the number of contact holes in the second group of resistive contact holes RPCT4, RPCT5, RPCT6. By forming multiple contact holes in each, the signal from the test gate pad TGP can be smoothly transmitted to the test switch element despite the high resistance of the resistive active layer RPACT. Furthermore, by forming the same number of contact holes in the first group of resistive contact holes RPCT1, RPCT2, RPCT3 and the second group of resistive contact holes RPCT4, RPCT5, RPCT6, the electrostatic discharge function of the resistive active layer RPACT can be performed uniformly on both sides, improving the reliability of the display device.

[0207] Figure 14 is an illustrative cross-sectional view of a display device according to an embodiment of this specification, cut along line VI-VI' in Figure 5a.

[0208] Referring to Figures 5a and 14, the 111DEMUX connection wiring DEML111 is positioned on the gate insulating film 130. The first gate metal layer, including the 111DEMUX connection wiring DEML111, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first interlayer insulating film 141 may be positioned covering the 111DEMUX connection wiring DEML111. The 111DEMUX connection wiring DEML111 may contain the same material as the indicator gate electrode described above.

[0209] A 13th DEMUX connection wiring DEML 13 is placed on the first interlayer insulating film 141. A second gate metal layer containing the 13th DEMUX connection wiring DEML 13 may be placed between the first interlayer insulating film 141 and the second interlayer insulating film 142. The second interlayer insulating film 142 may be placed over the 13th DEMUX connection wiring DEML 13. The 13th DEMUX connection wiring DEML 13 may contain the same material as the second capacitor electrode described above.

[0210] On the second interlayer insulating film 142, the second connection electrode DEMSD211 of the first DEMUX switch element that embodies the first color, and the 12th DEMUX connection wiring DEML12 are arranged. On the second interlayer insulating film 142, the first clock wiring CL1 and the second clock wiring CL2 are arranged. Between the second connection electrode DEMSD211 of the first DEMUX switch element that embodies the first color, and the 12th DEMUX connection wiring DEML12, the first clock wiring CL1 and the second clock wiring CL2 may be arranged sequentially.

[0211] The second connecting electrode DEMSD211 of the first DEMUX switch element that embodies the first color can penetrate the 11th DEMUX contact hole DECT11 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141. The second connecting electrode DEMSD211 of the first DEMUX switch element that embodies the first color can be connected to the 111th DEMUX connecting wiring DEML111 exposed by the 11th DEMUX contact hole DECT11.

[0212] The 12th DEMUX connection wiring DEML12 may penetrate the 11th DEMUX connection contact hole DEMCT11 formed in the second interlayer insulating film 142 and the first interlayer insulating film 141. The 12th DEMUX connection wiring DEML12 may be connected to the 111th DEMUX connection wiring DEML111, which is exposed by the 11th DEMUX connection contact hole DEMCT11.

[0213] The 12th DEMUX connection wiring DEML12 may penetrate the 1st DEMUX connection contact hole DEMCT1 formed in the 2nd interlayer insulating film 142. The 12th DEMUX connection wiring DEML12 may be connected to the 13th DEMUX connection wiring DEML13, which is exposed by the 1st DEMUX connection contact hole DEMCT1.

[0214] The first data metal layer, which includes the second connection electrode DEMSD211 and the 12th DEMUX connection wiring DEML12 of the first DEMUX switch element embodying the first color, may be positioned between the second interlayer insulating film 142 and the first planarization film 160. The first planarization film 160 may be positioned covering them. The second connection electrode DEMSD211 and the 12th DEMUX connection wiring DEML12 of the first DEMUX switch element embodying the first color may contain the same material as the first anode connection electrode described above.

[0215] A first power supply wiring PSL1 is placed on the first planarization film 160. The first power supply wiring PSL1 may be superimposed on the second connection electrode DEMSD211 of the first DEMUX switch element embodying the first color, the 12th DEMUX connection wiring DEML12, the first clock wiring CL1, the second clock wiring CL2, and the 111th DEMUX connection wiring DEML111. A second data metal layer containing the first power supply wiring PSL1 may be placed between the first planarization film 160 and the second planarization film 180. The second planarization film 180 may be placed over the first power supply wiring PSL1. The first power supply wiring PSL1 may contain the same material as the second anode connection electrode described above.

[0216] Figure 15 is an illustrative cross-sectional view of a display device according to an embodiment of this specification, cut along line VII-VII' of Figure 5a.

[0217] Referring to Figures 5a and 15, the 121st DEMUX connection wiring DEML121, the 23rd DEMUX connection wiring DEML23, and the 131st DEMUX connection wiring DEML131 are arranged on the gate insulating film 130. The second connection electrode DEMSD212 and the 22nd DEMUX connection wiring DEML22 of the first DEMUX switch element that embodies the second color are arranged on the second interlayer insulating film 142. The 131st DEMUX connection wiring DEML131 is arranged between the 121st DEMUX connection wiring DEML121 and the 23rd DEMUX connection wiring DEML23.

[0218] The first gate metal layer, including the 121st DEMUX connection wiring DEML121, the 23rd DEMUX connection wiring DEML23, and the 131st DEMUX connection wiring DEML131, may be positioned between the gate insulating film 130 and the first interlayer insulating film 141. The first gate metal layer may be positioned covering these. The 121st DEMUX connection wiring DEML121, the 23rd DEMUX connection wiring DEML23, and the 131st DEMUX connection wiring DEML131 may contain the same material as the indicated gate electrode described above.

[0219] On the second interlayer insulating film 142, the second connection electrode DEMSD212 and the 22nd DEMUX connection wiring DEML22 of the first DEMUX switch element that embodies the second color are arranged. Between these, the first clock wiring CL1, the second clock wiring CL2, and the 12th DEMUX connection wiring DEML12 may be arranged sequentially.

[0220] The second connecting electrode DEMSD212 of the first DEMUX switch element that embodies the second color can penetrate the 12th DEMUX contact hole DECT12 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142. The second connecting electrode DEMSD212 of the first DEMUX switch element that embodies the second color can be connected to the 121st DEMUX connecting wiring DEML121 exposed by the 12th DEMUX contact hole DECT12.

[0221] The 22nd DEMUX connection wiring DEML22 may penetrate the 12th DEMUX connection contact hole DEMCT12 formed in the first interlayer insulating film 141 and the second interlayer insulating film 142. The 22nd DEMUX connection wiring DEML22 may be connected to the 121st DEMUX connection wiring DEML121, which is exposed by the 12th DEMUX connection contact hole DEMCT12.

[0222] The 22nd DEMUX connection wiring DEML22 may penetrate the 2nd DEMUX connection contact hole DEMCT2 formed in the 1st interlayer insulating film 141 and the 2nd interlayer insulating film 142. The 22nd DEMUX connection wiring DEML22 may be connected to the 23rd DEMUX connection wiring DEML23, which is exposed by the 2nd DEMUX connection contact hole DEMCT2.

[0223] The first data metal layer, which includes the second connection electrode DEMSD212, the 22nd DEMUX connection wiring DEML22, the 12th DEMUX connection wiring DEML12, the first clock wiring CL1, and the second clock wiring CL2 of the first DEMUX switch element that embodies the second color, may be placed between the second interlayer insulating film 142 and the first planarization film 160. The first planarization film 160 may be placed over them. These may contain the same material as the first anode connection electrode described above.

[0224] A first power supply wiring PSL1 is placed on the first planarization film 160. The first power supply wiring PSL1 can be superimposed on the second connection electrode DEMSD212 of the first DEMUX switch element that embodies the second color, the 22nd DEMUX connection wiring DEML22, the 12th DEMUX connection wiring DEML12, the first clock wiring CL1, the second clock wiring CL2, the 121st DEMUX connection wiring DEML121, the 213th DEMUX connection wiring, and the 23rd DEMUX connection wiring DEML23.

[0225] The second data metal layer, including the first power wiring PSL1, may be positioned between the first planarization film 160 and the second planarization film 180. The second planarization film 180 may be positioned to cover the first power wiring PSL1. The first power wiring PSL1 may contain the same material as the second anode connection electrode described above.

[0226] Referring to Figures 5d, 14, and 15, at least one of the multiple DEMUX connection wires DEML111, DEML12, DEML13 (e.g., DEML13) connecting the first data pad to the first group DEMUX switch element may be located on a different layer from at least one of the multiple DEMUX connection wires DEML121, DEML22, DEML23 (e.g., DEML23) connecting the second data pad to the first group DEMUX switch element. At least one of the multiple DEMUX connection wires DEML121, DEML22, DEML23 (e.g., DEML23) connecting the second data pad to the first group DEMUX switch element may be located on a different layer from at least one of the multiple DEMUX connection wires DEML131, DEML32, DEML33 (e.g., DEML33) connecting the third data pad to the first group DEMUX switch element.

[0227] The 13th DEMUX connection wiring DEML13 and the 23rd DEMUX connection wiring DEML23 may be placed on different layers. The 23rd DEMUX connection wiring DEML23 and the 33rd DEMUX connection wiring DEML33 may be placed on different layers. The 13th DEMUX connection wiring DEML13 and the 33rd DEMUX connection wiring DEML33 may be placed on the same layer. Arranging the layers of DEMUX connection wiring as described above has the advantage of making wiring management easier and ensuring effective design area.

[0228] The display devices according to the embodiments of this specification can be applied to a variety of electronic devices. An electronic device according to one embodiment includes the display device described above and may further include modules or devices having other additional functions besides the display device.

[0229] Figure 16 is a block diagram of an electronic device according to one embodiment of this specification. Figure 17 is a schematic diagram of an electronic device according to various embodiments of this specification.

[0230] Referring to Figure 16, an electronic device 10 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power supply module 14.

[0231] The processor 12 may include at least one of the following: a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0232] Memory 13 stores data information necessary for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in memory 13, video data signals and / or input control signals are transmitted to the display module 11, which processes the provided signals and outputs video information via the display screen.

[0233] The power module 14 may include a power supply module such as a power adapter or a battery device. The power module 14 may also include a power conversion module. The power conversion module can convert the power supplied by the power supply module to generate the power necessary for the operation of the electronic device 10.

[0234] At least one of the components of the electronic device 10 described above can be incorporated into the display device according to the embodiment described above. Furthermore, some of the individual modules functionally contained within a single module can be incorporated into the display device, while others can be provided separately from the display device. For example, the display device includes a display module 11, while the processor 12, memory 13, and power supply module 14 can be provided not as a display device, but as other devices within the electronic device.

[0235] Referring to Figure 17, the various electronic devices to which the display device according to the embodiments herein is applied include image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptops 10_1c, TVs 10_1d, and desk monitors 10_1e. Furthermore, the various electronic devices to which the display device according to the embodiments herein is applied include wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as CIDs (Center Information Displays) located on the instrument panel, center fascia, and dashboard of an automobile, and rearview mirror displays.

[0236] According to the display device disclosed herein, the first and second test pads, when turned on, can receive a supply of data voltages to be applied to the first and second subpixels, respectively, which embody the first color. The implementer can turn on the test switch elements to verify whether the first and second DEMUX switch elements output appropriate data voltages to multiple subpixels. Furthermore, the test switch elements can be turned off in situations where measurement of the output data voltage is not necessary, such as for product shipment. This reduces interference with data lines located on the display area side (e.g., current leakage and parasitic capacitance).

[0237] The display device according to the embodiments of this specification may include an electrostatic discharge circuit connected via adjacent wiring to the output sections of a plurality of pads. It may also include a resistor connected to the test gate pad. Unlike a resistor, the electrostatic discharge circuit can perform the function of discharging static electricity to the outside of the display device by utilizing ground connection or the like. The resistor can facilitate the on / off switching of the test switch element and protect the display device from static electricity.

[0238] The display device according to the embodiments of this specification includes a plurality of test switch elements, a plurality of test pads, and a test gate pad for testing the data voltage output from the DEMUX switch element. By including these, it is possible to verify whether a first DEMUX switch element embodying a first color and a second DEMUX switch element embodying a first color uniformly output data voltage from the first data pad.

[0239] While embodiments of this specification have been described above with reference to the attached drawings, a person with ordinary skill in the art to which the embodiments disclosed herein belong will understand that the embodiments disclosed herein can be carried out in other specific forms without altering their technical idea or essential features. Therefore, the above embodiments should be understood to be illustrative and not limiting in all respects. [Explanation of symbols]

[0240] 10 equipment 100 Display Panels 10_1a Smartphone 10_1b Tablet PC 10_1c Laptop 10_1d TV 10_1e Desktop Monitor 10_2a Smart Glasses 10_2b Head-mounted display 10_2c Smartwatch 10_3 Electronic devices for vehicles 11 Display Module 12 processors 13 memory 130 Gate Insulator 14 Power Modules 141 First interlayer insulating film 142 Second Interlayer Insulating Film 15 memory 160 First planarization film 171 Pixel electrodes 171,172,173 Light-emitting element 172 Emitting layer 173 Common electrode 180 Second planarization film 190 Bank 200 Display drive circuit 300 circuit boards BF buffer membrane C1 Capacitor CE connection electrode CL1 First Clock Wiring CL2 Second Clock Wiring CLP1, CLP2 Multiple Clock Pads Cr chromium Cu copper DA display area DEMT11, DEMT12, DEMT13, DEMT14 Multiple sub-DEMUX switch elements DG Indicator Gate Socket DP1 First data pad DP1, DP2, DP3 Multiple data pads DP2 Second Data Pad DP3 Third Data Pad DT display transistor EA Illumination Area EDC (Electrostatic Discharge) Circuit EML light-emitting layer GP Multiple gate pads Mg Magnesium Molybdenum NDA Hidden Area Nd Neodymium Ni (nickel) PAD Pd Palladium RP resistance RPCT1, RPCT2, RPCT3: First group of resistor contact holes RPCT4, RPCT5, RPCT6 Second Group Resistance Contact Holes SP subpixel SP11, SP12, SP13 Multiple first subpixels SP11, SP12, SP13, SP21, SP22, SP23 Subpixels SP21, SP22, SP23: Multiple second subpixels SUB board TCO (Transparent Conductive Oxide) TEACT11, TEACT12 Channels TEACT21, TEACT22 Channels TEG Test Gate Foot TET1, TET2: First test switch element, second test switch element TET11, TET12, TET21, TET22: Multiple sub-test switch elements TGP Test Gate Pad TGP, TP1, TP2, DP1, DP2, DP3 Multiple pads TP1 First Test Pad TP2 Second Test Pad TP1, TP2 Multiple test pads

Claims

1. Multiple subpixels, Multiple data lines electrically connected to the multiple subpixels, Multiple data pads electrically connected to the aforementioned multiple data lines, A plurality of test pads, including a first test pad and a second test pad, which are separated from the plurality of data pads, A first group DEMUX switch element connects the first group data lines among the plurality of data lines to the plurality of data pads, A second group DEMUX switch element connects the second group data lines among the plurality of data lines to the plurality of data pads, A display device comprising a first test switch element positioned between the first electrode of any one of the first DEMUX switch elements included in the first group of DEMUX switch elements and the first test pad.

2. Among the multiple first DEMUX switch elements included in the first group of DEMUX switch elements, The remaining first DEMUX switch elements, excluding any one of the aforementioned first DEMUX switch elements, The display device according to claim 1, which is electrically isolated from the first test switch element.

3. The display device according to claim 1, further comprising a second test switch element disposed between the first electrode of any one of the second DEMUX switch elements included in the second group of DEMUX switch elements and the second test pad.

4. Among the multiple second DEMUX switch elements included in the second group of DEMUX switch elements, The remaining second DEMUX switch elements, excluding one of the aforementioned second DEMUX switch elements, The display device according to claim 3, which is electrically isolated from the second test switch element.

5. The gate electrode of the first test switch element and The display device according to claim 3, further comprising a resistor connected to the gate electrode of the second test switch element.

6. The display device according to claim 5, further comprising the plurality of data pads, the plurality of test pads, and an electrostatic discharge circuit electrically connected to the resistor.

7. The display device according to claim 1, wherein the first group DEMUX switching element includes a plurality of transistors connected in parallel.

8. The display device according to claim 3, wherein the second group DEMUX switching element includes a plurality of transistors connected in parallel.

9. The display device according to claim 1, wherein the first test switch element includes a plurality of transistors connected in series.

10. The display device according to claim 3, wherein the second test switch element includes a plurality of transistors connected in series.

11. The aforementioned multiple subpixels are, A first group subpixel connected to the first group DEMUX switch element via the first group data line, Includes a second group subpixel connected to the second group DEMUX switch element via the second group data line, Among the multiple first subpixels included in the first group subpixel, Any one of the first subpixels connected to any one of the aforementioned first DEMUX switch elements embodies a first color, Among the multiple second subpixels included in the second group subpixel, The display device according to claim 3, wherein any one second subpixel connected to any one of the second DEMUX switch elements embodies the first color.

12. Any one of the first subpixels is connected to the first electrode of any one of the first DEMUX switch elements. The display device according to claim 11, wherein any one of the second subpixels is connected to the first electrode of any one of the second DEMUX switch elements.

13. A display module that displays video, A power supply module for supplying power to the aforementioned display module, The display module includes a processor that transmits data signals and control signals. The aforementioned display module is Multiple subpixels, Multiple data lines electrically connected to the multiple subpixels, Multiple data pads electrically connected to the aforementioned multiple data lines, A plurality of test pads, including a first test pad and a second test pad, which are separated from the plurality of data pads, A first group DEMUX switch element connects the first group data lines among the plurality of data lines to the plurality of data pads, A second group DEMUX switch element connects the second group data lines among the plurality of data lines to the plurality of data pads, An electronic device comprising a first test switch element positioned between the first electrode of any one of the first DEMUX switch elements included in the first group of DEMUX switch elements and the first test pad.

14. It further includes a resistive active layer, The first test switch element includes a first test active layer and a first test gate electrode disposed on a gate insulating film covering the first test active layer. The resistive active layer is electrically connected to the gate electrode of the first test switch element. The first test active layer is, A first electrode connected to the first electrode of any one of the first DEMUX switch elements, The second electrode connected to the first test pad, and The electronic device according to claim 13, comprising a channel disposed between a first electrode of the first test active layer and a second electrode of the first test active layer.

15. The electronic device according to claim 14, wherein the first test active layer and the resistive active layer are arranged on the same layer.

16. The present invention further includes a second test switch element positioned between the first electrode of any one of the second DEMUX switch elements included in the second group of DEMUX switch elements and the second test pad, The second test switch element includes a second test active layer and a second test gate electrode disposed on a gate insulating film covering the second test active layer. The resistive active layer is electrically connected to the gate electrode of the second test switch element. The second test active layer is, A first electrode connected to the first electrode of any one of the second DEMUX switch elements, The second electrode connected to the second test pad, and The electronic device according to claim 14, comprising a channel disposed between the first electrode of the second test active layer and the second electrode of the first test active layer.

17. The first electrode of the first test switch element is connected to the first electrode of any one of the first DEMUX switch elements via a second test connection wiring. The second electrode of the first test switch element is connected to the first test pad via the first test connection wiring. The first electrode of the second test switch element is connected to the first electrode of any one of the second DEMUX switch elements via a fourth test connection wire. The second electrode of the second test switch element is connected to the second test pad via a third test connection wiring. The electronic device according to claim 16, wherein the second test connection wiring and the fourth test connection wiring are arranged on the same layer.

18. The electronic device according to claim 17, wherein the first test connection wiring and the third test connection wiring are arranged on different layers from each other.

19. Further including a first power supply wiring to which a first power supply voltage is applied, The electronic device according to claim 14, wherein the first power supply wiring is spaced apart from the first test switch element on a plane.

20. The electronic device according to claim 19, wherein the first power supply wiring is separated from the resistive active layer on a plane.

21. The electronic device according to claim 19, wherein the first power supply wiring is superimposed on the first group DEMUX switch element and the second group DEMUX switch element on a plane.

22. A first resistive connection electrode connected to the resistive active layer via a plurality of first group resistive contact holes, The electronic device according to claim 14, further comprising a second resistive connection electrode connected to the resistive active layer via a plurality of second group resistive contact holes.

23. The number of contact holes connecting the first resistive connection electrode and the resistive active layer is: The electronic device according to claim 22, wherein the number of contact holes connecting the second resistive connection electrode and the resistive active layer is the same.

24. The electronic device according to claim 22, wherein the resistance of the resistive active layer is 1000 Ω or more and 10000 Ω or less.

25. The plurality of data pads include a first data pad and a second data pad, At least one of the multiple DEMUX connection wires connecting the first data pad to the first group DEMUX switch element is: The electronic device according to claim 13, wherein the second data pad is arranged on a layer different from at least one of the plurality of DEMUX connection wirings that connect to the first group DEMUX switch element.

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