Data packet forwarding method, gateway device, storage medium and program
By using multiple processors and FPGA chips working together in the gateway device, and employing a weighted round-robin scheduling mode and load balancing algorithm, the problem of limited processing performance of a single CPU is solved, achieving high-speed forwarding of data packets and balanced utilization of resources.
WO2025248313A1 Publication Date: 2025-12-04CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PTE LTD
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Patent Information
- Application Number
- PCT/IB2025/051462
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-29
- Filing Date
- 2025-02-12
- Publication Date
- 2025-12-04
AI Technical Summary
Technical Problem
Existing gateway devices suffer from limited single-CPU processing performance and uneven load when handling elephant stream data packets, resulting in low packet forwarding performance and long latency.
Method used
Multiple processors and programmable chips (such as FPGAs) work together to dynamically allocate data packets to different data processors for processing through a weighted round-robin scheduling mode and load balancing algorithm, thereby achieving load balancing and high-speed forwarding.
Benefits of technology
It reduces packet forwarding latency, improves packet processing efficiency, and achieves high-speed packet forwarding and balanced resource utilization.
✦ Generated by Eureka AI based on patent content.
Abstract
Provided in the embodiments of the present disclosure are a data packet forwarding method, a gateway device, a storage medium and a program. The gateway device comprises a plurality of processors and a network card provided with a programmable chip, wherein the plurality of processors comprise a control processor and a plurality of data processors. The control processor sends to the programmable chip a scheduling mode setting instruction including a first scheduling mode, determines weighted round-robin values of the plurality of data processors on the basis of loads of the plurality of data processors, and sends the weighted round-robin values of the plurality of data processors to the programmable chip. The programmable chip receives a data packet sent by a source-end device, and determines, on the basis of the first scheduling mode and the weighted round-robin values of the plurality of data processors, a first data processor, the number of round-robin cycles of which has reached a corresponding weighted round-robin value, and the programmable chip then distributes the data packet to the first data processor for processing, receives the processed data packet fed back by the first data processor, and sends the processed data packet to a destination-end device. The solution can reduce the forwarding delay of data packets.
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