Compression circuit for information stored in memory, and electronic device comprising same

The compression circuit in electronic devices addresses memory management challenges by simultaneously scanning and compressing segments of volatile memory, enhancing processing efficiency and reducing delays through efficient memory usage and rapid restoration of processes.

WO2026111409A1PCT designated stage Publication Date: 2026-05-28SAMSUNG ELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Filing Date
2025-11-19
Publication Date
2026-05-28

AI Technical Summary

Technical Problem

Existing electronic devices face challenges in efficiently managing memory usage, particularly in volatile memory, due to the dynamic nature of software applications and processes, leading to increased demand and potential delays in processing when information is cached from non-volatile to volatile memory.

Method used

A compression circuit is employed within the electronic device that includes multiple processing circuits to scan and compress segments of information stored in volatile memory, utilizing a second volatile memory to store compressed data, allowing simultaneous scanning and compression of multiple segments, thereby reducing memory usage and enhancing processing speed.

Benefits of technology

The compression circuit effectively reduces memory usage and minimizes delays by compressing inactive process information, enabling rapid restoration and maintaining a high number of processes in a standby state, thus improving overall processing efficiency and speed.

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Abstract

This electronic device may comprise a first volatile memory and at least one processor including a compression circuit, wherein the compression circuit includes a second volatile memory, a first processing circuit and a second processing circuit, the first processing circuit comparing, in order to compress a first segment, the bit sequence of the first segment, which has a designated size and is included in a reference region, with the bit sequence of the first segment positioned next to the reference region. The reference region can be changed within the second volatile memory on the basis of the comparison. The first processing circuit can release, from the second volatile memory, a portion of the first segment in which the reference region has been changed on the basis of the comparison. The second processing circuit can store a portion of the second segment of information in a second volatile memory, which is a portion in which the first segment of the information was stored. Prior to completion of the comparison of the first segment of the information, the second processing circuit can use the reference region to begin comparison of a portion of the second segment of information stored in the second volatile memory in order to compress the second segment of information.
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Citation Information

Patent Citations

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