Sensor control board and display device

Abstract

The present invention relates to a sensor control board and a display device. The sensor control board comprises a clock generation circuit that generates a clock, and a phase adjustment circuit. The phase adjustment circuit adjusts a phase difference between a timing at which a pixel potential to be supplied to a plurality of image elements arranged in a lattice pattern in a self-luminous display is determined and the phase of the clock. The phase adjustment circuit uses, as a transmission signal, the clock the phase difference of which has been adjusted, and outputs the transmission signal to a position detector that is disposed on an upper layer or a lower layer of the self-luminous display and detects a position indicated on the self-luminous display.

Description

Sensor control board and display device

[0001] The present invention relates to a sensor control board and a display device, and particularly to a sensor control board provided in a display device having a self-emitting display and a position detector for controlling the position detector, and to the display device.

[0002] Conventionally, a display device having a display unit such as a liquid crystal display or an organic EL display and a position detector provided above or below the display unit for detecting a position indication is known. In such a display device, pixel elements are arranged at intersections of a plurality of source signal lines arranged horizontally on the display unit and a plurality of gate signal lines arranged vertically. The display device displays an image by sequentially driving each gate signal line and applying the potential of the source signal line to the corresponding pixel element. Also known is a sensor control board provided in the display device for controlling the operation of the position detector.

[0003] In this regard, Japanese Unexamined Patent Application Publication No. 2023-145227 discloses a sensor control board that outputs a transmission signal whose phase is adjusted so as to invert the phase at a timing synchronized with the vertical synchronization signal of the display device to the position detector in a display device including a display unit and a position detector.

[0004] Japanese Unexamined Patent Application Publication No. 2023-145227

[0005] Now, in such a display device, electromagnetic noise generated by the transmission signal transmitted to the position detector may affect the operation of the display unit. The potential of the source signal line is superimposed with electromagnetic noise having a component of the frequency of the transmission signal while the transmission signal is being transmitted to the position detector. Since the display device displays an image by applying the potential of the source signal line to the pixel element, noise occurs in the displayed image when electromagnetic noise is superimposed on the potential of the source signal line.

[0006] In the technology described in Japanese Patent Publication No. 2023-145227, when the display device is a liquid crystal display, the polarity of the potential applied to the image element is reversed for each frame of image display, thus canceling out the electromagnetic noise and reducing the noise generated in the image. However, when the display device is a self-emissive display such as an organic EL display, the polarity of the potential applied to the image element is not reversed for each frame. Therefore, in the technology described in Japanese Patent Publication No. 2023-145227, when the display device is a self-emissive display, there is a possibility that noise will be generated in the image due to the electromagnetic noise mentioned above.

[0007] The present invention has been made in view of these problems, and its objective is to provide a sensor control board and a display device that can reduce noise contained in an image displayed by a display device having a self-emissive display.

[0008] To solve the above problems, the first sensor control board according to the present invention includes a clock generation circuit that generates a clock, and a phase adjustment circuit that adjusts the phase difference between the timing at which the pixel potential supplied to a plurality of image elements arranged in a grid on a self-emissive display is determined and the clock, and outputs the clock with the adjusted phase difference as a transmission signal to a position detector arranged on the upper or lower layer of the self-emissive display that detects a position indicated on the self-emissive display.

[0009] Furthermore, in the second sensor control board according to the present invention, the phase adjustment circuit adjusts the phase of the clock so that the pixel potential is the same potential as the DC component of the pixel potential at the timing when the pixel potential is determined.

[0010] Furthermore, in the third sensor control board according to the present invention, the clock generation circuit generates the clock such that the horizontal synchronization frequency of the self-emissive display is an integer multiple of the clock frequency.

[0011] Furthermore, in the fourth sensor control board according to the present invention, the phase adjustment circuit adjusts the phase difference so that the phase difference is sequentially shifted by a reference value at each timing when the pixel potential is determined.

[0012] Furthermore, in the fifth sensor control board according to the present invention, the phase adjustment circuit adjusts the phase difference so that the phase difference is randomly and sequentially shifted within a predetermined range with respect to a reference value at each timing when the pixel potential is determined.

[0013] Furthermore, the sixth sensor control board according to the present invention includes a clock generation circuit that generates a clock, and an output circuit that outputs the clock to a position detector located on the upper or lower layer of the self-emissive display and detects a position indicated on the self-emissive display, and stops the output of the clock for a certain period of time including the timing at which the pixel potential supplied to a plurality of image elements arranged in a grid on the self-emissive display is determined.

[0014] Furthermore, in the seventh sensor control board according to the present invention, the timing at which the pixel potential is determined is synchronized with the horizontal synchronization period of the self-emissive display.

[0015] Furthermore, in the eighth sensor control board according to the present invention, the timing at which the pixel potential is determined is the timing at which the potential of the signal of the gate signal line, which is provided in the self-emissive display and selects the image element, transitions so as to interrupt the supply of the pixel potential to the image element by the source signal line provided in the self-emissive display.

[0016] Furthermore, in the ninth sensor control board according to the present invention, the self-emissive display is an organic electroluminescent display.

[0017] Furthermore, the tenth display device according to the present invention comprises a self-emissive display, a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display, a display controller for controlling the display operation of the self-emissive display, and a sensor control board for controlling the transmission and reception operation of the position detector while the display controller has stopped the display operation of the self-emissive display.

[0018] Furthermore, in the eleventh display device according to the present invention, the display controller controls the operation of the self-emissive display so that it displays in a first period and stops displaying in a second period following the first period during one cycle of vertical synchronization of the self-emissive display, and the sensor control board controls the transmission and reception operation of the position detector during the second period.

[0019] Furthermore, the twelfth display device according to the present invention comprises a self-emissive display, a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display, a sensor control board for controlling the transmission and reception operations of the position detector, and a display controller for controlling the display operation of the self-emissive display while the sensor control board is controlling the reception operation of the position detector.

[0020] Furthermore, in the thirteenth display device according to the present invention, the display controller stops controlling the display operation of the self-emissive display while the sensor control board is controlling the transmission operation to the position detector.

[0021] Furthermore, the fourteenth display device according to the present invention comprises: a self-emissive display; a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display; a display controller for controlling the display operation, including the timing of vertical synchronization of the self-emissive display; and a sensor control board for controlling the transmission and reception operation of the position detector such that burst periods in which burst transmission is performed to the position detector at the timing of vertical synchronization of the self-emissive display and transmission / reception periods in which transmission and reception to and from the position detector are repeated alternately.

[0022] Furthermore, in the fifteenth display device according to the present invention, the self-emissive display has a plurality of image elements arranged in a grid, and a plurality of source signal lines provided parallel to the display surface and parallel to each other, and which supply pixel potential to the image elements, and the position detector has a loop coil that transmits and receives magnetic signals with a position indicator that gives position indication to the position detector, and a portion of it is parallel to the source signal lines.

[0023] Furthermore, in the sixteenth display device according to the present invention, the self-emissive display is an organic electroluminescent display.

[0024] According to the present invention, the sensor control board and the display device can reduce noise contained in the image displayed by the display device having a self-emissive display.

[0025] This figure shows an example of a display device according to the first embodiment. This figure shows an example of the circuit configuration of the display controller and self-emissive display according to the first embodiment. This figure shows an example of an image element according to the first embodiment. This figure shows an example of the circuit configuration of the sensor control unit and position detector according to the first embodiment. This is a graph showing the relationship between the phase of the transmitted signal according to the first embodiment and the degree of flicker in the self-emissive display. This is an example of a timing chart showing the state transitions of each signal in the display device when the phase of the transmitted signal according to the first embodiment is not adjusted. This is an example of a timing chart showing the state transitions of each signal in the display device when the phase of the transmitted signal according to the first embodiment is adjusted. This is a flowchart showing an example of a series of operations of the display device according to the first embodiment. This is an example of a timing chart showing the state transitions of each signal in the display device according to the second embodiment. This is an example of a timing chart showing the state transitions of each signal in the display device according to the third embodiment. This is an example of a timing chart showing the state transitions of each signal in the display device according to the fourth embodiment. This is an example of a timing chart showing the state transitions of each signal in the display device according to the fifth embodiment. This is another example of a timing chart showing the state transitions of each signal in the display device according to the fifth embodiment. This is an example of a timing chart showing the state transitions of each signal in the display device according to the sixth embodiment.

[0026] Hereinafter, embodiments of the present invention (hereinafter referred to as "First Embodiment," "Second Embodiment," "Third Embodiment," "Fourth Embodiment," "Fifth Embodiment," or "Sixth Embodiment") will be described with reference to the attached drawings. To facilitate understanding of the description, the same reference numerals are used for identical components and steps in each drawing whenever possible, and redundant explanations are omitted.

[0027] ---First Embodiment--- First, the first embodiment will be described.

[0028] <Configuration> Figure 1 shows an example of a display device 1 according to the first embodiment. The display device 1 is a computer or monitor held by the user, such as a tablet, smartphone, personal computer monitor, or television receiver. The display device 1 is composed of, for example, a display controller 11, a self-emissive display 12, a sensor control unit 13, and a position detector 14. In the first embodiment, when the self-emissive display 12 and the position detector 14 are viewed from above, the axis extending horizontally from left to right is defined as the X-axis. When the self-emissive display 12 and the position detector 14 are viewed from above, the axis perpendicular to the X-axis and extending from top to bottom is defined as the Y-axis. When the self-emissive display 12 and the position detector 14 are viewed from above, the axis perpendicular to the X-axis and Y-axis and extending from back to front is defined as the Z-axis.

[0029] The display controller 11 controls the image display of the self-emissive display 12 according to the image signal input to the image terminal IMG. The display controller 11 also generates a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC according to the image signal, or extracts the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC contained in the image signal from the image signal. The display controller 11 outputs the extracted horizontal synchronization signal HSYNC to the sensor control unit 13 from terminal H. The display controller 11 also outputs the extracted vertical synchronization signal VSYNC to the sensor control unit 13 from terminal V.

[0030] The self-emissive display 12 is, for example, an organic electroluminescent (EL) display, and displays an image transmitted from the display controller 11 according to the control of the display controller 11.

[0031] The sensor control unit 13 controls the position detector 14 according to the horizontal synchronization signal HSYNC input to terminal H and the vertical synchronization signal VSYNC input to terminal V from the display controller 11. The sensor control unit 13 also outputs the indicated position of the position indicator 2 detected by the position detector 14 on the self-illuminating display 12 to an external processing unit or an internal processing unit (not shown).

[0032] The position detector 14 is, for example, an electromagnetic induction (EMR: Electro Magnetic Resonance) sensor, and transmits a transmission signal TX to the position indicator 2 according to the control of the sensor control unit 13. The position detector 14 also detects the indicated position on the self-emissive display 12 indicated by the position indicator 2 by receiving a resonant signal returned from the position indicator 2 that has received the transmission signal TX. The position detector 14 is configured to include a plurality of loop coils provided planarly on the back side such that, when the display device 1 is viewed from the display surface side of the self-emissive display 12, it includes at least the range of the display surface of the self-emissive display 12. The position detector 14 detects the position of the loop coil with the highest level of received signal as the indicated position on the self-emissive display 12 by the position indicator 2. The position detector 14 outputs information about the detected position to the sensor control unit 13.

[0033] The position indicator 2 is a pointing device that indicates a predetermined position on the self-emissive display 12. The position indicator 2 is configured to include a resonant circuit 20 consisting of an inductive element such as a coil and a capacitive element such as a capacitor. The resonant circuit 20 resonates in response to a signal transmitted from the position detector 14, and the resonant signal generated by this resonance is transmitted to the position detector 14, thereby transmitting the indicated position on the self-emissive display 12 indicated by the position indicator 2 to the position detector 14.

[0034] Figure 2 shows an example of the circuit configuration of the display controller 11 and self-emissive display 12 according to the first embodiment. As shown in Figure 2, the display controller 11 is configured to include a control circuit 110, a gate driver circuit 111, and a source driver circuit 112.

[0035] The gate driver circuit 111 is a circuit that drives the gate signal lines GL1 to GLn, and is located on the left side of the self-emissive display 12 when viewed from the display side (i.e., the Z-axis side). The gate driver circuit 111 drives the gate signal lines GL1 to GLn sequentially by outputting gate signals VG1 to VGn to the corresponding gate signal lines GL1 to GLn according to the control of the control circuit 110. The gate driver circuit 111 also supplies and extracts charge to the gate electrodes of the corresponding image elements 121 via the driven gate signal lines GL1 to GLn. The gate driver circuit 111 may also be located on the right side of the self-emissive display 12 when viewed from the display side (i.e., the Z-axis side).

[0036] The source driver circuit 112 is a circuit that drives the source signal lines SL1 to SLm, and is positioned on the lower side (i.e., the Y-axis side) when the self-emissive display 12 is viewed from the display side. The source driver circuit 112 outputs source signals VS1 to VSm, each having a potential set by the control circuit 110 for each source signal line SL1 to SLm, to the corresponding source signal lines SL1 to SLm at timings controlled by the control circuit 110. The source driver circuit 112 supplies source signals VS1 to VSm corresponding to the image element 121 to the source electrode of the image element 121 corresponding to the intersection of the gate signal lines GL1 to GLn driven by the gate driver circuit 111 and the source signal lines SL1 to SLm. The source driver circuit 112 may also be positioned on the upper side of the self-emissive display 12 when the self-emissive display 12 is viewed from the display side (i.e., the Z-axis side).

[0037] The self-emissive display 12 comprises gate signal lines GL1 to GLn arranged vertically, source signal lines SL1 to SLm arranged horizontally, and image elements 121 positioned at each intersection of the gate signal lines GL1 to GLn and the source signal lines SL1 to SLm. The self-emissive display 12 drives one of the corresponding gate signal lines GL1 to GLn according to the gate signals VG1 to VGn transmitted from the gate driver circuit 111. The self-emissive display 12 also drives each image element 121 corresponding to the source signals VS1 to VSm with the brightness indicated by the source signals VS1 to VSm transmitted from the source driver circuit 112.

[0038] The gate signal lines GL1 to GLn are arranged vertically in n lines in the self-emissive display 12. The gate signal lines GL1 to GLn are driven by gate signals VG1 to VGn transmitted from the gate driver circuit 111 and relay the exchange of charge between the gate electrode of the image element 121 at the intersection with the source signal lines SL1 to SLm and the gate driver circuit 111.

[0039] Source signal lines SL1 to SLm are arranged horizontally in m lengths in the self-emissive display 12. Source signal lines SL1 to SLm are driven by source signals VS1 to VSm transmitted from the source driver circuit 112 and relay the charge exchange between the source electrode of the image element 121 at the intersection with the gate signal lines GL1 to GLn and the source driver circuit 112.

[0040] The image element 121 is, for example, an organic EL image element, and a total of n × m images are arranged in the self-emissive display 12 at the intersections of the gate signal lines GL1 to GLn and the source signal lines SL1 to SLm. One of the gate signal lines GL1 to GLn of the image element 121 is connected to the gate electrode, and one of the source signal lines SL1 to SLm is connected to the source electrode. When charge is supplied to the gate electrode via the gate signal lines GL1 to GLn connected to the gate electrode, the image element 121 displays a corresponding image with a brightness according to the potential of the source signal lines SL1 to SLm connected to the source electrode.

[0041] The control circuit 110 is a circuit for controlling the self-emitting display 12. The control circuit 110 generates the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC according to the image signal input via the image terminal IMG, or extracts the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC included in the image signal from the image signal. The control circuit 110 outputs the horizontal synchronization signal HSYNC from the terminal H to the sensor control unit 13 and outputs the vertical synchronization signal VSYNC from the terminal V to the sensor control unit 13.

[0042] Also, the control circuit 110 controls the gate driver circuit 111 to drive the gate signal lines GL1 to GLn in order at the timing according to the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. Further, the control circuit 110 controls the source driver circuit 112 so that each pixel element 121 displays an image corresponding to the image data included in the image signal.

[0043] FIG. 3 is a diagram showing an example of the pixel element 121 according to the first embodiment. As shown in FIG. 3, the pixel element 121 includes, for example, a light-emitting element DI, thin film transistors TFT1 and TFT2, and a capacitive element C.

[0044] The thin film transistor TFT1 functions as a switching element in the pixel element 121. The thin film transistor TFT1 is of P type in this example. When charge is supplied to the gate electrode, the state between the source electrode and the drain electrode is made non-conductive. Also, when charge is withdrawn from the gate electrode of the thin film transistor TFT1, the state between the source electrode and the drain electrode is made conductive. Further, when there is no change in the potential applied to the gate electrode of the thin film transistor TFT1, the state between the source electrode and the drain electrode is maintained. The gate electrode of the thin film transistor TFT1 is connected to the gate signal line GL, the source electrode is connected to the source signal line SL, and the drain electrode is connected to one end of both ends of the capacitive element C and the gate electrode of the thin film transistor TFT2.

[0045] The thin-film transistor TFT2 functions as an output control element in the image element 121, controlling the potential and current supplied to the light-emitting element DI. The thin-film transistor TFT2 controls the value of the current flowing from the source electrode to the drain electrode according to the potential applied to the gate electrode. The gate electrode of the thin-film transistor TFT2 is connected to the drain electrode of the thin-film transistor TFT1 and one of the ends of the capacitive element C, the source electrode is connected to the power line W_VDD, and the drain electrode is connected to the anode terminal of the light-emitting element DI. The power line W_VDD is the wiring to which the power supply potential VDD is supplied. In this example, the thin-film transistor TFT2 is a P-type, and when the potential applied to the gate electrode is approximately the same as the power supply potential VDD, the state between the source electrode and the drain electrode is made non-conductive, stopping the supply of current to the light-emitting element DI.

[0046] Capacitive element C is, for example, a capacitor, and holds a potential to supply to the gate electrode of thin-film transistor TFT2. One end of capacitive element C is connected to the drain electrode of thin-film transistor TFT1 and the gate electrode of thin-film transistor TFT2, and the other end is connected to the power line W_VDD. When thin-film transistor TFT1 is in a conducting state, capacitive element C shifts or maintains the potential of one end so that it is the same potential as the source signal line SL. When thin-film transistor TFT1 is in a non-conducting state, capacitive element C supplies the held potential to the gate electrode of thin-film transistor TFT2.

[0047] The light-emitting element DI is a light-emitting element used in organic EL displays such as OLEDs (Organic Light Emitting Diodes). The light-emitting element DI emits light with a brightness corresponding to the current when current flows from the anode terminal to the cathode terminal. The anode terminal of the light-emitting element DI is connected to the drain terminal of a thin-film transistor TFT2, and the cathode terminal is connected to the reference line W_GND. The reference line W_GND is a wire having a potential of reference potential GND. The reference potential GND is, for example, the ground potential.

[0048] When charges are drawn from the gate electrode of the thin film transistor TFT1 through the gate signal line GL, the pixel element 121 configured as described above sets the state of the thin film transistor TFT1 to the conductive state. Subsequently, the pixel element 121 supplies the potential of the source signal line SL (pixel potential VS) to the capacitor element C, and the capacitor element C holds the supplied potential. Further, when charges are supplied to the gate electrode of the thin film transistor TFT1 through the gate signal line GL, the pixel element 121 sets the state of the thin film transistor TFT1 to the non-conductive state. That is, the pixel potential VS supplied to the pixel element 121 held by the capacitor element C is determined at the timing when the state of the thin film transistor TFT1 is set to the non-conductive state. Subsequently, the pixel element 121 supplies the potential (pixel potential VS) held by the capacitor element C to the gate electrode of the thin film transistor TFT2. The pixel element 121 controls the value of the current supplied from the thin film transistor TFT2 to the light emitting element DI according to the potential held by the capacitor element C. The pixel element 121 causes the light emitting element DI to emit light with a luminance according to the value of the current supplied thereto or stops the emission.

[0049] As described above, the self-emitting display 12 has been explained. Subsequently, the sensor control unit 13 and the position detector 14 will be described. FIG. 4 is a diagram showing an example of the circuit configuration of the sensor control unit 13 and the position detector 14 according to the first embodiment. As shown in FIG. 4, the sensor control unit 13 includes a control circuit 130, a sensor control board 131, a switching circuit 132, an amplifier circuit 133, and a receiving circuit 134.

[0050] The control circuit 130 controls the sensor control board 131 and the switching circuit 132 according to the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC output from the display controller 11. Further, the control circuit 130 outputs a signal indicating the指示 position on the self-emitting display 12 of the position indicator 2 output from the receiving circuit 134 to an external processing device or an internal processing unit (not shown) according to the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC.

[0051] Specifically, the control circuit 130 controls the sensor control board 131 and the switching circuit 132 during the period between alternations of the vertical synchronization signal VSYNC, causing the position detector 14 to perform position detection (scanning) of the position indicator 2 multiple times. The control circuit 130 also controls the switching operation of the switching circuit 132 by outputting a selection signal SEL to the switching circuit 132. Here, during the scan period in which the scan process is performed once, the control circuit 130 sequentially executes burst processing, data transmission / reception processing, and coordinate processing.

[0052] The control circuit 130 performs burst processing during the burst period, which is the first period in the scan period. Here, burst processing is performed to allow energy to be stored in the resonant circuit 20 provided in the position indicator 2 by continuously transmitting a transmission signal TX from the position detector 14 to the position indicator 2. During burst processing, the control circuit 130 controls the sensor control board 131 and the switching circuit 132 to continue transmitting the transmission signal TX to the position detector 14. The burst period is longer than the data period, in which data transmission and reception processing takes place, and the coordinate period, in which coordinate processing takes place, which follow the burst period.

[0053] The control circuit 130 performs data transmission and reception processing during the data period, which is the period following the burst period in the scan period. Here, the data transmission and reception processing is the process of transmitting and receiving information between the position detector 14 and the position indicator 2, for example, the unique ID of the position indicator 2. The control circuit 130 alternately transmits the transmission signal TX to the position detector 14 and receives the reception signal RX from the position detector 14 by alternately switching the connection destination of the switching circuit 132 between the amplification circuit 133 and the phase adjustment circuit 1312 using the selection signal SEL.

[0054] The control circuit 130 performs coordinate processing in the coordinate period, which is the period following the data period in the scan period. Here, coordinate processing is a process to detect the position (coordinates) of the position indicator 2 on the self-illuminating display 12. The control circuit 130 alternately switches the connection destination of the switching circuit 132 to either the amplification circuit 133 or the phase adjustment circuit 1312 using the selection signal SEL, and alternately transmits the transmission signal TX to the position detector 14 and receives the reception signal RX from the position detector 14.

[0055] Furthermore, the control circuit 130 controls the timing at which the output circuit 1311 outputs the clock. Specifically, the control circuit 130 controls the output circuit 1311 so that it stops outputting the clock while the switching circuit 132 is connected to the amplification circuit 133. Also, the control circuit 130 controls the output circuit 1311 so that it outputs the clock while the switching circuit 132 is connected to the phase adjustment circuit 1312.

[0056] Furthermore, the control circuit 130 controls the operation of the phase adjustment circuit 1312 so as to adjust the phase of the clock output from the output circuit 1311 based on the timing at which the pixel potential VS supplied to the image element 121 is determined. The control circuit 130 also stores the adjustment value for the clock phase in advance. Details of the phase adjustment will be described later, so the explanation is omitted here.

[0057] The sensor control board 131 generates a transmission signal TX to drive the position detector 14 when the position detector 14 transmits a signal to the position indicator 2, in accordance with the control of the control circuit 130, and transmits the transmission signal TX to the position detector 14 via the switching circuit 132. The sensor control board 131 is configured to include, for example, a clock generation circuit 1310, an output circuit 1311, and a phase adjustment circuit 1312.

[0058] The clock generation circuit 1310 is, for example, an oscillator, and generates a clock at a frequency that allows the resonant circuit 20 of the position indicator 2 to resonate (for example, a frequency close to or approximately equal to the resonant frequency), and outputs the generated clock to the output circuit 1311. The clock generation circuit 1310 also generates a clock such that the horizontal synchronization frequency of the self-emissive display 12 is an integer multiple of the clock frequency.

[0059] The output circuit 1311 is, for example, a current driver, and according to the control of the control circuit 130, it outputs the clock output from the clock generation circuit 1310 to the phase adjustment circuit 1312 or stops the clock output.

[0060] The phase adjustment circuit 1312 adjusts the phase of the clock output from the output circuit 1311 based on the timing at which the pixel potential VS supplied to the image element 121 is determined, according to the control of the control circuit 130. Specifically, the phase adjustment circuit 1312 adjusts the phase of the clock so that the pixel potential VS is at the same potential as the DC component VC of the pixel potential VS at the timing at which the pixel potential VS is determined. Furthermore, the timing at which the pixel potential VS is determined is synchronized with the horizontal synchronization period of the self-emissive display 12. Specifically, the timing at which the pixel potential VS is determined is the timing at which the signal potential of the gate signal line GL that selects the image element 121 transitions so as to cut off the supply of the pixel potential VS from the source signal line SL to the image element 121. In other words, the timing at which the pixel potential VS is determined is the timing at which the state of the thin-film transistor TFT1 in the image element 121 transitions from a conductive state to a non-conductive state. The phase adjustment circuit 1312 uses the adjusted clock as the transmission signal TX and outputs the transmission signal TX to the position detector 14 via the switching circuit 132.

[0061] Here, with reference to Figure 5, the relationship between the phase of the transmitted signal TX and the noise contained in the image displayed by the self-emissive display 12 will be explained. Figure 5 is a graph showing the relationship between the phase of the transmitted signal TX and the degree of flicker in the self-emissive display 12 according to the first embodiment. In Figure 5, the horizontal axis represents the phase [°] ([degree]) of the transmitted signal TX. Also, in Figure 5, the vertical axis represents the degree of flicker in the self-emissive display 12 [dB]. As shown in Figure 5, the degree of flicker of the self-emissive display 12 changes according to the phase of the transmitted signal TX, and in this example, the lowest value of approximately -70 [dB] is obtained when the phase of the transmitted signal TX is approximately 100 [°] to 115 [°]. In this example, the control circuit 130 of the sensor control unit 13 controls the operation of the phase adjustment circuit 1312 so as to delay the phase of the transmitted signal TX by 110 [°].

[0062] Returning to Figure 4, the switching circuit 132 is connected to the control circuit 130, the amplification circuit 133, the phase adjustment circuit 1312, and the position detector 14. According to the control of the control circuit 130, the switching circuit 132 switches the connection destination of the position detector 14 to either the amplification circuit 133 or the phase adjustment circuit 1312. Specifically, the switching circuit 132 switches the connection destination of the position detector 14 to either the amplification circuit 133 or the phase adjustment circuit 1312 according to the selection signal SEL output from the control circuit 130.

[0063] The amplification circuit 133 is, for example, an operational amplifier, and performs signal amplification on the signal indicating the position of the position indicator 2 supplied from the position detector 14 via the switching circuit 132, and outputs the amplified signal to the receiving circuit 134.

[0064] The receiving circuit 134 performs predetermined processing on the position indication signal from the position detector 14 supplied via the switching circuit 132 and the amplification circuit 133, and outputs the processed signal to the control circuit 130. Specifically, the receiving circuit 134 reduces high-frequency components in the position indication signal from the position detector 14 supplied via the amplification circuit 133 using a low-pass filter or the like. Subsequently, the receiving circuit 134 converts the signal with reduced high-frequency components into a digital signal using an analog-to-digital conversion circuit or the like, and outputs the converted digital signal to the control circuit 130.

[0065] The position detector 14 drives the loop coils 1411 and 1412 according to the transmission signal TX output from the sensor control board 131 via the switching circuit 132, and transmits the transmission signal TX to the position indicator 2. The position detector 14 also receives the received signal RX transmitted from the position indicator 2 using the loop coils 1411 and 1412, and transmits the received signal RX to the amplification circuit 133 via the switching circuit 132. The position detector 14 is composed of a sensor unit 141 and a selection circuit 142.

[0066] The sensor unit 141 is composed of a plurality of loop coils 1411 and 1412. The plurality of loop coils 1411 and 1412 are arranged to intersect each other and form a two-dimensional grid. One end of each loop coil 1411 and 1412 is connected to the selection circuit 142, and a reference potential GND is supplied to the other end.

[0067] Multiple loop coils 1411 are wired to the sensor unit 141 so as to be arranged in a line along the X-axis direction and extending in the Y-axis direction. Each loop coil 1411 has a long rectangular shape with a substantially constant width regardless of its position in the X-axis direction. Multiple loop coils 1412 are wired to the sensor unit 141 so as to be arranged in a line along the Y-axis direction and extending in the X-axis direction. Each loop coil 1412 has a long rectangular shape with a substantially constant width regardless of its position in the Y-axis direction. Note that the portion of each loop coil 1411 extending in the Y-axis direction is arranged to be parallel to the source signal line SL.

[0068] The selection circuit 142 switches the connection destination between itself and the sensor unit 141 in response to a control signal from the sensor control unit 13. As a result, one of the multiple loop coils 1411 and 1412 is selectively connected to the sensor control unit 13.

[0069] The configuration of the display device 1 has been described above. Next, the potential transitions of various signals in the display device 1 will be explained in detail. Figure 6A is an example of a timing chart showing the state transitions of each signal in the display device 1 when the phase of the transmission signal TX according to the first embodiment is not adjusted. In Figures 6A, 6B and 8 to 12, potential "H" represents a potential where the logic is "1", such as the power supply potential VDD. Also, in Figures 6A, 6B and 8 to 10, potential "L" represents a potential where the logic is "0", such as the reference potential GND.

[0070] Before time t1, the sensor control unit 13 continuously transmits a transmission signal TX, which is a clock having a predetermined frequency, to the position detector 14. Before time t1, the position detector 14 supplies the transmission signal TX to the loop coil 1411, and the loop coil 1411 transmits a magnetic signal to the position indicator 2. Also before time t1, the display controller 11 supplies a source signal VS having a potential VC as a DC component to the source signal line SL of the self-emissive display 12. Also before time t1, the source signal line SL is subjected to a back electromotive force according to electromagnetic induction by the magnetic field generated in accordance with the current of the transmission signal TX flowing through the loop coil 1411. As a result, before time t1, the source signal VS propagating to the source signal line SL alternates according to the frequency of the transmission signal TX, with the DC component VC as the bias potential and having an amplitude of potential α. In other words, prior to time t1, the source signal VS alternates between potential VC - potential α and potential VC + potential α according to the frequency of the transmitted signal TX.

[0071] At time t1, the display controller 11 transitions the potential of the gate signal VG from "H" to "L". At time t1, the thin-film transistor TFT1 of the image element 121, which is connected to the gate signal line GL to which the gate signal VG is supplied, changes from a non-conductive state to a conductive state. Also at time t1, the image element 121 begins to receive the potential of the source signal VS from the source signal line SL. At time t1, the transmission signal TX and the source signal VS continue to alternate. Also at time t1, the potential of the horizontal synchronization signal HSYNC remains "H".

[0072] At time t2, the display controller 11 transitions the potential of the gate signal VG from "L" to "H". At time t2, the state of the thin-film transistor TFT1 of the image element 121 connected to the gate signal line GL to which the gate signal VG is supplied changes from a conductive state to a non-conductive state. Also at time t2, the supply of the potential of the source signal VS from the source signal line SL to the image element 121 stops. As a result, at time t2, the pixel potential VS supplied to the image element 121 is determined to be the potential of the source signal VS at time t2. In Figure 6A, at time t2, the pixel potential VS is determined to be potential VC-α.

[0073] At time t3, the display controller 11 transitions the potential of the horizontal synchronization signal HSYNC from "H" to "L". As a result, the display device 1 switches the selection of the gate signal line GL and starts display processing for the image element 121 connected to the switched gate signal line GL. At times t4 to t6, the display device 1 performs the same processing as at times t1 to t3.

[0074] As shown in Figure 6A, if the phase of the transmitted signal TX is not adjusted, the potential of the pixel potential VS will increase or decrease within an amplitude of ±α at the timing when the pixel potential VS of the image element 121 is determined. This is because the magnetic field generated by the current of the transmitted signal TX flowing through the loop coil 1411 generates a back electromotive force relative to the source signal line SL. The back electromotive force is in opposite phase to the potential of the source signal line SL on the opposite side of the loop coil 1411 in the X-axis direction and to the potential of the source signal line SL on the X-axis side of the loop coil 1411. As a result, if the clock phase is not adjusted, the image on the self-emissive display 12 will have a difference in brightness between the X-axis side and the opposite side of the loop coil 1411, causing flickering.

[0075] Next, we will explain the case where the phase of the transmitted signal TX is adjusted. Figure 6B is an example of a timing chart showing the state transitions of each signal in the display device 1 when the phase of the transmitted signal TX is adjusted according to the first embodiment.

[0076] Before time t10, the control circuit 130 of the sensor control unit 13 performs phase adjustment on the clock transmitted from the output circuit 1311. Specifically, at the timing when the pixel potential VS supplied to the image element 121 is determined, the control circuit 130 adjusts the phase of the clock output from the output circuit 1311 so that the potential of the pixel potential VS becomes approximately equal to the potential of the DC component VC of the pixel potential VS. Before time t10, the control circuit 130 continues to transmit the adjusted clock as a transmission signal TX to the position detector 14. Before time t10, the source signal VS alternates between potential VC - potential α and potential VC + potential α according to the frequency of the transmission signal TX, as explained with reference to Figure 6A.

[0077] At time t10, the display controller 11 transitions the potential of the gate signal VG from "H" to "L". As a result, at time t10, the image element 121 begins to receive the potential of the source signal VS from the source signal line SL. At time t10, the transmission signal TX and the source signal VS continue to alternate. Also at time t10, the potential of the horizontal synchronization signal HSYNC remains "H".

[0078] At time t11, the display controller 11 transitions the potential of the gate signal VG from "L" to "H". As a result, at time t11, the pixel potential VS supplied to the image element 121 is determined to be the potential of the source signal VS at time t11. At time t11, the potential of the continuously alternating source signal VS is approximately the potential of the DC component VC of the source signal due to the phase adjustment of the transmission signal TX. That is, in Figure 6B, at time t11, the pixel potential VS is determined to be the potential VC.

[0079] At time t12, the display controller 11 transitions the potential of the horizontal synchronization signal HSYNC from "H" to "L", and then transitions it back from "L" to "H". As a result, the display device 1 switches the selection of the gate signal line GL and starts display processing for the image element 121 connected to the switched gate signal line GL. At times t13 to t15, the display device 1 performs the same processing as at times t10 to t12.

[0080] As shown in Figure 6B, when the phase of the transmitted signal TX is adjusted, the potential of the pixel potential VS is determined to the value of potential VC at the timing when the pixel potential VS of the image element 121 is determined. Therefore, when the phase of the transmitted signal TX is adjusted, noise such as flickering that appears in the image of the self-emissive display 12 when the phase of the transmitted signal TX is not adjusted is suppressed.

[0081] The potential transitions of various signals in the display device 1 have been described above. Next, the sequence of processing steps of the display device 1 will be described in detail. Figure 7 is a flowchart showing an example of the sequence of processing steps of the display device 1 according to the first embodiment.

[0082] (Step SP10) The display device 1 generates a clock using the clock generation circuit 1310. The display device 1 outputs the clock generated by the clock generation circuit 1310 to the output circuit 1311. Then, the process proceeds to the process of step SP12.

[0083] (Step SP12) The display device 1 controls the clock output by the output circuit 1311 using the control circuit 130 of the sensor control unit 13. The display device 1 causes the output circuit 1311 to output a clock during the burst period. The display device 1 also controls the output circuit 1311 to alternately output and stop the clock during the data period and the coordinate period. As a result, the display device 1 alternately transmits a transmission signal TX to the position detector 14 and receives a reception signal RX from the position detector 14. Then, the process moves on to the process of step SP14.

[0084] (Step SP14) The display device 1 controls the operation of the phase adjustment circuit 1312, which adjusts the phase of the clock output from the output circuit 1311 based on the timing at which the pixel potential VS supplied to the image element 121 is determined by the control circuit 130 of the sensor control unit 13. The phase adjustment circuit 1312 is controlled to invert the phase of the clock at predetermined timing intervals. Then, the process moves on to the process of step SP16.

[0085] (Step SP16) The display device 1 uses the phase-adjusted clock of the phase adjustment circuit 1312 as the transmission signal TX and outputs the transmission signal TX from the position detector 14 to the position indicator 2. Then, the series of processes shown in Figure 7 is completed.

[0086] <Effects> In the first embodiment described above, the sensor control board 131 includes a clock generation circuit 1310 that generates a clock and a phase adjustment circuit 1312. The phase adjustment circuit 1312 adjusts the phase difference between the timing at which the pixel potential VS supplied to a plurality of image elements 121 arranged in a grid on the self-emissive display 12 is determined and the clock. The phase adjustment circuit 1312 also outputs the transmission signal TX of the adjusted-phase-difference clock to a position detector 14 which is arranged on the upper or lower layer of the self-emissive display 12 and detects the position indicated on the self-emissive display 12.

[0087] In the first embodiment, the sensor control board 131 includes a clock generation circuit 1310 that generates a clock and a phase adjustment circuit 1312. The phase adjustment circuit 1312 adjusts the phase of the clock with reference to the timing at which the pixel potential VS supplied to a plurality of image elements 121 arranged in a grid pattern on the self-emissive display 12 is determined. The phase adjustment circuit 1312 also outputs the transmission signal TX of the clock with the adjusted phase difference to a position detector 14 which is located on the upper or lower layer of the self-emissive display 12 and detects the position indicated on the self-emissive display 12.

[0088] As a result, the sensor control board 131 phase-adjusts the clock to produce the transmission signal TX, thereby reducing the influence of electromagnetic noise in the transmission signal TX on the pixel potential VS. Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12.

[0089] Furthermore, in the first embodiment, the phase adjustment circuit 1312 adjusts the phase of the clock so that the pixel potential VS is at the same potential as the DC component VC of the pixel potential VS at the timing when the pixel potential VS is determined.

[0090] As a result, even if the pixel potential VS changes due to electromagnetic noise in the transmitted signal TX, at the timing when the pixel potential VS is determined, the potential of the pixel potential VS will be the same as the DC component VC of the pixel potential VS. Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12.

[0091] In the first embodiment, the clock generation circuit 1310 generates a clock such that the horizontal synchronization frequency of the self-emissive display 12 is an integer multiple of the clock frequency.

[0092] As a result, the sensor control board 131 does not need to adjust the phase of the clock that is the source of the transmitted signal TX for each horizontal synchronization, because the horizontal synchronization frequency is an integer multiple of the clock frequency. Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12 in a simpler way.

[0093] Furthermore, in the first embodiment, the timing at which the pixel potential VS is determined is synchronized with the horizontal synchronization period of the self-emissive display 12.

[0094] Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12 with each horizontal synchronization.

[0095] Furthermore, in the first embodiment, the timing at which the pixel potential VS is determined is the timing at which the signal potential of the gate signal line GL transitions so as to interrupt the supply of the pixel potential VS to the image element 121 by the source signal line SL provided in the self-emissive display 12.

[0096] As a result, the sensor control board 131 adjusts the phase of the clock in accordance with the timing of the transition of the potential VG of the gate signal line GL to produce the transmission signal TX. Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1, which has a self-emissive display 12, with higher precision.

[0097] Furthermore, in the first embodiment, the self-emissive display 12 is an organic EL display.

[0098] Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having an organic EL display.

[0099] ---Second Embodiment--- Next, the second embodiment will be described.

[0100] <Configuration> The configuration of the display device 1 according to the second embodiment will be described with reference to Figure 4. The display device 1 according to the second embodiment is configured in which the phase adjustment circuit 1312 in the sensor control board 131 is omitted compared to the display device 1 according to the first embodiment. However, the display device 1 according to the second embodiment may have the phase adjustment circuit 1312 provided in the sensor control board 131. In that case, the phase adjustment circuit 1312 outputs the clock output from the output circuit 1311 as a transmission signal TX without performing phase adjustment, except when phase adjustment is required due to other factors.

[0101] In addition to controlling the output circuit 1311 as described in the first embodiment, the control circuit 130 further controls the operation of the output circuit 1311 so as to stop the clock output for a certain period of time, including the timing at which the pixel potential VS supplied to the image element 121 is determined.

[0102] <Flow of Operations> The operation of the display device 1 according to the second embodiment will be explained with reference to Figure 8. Figure 8 is an example of a timing chart showing the state transitions of each signal in the display device 1 according to the second embodiment.

[0103] Before time t20, the control circuit 130 of the sensor control unit 13 controls the output circuit 1311 to continue outputting the transmission signal TX to the position detector 14. Before time t20, the source signal VS alternates between potential VC - potential α and potential VC + potential α according to the frequency of the transmission signal TX. Also, before time t20, the potential of the horizontal synchronization signal HSYNC remains "H".

[0104] At time t20, the display controller 11 transitions the potential of the gate signal VG from "H" to "L". As a result, at time t20, the image element 121 begins to receive the potential of the source signal VS from the source signal line SL. Also at time t20, the control circuit 130 controls the operation of the output circuit 1311 to stop the output of the transmit signal TX. At time t20, the source signal VS stops alternating in conjunction with the cessation of the output of the transmit signal TX. Also at time t20, the potential of the horizontal synchronization signal HSYNC remains "H".

[0105] At time t21, the display controller 11 transitions the potential of the gate signal VG from "L" to "H". As a result, at time t21, the pixel potential VS supplied to the image element 121 is determined to be the potential of the source signal VS at time t21. At time t21, the potential of the continuously alternating source signal VS is exactly the potential of the DC component VC of the source signal because the output of the transmission signal TX has stopped. That is, in Figure 8, at time t21, the pixel potential VS is determined to be the potential VC.

[0106] At time t22, the display controller 11 transitions the potential of the horizontal synchronization signal HSYNC from "H" to "L," and then transitions it back from "L" to "H." As a result, the display device 1 switches the selection of the gate signal line GL and starts display processing for the image element 121 connected to the switched gate signal line GL. The control circuit 130 also controls the operation of the output circuit 1311 to resume outputting the transmission signal TX. At time t22, the source signal VS resumes alternation in conjunction with the resumption of outputting the transmission signal TX. At times t23 to t25, the display device 1 performs the same processing as at times t20 to t22.

[0107] In this example, the control circuit 130 controls the operation of the output circuit 1311 to stop the output of the transmission signal TX at time t20, but this is merely an example and is not limited to this. The control circuit 130 may control the operation of the output circuit 1311 to stop the output of the transmission signal TX at any time, as long as the output of the transmission signal TX has stopped during the period including time t21 (in this example, from time t20 to t22). For example, the control circuit 130 may stop the output of the transmission signal TX at a timing earlier than time t20, or it may stop the output of the transmission signal TX at a timing immediately before time t21.

[0108] <Effects> In the second embodiment described above, the sensor control board 131 comprises a clock generation circuit 1310 that generates a clock and an output circuit 1311. The output circuit 1311 outputs a clock to the position detector 14 and stops outputting the clock for a certain period of time, including the timing at which the pixel potential VS supplied to the image element 121 is determined.

[0109] With this configuration, the sensor control board 131 stops the clock output at the timing when the pixel potential VS supplied to the image element 121 is determined, thereby reducing the influence of electromagnetic noise from the clock (i.e., the transmitted signal TX) on the pixel potential VS. Therefore, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12.

[0110] ---Third Embodiment--- Next, the third embodiment will be described.

[0111] <Flow of Operations> In the third embodiment, the control method of the display controller 11 and the sensor control unit 13 differs from that of the second embodiment. The configuration of the display device 1 is the same as that of the display device 1 in the second embodiment, so the explanation of the similar parts will be omitted. Figure 9 is an example of a timing chart showing the state transitions of each signal in the display device 1 according to the third embodiment. In Figures 9 and 12, the state "DISPLAY" indicates the driving state of the gate driver circuit 111 and the source driver circuit 112 that perform the display operation of the self-emissive display 12. Also, in Figures 9 and 12, the state "EMR" indicates the operating state of the position detector 14.

[0112] At time t30, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." Also at time t30, the display controller 11 drives the gate driver circuit 111 and the source driver circuit 112 to start the display operation of the self-emissive display 12. Also at time t30, the sensor control unit 13 stops the operation control of the position detector 14. Specifically, at time t30, the sensor control unit 13 stops the output of the transmission signal TX and also stops the reception operation of the reception signal RX from the position detector 14.

[0113] At time t31, the display controller 11 stops driving the gate driver circuit 111 and the source driver circuit 112, thereby stopping the display operation of the self-emissive display 12. Also at time t31, the sensor control unit 13 starts operation control for the position detector 14. Specifically, at time t31, the sensor control unit 13 starts operation control for the position detector 14 so that it performs transmission and reception operations with the position detector 14 in the order of burst period, data period, and coordinate period as described in the first embodiment.

[0114] At time t32, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." Thereafter, the display device 1 repeats the same operation as at times t30 to t31.

[0115] <Effects> In the third embodiment described above, the display device 1 comprises a self-emissive display 12, a position detector 14, and a sensor control board 131. The position detector 14 is positioned above or below the self-emissive display 12 and detects the position indicated on the self-emissive display 12. The display controller 11 controls the display operation of the self-emissive display 12. The sensor control board 131 controls the transmission and reception operation of the position detector 14 while the display controller 11 has stopped the display operation of the self-emissive display 12.

[0116] With this configuration, the display device 1 reduces the influence of electromagnetic noise associated with the transmission and reception operations of the position detector 14 on the display operation of the self-emissive display 12. Therefore, the display device 1 can reduce the noise contained in the image displayed by the self-emissive display 12.

[0117] Furthermore, the display controller 11 controls the operation of the self-emissive display 12 so that it displays during the first period (time t30 to t31) and stops displaying during the second period (time t31 to t32) following the first period, within one cycle of vertical synchronization of the self-emissive display 12. In addition, the sensor control board 131 controls the transmission and reception operation of the position detector 14 during the second period.

[0118] In this configuration, the display device 1 separates the transmission and reception operation period of the position detector 14 from the display operation period of the self-emissive display 12 using a time-division multiplexing mechanism. Therefore, the display device 1 can reduce noise contained in the image displayed by the self-emissive display 12.

[0119] Furthermore, the self-emissive display 12 includes a plurality of image elements 121 arranged in a grid pattern, and a plurality of source signal lines SL provided parallel to the display surface and parallel to each other, which also supply pixel potentials VS to the image elements 121. The position detector 14 also has a loop coil 1411 that transmits and receives magnetic signals with a position indicator 2 that provides position indications to the position detector 14, and a portion of the loop coil is parallel to the source signal lines SL.

[0120] With this configuration, the display device 1 is able to reduce the electrical influence that the magnetic field generated from the loop coil 1411 has on the source signal line SL. Therefore, the display device 1 can reduce the noise generated in the image displayed by the self-emissive display 12 due to the transmission and reception operation of the position detector 14.

[0121] ---Fourth Embodiment--- Next, the fourth embodiment will be described.

[0122] <Flow of Operations> In the fourth embodiment, the control method of the display controller 11 and the sensor control unit 13 differs from that of the second and third embodiments. The configuration of the display device 1 is the same as that of the display device 1 in the second embodiment, so the explanation of the similar parts will be omitted. Figure 10 is an example of a timing chart showing the state transitions of each signal in the display device 1 according to the fourth embodiment. In Figure 10, the state "DISPLAY" indicates the driving state of the gate driver circuit 111 and source driver circuit 112 that perform the display operation of the self-emissive display 12. Also in Figure 10, the state "EMR" indicates the operating state of the position detector 14.

[0123] At time t41, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." Also at time t41, the display controller 11 stops driving the gate driver circuit 111 and the source driver circuit 112, stopping the display operation of the self-emissive display 12. Also at time t41, the sensor control unit 13 starts the burst period operation for the position detector 14.

[0124] At time t42, the display controller 11 maintains the display operation of the self-emissive display 12 in a stopped state. Also at time t42, the sensor control unit 13 stops the operation of the position detector 14 during the burst period and starts the operation of the data period and coordinate period. Specifically, at time t42, the sensor control unit 13 transmits the transmission signal TX to the position detector 14.

[0125] At time t43, the sensor control unit 13 stops transmitting the transmission signal TX to the position detector 14 and starts receiving the reception signal RX. Also at time t43, the display controller 11 resumes the display operation of the self-emissive display 12.

[0126] At time t44, the sensor control unit 13 stops receiving the received signal RX from the position detector 14 and starts transmitting the transmission signal TX to the position detector 14. Also at time t44, the display controller 11 stops the display operation of the self-emissive display 12.

[0127] <Effects> In the fourth embodiment described above, the display device 1 comprises a self-emissive display 12, a position detector 14, and a sensor control board 131. The position detector 14 is positioned above or below the self-emissive display 12 and detects the position indicated on the self-emissive display 12. The sensor control board 131 controls the transmission and reception operations of the position detector 14. The display controller 11 controls the display operation of the self-emissive display 12 while the sensor control board 131 is controlling the reception operation of the position detector 14.

[0128] With this configuration, the display device 1 performs the display operation of the self-emissive display 12 while the position detector 14 controls the receiving operation, thereby reducing noise contained in the image displayed by the self-emissive display 12.

[0129] Furthermore, the display controller 11 stops controlling the display operation of the self-emissive display 12 while the sensor control board 131 is controlling the transmission operation to the position detector 14.

[0130] With this configuration, the display device 1 reduces the influence of electromagnetic noise associated with the transmission operation of the position detector 14 on the display operation of the self-emissive display 12. Therefore, the display device 1 can reduce the noise contained in the image displayed by the self-emissive display 12.

[0131] ---Fifth Embodiment--- Next, the fifth embodiment will be described.

[0132] <Flow of Operations> In the fifth embodiment, the method of adjusting the phase difference between the output clock generated by the clock generation circuit 1310 and the pixel potential VS differs from that of the first embodiment. Specifically, in the fifth embodiment, the phase adjustment circuit 1312 adjusts the phase difference so that the phase difference between the timing and the clock changes by a reference value for each timing of the determination of the pixel potential VS. The reference value is, for example, a value such as 45°, 90°, or 180°, and is preferably 180°. The configuration of the display device 1 is the same as that of the display device 1 in the first embodiment, so the explanation of the similar parts will be omitted.

[0133] Figure 11A is an example of a timing chart showing the state transitions of each signal in the display device 1 according to the fifth embodiment. In the example shown in Figure 11A, the reference value is 180°.

[0134] At time t50, the display controller 11 transitions the potential of the gate signal VG from "H" to "L". As a result, at time t50, the image element 121 begins to receive the potential of the source signal VS from the source signal line SL. At time t50, the transmit signal TX and the source signal VS continue to alternate. Also, at time t50, the potential of the horizontal synchronization signal HSYNC remains "H".

[0135] At time t51, the display controller 11 transitions the potential of the gate signal VG from "L" to "H". As a result, at time t51, the pixel potential VS supplied to the image element 121 is determined to be the potential of the source signal VS at time t51. At time t51, the potential of the source signal VS is the lowest potential during the alternation, which is potential VC-α. That is, at time t51, the pixel potential VS is determined to be potential VC-α.

[0136] At time t52, the display controller 11 transitions the potential of the horizontal synchronization signal HSYNC from "H" to "L," and then transitions it back from "L" to "H." As a result, the display device 1 switches the selection of the gate signal line GL and starts display processing for the image element 121 connected to the switched gate signal line GL.

[0137] From time t53 to t64, the display device 1 performs the same processing as from t50 to t52. At time t54, the potential of the source signal VS becomes the highest potential during the alternation, which is potential VC + α. At time t57, the potential of the source signal VS becomes VC - α again. At time t60, the potential of the source signal VS becomes VC + α again. At time t63, the potential of the source signal VS becomes VC - α again.

[0138] Figure 11B is another example of a timing chart showing the state transitions of each signal in the display device 1 according to the fifth embodiment. In the example shown in Figure 11B, the reference value is 90°. The timing chart shown in Figure 11B is the same as in Figure 11A, except that the reference value is 90° instead of 180°. Therefore, a detailed explanation of the state transitions of each signal from time t70 to t83 is omitted.

[0139] The times t71, t74, t77, t80, and t83 in which the pixel potential VS supplied to the image element 121 is determined will be described below. At time t71, the potential of the source signal VS becomes the potential VC + α, which is the highest potential in the alternation. Subsequently, at time t74, the potential of the source signal VS becomes approximately the potential of the DC component VC of the source signal. Subsequently, at time t77, it becomes the potential VC - α. Subsequently, at time t80, the potential of the source signal VS becomes approximately the potential of the DC component VC of the source signal again. Subsequently, at time t83, the potential of the source signal VS becomes once again the potential VC + α.

[0140] Furthermore, in the fifth embodiment, the phase adjustment circuit 1312 changes the phase difference by a reference value at each timing when the pixel potential VS is determined, but is not limited to this. The phase adjustment circuit 1312 may change the phase difference by a random value that changes within a predetermined range with respect to the reference value at each timing when the pixel potential VS is determined.

[0141] The predetermined range is, for example, a predetermined range of phase difference, such as -10° to +10°. However, the predetermined range is not limited to the above, and may also be a percentage, such as 95%° to 105%°.

[0142] The phase adjustment circuit 1312 further includes a random number generation circuit that generates a signal containing information about the phase difference value that changes within a predetermined range. The phase adjustment circuit 1312 adds the phase difference value indicated by the signal output from the random number generation circuit to the reference value. If the predetermined range is a ratio, the phase adjustment circuit 1312 multiplies the reference value by the phase difference value indicated by the signal output from the random number generation circuit. The phase adjustment circuit 1312 then adjusts the phase difference between the clock output from the clock generation circuit and the timing at which the pixel potential VS is determined so that the phase difference after addition or multiplication becomes the result.

[0143] <Effect> In the fifth embodiment described above, the phase adjustment circuit 1312 adjusts the phase difference between the pixel potential VS and the clock so that the phase difference changes by a reference value each time the pixel potential VS is determined.

[0144] In this configuration, the phase difference between the pixel potential VS and the clock shifts sequentially by a reference value each time the pixel potential VS is determined, so the noise contained in the image displayed by the self-emissive display 12 changes periodically. Since the period of change is too short for humans to perceive, noise such as flicker contained in the image displayed by the self-emissive display 12 is suppressed, and therefore the noise contained in the image displayed by the self-emissive display 12 can be reduced.

[0145] Furthermore, the fifth embodiment is particularly effective when it is difficult to precisely maintain a constant phase difference between the clock and the pixel potential VS, such as when it is difficult to adjust the frequency of the horizontal synchronization signal HSYNC to be an integer multiple of the clock.

[0146] Furthermore, the phase adjustment circuit 1312 adjusts the phase difference so that, at each timing when the pixel potential VS is determined, the phase difference is randomly and sequentially shifted within a predetermined range with respect to a reference value.

[0147] With this configuration, the phase adjustment circuit 1312 includes a random number component in the amount of change in the phase difference, thereby further reducing noise contained in the image displayed by the self-emissive display 12.

[0148] ---Sixth Embodiment--- Next, the sixth embodiment will be described.

[0149] <Flow of Operations> In the sixth embodiment, the control method of the display controller 11 and the sensor control unit 13 differs from that of the third and fourth embodiments. Note that the configuration of the display device 1 is the same as that of the display device 1 in the second embodiment, so the explanation of the similar parts will be omitted. Figure 12 is an example of a timing chart showing the state transitions of each signal in the display device 1 according to the sixth embodiment.

[0150] At time t90, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." Also at time t90, the sensor control unit 13 starts the burst period operation for burst transmission to the position detector 14. In other words, at time t90, the frame switching due to the vertical synchronization signal VSYNC and the start of the burst period occur at approximately the same time.

[0151] At time t91, the sensor control unit 13 stops the burst period operation for the position detector 14.

[0152] At time t92, the sensor control unit 13 starts the operation of the data period and the coordinate period. Specifically, at time t92, the sensor control unit 13 starts the operation of the transmit / receive period, in which it alternately transmits the transmit signal TX and the receive signal RX to the position detector 14.

[0153] At time t93, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." In other words, at time t93, the frame switching timing due to the vertical synchronization signal VSYNC occurs during the transmission and reception period.

[0154] At time t94, the sensor control unit 13 stops the operation of the position detector 14 during the transmission and reception period.

[0155] At time t95, the sensor control unit 13 starts the burst period operation for the position detector 14.

[0156] At time t96, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L," and then transitions it back from "L" to "H." In other words, at time t96, the frame switching timing due to the vertical synchronization signal VSYNC falls within the burst period.

[0157] From time t97 to t99, the display controller 11 transitions the potential of the vertical synchronization signal VSYNC from "H" to "L" and then transitions it back from "L" to "H", similar to the transitions at time t90, t93, and t96.

[0158] <Effects> In the sixth embodiment described above, the display device 1 comprises a self-emissive display 12, a position detector 14, a display controller 11, and a sensor control board 131. The position detector 14 is arranged on the upper or lower layer of the self-emissive display 12 and detects the position indicated on the self-emissive display 12. The display controller 11 controls the display operation, including the timing of the vertical synchronization of the self-emissive display 12. The sensor control board 131 controls the transmission and reception operation of the position detector 14 such that burst periods in which burst transmissions are made to the position detector 14 at the timing of the vertical synchronization of the self-emissive display 12 and transmission / reception periods in which transmission and reception to and from the position detector 14 are repeated alternately.

[0159] In this configuration, burst periods and transmission / reception periods occur alternately with each vertical synchronization timing in the transmission / reception operation for the position detector 14. During the transmission / reception period, the alternating transmission and reception cause noise such as flickering in the image displayed by the display device 1. In contrast, during the burst period, flickering like that that occurs during the transmission / reception period is less likely to occur in the image.

[0160] In the sixth embodiment, by alternating between periods in which flickering is less likely to occur and periods in which it is more likely to occur at the frame switching timing, flicker noise introduced into the image is suppressed. Therefore, the display device 1 can further reduce the noise contained in the image displayed by the self-emissive display 12.

[0161] ---Modifications--- It should be noted that the present invention is not limited to the embodiments described above. That is, any design modifications made to the above embodiments by those skilled in the art are also included within the scope of the present invention, as long as they retain the features of the present invention. Furthermore, the elements of the above embodiments and the modifications described later can be combined to the extent that it is technically possible, and any combination thereof is also included within the scope of the present invention, as long as it retains the features of the present invention.

[0162] For example, in the first embodiment, the sensor control board 131 adjusts the phase of the clock output from the output circuit 1311 using a phase adjustment circuit 1312, but is not limited to this. The sensor control board 131 may, for example, adjust the frequency of the clock output from the output circuit 1311 using a frequency adjustment circuit instead of the phase adjustment circuit 1312. Specifically, the sensor control board 131 may adjust the frequency of the clock output from the output circuit 1311 so that the pixel potential VS is approximately equal to the DC component VC of the pixel potential VS at the timing when the pixel potential VS is determined. The degree of frequency adjustment is determined, for example, within the range in which the resonant circuit 20 of the position indicator 2 can resonate.

[0163] With this configuration, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12 by means of frequency adjustment rather than phase adjustment.

[0164] Furthermore, the sensor control board 131 may adjust the amplitude of the clock output from the output circuit 1311 by using an amplitude adjustment circuit, such as an amplification circuit, instead of the phase adjustment circuit 1312. Specifically, the sensor control board 131 may control the operation of the amplitude adjustment circuit so that the amplitude of the transmitted signal TX is reduced during the period including the timing when the pixel potential VS is determined compared to other periods. The degree of amplitude reduction is determined, for example, within a range that allows transmission and reception with the position detector 14.

[0165] With this configuration, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1 having the self-emissive display 12 by using a simple amplitude adjustment circuit such as an amplification circuit, without using a phase adjustment circuit 1312.

[0166] Furthermore, the self-emissive display 12 is an organic EL display, but is not limited to this. The self-emissive display 12 can be any display in which the self-emissive elements are arranged in a grid and the polarity of the potential applied to the image element 121 does not reverse with each frame of image display. The self-emissive display 12 may be, for example, a quantum dot display.

[0167] With this configuration, the sensor control board 131 can reduce noise contained in the image displayed by the display device 1, which has various self-emissive displays 12, not limited to organic EL displays.

[0168] 12...Self-illuminating display, 14...Position detector, 121...Image element, 131...Sensor control board, 1310...Clock generation circuit, 1312...Phase adjustment circuit

Claims

1. A sensor control board comprising: a clock generation circuit that generates a clock; and a phase adjustment circuit that adjusts the phase difference between the timing at which the pixel potential supplied to a plurality of image elements arranged in a grid on a self-emissive display is determined and the clock, and outputs the clock with the adjusted phase difference as a transmission signal to a position detector arranged in the upper or lower layer of the self-emissive display that detects a position indicated on the self-emissive display.

2. The sensor control board according to claim 1, wherein the phase adjustment circuit adjusts the phase of the clock so that the pixel potential is the same potential as the DC component of the pixel potential at the timing when the pixel potential is determined.

3. The sensor control board according to claim 1, wherein the clock generation circuit generates the clock such that the horizontal synchronization frequency of the self-emissive display is an integer multiple of the frequency of the clock.

4. The sensor control board according to claim 1, wherein the phase adjustment circuit adjusts the phase difference so that the phase difference is sequentially shifted by a reference value each time the pixel potential is determined.

5. The sensor control board according to claim 1, wherein the phase adjustment circuit adjusts the phase difference so that the phase difference is randomly and sequentially shifted within a predetermined range with respect to a reference value at each timing when the pixel potential is determined.

6. A sensor control board comprising: a clock generation circuit that generates a clock; an output circuit that outputs the clock to a position detector located on the upper or lower layer of a self-emissive display and detects a position indicated on the self-emissive display, and stops the output of the clock for a certain period of time including the timing at which the pixel potential supplied to a plurality of image elements arranged in a grid on the self-emissive display is determined.

7. The timing at which the pixel potential is determined is synchronized with the horizontal synchronization period of the self-emissive display, according to any one of claims 1 to 6, for the sensor control board.

8. The timing at which the pixel potential is determined is the timing at which the potential of the signal of a gate signal line provided in the self-emissive display for selecting the image element transitions so as to interrupt the supply of the pixel potential to the image element by a source signal line provided in the self-emissive display.

9. The sensor control board according to any one of claims 1 to 6, wherein the self-illuminating display is an organic electroluminescent display.

10. A display device comprising: a self-emissive display; a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display; a display controller for controlling the display operation of the self-emissive display; and a sensor control board for controlling the transmission and reception operation of the position detector while the display controller has stopped the display operation of the self-emissive display.

11. The display device according to claim 10, wherein the display controller controls the operation of the self-emissive display so that it displays in a first period and stops displaying in a second period following the first period during one cycle of vertical synchronization of the self-emissive display, and the sensor control board controls the transmission and reception operation of the position detector during the second period.

12. A display device comprising: a self-emissive display; a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display; a sensor control board for controlling the transmission and reception operations of the position detector; and a display controller for controlling the display operation of the self-emissive display while the sensor control board is controlling the reception operation of the position detector.

13. The display device according to claim 12, wherein the display controller stops controlling the display operation of the self-emissive display while the sensor control board is controlling the transmission operation to the position detector.

14. A display device comprising: a self-emissive display; a position detector disposed above or below the self-emissive display for detecting a position indicated on the self-emissive display; a display controller for controlling the display operation, including the timing of vertical synchronization of the self-emissive display; and a sensor control board for controlling the transmission and reception operation of the position detector such that burst periods in which burst transmission is performed to the position detector at the timing of vertical synchronization of the self-emissive display and transmission / reception periods in which transmission and reception to and from the position detector are repeated alternately.

15. The display device according to any one of claims 10 to 14, wherein the self-emissive display has a plurality of image elements arranged in a grid, and a plurality of source signal lines provided parallel to the display surface and parallel to each other and supplying pixel potential to the image elements, and the position detector has a loop coil that transmits and receives magnetic signals with a position indicator that gives position indication to the position detector and a portion of the loop coil is parallel to the source signal lines.

16. The display device according to any one of claims 10 to 14, wherein the self-emissive display is an organic electroluminescent display.

Images