Systems and methods for in-body security employing hardware-level systems in bidirectional neural interfaces

Abstract

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Claims

1. A neural interface device comprising:an electrode array implanted between a brain and a scalp that records neural signals from neural tissue of the brain adjacent to the electrode array; andan integrated circuit in electrical communication with the electrode array, the integrated circuit comprising an analog-to-digital converter (ADC) producing digitized electrical signal output, wherein the ADC comprises an encryption module, wherein the encryption module:receives the digitized electrical signal output from the ADC;encrypts the digitized electrical signal output during digitization to generate an encrypted output by applying a symmetric cryptographic algorithm; andprovides the encrypted output to a transmitter for transmission to an external device of a brain-computer interface.

2. The neural interface device of claim 1, wherein the ADC comprises a successive approximation register (SAR) architecture.

3. The neural interface device of claim 1 or claim 2, wherein the encryption module comprises a bit stream cipher, wherein the encryption module applies the bit stream cipher to the digitized electrical signal output of the ADC.

4. The neural interface device of any one of claims 1-3, wherein the encryption module comprises a block stream cipher, wherein the encryption module applies the block stream cipher to the digitized electrical signal output of the ADC.

5. The neural interface device of any one of claims 1-4, wherein a cipher of the encryption module comprises 1-, 8-, 128-, 192- or 256- bits.

6. The neural interface device of any one of claims 1-5, comprising:a wireless transmitter communicatively coupled to the integrated circuit or the encryption module and an external processor.

7. The neural interface device of any one of claims 1-6, comprising: control logic for operating the integrated circuit or electrode array; memory for storing recordings from the electrode array; and a power management unit for providing power to the integrated circuit or electrode array.

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