Flash array system and program current stablilization method

Abstract

A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current. This invention can reduce variance of programming current by the bit-line decoder diverted pull-up current, so can obtain more exact programming current to get preferable productivity, and this mechanism can be used for upgrading bit-line.

Description

technical field

[0001] The present invention relates to integrated circuit (IC) design; more particularly, to a system for suppressing programming current disturbances that may occur when programming memory devices. Background technique

[0002] In recent years, flash memory (flash memory) has become the most popular among read-only memory (ROM) due to its simple and fast permanent storage of data in computers, digital cameras and other portable devices. one of the Compared with other storage methods in use, such as hard drives (hard drives) and random-access memory (random-access memory (RAM), etc., flash memory has the advantages of both. And the flash memory is a solid (solid) device, that is, there are no moving components in it, which allows the flash memory to provide users with a faster and more reliable storage method, especially in an environment that causes mechanical errors in the movable components , this advantage is even more pronounced. Flash memory is also...

Examples

Embodiment Construction

[0060] FIG. 1 is a partial schematic diagram of a conventional flash memory array 100, in which bit lines 102 and 104 provide column addresses required for selecting a plurality of adjacent flash memory cells. Each flash memory cell includes at least one transistor. Flash memory cells 106 and 108 are coupled to bit line 102 , while flash memory cells 110 and 112 are coupled to bit line 104 . The word line 114 is coupled to the flash memory cells 106 and 110 , and the word line 116 is coupled to the flash memory cells 108 and 112 to provide row addresses for selecting the flash memory cells. A select line 118 is connected to the flash memory cells 106, 108, 110 and 112 to provide a programming voltage required for programming.

[0061] When the flash memory cell 106 is to be programmed to a predetermined state, a programming voltage is provided to the select line 118 , and voltages are provided to the bit line 102 and the word line 114 to position and select the flash memory c...

technical field

[0001] The present invention relates to integrated circuit (IC) design; more particularly, to a system for suppressing programming current disturbances that may occur when programming memory devices. Background technique

[0002] In recent years, flash memory (flash memory) has become the most popular among read-only memory (ROM) due to its simple and fast permanent storage of data in computers, digital cameras and other portable devices. one of the Compared with other storage methods in use, such as hard drives (hard drives) and random-access memory (random-access memory (RAM), etc., flash memory has the advantages of both. And the flash memory is a solid (solid) device, that is, there are no moving components in it, which allows the flash memory to provide users with a faster and more reliable storage method, especially in an environment that causes mechanical errors in the movable components , this advantage is even more pronounced. Flash memory is also...

Examples

Embodiment Construction

[0060] FIG. 1 is a partial schematic diagram of a conventional flash memory array 100, in which bit lines 102 and 104 provide column addresses required for selecting a plurality of adjacent flash memory cells. Each flash memory cell includes at least one transistor. Flash memory cells 106 and 108 are coupled to bit line 102 , while flash memory cells 110 and 112 are coupled to bit line 104 . The word line 114 is coupled to the flash memory cells 106 and 110 , and the word line 116 is coupled to the flash memory cells 108 and 112 to provide row addresses for selecting the flash memory cells. A select line 118 is connected to the flash memory cells 106, 108, 110 and 112 to provide a programming voltage required for programming.

[0061] When the flash memory cell 106 is to be programmed to a predetermined state, a programming voltage is provided to the select line 118 , and voltages are provided to the bit line 102 and the word line 114 to position and select the flash memory c...

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