Fingerprint sensor device and electronic device

Abstract

The present invention discloses a fingerprint sensor device. The fingerprint sensor device comprises: a first unit, the first unit comprises a plurality of switch tubes; a plurality of second units located on the first unit, the second units are used to provide induction signals; a plurality of third units are used to provide detection signals according to the induction signals; and a plurality of fourth units, the plurality of fourth units are respectively connected between the corresponding second units and the third units, and are used to provide a release path for electrostatic charges and a conduction path for the induction signals, wherein each fourth unit comprises at least one electrostatic protection element, and the parasitic diode of at least one of the plurality of switch tubes provides at least one of the electrostatic protection elements. The fingerprint sensor device uses the parasitic diode of the switch tube to form at least one of the electrostatic protection elements, which reduces the area occupied by the circuit, so that the plurality of fourth units can be respectively connected to the corresponding plurality of second units, thereby improving the electrostatic protection capability of the fingerprint sensor device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a fingerprint sensor device and an electronic device. Background Art

[0002] The fingerprint sensor device in the prior art has a plurality of second units. When a user places a finger on the surface of the fingerprint sensor device, the pattern of the fingerprint is determined by utilizing the change in the capacitance value of the second unit.

[0003] Figure 1 FIG. 1 shows a schematic diagram of a fingerprint sensor device according to the prior art. Figure 1 As shown, the fingerprint sensor device 100 includes a first unit 110, a second unit 120 located on the first unit 110, and a protective layer 130 covering the second unit 120. A third unit 140 connected to the second unit 120 is formed on the first unit 110, and the second unit 120 includes a plurality of second units 120 arranged in a matrix. When a finger 150 contacts or approaches the protective layer 130, the ridges and valleys of the finger 150 and each second unit 120 will form a flat capacitor Cr and Cv, so that the third unit can detect the sensing signal of each second unit 120, and judge the valley or peak of each second unit 120 corresponding to the finger according to the size of the sensing signal, so as to read the fingerprint image of the finger 150.

[0004] Figure 2 and Figure 3 The charge distribution diagrams of the fingerprint sensor device are shown respectively when the finger is positively charged and when the finger is negatively charged. Figure 2 As shown in FIG. 1 , when the finger 150 carries a positive charge Qp in an ESD event, the sensing substrate of the fingerprint sensor device 100 carries negative charges Qn1 and Qn2, and the gate of the semiconductor element 180 in the fingerprint sensor device 100 accumulates positive charges Qp1 and Qp2 respectively. Figure 3 The charge distribution of the fingerprint sensor device 100 is shown when the finger 150 carries a negative charge in an ESD event. At this time, the gate of the semiconductor element 180 gathers negative charges Qn1 and Qn2 respectively. In an ESD event, whether the finger 150 carries a positive charge or a negative charge, as the ESD energy increases, the positive charge or negative charge gathered on the gate of the semiconductor element 180 in the fingerprint sensor device 100 will increase, and the electric field strength formed between the gate of the semiconductor element 180 and the first unit will increase. The voltage difference between the two ends of the above electric field increases with the increase of ESD energy. When this voltage difference is greater than the breakdown voltage of the gate of the semiconductor element, it will cause damage or destruction of the semiconductor element, resulting in reduced performance or functional failure of the fingerprint sensor device.

[0005] Therefore, it is urgent to further improve the fingerprint sensor device in the prior art to solve the above problems. Summary of the invention

[0006] In view of the above problems, the object of the present invention is to provide a fingerprint sensor device and an electronic device, wherein at least one of the electrostatic protection elements is formed by a parasitic diode of a switching tube, thereby reducing the area occupied by the circuit, so that multiple fourth units can be respectively connected to corresponding multiple second units, thereby improving the electrostatic protection capability of the fingerprint sensor device.

[0007] According to a first aspect of the present invention, there is provided a fingerprint sensing device, comprising: a first unit, the first unit comprising a plurality of switch tubes; a plurality of second units located on the first unit, the second units being used to provide sensing signals; a plurality of third units being used to provide detection signals according to the sensing signals; and a plurality of fourth units, the plurality of fourth units being respectively connected between corresponding second units and third units, and being used to provide a release path for electrostatic charges and a conduction path for sensing signals, wherein each fourth unit comprises at least one electrostatic protection element, and a parasitic diode of at least one switch tube among the plurality of switch tubes provides at least one of the electrostatic protection elements.

[0008] Preferably, the multiple switching tubes include: a first switching tube, a first end of the first switching tube is connected to the second unit, and a second end is connected to the output end of the third unit; and a second switching tube, a first end of the second switching tube is connected to the second unit, and a second end is connected to the reference ground, wherein the second switching tube is an NMOS transistor, and the electrostatic protection element includes a parasitic diode of the second switching tube, when the second switching tube is in the on state, the parasitic diode of the second switching tube provides at least a part of the electrostatic release path between the positively charged electrostatic charge and the negatively charged electrostatic charge and the reference ground, and when the second switching tube is in the off state, the parasitic diode of the second switching tube provides at least a part of the electrostatic release path between the negatively charged electrostatic charge and the reference ground.

[0009] Preferably, the first switch tube is a PMOS transistor, the electrostatic protection element includes a parasitic diode of the first switch tube and a parasitic diode of the second switch tube, the body region of the first switch tube is connected to the reference power supply, and the parasitic diode of the first switch tube provides at least a portion of the electrostatic release path between the positively charged electrostatic charge and the reference ground.

[0010] Preferably, the plurality of switch tubes include: a first switch tube, a first end of the first switch tube is connected to the second unit, and a second end is connected to the output end of the third unit; a second switch tube, a first end of the second switch tube is connected to the second unit, and a second end is connected to the input end of the third unit; and a third switch tube, a first end of the third switch tube is connected to a reference power supply, and a second end is connected to the second unit; wherein the second switch tube is an NMOS transistor, the third switch tube is a PMOS transistor, the electrostatic protection element includes a parasitic diode of the second switch tube and a parasitic diode of the third switch tube, and when the second switch tube When the second switch tube is in the on state and / or the third switch tube is in the on state, the parasitic diode of the second switch tube and / or the parasitic diode of the third switch tube provides at least a part of the electrostatic release path between the positively charged electrostatic charge, the negatively charged electrostatic charge and the reference ground; when the second switch tube is in the off state, the parasitic diode of the second switch tube provides at least a part of the electrostatic release path between the negatively charged electrostatic charge and the reference ground; when the third switch tube is in the off state, the parasitic diode of the third switch tube provides at least a part of the electrostatic release path between the positively charged electrostatic charge and the reference ground.

[0011] Preferably, the NMOS transistor and / or the PMOS transistor includes a source region, a drain region and a gate region, and the surfaces of the source region and the drain region include metal pads, wherein the cross-sectional areas of the source region and the drain region in a direction perpendicular to the first unit are different, the distance between the metal pad on the surface of the larger one of the source region and the drain region and the gate region is greater than the distance between the metal pad on the surface of the other one of the source region and the drain region and the gate region, and the larger one of the source region and the drain region provides at least one of the parasitic diode of the first switch tube, the parasitic diode of the second switch tube and the parasitic diode of the third switch tube.

[0012] Preferably, it further comprises: a clamping transistor connected to the electrostatic protection element, and at least one of the clamping transistors is formed in the first unit.

[0013] According to a second aspect of the present invention, there is provided an electronic device comprising the fingerprint sensing device as described above.

[0014] The fingerprint sensor device and electronic device provided by the present invention have multiple fourth units, and the multiple fourth units are respectively connected to the corresponding multiple second units. The fingerprint sensor device and electronic device use the parasitic diode of the switch tube to form at least a part of the fourth unit, thereby reducing the area occupied by the circuit. The multiple fourth units can be respectively connected to the corresponding multiple second units, thereby improving the electrostatic protection capability of the fingerprint sensor device and the electronic device.

[0015] Furthermore, the fingerprint sensor device and the electronic device have a clamping transistor, which can protect the components in the fingerprint sensor device when the electrostatic voltage is too high, thereby further reducing the area requirement of the fourth unit and improving the electrostatic protection capability of the fingerprint sensor device and the electronic device.

[0016] Furthermore, the introduction of the voltage adjustment module reduces the area requirement for other components in the fourth unit, reduces parasitic capacitance, and optimizes the performance of the fingerprint sensor device and the electronic device; further, the fourth unit is located in the first unit, shortens the length of the wire, reduces parasitic resistance, further improves the electrostatic protection capability, and improves the rapid discharge effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a fingerprint sensor device according to the prior art is shown;

[0019] Figure 2 shows the charge distribution diagram of the fingerprint sensor device when the finger is positively charged;

[0020] Figure 3 shows the charge distribution diagram of the fingerprint sensor device when the finger is negatively charged;

[0021] Figure 4 shows a schematic diagram of a fourth unit according to the prior art;

[0022] Figure 5 A schematic diagram of a fingerprint sensing device according to an embodiment of the present invention is shown;

[0023] Figures 6a to 6c Schematic diagrams of a third unit and a fourth unit according to an embodiment of the present invention are respectively shown;

[0024] Figures 7a to 7c They are shown according to Figures 6a to 6c The timing diagram of the switch tube in FIG.

[0025] Figure 8a and 8b They are shown respectively Figures 6a to 6c Schematic diagram of the structure of the switching tube.

[0026] Figures 9a to 9d Schematic diagrams of the fourth unit according to an embodiment of the present invention are respectively shown;

[0027] Fig.10 A schematic diagram of an electronic device according to an embodiment of the present invention is shown.

[0028] Reference numerals list

[0029] 100, 200 Fingerprint sensor

[0030] 110, 220 Unit 1

[0031] 120 Unit 2

[0032] 130 protective layer

[0033] 140 Unit 3

[0034] 150 fingers

[0035] 160 Shielding Grid

[0036] 170, 210 Unit 4

[0037] 171 Voltage Regulator Module

[0038] 180 Semiconductor components

[0039] 221 First doping region

[0040] 222 second doping region

[0041] 223 Dielectric layer

[0042] 224 Metal Layer

[0043] 225 Metal Pad

[0044] 300 Electronic equipment DETAILED DESCRIPTION

[0045] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0046] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0047] Figure 4 FIG. 4 shows a schematic diagram of a fourth unit according to the prior art. Figure 4As shown, the fourth unit 170 of the prior art includes a first diode D1 and a second diode D2. The fourth unit 170 is used to release static electricity and provide a normal conduction path for the induction signal and the working current in the circuit. Preferably, a voltage adjustment module 171 is further included between the first diode D1 and the second diode D2, and the first end of the voltage adjustment module 171 is connected to the first end of the first diode D1 via a metal connection, and the second end of the voltage adjustment module 171 is connected to the second end of the second diode D2 via a metal connection.

[0048] In the prior art, for high-resolution sensors, for example, DPI (Dots Per Inch) is greater than 508, and the area of ​​each sensing unit is less than 50um*50um. In order to meet the ESD protection requirements, the first diode D1 and the second diode D2 need to be implemented in large sizes, and ESD protection cannot be achieved in the 50um*50um sensing unit area. The large-sized first diode D1 and the second diode D2 increase the parasitic capacitance of the sensing electrode node to the ground, which deteriorates the sensor performance. Therefore, multiple second units often share the same fourth unit, but this structure is not conducive to improving the electrostatic protection capability of the second unit.

[0049] In addition, in the prior art, the voltage adjustment module 171 is relatively large in size, and is often formed separately and then connected to the first diode and the second diode. For example, if an aluminum wire with a thickness of 1 μm and a width of 30 μm is used, the parasitic resistance value of the aluminum wire with a length of 1 mm is 1Ω. In actual situations, the circuit often has parasitic resistances Rpar1 and Rpar2 greater than 1Ω. The presence of parasitic resistances will reduce the electrostatic protection capability of the integrated circuit, and the voltage drop of the parasitic resistances affects the effect of rapid discharge.

[0050] Figure 5 A schematic diagram of a fingerprint sensing device according to an embodiment of the present invention is shown.

[0051] like Figure 5 As shown, the fingerprint sensing device 200 includes a first unit 110 , a second unit 120 , a fourth unit 210 and a third unit 140 , and the second unit 120 is covered with a protection layer 130 .

[0052] The first unit 110 is, for example, a substrate. A plurality of second units 120 are formed on the first unit 110.

[0053] The second unit 120 is, for example, a sensing electrode plate, and the plurality of second units 120 include a plurality of second units 120 arranged in a matrix to form at least a portion of the pixel units arranged in a matrix. Taking the second unit in the i-th row, j-th column and the i-th row, j+1-th column of the array as an example, when the finger 150 contacts or approaches the protective layer 130, the ridge and valley of the finger 150 respectively form a flat plate capacitor C with the second unit 120.ri,j and C vi,j+1 , thereby providing a sensing signal. Preferably, a shielding grid 160 is formed between the plurality of second units 120 arranged in a matrix, and the shielding grid 160 is used to shield interference signals to improve the accuracy of fingerprint detection.

[0054] The fourth unit 210 is, for example, an electrostatic protection circuit, and a plurality of fourth units 210 are respectively connected to the corresponding second units 120, and are used to provide an electrostatic discharge path between the electrostatic charge and the reference ground and a conduction path for the induction signal. The fourth unit 210 receives the induction signal and the electrostatic charge, and transmits the induction signal to the third unit 140, and releases the electrostatic charge to the reference ground, thereby preventing the semiconductor element in the first unit from being broken down, and the semiconductor element includes, for example, the element in the third unit 140.

[0055] The fourth unit 210 includes a voltage adjustment module, which is used to prevent damage to the device between the reference power supply and the reference ground caused by excessive electrostatic voltage. The fourth unit 210 is located in the first unit 110, thereby shortening the length of the wire between the fourth unit 210 and the second unit 120, reducing the size of the parasitic resistance, improving the electrostatic protection capability of the circuit, and improving the effect of rapid discharge. Furthermore, the fourth unit is formed in the first unit, which reduces the area occupied by the circuit, which is conducive to forming a small-area pixel unit.

[0056] The third unit 140 is, for example, a detection circuit, which includes, for example, a plurality of integration circuits. The plurality of third units 140 are respectively connected to the corresponding fourth units 210 to receive the sensing signal and output the detection signal. The third unit 140 includes: an operational amplifier, the in-phase input terminal of the operational amplifier is connected to the reference ground, and the inverting input terminal is connected to the output terminal of the fourth unit 210; and a first capacitor, the first terminal of the first capacitor is connected to the inverting input terminal of the operational amplifier, and the second terminal is connected to the output terminal of the operational amplifier. The third unit 140 is used to detect the sensing signal of each second unit 120, the sensing signal includes the capacitance between the ridge and valley of the finger 150 and the second unit 120, and the valley or peak of each second unit 120 corresponding to the finger is determined according to the size of the sensing signal, so as to read the fingerprint image of the finger 150.

[0057] Understandably, Figure 3 The figure only schematically shows the connection relationship between the second unit 120 and the fourth unit 210 and the third unit 140, without limiting the positions of the fourth unit 210 and the third unit 140.

[0058] Figures 6a to 6c Schematic diagrams of the third unit and the fourth unit according to the embodiments of the present invention are respectively shown.

[0059] like Figure 6a As shown, the third unit includes: an operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference ground, and the inverting input terminal is connected to the output terminal of the fourth unit; a first capacitor C1, the first terminal of the first capacitor C1 is connected to the inverting input terminal of the operational amplifier U1, and the second terminal is connected to the output terminal of the operational amplifier U1. A second capacitor C2 is formed between the second unit and the finger.

[0060] The fourth unit includes: a first switch tube SW1, a first end of the first switch tube SW1 is connected to the first end of the first capacitor C1, and a second end is connected to the second end of the first capacitor C1; and a second switch tube SW2, a first end of the second switch tube SW2 is connected to the second unit (not shown), and a second end is connected to the reference ground.

[0061] For example, the end of the second switch SW2 connected to the second unit adopts an asymmetric (or symmetric) MOS tube structure with an enlarged active area, and the end of the first switch SW1 connected to the second unit adopts a common MOS tube structure. The second switch SW2 is an N-channel field effect transistor, and the parasitic diode D2 of the second switch SW2 provides at least a part of the electrostatic discharge path between the electrostatic charge and the reference ground.

[0062] like Figure 6b As shown, the third unit includes: an operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage V ref , the inverting input end is connected to the output end of the fourth unit; the first capacitor C1, the first end of the first capacitor C1 is connected to the inverting input end of the operational amplifier U1, and the second end is connected to the output end of the operational amplifier U1. A second capacitor C2 is formed between the second unit and the finger.

[0063] The fourth unit includes: a first switch tube SW1, a first end of the first switch tube SW1 is connected to the first end of the first capacitor C1, and a second end is connected to the second end of the first capacitor C1; and a second switch tube SW2, a first end of the second switch tube SW2 is connected to the second unit (not shown), and a second end is connected to the reference ground.

[0064] For example, the first switch tube SW1 and the second switch tube SW2 are respectively connected to one end of the second unit and adopt an asymmetric (or symmetric) MOS tube structure with an enlarged active area. The first switch tube SW1 is a P-channel field effect transistor, the second switch tube SW2 is an N-channel field effect transistor, and the parasitic diode D1 of the first switch tube SW1 and the parasitic diode D2 of the second switch tube SW2 respectively provide at least a part of the electrostatic discharge path between the electrostatic charge and the reference ground.

[0065] like Figure 6cAs shown, the third unit includes: an operational amplifier U1, the non-inverting input terminal of the operational amplifier U1 is connected to the reference power supply, and the inverting input terminal is connected to the output terminal of the fourth unit; a first capacitor C1, the first end of the first capacitor C1 is connected to the inverting input terminal of the operational amplifier U1, and the second end is connected to the output terminal of the operational amplifier U1. A second capacitor C2 is formed between the second unit and the finger.

[0066] The fourth unit includes: a first switch tube SW1, a first end of the first switch tube SW1 is connected to the first end of the first capacitor C1, and a second end is connected to the second end of the first capacitor C1; a third switch tube SW3, a first end of the third switch tube SW3 is connected to the reference power supply, and a second end is connected to the second unit (not shown); and a second switch tube SW2, connected between the second end of the third switch tube SW3 and the inverting input terminal of the operational amplifier U1.

[0067] For example, the second switch SW2 and the third switch SW3 are respectively connected to one end of the second unit and adopt an asymmetric (or symmetric) MOS tube structure with an enlarged active area, and the body region of the second switch SW2 is connected to the reference ground. The second switch SW2 is an N-channel field effect transistor, the third switch SW3 is a P-channel field effect transistor, and the parasitic diode D1 of the third switch SW3 and the parasitic diode D2 of the second switch SW2 respectively provide at least a part of the electrostatic discharge path between the electrostatic charge and the reference ground.

[0068] Figures 7a to 7c They are shown according to Figures 6a to 6c Timing diagram of the switching tube in .

[0069] Figure 7a yes Figure 6a The control timing diagram of the switch tube in the third unit in FIG. 1 shows that the fingerprint sensor device has different electrostatic release paths when working in different time periods. In the PH1 and PH6 time periods, the control end of the second switch tube SW2 receives a high level, and the second switch tube SW2 is turned on, which can provide an electrostatic release path between the positive and negative electrostatic charges from the second unit and the reference ground; in the PH2-PH5 time period, the control end of the second switch tube SW2 receives a low level, and the second switch tube SW2 is turned off. Figure 6a The parasitic diode D2 of the second switch tube SW2 can provide an electrostatic discharge path between the negatively charged electrostatic charge from the second unit and the reference ground.

[0070] Figure 7b yes Figure 6bThe control timing diagram of the switch tube in the third unit in the fingerprint sensor device circuit has different electrostatic release paths when working in different time periods. In the PH1 and PH6 time periods, the control end of the second switch tube SW2 receives a high level, and the second switch tube SW2 is turned on, which can provide an electrostatic release path between the positive and negative electrostatic charges from the second unit and the reference ground; in the PH2-PH5 time period, the control end of the second switch tube SW2 receives a low level, and the second switch tube SW2 is turned off. Figure 6b The parasitic diode D2 of the second switch tube SW2 can provide an electrostatic discharge path between the negatively charged electrostatic charge from the second unit and the reference ground; in the PH2-PH5 time period, since the bulk of the first switch tube SW1 is connected to the reference power supply, the parasitic diode D1 of the first switch tube SW1 can provide an electrostatic discharge path between the positively charged electrostatic charge from the second unit and the reference ground.

[0071] Figure 7c yes Figure 6c The control timing diagram of the switch tube in the third unit in the fingerprint sensor device circuit has different electrostatic release paths when working in different time periods. In the PH1, PH3~PH5, PH7~PH9 time periods, the first switch tube SW1 and the third switch tube SW3 are turned off, and the second switch tube SW2 is turned on (or off). The parasitic diodes D1 and D2 of the third switch tube SW3 and the second switch tube SW2 respectively provide electrostatic release paths between the positive and negative electrostatic charges from the second unit and the reference ground; in the PH2 and PH6 time periods, the first switch tube SW1 and the third switch tube SW3 are turned on, and the second switch tube SW2 is turned off. Figure 6c The third switch tube SW3 that is turned on in the middle can provide an electrostatic discharge path between the positive and negative electrostatic charges from the second unit and the reference ground, and the parasitic diode D2 of the second switch tube SW2 can provide an electrostatic discharge path between the negative electrostatic charges from the second unit and the reference ground.

[0072] It should be understood that the above are only three embodiments of using parasitic diodes in combination with control timing to provide electrostatic discharge paths to achieve electrostatic protection. However, the present application is not limited thereto, and using parasitic diodes in combination with different circuit topologies and control timing can generate different electrostatic discharge paths to achieve electrostatic protection.

[0073] Figure 8a and 8b They are shown respectively Figures 6a to 6c Schematic diagram of the structure of the switching tube.

[0074] like Figure 8a As shown, Figure 8aThe switch tube includes a top view and a cross-sectional view along line AA. The switch tube includes, for example Figures 6a to 6c The switch tube SW2 in the switch tube. The switch tube includes a first unit 220, a first doping region 221, a second doping region 222, a dielectric layer 223 and a metal layer 224. The first doping region 221 and the second doping region 222 are located in the first unit 220. For example, the first doping region 221 and the second doping region 222 are respectively formed on the same surface of the first unit 220 by ion implantation. The first unit 220 is, for example, a P-type first unit 220. The first doping region 221 and the second doping region 222 are, for example, both N+ doping regions. The dielectric layer 223 is formed on the surface of the first unit 220, and the metal layer 224 is formed on the surface of the dielectric layer 223. The dielectric layer 223 and the metal layer 224 are located between the first doping region 221 and the second doping region 222 in a top view. The metal layer 224 forms the gate of the switch tube, the first doping region 221 and the second doping region 222 form the source and drain of the switch tube respectively, and a plurality of metal pads 225 are formed on the surfaces of the first doping region 221, the second doping region 222 and the metal layer 224. A parasitic diode D2 is formed between the first doping region 221 and the first unit 220, and the parasitic diode D2 provides at least a part of the electrostatic discharge path between the electrostatic charge and the reference ground.

[0075] like Figure 8b As shown, Figure 8b The switch tube includes a top view and a cross-sectional view along line BB. The switch tube includes, for example Figure 6b The switch SW1 and Figure 6c The switch tube SW3 in the embodiment of the present invention. The switch tube includes a first unit 220, a first doping region 221, a second doping region 222, a dielectric layer 223 and a metal layer 224. The first doping region 221 and the second doping region 222 are located in the first unit 220. For example, the first doping region 221 and the second doping region 222 are respectively formed on the same surface of the first unit 220 by ion implantation. The first unit 220 is, for example, an N-type first unit 220. The first doping region 221 and the second doping region 222 are, for example, both P+ doping regions. The dielectric layer 223 is formed on the surface of the first unit 220, and the metal layer 224 is formed on the surface of the dielectric layer 223. The dielectric layer 223 and the metal layer 224 are located between the first doping region 221 and the second doping region 222 in a top view. The metal layer 224 forms the gate of the switch tube, the first doping region 221 and the second doping region 222 form the source and drain of the switch tube respectively, and a plurality of metal pads 225 are formed on the surfaces of the first doping region 221, the second doping region 222 and the metal layer 224. A parasitic diode D1 is formed between the second doping region 222 and the first unit 220, and the parasitic diode D1 provides at least a part of the electrostatic discharge path between the electrostatic charge and the reference ground.

[0076] In this embodiment, the first doped region 221 and the second doped region 222 respectively form the source region and the drain region of the switching tube, the cross-sectional areas of the source region and the drain region in the direction perpendicular to the first unit are different, the distance between the metal pad on the surface of the larger one of the source region and the drain region and the gate region is greater than the distance between the metal pad on the surface of the other one of the source region and the drain region and the gate region, and the larger one of the source region and the drain region provides at least one of the parasitic diode of the first switching tube, the parasitic diode of the second switching tube, and the parasitic diode of the third switching tube.

[0077] In an alternative embodiment, the first doped region 221 and the second doped region 222 respectively form the source region and the drain region of the switching tube, the cross-sectional area of ​​the source region and the drain region in the direction perpendicular to the first unit is the same, and one of the source region and the drain region connected to the second unit provides at least one of the parasitic diode of the first switching tube, the parasitic diode of the second switching tube, and the parasitic diode of the third switching tube.

[0078] Figures 9a to 9d Schematic diagrams of the fourth unit according to the embodiments of the present invention are respectively shown.

[0079] In this embodiment, the fourth unit 210 includes: an input end, connected to the second unit, for receiving an input signal, the input signal including an induction signal and an electrostatic charge; an output end, connected to the input end, for providing an induction signal; a first electrostatic protection element, a first end of the first electrostatic protection element is connected to a reference power supply, and a second end is connected between the input end and the output end; and a second electrostatic protection element, a first end of the second electrostatic protection element is connected between the input end and the output end, and a second end is connected to a reference ground; a voltage adjustment module, connected between the power supply voltage and the reference ground, for preventing damage to the device between the reference power supply and the reference ground caused by excessive electrostatic voltage. In an alternative embodiment, the voltage adjustment module can also be pulled down to the ground (or pulled up to the power supply) through a resistor or an equivalent resistor.

[0080] like Figure 9a and 9bAs shown, the fourth unit 210 includes: an input terminal for receiving an input signal, the input signal includes an induction signal and an electrostatic charge carried; an output terminal connected to the input terminal for outputting an induction signal; a first diode D1 for releasing positive electrostatic charge, the cathode end of the first diode D1 is connected to the reference power supply, and the anode end is connected between the input terminal and the output terminal; a second diode D2 for releasing negative electrostatic charge, the cathode end of the second diode D2 is connected between the input terminal and the output terminal, and the anode end is connected to the reference ground; and a clamping transistor M3 for clamping the electrostatic charge to release the electrostatic charge within a specific size range when the device is working normally, the first channel end of the clamping transistor M3 is connected to the reference power supply, the second channel end is connected to the reference ground, and the control end is connected to the reference power supply or the reference ground. The first diode D1 and the clamping transistor M3 provide an electrostatic release path between the positive electrostatic charge and the reference ground, and the second diode D2 provides an electrostatic release path between the negative electrostatic charge and the reference ground.

[0081] When the clamp transistor M3 is an NMOS transistor, the control end of the clamp transistor M3 is connected to the reference ground; when the clamp transistor M3 is a PMOS transistor, the control end of the clamp transistor M3 is connected to the reference power supply.

[0082] like Fig.9c and 9d As shown, the fourth unit 210 includes: an input terminal for receiving an input signal, the input signal includes an induction signal and an electrostatic charge carried; an output terminal connected to the input terminal for outputting an induction signal; a first transistor M1 for releasing positive electrostatic charge, the first channel terminal and the control terminal of the first transistor M1 are respectively connected to the reference power supply, and the second channel terminal is connected between the input terminal and the output terminal; a second transistor M2 for releasing negative electrostatic charge, the first channel terminal of the second transistor M2 is connected between the input terminal and the output terminal, and the second channel terminal and the control terminal are respectively connected to the reference ground; and a clamping transistor M3 for clamping the electrostatic charge to release the electrostatic charge within a specific size range when the device is working normally, the first channel terminal of the clamping transistor M3 is connected to the reference power supply, the second channel terminal is connected to the reference ground, and the control terminal is connected to the reference power supply or the reference ground. Among them, the first transistor M1 and the clamping transistor M3 provide an electrostatic release path between the positive electrostatic charge and the reference ground, and the second transistor M2 provides an electrostatic release path between the negative electrostatic charge and the reference ground.

[0083] The first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. When the clamping transistor M3 is an NMOS transistor, the control end of the clamping transistor M3 is connected to the reference ground; when the clamping transistor M3 is a PMOS transistor, the control end of the clamping transistor M3 is connected to the reference power supply.

[0084] Fig.10 A schematic diagram of an electronic device according to an embodiment of the present invention is shown.

[0085] like Fig.10 As shown, the electronic device 300 includes at least one fingerprint sensor device 200. The electronic device 300 also includes a display panel, for example, and the fingerprint sensor device 200 is formed on the display panel for touch sensing or full-screen fingerprint recognition. The display panel includes any one of a liquid crystal display panel, a plasma display panel, an organic light emitting diode display panel, and an electrophoretic display panel.

[0086] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A fingerprint sensor device, characterized in that: include: A first unit, wherein the first unit comprises a plurality of switch tubes; a plurality of second units located on the first unit, wherein the second units are used to provide sensing signals; A plurality of third units, configured to provide detection signals according to the sensing signals; as well as a plurality of fourth units, wherein the plurality of fourth units are respectively connected between the corresponding second units and the third units, and are used to provide an electrostatic discharge path and a conduction path for the induction signal, Among them, each fourth unit includes at least one electrostatic protection element and a clamping transistor, the clamping transistor is connected to the electrostatic protection element for protecting the electrostatic protection element, and the parasitic diode of at least one switching tube among the multiple switching tubes provides at least one of the electrostatic protection elements.

2. The fingerprint sensor device according to claim 1, characterized in that: The plurality of switch tubes include: a first switch tube, wherein a first end of the first switch tube is connected to the second unit, and a second end of the first switch tube is connected to an output end of the third unit; and a second switch tube, wherein a first end of the second switch tube is connected to the second unit, and a second end of the second switch tube is connected to a reference ground; Wherein, the second switch tube is an NMOS transistor, and the electrostatic protection element includes a parasitic diode of the second switch tube. When the second switch tube is in the on state, the parasitic diode of the second switch tube provides at least a part of the electrostatic discharge path between the positive electrostatic charge and the negative electrostatic charge and the reference ground. When the second switch tube is in the off state, the parasitic diode of the second switch tube provides at least a part of the electrostatic discharge path between the negatively charged electrostatic charge and the reference ground.

3. The fingerprint sensor device according to claim 2, characterized in that: The first switch tube is a PMOS transistor, and the electrostatic protection element includes a parasitic diode of the first switch tube and a parasitic diode of the second switch tube. A body region of the first switch tube is connected to a reference power supply, and a parasitic diode of the first switch tube provides at least a portion of the electrostatic discharge path between the positively charged electrostatic charge and the reference ground.

4. The fingerprint sensor device according to claim 2, characterized in that: The plurality of switch tubes include: A first switch tube, wherein a first end of the first switch tube is connected to the second unit, and a second end of the first switch tube is connected to an output end of the third unit; a second switch tube, wherein a first end of the second switch tube is connected to the second unit, and a second end of the second switch tube is connected to an input end of the third unit; and a third switch tube, wherein a first end of the third switch tube is connected to a reference power supply, and a second end of the third switch tube is connected to the second unit; The second switch tube is an NMOS transistor, the third switch tube is a PMOS transistor, and the electrostatic protection element includes a parasitic diode of the second switch tube and a parasitic diode of the third switch tube. When the second switch tube and / or the third switch tube is in the on state, the parasitic diode of the second switch tube and / or the parasitic diode of the third switch tube provides at least a part of the electrostatic discharge path between the positive electrostatic charge and the negative electrostatic charge and the reference ground. When the second switch tube is in the off state, the parasitic diode of the second switch tube provides at least a part of the electrostatic discharge path between the negatively charged electrostatic charge and the reference ground. When the third switch tube is in the off state, the parasitic diode of the third switch tube provides at least a portion of the electrostatic discharge path between the positively charged electrostatic charge and the reference ground.

5. The fingerprint sensor device according to claim 3 or 4, characterized in that: The NMOS transistor and / or the PMOS transistor comprises a source region, a drain region and a gate region, and surfaces of the source region and the drain region comprise metal pads, Among them, the cross-sectional areas of the source region and the drain region in a direction perpendicular to the first unit are different, the distance between the metal pad on the surface of the larger one of the source region and the drain region and the gate region is greater than the distance between the metal pad on the surface of the other of the source region and the drain region and the gate region, and the larger one of the source region and the drain region provides at least one of the parasitic diode of the first switch tube, the parasitic diode of the second switch tube, and the parasitic diode of the third switch tube.

6. The fingerprint sensor device according to claim 1, characterized in that: At least one of the clamp transistors is formed in the first cell.

7. An electronic device, characterized in that: The invention comprises a fingerprint sensing device as claimed in any one of claims 1 to 6.

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