Magnetic storage device

Abstract

The embodiment provides a magnetic storage device capable of performing a stable reading operation. The magnetic storage device of the embodiment comprises: a magnetic storage wire (MML) which is a linear magnetic body and has a first magnetic region and a second magnetic region with variable magnetization directions; a magnetoresistive element (11) having either a first resistor corresponding to the magnetization direction of the first magnetic region or a second resistor corresponding to the magnetization direction of the second magnetic region; and a reading circuit (40) which compares the first resistor of the magnetoresistive element (11) with the second resistor of the magnetoresistive element (11). The reading circuit (40) outputs first data when the first resistor and the second resistor are unchanged, and outputs second data when the first resistor and the second resistor are different.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2018-51178 (filing date: March 19, 2018) as a basic application. This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a magnetic storage device. Background Art

[0004] As a magnetic storage device, a magnetic storage device using a magnetic thin wire having a plurality of magnetic regions is known. Summary of the invention

[0005] Embodiments provide a magnetic storage device capable of performing a stable reading operation.

[0006] The magnetic storage device of the embodiment comprises: a magnetic wire, which is a linear magnetic body and has a first magnetic region and a second magnetic region with variable magnetization directions; a magnetoresistive element, which has either a first resistor corresponding to the magnetization direction of the first magnetic region or a second resistor corresponding to the magnetization direction of the second magnetic region; and a read circuit, which compares the first resistor of the magnetoresistive element with the second resistor of the magnetoresistive element; and the read circuit outputs the first data when the first resistor and the second resistor are unchanged, and outputs the second data when the first resistor and the second resistor are different.

[0007] The reading circuit may output the first data when the difference between the first resistor and the second resistor is less than a first value, and output the second data when the difference between the first resistor and the second resistor is greater than the first value.

[0008] It may also be that the magnetoresistive element has an MTJ (magnetic tunnel junction) structure formed by a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer, and the second magnetic layer has the same magnetization direction as the first magnetic region due to magnetic induction from the first magnetic region of the magnetic wire.

[0009] It may also be that the magnetoresistive element has a low resistance state when the magnetization direction of the second magnetic layer is parallel to the magnetization direction of the first magnetic layer, and has a high resistance state higher than the low resistance state when the magnetization direction of the second magnetic layer is antiparallel to the magnetization direction of the first magnetic layer.

[0010] The magnetoresistive element may include a first magnetic layer and a nonmagnetic layer, and the magnetoresistive element may include an MTJ (magnetic tunnel junction) structure formed by the first magnetic region of the magnetic wire, the first magnetic layer, and the nonmagnetic layer between the first magnetic region and the first magnetic layer.

[0011] It may also be that the magnetoresistive element has a low resistance state when the magnetization direction of the first magnetic zone is parallel to the magnetization direction of the first magnetic layer, and has a high resistance state higher than the low resistance state when the magnetization direction of the first magnetic zone is antiparallel to the magnetization direction of the first magnetic layer.

[0012] It may also be that: the reading circuit has a shift driver to shift the first magnetic region and the second magnetic region of the magnetic wire, the first magnetic region of the magnetic wire is configured at a first position within the magnetic wire, and after the reading circuit reads the first resistor corresponding to the magnetization direction of the first magnetic region, the shift driver shifts the second magnetic region to the first position.

[0013] It may also be that: the reading circuit has: a first circuit, which reads out the first resistor and the second resistor of the magnetoresistive element; and a read amplifier, which compares the first resistor read out by the first circuit with the second resistor; and the first circuit includes: a second circuit, which supplies or stops supplying a reading current to the magnetoresistive element; a capacitor, which accumulates a signal corresponding to either the first resistor or the second resistor; and a third circuit, which sets the timing for accumulating the signal in the capacitor.

[0014] It may also be that: the reading circuit has: a first circuit, which reads out the first resistor and the second resistor of the magnetoresistive element; and a read amplifier, which compares the first resistor read out by the first circuit with the second resistor; and the first circuit includes: a second circuit, which supplies or stops supplying a reading current to the magnetoresistive element; a first capacitor, which accumulates a signal corresponding to the first resistor; a second capacitor, which accumulates a signal corresponding to the second resistor; a third circuit, which sets a timing for accumulating the signal corresponding to the first resistor into the first capacitor; and a fourth circuit, which sets a timing for accumulating the signal corresponding to the second resistor into the second capacitor.

[0015] It may also be that the reading circuit comprises: a first circuit for reading the first resistance and the second resistance of the magnetoresistive element; and a read amplifier for comparing the first resistance read by the first circuit with the second resistance; and the read amplifier comprises a first circuit for setting the first value.

[0016] According to the embodiment, a magnetic storage device capable of performing a stable reading operation can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram showing the structure of the magnetic storage device according to the first embodiment.

[0018] Figure 2 It is a diagram showing the circuit configuration of the memory cell array according to the first embodiment.

[0019] Figure 3 It is a perspective view showing an example of the configuration of the memory cell array according to the first embodiment.

[0020] Figure 4 It is a diagram showing the magnetic domains and information storage method of the magnetic memory wire according to the first embodiment.

[0021] Figure 5 (a) to (r) are diagrams showing the sequence of writing and reading with respect to the magnetic memory thin wire according to the first embodiment.

[0022] Figure 6 (a) to (d) are schematic diagrams of reading the magnetic memory thin wire according to the first embodiment.

[0023] Figure 7 (a) to (d) are diagrams showing a reading method of the magnetic storage device according to the first embodiment.

[0024] Figure 8 (a) to (d) are diagrams showing a reading method of the magnetic storage device according to the first embodiment.

[0025] Fig. 9 This is a circuit diagram showing the configuration of a reading circuit according to the first embodiment.

[0026] Fig.10 This is a circuit diagram showing the configuration of a sense amplifier according to the first embodiment.

[0027] Fig.11 This is a flowchart showing the reading operation in the first embodiment.

[0028] Fig.12 This is a timing chart of each signal in the read operation of the first embodiment.

[0029] Fig.13 This is a circuit diagram showing the configuration of a reading circuit according to the second embodiment.

[0030] Fig.14 This is a circuit diagram showing the configuration of a reading circuit according to a modification of the second embodiment.

[0031] Fig.15This is a circuit diagram showing the configuration of a reading circuit according to another modified example of the second embodiment.

[0032] Fig.16 This is a circuit diagram showing the configuration of a sense amplifier according to the second embodiment.

[0033] Fig.17 This is a flowchart showing the reading operation in the second embodiment.

[0034] Fig.18 This is a timing chart of each signal in the read operation of the second embodiment.

[0035] Fig.19 It is a diagram showing a memory chip in which the magnetic storage device according to the first and second embodiments is arranged.

[0036] Fig. 20 The figure shows an SSD (Solid state drive) equipped with a memory chip. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following description, the same symbols are used to mark the components having the same function and configuration. In addition, each embodiment shown below is an example of a device or method for concretely implementing the technical idea of ​​the embodiment, and does not specify the material, shape, structure, configuration, etc. of the components as described below.

[0038] Each functional block can be implemented as a combination of hardware, computer software, or both. Each functional block does not necessarily have to be distinguished as in the following examples. For example, a portion of the functions can also be implemented by other functional blocks different from the illustrated functional blocks. Furthermore, the illustrated functional blocks can also be divided into finer functional sub-blocks.

[0039] [1] First Embodiment

[0040] A magnetic storage device according to the first embodiment will be described. This magnetic storage device is also called a magnetic wall movement memory.

[0041] [1-1] Configuration of magnetic storage device

[0042] use Figure 1 The configuration of the magnetic storage device according to the first embodiment will be described. Figure 1 The magnetic storage device 1 includes a memory cell array 10 , a word line (WL) decoder 20 , a bit line (BL) decoder 30 , a read circuit 40 , a shift driver 50 , a field line (FL) driver 60 , and a controller 70 .

[0043] The memory cell array 10 has a plurality of magnetic storage wires (or magnetic wires). The magnetic storage wires include a plurality of magnetic regions (or magnetic walls) for storing data. The magnetic storage wires are arranged in rows and columns. The magnetic storage wires are electrically connected between the word lines WL and the bit lines BL. Details of the magnetic storage wires will be described below.

[0044] The word line decoder 20 selects one word line from a plurality of word lines WL according to the row address. The bit line decoder 30 selects one bit line from a plurality of bit lines BL according to the column address. The read circuit 40 has a read amplifier, and reads data from the magnetic storage wires in the memory cell array 10. During the read operation, the shift driver 50 applies a voltage that moves the magnetic regions (or magnetic walls) in the magnetic storage wires. That is, an offset current that shifts the magnetic regions arranged in the magnetic storage wires is output. During writing, the field line driver 60 causes current to flow through the field lines, and generates an induced magnetic field corresponding to the write data from the field lines.

[0045] [1-1-1] Configuration of Memory Cell Array 10

[0046] Next, use Figure 2 The circuit configuration of the memory cell array 10 according to the first embodiment will be described. Figure 2 2 is a diagram showing a circuit configuration of the memory cell array 10 .

[0047] The magnetic storage wire MML is electrically connected between the word line WL and the bit line BL. One end of the magnetic storage wire MML is connected to the word line WL via the magnetoresistive element (or resistance change element, variable resistance element) 11 and the selection element 12 in sequence. That is, one end of the magnetic storage wire MML is connected to one end of the magnetoresistive element 11, and the other end of the magnetoresistive element 11 is connected to one end of the selection element 12. The other end of the selection element 12 is connected to the word line WL. Furthermore, the other end of the magnetic storage wire MML is connected to the bit line BL.

[0048] The magnetoresistance effect element 11 includes, for example, an MTJ (magnetic tunnel junction) element whose resistance changes according to the magnetization state. The selection element 12 includes, for example, an element that becomes a low resistance state after applying a voltage above a threshold voltage, and becomes a high resistance state after applying a voltage below the threshold voltage. The selection element 12 may also be, for example, a two-terminal switching element. For example, when the voltage applied between the two terminals is below the threshold, the switching element is in a "high resistance" state, for example, an electrically non-conductive state. In addition, when the voltage applied between the two terminals is above the threshold, the switching element is in a "low resistance" state, for example, an electrically conductive state. The switching element may also be configured to achieve the above-mentioned function regardless of the polarity of the voltage. The switching element includes at least one chalcogen element selected from the group consisting of Te, Se and S. Or it may also include a compound containing the chalcogen element, namely a chalcogenide. In addition, the switching element may also include at least one element selected from the group consisting of B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

[0049] For example, a plurality of magnetic storage wires MML, magnetoresistive elements 11, and selection elements 12 arranged in a first direction are connected to the same word line WL at the other end of the selection element 12. On the other hand, a plurality of magnetic storage wires MML, magnetoresistive elements 11, and selection elements 12 arranged in a second direction intersecting the first direction are connected to the same bit line BL at the other end of the magnetic storage wires MML.

[0050] Figure 3 FIG. 1 is a perspective view showing an example of the structure of the memory cell array 10. Figure 3 In the diagram, two directions orthogonal to each other are defined as an X direction and a Y direction, and a direction orthogonal to the X direction and the Y direction (XY plane) and in which the magnetic memory thin line MML extends is defined as a Z direction.

[0051] Several bit lines BL extending in the Y direction are arranged in the X direction. On the bit lines BL, magnetic storage fine lines MML, magnetoresistive effect elements 11, and selection elements 12 are arranged in the Z direction. The magnetoresistive effect element 11 is composed of, for example, an MTJ element. The MTJ element includes a magnetic layer 11R, a non-magnetic layer 11N, and a magnetic layer 11S. Details of the MTJ element will be described below.

[0052] The structure of the memory cell array 10 is described in detail. A magnetic memory fine line MML is provided on the bit line BL. A magnetic layer 11S is provided on the magnetic memory fine line MML. The magnetic layer 11S extends only a certain distance in the Y direction, and a non-magnetic layer 11N and a magnetic layer 11R are provided in sequence on the extended magnetic layer 11S. On the magnetic layer 11R, a word line WL is provided via a selection element 12.

[0053] The magnetic memory thin wires MML, the magnetoresistance effect elements 11, and the selection elements 12 arranged in the Z direction are arranged in rows and columns in the X and Y directions. The word lines WL are arranged on the selection elements 12 arranged in the X direction. Furthermore, the field lines FL are arranged on the magnetic layer 11S. The field lines FL are arranged in a zigzag shape in the X direction so as to pass between the magnetoresistance effect elements 11 adjacent in the X direction and the Y direction.

[0054] The MTJ element is described in detail below. The MTJ element includes a magnetic layer 11R, a non-magnetic layer 11N, and a magnetic layer 11S. The non-magnetic layer 11N is arranged between the magnetic layer 11R and the magnetic layer 11S. The magnetic layer 11R functions as a reference layer, and the magnetic layer 11S functions as a storage layer. The non-magnetic layer 11N functions as a tunnel barrier. In addition, the MTJ element may also include another layer.

[0055] The magnetic layer (storage layer) 11S is magnetized in a direction along a certain axis. For example, the magnetization of the magnetic layer 11S is stably performed in a direction parallel to the boundary surface of the layers 11S, 11R, and 11N. The magnetization direction of the magnetic layer 11S can be reversed according to the magnetization direction of the magnetic region of the magnetic storage fine line MML.

[0056] The magnetic layer (reference layer) 11R has a magnetization with a fixed or unchanged direction, for example, a coercive force greater than the coercive force of the magnetic layer (storage layer) 11S. The so-called "fixed" or "unchanged" magnetization direction of the magnetic layer 11R means that the magnetization direction of the magnetic layer 11R will not be reversed according to the magnetization direction of the magnetic storage fine line MML that reverses the magnetization of the magnetic layer (storage layer) 11S.

[0057] The group of the magnetic layer 11R, the non-magnetic layer 11N, and the magnetic layer 11S represents the magnetoresistance effect. Specifically, if the magnetization direction of the magnetic layer 11S is parallel and anti-parallel to the magnetization direction of the magnetic layer 11R, the MTJ element represents the minimum and maximum resistance values, respectively. The magnetoresistance effect element (MTJ element) 11 can take a low resistance state when the relative relationship between the magnetization directions of the magnetic layer (storage layer) 11S and the magnetic layer (reference layer) 11R is parallel, and can take a high resistance state when it is anti-parallel.

[0058] [1-1-2] Structure of magnetic storage wire and information storage method

[0059] Next, use Figure 4 The structure of the magnetic memory thin wire MML and the information storage method according to the first embodiment will be described. Figure 4 Yes means Figure 3The diagram shows a cross-sectional structure of one magnetic memory line MML along line AA′, an example of magnetic domains (or magnetization states) included in the magnetic memory line MML, and an information storage method using these magnetic domains.

[0060] The magnetic storage thin wire MML provided in the magnetic storage device includes, for example, Figure 3 The linear ferromagnetic body extending along the Z direction as shown. The linear ferromagnetic body can be, for example, Figure 4 The central portion of the magnetic storage line MML may be hollow in the form of a cylinder (e.g., a cylindrical shape), or may be a shape without a hollow central portion. The ferromagnetic body has a plurality of magnetic regions along the Z direction. For example, the cross section of the cylindrical magnetic film of the magnetic storage line MML has magnetic regions M1, M2, M3, ... along the Z direction.

[0061] Each magnetic region can maintain magnetization (or magnetization state) in one direction or in a direction opposite to one direction. Figure 4 As shown, each magnetic zone has a magnetization direction formed in the order of N pole and S pole from the outside of the cylinder, and a magnetization direction formed in the order of S pole and N pole from the outside of the cylinder. The boundary between the magnetic zones is called a magnetic wall. In addition, the magnetization direction of each magnetic zone can be a direction perpendicular to the Z direction extending the magnetic storage fine line MML (perpendicular magnetization film), or it can also be the Z direction extending the magnetic storage fine line MML (in-plane magnetization film).

[0062] In the Z direction, when the magnetization directions of two adjacent magnetic regions are the same, the first data is stored. On the other hand, when the magnetization directions of two adjacent magnetic regions are different, the second data different from the first data is stored. For example, because the magnetization directions of magnetic regions M1 and M2 are the same, "0" is stored. On the other hand, because the magnetization directions of magnetic regions M2 and M3 are different, "1" is stored. In addition, when the magnetization directions are the same as between magnetic regions M1 and M2, there is no magnetic wall between magnetic regions M1 and M2.

[0063] [1-2] Write and read operations

[0064] Next, the writing and reading actions of the magnetic storage device of the first embodiment are described. In the reading and writing of data, the magnetic domain to be read or written is shifted to the position of the mechanism for reading or writing (hereinafter referred to as the reading position or the writing position). That is, the magnetic wall between the magnetic domains is shifted in such a way that the magnetic domain to be read or written is moved to the reading position or the writing position. The displacement of the magnetic wall is performed, for example, by passing a current through the magnetic storage fine wire MML.

[0065] Figure 5 1 is a diagram showing the sequence of writing and reading on the magnetic memory thin line MML. Here, the conceptual sequence of writing and reading is shown.

[0066] First, the order of writing is described. In writing, if Figure 5 In the state before writing shown in (a), if "0" is written by the writing unit as shown in (b), then "0" is written in the first magnetic interval of the magnetic storage line MML. Next, as shown in (c), if "1" is written by the writing unit, then "0" in the first magnetic interval of the magnetic storage line MML is shifted to the second magnetic interval, and "1" is written in the first magnetic interval. Furthermore, as shown in (d), if "0" is written by the writing unit, then "0" in the second magnetic interval of the magnetic storage line MML is shifted to the third magnetic interval, "1" in the first magnetic interval is shifted to the second magnetic interval, and "0" is written in the first magnetic interval.

[0067] The subsequent writing is also similarly performed, as shown in (e) to (i), the previously written data is shifted in the direction away from the writing position, and the data is written to the first magnetic section.

[0068] Next, the order of reading is described. Figure 6 This is a schematic diagram of the reading of the magnetic memory fine line MML. Figure 5 As shown in (j), a read current is passed through the magnetic memory line MML, and the "1" stored in the first magnetic interval of the magnetic memory line MML is read by the read unit.

[0069] Next, if Figure 6 As shown in (a), a bias current is passed through the magnetic storage fine line MML to shift the magnetic domain in the magnetic storage fine line MML toward the direction close to the reading position. Figure 5 As shown in (k), for example, the "0" existing in the second magnetic interval before reading is shifted to the first magnetic interval, and the "1" existing in the third magnetic interval is shifted to the second magnetic interval. Figure 5 (k) and Figure 6 As shown in (b), a read current is passed through the magnetic memory line MML, and the "0" stored in the first magnetic interval of the magnetic memory line MML is read by the read unit.

[0070] Next, if Figure 6 As shown in (c), an offset current is passed through the magnetic storage line MML to shift the magnetic domain in the magnetic storage line MML toward the reading position. Figure 5 As shown in (l), for example, in Figure 5 In the reading shown in (k), the "1" existing in the second magnetic interval is shifted to the first magnetic interval, and the "0" existing in the third magnetic interval is shifted to the second magnetic interval. Figure 5 (l) and Figure 6As shown in (d), a read current is passed through the magnetic memory line MML, and the "1" existing in the first magnetic interval of the magnetic memory line MML is read by the read unit.

[0071] The subsequent reading is also similar, as shown in (m) to (r), each magnetic domain (or each magnetic wall) in the magnetic storage fine line MML is shifted in the direction close to the reading position, and the data stored in the first magnetic domain is read.

[0072] [1-2-1] Reading Action

[0073] Next, use Figure 7 An overview of the reading method of the magnetic storage device according to the first embodiment will be described. Figure 7 1 is a diagram showing a reading method of a magnetic memory device, and schematically shows a magnetoresistive element (eg, MTJ element) 11 and a magnetic memory thin line MML.

[0074] The positional relationship between the magnetic layer 11S of the magnetoresistive element 11 and the read position RP is set so that the magnetic layer 11S has the same magnetization direction as the magnetic region at the read position RP due to magnetic induction (or induced magnetic field) from the magnetic region existing at the read position RP to the magnetic layer 11S of the magnetoresistive element 11.

[0075] exist Figure 7 In the initial state shown in (a), the magnetic zone M1 is arranged at the reading position RP, and the magnetic zones M2, M3, M4, and M5 are arranged in sequence in the direction away from the reading position RP. At this time, the magnetic layer 11S maintains the same magnetization direction as the magnetic zone M1 by the magnetic induction from the magnetic zone M1 arranged at the reading position RP. As a result, the magnetic layer 11S of the magnetoresistive effect element 11 maintains a magnetization direction parallel to (in the same direction as) the magnetic layer 11R. As a result, the resistance of the magnetoresistive effect element 11 becomes low resistance, and the reading circuit 40 reads that the magnetoresistive effect element 11 is in a low resistance state.

[0076] Next, if Figure 7 As shown in (b), the magnetic domain in the magnetic storage fine line MML is shifted toward the direction of the reading position RP, and the magnetic domain M2 is set at the reading position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M2 through the magnetic induction from the magnetic domain M2 configured at the reading position RP. As a result, the magnetic layer 11S maintains a magnetization direction parallel to the magnetic layer 11R. Figure 7 Similarly to the case (a), the resistance of the magnetoresistance effect element 11 becomes low resistance, and the reading circuit 40 reads that the magnetoresistance effect element 11 is in the low resistance state.

[0077] So, when Figure 7 The first readout shown in (a) and Figure 7In the case where the second read-out shown in (b) is in the low resistance state, the read circuit 40 outputs "0", for example. That is, "0" is output as the data stored in the magnetic regions M1 and M2. In addition, the case where the first and second read-outs are in the low resistance state is described here, but even in the case where the first and second read-outs are in the high resistance state, the read circuit 40 outputs "0".

[0078] Next, if Figure 7 As shown in (c), the magnetic domain in the magnetic storage fine line MML is shifted toward the direction of the reading position RP, and the magnetic domain M3 is set at the reading position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M3 through the magnetic induction from the magnetic domain M3 configured at the reading position RP. As a result, the magnetic layer 11S maintains a magnetization direction that is antiparallel (in the opposite direction) to the magnetic layer 11R. As a result, the resistance of the magnetoresistive effect element 11 becomes a high resistance, and the reading circuit 40 reads that the magnetoresistive effect element 11 is in a high resistance state.

[0079] So, in Figure 7 The second readout shown in (b) and Figure 7 When the third reading shown in (c) shows a different resistance state, the reading circuit 40 outputs, for example, "1". That is, "1" is output as data stored in the magnetic regions M2 and M3.

[0080] Next, if Figure 7 As shown in (d), the magnetic domain in the magnetic storage fine line MML is shifted toward the direction of the reading position RP, and the magnetic domain M4 is set at the reading position RP. The magnetic layer 11S maintains the same magnetization direction as the magnetic domain M4 through the magnetic induction from the magnetic domain M4 configured at the reading position RP. As a result, the magnetic layer 11S maintains a magnetization direction parallel to the magnetic layer 11R. As a result, the resistance of the magnetoresistive effect element 11 becomes low resistance, and the reading circuit 40 reads that the magnetoresistive effect element 11 is in a low resistance state.

[0081] So, in Figure 7 The third readout shown in (c) and Figure 7 When the fourth reading shown in (d) is a different resistance state, the reading circuit 40 outputs, for example, "1." That is, "1" is output as data stored in the magnetic regions M3 and M4.

[0082] In a reading method of one embodiment, when the resistance state of the previous reading is the same as the resistance state of the current reading, it is determined to be the first data (for example, "0"). On the other hand, when the resistance state of the previous reading is different from the resistance state of the current reading, it is determined to be the second data (for example, "1"). That is, in two consecutive readings, when the readings are both low resistance states or both high resistance states, it is determined to be the first data, and when different resistance states are read, it is determined to be the second data. In other words, the resistance of the magnetoresistance effect element 11 relative to the two magnetic regions connected in the magnetic storage fine line MML is read, and when the resistance of the magnetoresistance effect element 11 has not changed, it is determined to be the first data, and when the resistance of the magnetoresistance effect element 11 has changed, it is determined to be the second data.

[0083] Next, use Figure 8 The reading method according to the first embodiment will be described. Figure 8 A magnetoresistive element (for example, MTJ element) thin line MML is schematically shown.

[0084] exist Figure 8 In the mechanism shown, replace Figure 7 The magnetic layer (storage layer) 11S of the magnetoresistive element 11 shown in the figure is used to configure the magnetic domain of the magnetic storage fine line MML. That is, Figure 7 The position of the magnetic layer 11S shown is the reading position RP, and the magnetic domain to be read of the magnetic memory thin line MML is arranged at the reading position RP. Therefore, the magnetic domain arranged at the reading position RP functions as the memory layer of the magnetoresistive element 11 .

[0085] If the magnetic domain arranged at the reading position RP has a magnetization direction parallel to (in the same direction as) the magnetic layer 11R, the resistance of the magnetoresistive element 11 becomes low resistance. The reading circuit 40 reads that the magnetoresistive element 11 is in a low resistance state.

[0086] On the other hand, if the magnetic domain arranged at the reading position RP has a magnetization direction antiparallel to (opposite to) the magnetic layer 11R, the resistance of the magnetoresistive element 11 becomes high resistance. The reading circuit 40 reads that the magnetoresistive element 11 is in a high resistance state.

[0087] The displacement of the magnetic domain of the other magnetic memory thin wires MML, the determination of data based on the resistance state of the magnetoresistive element 11, etc. are similar to the above Figure 7 The reading method shown is the same.

[0088] Next, the details of the read operation of the magnetic storage device according to Embodiment 1 will be described. First, the read circuit 40 used in the read operation will be described.

[0089] Fig. 91 is a circuit diagram showing the configuration of a read circuit according to Embodiment 1. The read circuit 40 includes a capacitor C1, a sense amplifier 46, an equalizer circuit 41, a multiplexer (Mux) 42, p-channel MOS transistors (hereinafter referred to as pMOS transistors) PT1 and PT2, and n-channel MOS transistors (hereinafter referred to as nMOS transistors) NT1 and NT2.

[0090] The following describes Fig. 9 The circuit connection of the reading circuit shown in FIG. 4 is shown. The first input terminal of the sense amplifier 46 is connected to the first electrode of the capacitor C1, the gate of the pMOS transistor PT1, and the first terminal of the equalizer circuit 41. The second input terminal of the sense amplifier 46 is connected to the drain of the pMOS transistor PT1, the drain of the nMOS transistor NT1, and the second terminal of the equalizer circuit 41. The source of the nMOS transistor NT1 is connected to the drain of the pMOS transistor PT2 and the input terminal of the multiplexer 42 via the nMOS transistor NT2. The power supply voltage VDD is supplied to the second electrode of the capacitor C1 and the source of the pMOS transistor PT1. Furthermore, the offset voltage VS is supplied to the source of the pMOS transistor PT2.

[0091] The shift signal SFTn is input to the gate of the pMOS transistor PT2. The clamp signal VCLMP is input to the gate of the nMOS transistor NT1, and the read enable signal RE is input to the gate of the nMOS transistor NT2. The equalization signals EQ and EQn are input to the gates of the transistors of the equalization circuit 41. The output signal DOUT is output from the sense amplifier 46. In addition, "n" after the symbol of the signal indicates a row active signal.

[0092] In addition, the output terminal of the multiplexer 42 is connected to the reference voltage terminal VSS via the magnetoresistive element 11 and the magnetic memory thin line MML.

[0093] In the reading circuit 40, the circuit preceding the sense amplifier 46 functions as a preamplifier for reading the resistance state of the magnetoresistive element 11. The preamplifier accumulates a state signal corresponding to the resistance state of the magnetoresistive element 11 in the capacitor C1.

[0094] Fig.10 2 is a circuit diagram showing the configuration of the sense amplifier 46 of the read circuit 40. The sense amplifier 46 includes pMOS transistors PT11 to PT18, nMOS transistors NT11 to NT16, and an OR gate circuit 43.

[0095] The following describes Fig.10 The circuit connections of sense amplifier 46 are shown.

[0096] The power supply voltage VDD is supplied to the source of the pMOS transistor PT11. The drain of the pMOS transistor PT11 is connected to the drain and gate of the nMOS transistor NT11. The source of the nMOS transistor NT11 is connected to the reference voltage terminal VSS.

[0097] The source of the pMOS transistors PT12 and PT13 is supplied with a power supply voltage. The drain of the pMOS transistor PT12 is connected to the drain of the nMOS transistor NT12, the drain of the pMOS transistor PT13, the gates of the pMOS transistor PT14 and the nMOS transistor NT13. The source of the nMOS transistor NT12 is connected to the reference voltage terminal VSS.

[0098] The power supply voltage VDD is supplied to the source of the pMOS transistor PT14. The drain of the pMOS transistor PT14 is input to the drain of the nMOS transistor NT13 and the first input terminal of the OR circuit 43. The source of the nMOS transistor NT13 is connected to the reference voltage terminal VSS.

[0099] The power supply voltage VDD is supplied to the source of the pMOS transistor PT15. The drain of the pMOS transistor PT15 is connected to the drain and gate of the nMOS transistor NT14. The source of the nMOS transistor NT14 is connected to the reference voltage terminal VSS.

[0100] The power supply voltage VDD is supplied to the sources of the pMOS transistors PT16 and PT17. The drain of the pMOS transistor PT16 is connected to the drain of the nMOS transistor NT15, the drain of the pMOS transistor PT17, the gates of the pMOS transistor PT18 and the nMOS transistor NT16. The source of the nMOS transistor NT15 is connected to the reference voltage terminal VSS.

[0101] The power supply voltage VDD is supplied to the source of the pMOS transistor PT18. The drain of the pMOS transistor PT18 is input to the drain of the nMOS transistor NT16 and the second input terminal of the OR circuit 43. The source of the nMOS transistor NT16 is connected to the reference voltage terminal VSS.

[0102] The gates of the pMOS transistors PT11 and PT16 correspond to the first input terminal of the sense amplifier 46. The voltage VSAMP is input to the gates of the pMOS transistors PT11 and PT16. The gates of the pMOS transistors PT12 and PT15 correspond to the second input terminal of the sense amplifier 46. The state signal VEVAL is input to the gates of the pMOS transistors PT12 and PT15. The offset voltage VOFST is input to the gates of the pMOS transistors PT13 and PT17. Furthermore, the signal DOUT is output from the output terminal of the OR gate circuit 43.

[0103] In addition, the pMOS transistors PT13 and PT17 to which the offset voltage VOFST is input are provided to correct errors that occur when comparing the state signal due to the temperature characteristics of the elements and manufacturing variations. Specifically, the sense amplifier 46 outputs, for example, "L" when the difference between the state signal VEVAL and the voltage VSAMP is less than the threshold voltage, and outputs, for example, "H" when the difference is greater than the threshold voltage. The offset voltage VOFST sets the threshold voltage at this time.

[0104] Next, use Fig.11 An outline of the reading operation according to the first embodiment will be described. Fig.11 2 is a flowchart showing a reading operation. The reading operation is executed by the controller 70.

[0105] According to the magnetization direction of the magnetic region M1 at the read position RP, the resistance of the magnetoresistive element (e.g., MTJ element) 11 changes to a low resistance state or a high resistance state. The state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M1 is sampled to the capacitor C1 (step S1).

[0106] Next, the magnetic domain (or magnetic wall) is shifted to update the magnetic domain at the reading position RP. For example, as described above, the magnetic domain M2 is shifted to the reading position RP and the magnetic domain M3 is shifted to the position of the magnetic domain M2 (step S2).

[0107] Next, a state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M2 is obtained. Next, the state signal corresponding to the magnetic region M2 shifted to the reading position RP is compared with the state signal accumulated in the capacitor C1 (the state signal of the previous magnetic region M1), and the bit information stored between the magnetic region M1 and the magnetic region M2 is read based on the comparison result (step S3).

[0108] Next, it is determined whether the last bit information has been read (step S4). If the last bit information has not been read (No), the process returns to step S1 and the operations after step S1 are repeatedly performed. On the other hand, if the last bit information has been read (Yes), the reading operation is terminated.

[0109] Next, use Fig.12 Describe the details of the read operation. Fig.12 2 is a timing chart of each signal in the read operation. In addition, the clamp signal VCLMP is omitted.

[0110] First, the shift signal SFTn, the read enable signal RE, and the equalization signal EQ are all set to be inactive. That is, the shift signal SFTn becomes "H", and the read enable signal RE and the equalization signal EQ become "L".

[0111] Here, before time T1, the read enable signal RE (e.g., "H") is activated. Thus, a state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M1 is obtained. Next, at time T1, the equalization signal EQ (e.g., "H") is activated. Thus, the equalization circuit 41 becomes conductive, and the voltage VSAMP becomes equal to the potential of the state signal VEVAL.

[0112] Next, at time T2, the equalization signal EQ is set to be inactive (for example, "L"), whereby the equalization circuit 41 is turned off and the voltage VSAMP is sampled to the capacitor C1.

[0113] Next, the read enable signal RE is set to invalid (e.g., "L"). Furthermore, at time T3, the shift signal SFTn (e.g., "L") is activated. As a result, the offset current flows through the magnetic storage line MML, and the magnetic domain in the magnetic storage line MML shifts toward the read position RP. As a result, the magnetic domain M2 shifts to the read position RP.

[0114] Next, after the shift signal SFTn is set to invalid (e.g., "H"), at time T4, the read enable signal RE (e.g., "H") is activated. As a result, the resistance of the magnetoresistive element 11 changes to a low resistance state or a high resistance state according to the magnetization direction of the magnetic region M2 shifted to the read position RP. As a result, a state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 is obtained. Then, the read amplifier 46 compares the state signal VEVAL with the voltage VSAMP, and outputs data D1 by the signal DOUT according to the comparison result. When the state signal VEVAL is approximately equal to the voltage VSAMP, that is, when the difference between the state signal VEVAL and the voltage VSAMP is below the threshold voltage, the read amplifier 46 outputs "L". On the other hand, when the state signal VEVAL is different from the voltage VSAMP, that is, when the difference between the state signal VEVAL and the voltage VSAMP is greater than the threshold voltage, the read amplifier 46 outputs "H".

[0115] Thereafter, at times T5 to T8 and times T9 to T12, the same actions as those at times T1 to T4 are performed, the state signal VEVAL is compared with the voltage VSAMP, and data D2 and D3 are outputted respectively by the signal DOUT according to the comparison results.

[0116] [1-3] Effects of the First Embodiment

[0117] According to the first embodiment, it is possible to provide a magnetic storage device capable of performing a stable reading operation.

[0118] The effects of the first embodiment are described in detail below. The magnetic storage device of the first embodiment includes a magnetic storage wire MML, a magnetoresistive element 11, and a read circuit 40. The magnetic storage wire MML is a linear magnetic body, and has a plurality of magnetic regions including adjacent first magnetic regions and second magnetic regions along the direction in which the magnetic body extends. The magnetization directions of the plurality of magnetic regions are variable. The magnetoresistive element 11 has either a first resistor corresponding to the magnetization direction of the first magnetic region or a second resistor corresponding to the magnetization direction of the second magnetic region. The read circuit 40 reads the first resistor and the second resistor of the magnetoresistive element 11, and compares the first resistor with the second resistor. The read circuit 40 outputs the first data when the first resistor and the second resistor are unchanged, and outputs the second data when the first resistor and the second resistor are different (or have changed).

[0119] In the first embodiment, it is detected whether the resistance states corresponding to the first magnetic area and the second magnetic area adjacent to the same magnetic storage fine line MML remain unchanged or different. The data stored in the two adjacent magnetic areas is determined based on whether the resistance states corresponding to the two adjacent magnetic areas remain unchanged or have changed, rather than determining the data stored in each magnetic area based on the resistance state corresponding to each magnetic area. In this way, according to the first embodiment, since it is detected whether the resistance state has changed, a stable reading operation can be performed to resist the magnetization unevenness of the magnetic areas of the magnetic storage fine line MML.

[0120] [2] Second Embodiment

[0121] In the second embodiment, another reading circuit is used to read data from a resistor corresponding to the magnetization direction of a magnetic domain. The following mainly describes the differences from the first embodiment.

[0122] [2-1] Reading action

[0123] The reading operation of the magnetic storage device 1 according to the second embodiment will be described. First, the reading circuit 40 used in the reading operation will be described.

[0124] Fig.13 4 is a circuit diagram showing the configuration of a reading circuit according to Embodiment 2. The reading circuit 40 includes capacitors C11 and C12, a sense amplifier 47, pass transistors 44 and 45, a multiplexer 42, PMOS transistors PT2 and PT21, and an nMOS transistor NT2.

[0125] The following describes Fig.13 The circuit connection of the reading circuit shown is shown in FIG. 1. The first input terminal of the sense amplifier 47 is connected to the first electrode of the capacitor C11 and the first terminal of the pass transistor 44. The second input terminal of the sense amplifier 47 is connected to the first electrode of the capacitor C12 and the first terminal of the pass transistor 45.

[0126] The drain of the pMOS transistor PT21 is connected to the second terminals of the pass transistors 44 and 45. The drain of the pMOS transistor PT21 is also connected to the drain of the pMOS transistor PT2 and the input terminal of the multiplexer 42 via the nMOS transistor NT2.

[0127] The power supply voltage VDD is supplied to the second electrodes of the capacitors C11 and C12 and the source of the pMOS transistor PT21. Furthermore, the offset voltage VS is supplied to the source of the pMOS transistor PT2.

[0128] The shift signal SFTn is input to the gate of the pMOS transistor PT2. The sampling signals SMP1 and SMP1n are respectively input to the gate of the pass transistor 44. The sampling signals SMP2 and SMP2n are respectively input to the gate of the pass transistor 45. The read enable signal RE is input to the gate of the nMOS transistor NT2. The load signal VLOAD is input to the gate of the pMOS transistor PT21. The voltage of the first input terminal of the sense amplifier 47 is recorded as VSMP1, and the voltage of the second input terminal of the sense amplifier 47 is recorded as VSMP2. Furthermore, the output signal DOUT is output from the sense amplifier 47.

[0129] In the reading circuit 40, the circuit preceding the sense amplifier 47 functions as a preamplifier for reading the resistance state of the magnetoresistive element 11. The preamplifier causes the capacitors C11 and C12 to accumulate a state signal corresponding to the resistance state of the magnetoresistive element 11.

[0130] In addition, the pMOS transistor PT21 to which the load signal VLOAD is input performs constant current control to make the read current constant. Therefore, it is possible to prevent excess current from flowing through the selection element 12, the magnetoresistive element 11, and the magnetic storage fine wire MML. Fig.13 In the circuit shown, the following Fig.14 and Fig.15 Compared with the circuit shown in the figure, the nMOS transistor NT1 can be reduced, so the circuit area can be reduced.

[0131] Fig.14 is a circuit diagram showing the configuration of a read circuit of a variation. Fig.13 In the circuit shown in FIG. 1 , an nMOS transistor NT1 is connected between the drain of the pMOS transistor PT21 and the drain of the nMOS transistor NT2. A clamp signal VCLMP is input to the gate of the nMOS transistor NT1. Fig.13 The structure shown is the same.

[0132] The pMOS transistor PT21 to which the load signal VLOAD is input performs constant current control to make the read current constant. The nMOS transistor NT1 to which the clamp signal VCLMP is input performs constant voltage control. Therefore, it is possible to prevent excess current and voltage from being applied to the selection element 12, the magnetoresistive element 11, and the magnetic memory fine line MML.

[0133] Fig.15 is a circuit diagram showing the configuration of a reading circuit of another variation. Fig.14 In the circuit shown in FIG. 1 , a load signal VLOAD is input to the gate of the pMOS transistor PT21, and the gate of the pMOS transistor PT21 is connected to the drain thereof. Fig.14 The structure shown is the same.

[0134] The nMOS transistor NT1 to which the clamp signal VCLMP is input performs constant voltage control, thereby preventing an excessive voltage from being applied to the selection element 12, the magnetoresistive element 11, and the magnetic memory thin line MML.

[0135] Fig.16 2 is a circuit diagram showing the structure of the sense amplifier 47 of the read circuit 40 according to the second embodiment. Fig.10 In the circuit shown, voltage VSMP1 is input to the gate of pMOS transistor PT11, and voltage VSMP2 is input to the gate of pMOS transistor PT12. Furthermore, voltage VSMP2 is input to the gate of pMOS transistor PT15, and voltage VSMP1 is input to the gate of pMOS transistor PT16. Fig.10 The structure shown is the same.

[0136] Next, use Fig.17 An outline of the reading operation according to the second embodiment will be described. Fig.17 2 is a flowchart showing a reading operation. The reading operation is executed by the controller 70.

[0137] The resistance of the magnetoresistive element 11 changes to a low resistance state or a high resistance state according to the magnetization direction of the magnetic region M1 at the read position RP. The state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M1 is sampled to the capacitor C11 (step S11).

[0138] Next, the magnetic domain (or magnetic wall) is shifted to update the magnetic domain at the reading position RP. For example, as described above, the magnetic domain M2 is shifted to the reading position RP and the magnetic domain M3 is shifted to the position of the magnetic domain M2 (step S12).

[0139] Thus, the resistance of the magnetoresistive element 11 changes to low resistance or high resistance according to the magnetization direction of the magnetic region M2 shifted to the reading position RP. The state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 changed according to the magnetization direction of the magnetic region M2 is sampled to the capacitor C12 (step S13).

[0140] Next, the state signal accumulated in capacitor C11 (the state signal of the previous magnetic zone M1) is compared with the state signal accumulated in capacitor C12 (the state signal of the current magnetic zone M2), and the bit information stored between magnetic zone M1 and magnetic zone M2 is read based on the comparison result (step S14).

[0141] Next, it is determined whether the last bit information has been read (step S15). If the last bit information has not been read (No), the process proceeds to step S16 and the processes after step S16 are executed. On the other hand, if the last bit information has been read (Yes), the reading operation is terminated.

[0142] In step S16, the magnetic zone is shifted to update the magnetic zone at the reading position RP. For example, after step S12, the magnetic zone M3 is shifted to the reading position RP and the magnetic zone M4 is shifted to the position of the magnetic zone M3 (step S16).

[0143] Thus, the resistance of the magnetoresistive element 11 changes to low resistance or high resistance according to the magnetization direction of the magnetic region M3 shifted to the read position RP. The state signal VEVAL corresponding to the resistance of the MTJ element 11 changed according to the magnetization direction of the magnetic region M3 is sampled to the capacitor C11 (step S17).

[0144] Next, the state signal accumulated in capacitor C12 (the state signal of the previous magnetic zone M2) is compared with the state signal accumulated in capacitor C11 (the state signal of the current magnetic zone M3), and the bit information stored between magnetic zone M2 and magnetic zone M3 is read based on the comparison result (step S18).

[0145] Next, it is determined whether the last bit information has been read (step S19). If the last bit information has not been read (No), the process returns to step S12 and the operations after step S12 are repeatedly performed. On the other hand, if the last bit information has been read (Yes), the reading operation is terminated.

[0146] Next, use Fig.18 Narrative Figure 13 to Figure 15 Details of the read action of the circuit shown. Fig.18 2 is a timing chart of each signal in the read operation. In addition, the clamp signal VCLMP and the load signal VLOAD are omitted.

[0147] First, the shift signal SFTn, the read enable signal RE, the signals SMP1, SMP1n, and the signals SMP2, SMP2n are all set to be inactive. That is, the shift signal SFTn becomes "H", and the read enable signal RE, the signals SMP1, SMP1n, and the signals SMP2, SMP2n become "L".

[0148] Here, at time T21, the shift signal SFTn (e.g., "L") is activated. As a result, an offset current flows through the magnetic storage line MML, and the magnetic region in the magnetic storage line MML shifts toward the reading position RP. At this time, the magnetic region M1 shifts to the reading position RP. As a result, the resistance of the MTJ element 11 changes to a low resistance or a high resistance according to the magnetization direction of the magnetic region M1 shifted to the reading position RP.

[0149] Next, after the shift signal SFTn is set to inactive (eg, "H"), the read enable signal RE is activated (eg, "H") at time T22. Thus, at the node SN, a state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M1 is obtained.

[0150] Next, at time T23, the signal SMP1 is activated (e.g., "H"). As a result, the pass transistor 44 is turned on, and the voltage VSMP1 is equal to the potential of the state signal VEVAL. Next, at time T24, the signal SMP1 is set to be invalid (e.g., "L"). As a result, the pass transistor 44 is turned off, and the voltage VSMP1 is sampled to the capacitor C11.

[0151] Next, the read enable signal RE is set to invalid (e.g., "L"). Furthermore, at time T25, the shift signal SFTn (e.g., "L") is activated. As a result, the offset current flows through the magnetic storage line MML, and the magnetic region in the magnetic storage line MML shifts toward the reading position RP. At this time, the magnetic region M2 shifts to the reading position RP. As a result, the resistance of the magnetoresistive effect element 11 changes to a low resistance or a high resistance according to the magnetization direction of the magnetic region M2 shifted to the reading position RP.

[0152] Next, after the shift signal SFTn is set to inactive (eg, "H"), the read enable signal RE is activated (eg, "H") at time T26. Thus, at the node SN, a state signal VEVAL corresponding to the resistance of the magnetoresistive element 11 that changes according to the magnetization direction of the magnetic region M2 is obtained.

[0153] Next, at time T27, the signal SMP2 is activated (e.g., "H"). As a result, the pass transistor 45 is turned on, and the voltage VSMP2 is equal to the potential of the state signal VEVAL. Next, at time T28, the signal SMP2 is set to be invalid (e.g., "L"). As a result, the pass transistor 45 is turned off, and the voltage VSMP2 is sampled to the capacitor C12. Thereafter, the read enable signal RE is set to be invalid (e.g., "L").

[0154] Next, the sense amplifier 47 compares the voltage VSMP1 with the voltage VSMP2, and outputs data D1 as a signal DOUT according to the comparison result. When the voltage VSMP1 is substantially equal to the voltage VSMP2, that is, when the difference between the voltage VSMP1 and the voltage VSMP2 is less than the threshold value, the sense amplifier 47 outputs "L". On the other hand, when the voltage VSMP1 is different from the voltage VSMP2, that is, when the difference between the voltage VSMP1 and the voltage VSMP2 is greater than the threshold value, the sense amplifier 47 outputs "H".

[0155] Thereafter, at time T29 to T37, the same operation as that at time T21 to T29 is performed, the voltage VSMP1 is compared with the voltage VSMP2, and data D2 and D3 are outputted respectively by the signal DOUT according to the comparison result.

[0156] The other structures and operations are the same as those of the first embodiment.

[0157] [2-2] Effects of the Second Embodiment

[0158] According to the second embodiment, similarly to the first embodiment, a magnetic storage device capable of performing a stable reading operation can be provided.

[0159] Furthermore, in the second embodiment, the signals of the resistance states corresponding to the two adjacent magnetic domains in the magnetic memory fine line MML are respectively stored in the capacitors C11 and C12. Furthermore, in the reading of the resistance states corresponding to the magnetic domains following the two magnetic domains, the signals are alternately stored in the capacitors C11 and C12. Thus, by comparing the signals stored in the capacitors C11 and C12, the data stored in the continuous magnetic domains can be determined. Thus, the data reading speed can be improved.

[0160] [3] Other changes, etc.

[0161] Fig.19 This is a diagram showing a memory chip (semiconductor device) on which a plurality of magnetic storage devices 1 according to the first and second embodiments are arranged. Fig. 20 This diagram shows an SSD equipped with a memory chip.

[0162] like Fig.19 As shown, a plurality of magnetic storage devices 1 of the first and second embodiments are arranged in an array on a memory chip 100. A peripheral circuit and a pad 2 are provided on the memory chip 100. The peripheral circuit includes a circuit for controlling the writing and reading operations of the magnetic storage device 1, and a power supply circuit for generating various power supplies to the magnetic storage device 1. The pad includes an electrode for connecting to the outside.

[0163] In addition, if Fig. 20 As shown, for example, a plurality of memory chips 100 are stacked to form a multi-chip 200. Furthermore, the multi-chip 200 is mounted on an SSD (Solid state drive) 400 or the like together with a memory controller 300 for controlling the multi-chip 200.

[0164] In this specification, the term “electrical connection” includes physically connecting a plurality of conductors or elements so that current flows between the plurality of conductors or elements.

[0165] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0166] [Explanation of Symbols]

[0167] 1 Magnetic storage device

[0168] 10 Memory Cell Array

[0169] 11 Magnetoresistance effect element

[0170] 11N non-magnetic layer

[0171] 11R Magnetic layer (reference layer)

[0172] 11S magnetic layer (storage layer)

[0173] 12 Select components

[0174] 20 Word Line (WL) Decoder

[0175] 30-bit line (BL) decoder

[0176] 40 Reading Circuit

[0177] 41 Equalization circuit

[0178] 44, 45 channel transistor

[0179] 46, 47 Sense amplifier

[0180] 50 Shift drive

[0181] 60 Field Line (FL) Driver

[0182] 70 Controller

[0183] 100 Memory Chip

[0184] More than 200 chips

[0185] 300 Storage Controller

[0186] 400 SSD

[0187] M1, M2, M3, M4, M5 magnetic zones

[0188] MML Magnetic Memory Thin Line

Claims

1. A magnetic storage device comprising: A magnetic wire, which is a linear magnetic body and has a first magnetic region and a second magnetic region with variable magnetization directions; a magnetoresistive element having either a first resistor corresponding to the magnetization direction of the first magnetic region or a second resistor corresponding to the magnetization direction of the second magnetic region; and a reading circuit that compares the first resistance of the magnetoresistive element with the second resistance of the magnetoresistive element; and The reading circuit outputs first data when the first resistor and the second resistor are in the same resistance state, and outputs second data when the first resistor and the second resistor are in different resistance states.

2. The magnetic storage device according to claim 1, wherein The reading circuit outputs the first data when a difference between the first resistor and the second resistor is less than a first value, and outputs the second data when the difference between the first resistor and the second resistor is greater than the first value.

3. The magnetic storage device according to claim 1, wherein The magnetoresistive element has an MTJ (magnetic tunnel junction) structure formed by a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer, and The second magnetic layer has the same magnetization direction as that of the first magnetic region due to magnetic induction from the first magnetic region of the magnetic wire.

4. The magnetic storage device according to claim 3, wherein The magnetoresistive element has a low resistance state when the magnetization direction of the second magnetic layer is parallel to the magnetization direction of the first magnetic layer. When the magnetization direction of the second magnetic layer is antiparallel to the magnetization direction of the first magnetic layer, the second magnetic layer has a high resistance state higher than a low resistance state.

5. The magnetic storage device according to claim 1, wherein The magnetoresistive element comprises a first magnetic layer and a non-magnetic layer. The magnetoresistive element has an MTJ (magnetic tunnel junction) structure formed by the first magnetic region of the magnetic wire, the first magnetic layer, and the nonmagnetic layer between the first magnetic region and the first magnetic layer.

6. The magnetic storage device according to claim 5, wherein The magnetoresistive element has a low resistance state when the magnetization direction of the first magnetic region is parallel to the magnetization direction of the first magnetic layer. When the magnetization direction of the first magnetic region is antiparallel to the magnetization direction of the first magnetic layer, the first magnetic region has a high resistance state higher than a low resistance state.

7. The magnetic storage device according to claim 1, wherein The reading circuit includes a shift driver for shifting the first magnetic region and the second magnetic region of the magnetic wire. The first magnetic region of the magnetic wire is arranged at a first position within the magnetic wire, After the read circuit reads the first resistor corresponding to the magnetization direction of the first magnetic region, the shift driver shifts the second magnetic region to the first position.

8. The magnetic storage device according to claim 1, wherein The read circuit includes: a first circuit for reading the first resistance and the second resistance of the magnetoresistive element; and a sense amplifier for comparing the first resistance read by the first circuit with the second resistance; and The first circuit includes: a second circuit that supplies or stops supplying a read current to the magnetoresistive element; a capacitor that accumulates a signal corresponding to either the first resistor or the second resistor; and a third circuit that sets a timing for accumulating the signal in the capacitor.

9. The magnetic storage device according to claim 1, wherein The read circuit includes: a first circuit for reading the first resistance and the second resistance of the magnetoresistive element; and a sense amplifier for comparing the first resistance read by the first circuit with the second resistance; and The first circuit includes: a second circuit that supplies or stops supplying a read current to the magnetoresistive element; a first capacitor that accumulates a signal corresponding to the first resistor; a second capacitor that accumulates a signal corresponding to the second resistor; a third circuit that sets a timing for accumulating the signal corresponding to the first resistor in the first capacitor; and a fourth circuit that sets a timing for accumulating the signal corresponding to the second resistor in the second capacitor.

10. The magnetic storage device according to claim 2, wherein The read circuit includes: a first circuit for reading the first resistance and the second resistance of the magnetoresistive element; and a sense amplifier for comparing the first resistance read by the first circuit with the second resistance; and The sense amplifier includes a first circuit for setting the first value.

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