Display device

Abstract

A display device is provided. The display device includes: a substrate; a gate line disposed on the substrate to transmit a gate signal; a first reference voltage line spaced apart from the gate line to transmit a reference voltage; a second reference voltage line disposed on the gate line and the first reference voltage line and electrically connected to the first reference voltage line; an insulating layer disposed on the second reference voltage line; and a pixel electrode layer disposed on the insulating layer, wherein the pixel electrode layer includes a first pixel electrode, the first pixel electrode having a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being disposed on a first side relative to the gate line, the second sub-pixel electrode being disposed on a second side relative to the gate line opposite the first side, and the second reference voltage line may overlap with the first pixel electrode and may intersect the first pixel electrode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0111774, filed on September 18, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a display device. Background Art

[0003] A display device such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, etc. generally includes a plurality of pixels, which are units for displaying an image.

[0004] The display panel of a liquid crystal display (LCD) includes a liquid crystal layer containing liquid crystal molecules; electric field-generating electrodes for controlling the orientation of the liquid crystal molecules in the liquid crystal layer; a plurality of signal lines for applying a voltage to at least some of the electric field-generating electrodes; and a plurality of switching elements connected to the plurality of signal lines. When a voltage is applied to the electric field-generating electrodes, an electric field is generated in the liquid crystal layer, thereby reorienting the liquid crystal molecules. Consequently, an image can be displayed by adjusting the amount of transmitted light. The display panel may include at least one polarizer to control the amount of transmitted light.

[0005] The electric field generating electrodes included in the liquid crystal display include pixel electrodes for receiving a data voltage and common electrodes for receiving a common voltage. The pixel electrodes may receive the data voltage through switching elements, which may be formed of, for example, thin film transistors.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the Invention

[0007] A device constructed according to an exemplary embodiment of the invention provides a display device that can have increased aperture ratio and transmittance.

[0008] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0009] An exemplary embodiment of the present invention provides a display device, comprising: a substrate; a gate line disposed on the substrate and configured to transmit a gate signal; a first reference voltage line spaced apart from the gate line and configured to transmit a reference voltage; a second reference voltage line disposed on the gate line and the first reference voltage line and electrically connected to the first reference voltage line; an insulating layer disposed on the second reference voltage line; and a pixel electrode layer disposed on the insulating layer, wherein the pixel electrode layer may include a first pixel electrode, the first pixel electrode including a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode being disposed at a first side relative to the gate line in a plan view, the second sub-pixel electrode being disposed at a second side relative to the gate line opposite to the first side in a plan view, and the second reference voltage line may overlap with the first pixel electrode and may cross the first pixel electrode.

[0010] Another exemplary embodiment of the present invention provides a display device, comprising: a substrate; a gate line disposed on the substrate and configured to transmit a gate signal; a plurality of data lines disposed on the substrate, configured to transmit a data voltage, and intersecting the gate lines; an insulating layer disposed on the plurality of data lines; and a plurality of color filters disposed on the insulating layer, wherein one of the plurality of color filters may have an opening that overlaps with three or more contact holes arranged in a row and disposed in the insulating layer.

[0011] Another exemplary embodiment of the present invention provides a display device, comprising: a gate line configured to transmit a gate signal; a first reference voltage line spaced apart from the gate line and configured to transmit a reference voltage; a plurality of data lines crossing the gate line and the first reference voltage line; a first transistor electrically connected to the gate line and the data line; a second transistor electrically connected to the gate line and the data line; a third transistor electrically connected to the second transistor; and a second reference voltage line configured to transmit a reference voltage and disposed in a different conductive layer from the first reference voltage line, wherein a drain electrode included in the third transistor may be electrically connected to the first reference voltage line, the second reference voltage line may include a drain electrode of the third transistor, and the second reference voltage line may cross the first reference voltage line.

[0012] According to the embodiments of the present invention, the aperture ratio and transmittance of a display device can be increased.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. In the drawings:

[0015] Figure 1 FIG. 1 shows an equivalent circuit diagram of one pixel of a display device according to an embodiment,

[0016] Figure 2 A layout diagram showing a portion of one pixel of a display device according to an embodiment is shown,

[0017] Figure 3 Shown Figure 2 A sectional view of the display device shown in FIG. 1 taken along line IIIa-IIIb,

[0018] Figure 4 Shown Figure 2 A sectional view of the display device shown in FIG. 1 taken along line IVa-IVb,

[0019] Figure 5 shows a plan layout diagram of a display area of ​​a display device according to an embodiment,

[0020] Figure 6 A layout diagram showing a portion of one pixel of a display device according to an embodiment is shown,

[0021] Figure 7 A layout diagram showing three pixels of a display device according to an embodiment, and

[0022] Figure 8 A layout diagram showing three color filters of three pixels of a display device according to an embodiment is shown. DETAILED DESCRIPTION

[0023] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of devices or methods that employ one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making the various exemplary embodiments unnecessarily vague. In addition, the various exemplary embodiments can be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment.

[0024] Unless otherwise indicated, the exemplary embodiments shown will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0025] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or need for the specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0026] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bound to" another element or layer, the element or layer may be directly on, directly connected to or directly bound to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bound to" another element or layer, there are no intermediate elements or intermediate layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis and the z-axis) and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be named a second element without departing from the teachings of the disclosure.

[0028] For descriptive purposes, spatially relative terms such as "below," "beneath," "beneath," "below," "above," "upper," "on," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another(s) element(s) as shown in the accompanying drawings. In addition to including the orientations depicted in the accompanying drawings, the spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is turned over, elements or features described as "below" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), with the spatially relative descriptors used herein interpreted accordingly.

[0029] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be restrictions. As used herein, the "one (kind / person)" and "said (the)" in the singular are also intended to include plural forms, unless the context clearly indicates otherwise. In addition, when using the terms "comprising" and / or "including" and their variations in this manual, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as degree terms, and are so used to explain the measured values, calculated values ​​and / or the inherent deviation of the values ​​that will be recognized by those of ordinary skill in the art.

[0030] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic representations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as being limited to the specific illustrated shapes of the regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and, as such, are not necessarily intended to be limiting.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0032] First, refer to Figure 1 A display device according to an exemplary embodiment will be described.

[0033] Figure 1 An equivalent circuit diagram of one pixel PX of a display device according to an exemplary embodiment is shown.

[0034] The display device according to the exemplary embodiment includes a plurality of pixels PX serving as a unit for displaying an image. Figure 1 , one pixel PX may include a first subpixel PXaa and a second subpixel PXbb. The first subpixel PXaa may include a first transistor Qa connected to one data line 171 and one gate line 121, and a first liquid crystal capacitor Clca connected to the first transistor Qa. The second subpixel PXbb may include a second transistor Qb and a third transistor Qc connected to one data line 171 and one gate line 121, and a second liquid crystal capacitor Clcb connected to the second transistor Qb and the third transistor Qc.

[0035] The first transistor Qa includes a gate electrode connected to the gate line 121, a source electrode connected to the data line 171, and a drain electrode connected to the first liquid crystal capacitor Clca. The first transistor Qa can be controlled according to a gate signal transmitted from the gate line 121 to transmit a data voltage transmitted from the data line 171 to the first liquid crystal capacitor Clca.

[0036] Similar to the first transistor Qa, the second transistor Qb includes a gate electrode connected to the gate line 121, a source electrode connected to the data line 171, and a drain electrode connected to one side of the second liquid crystal capacitor Clcb and the source electrode of the third transistor Qc. The second transistor Qb can be controlled according to a gate signal transmitted from the gate line 121 to transmit a data voltage transmitted from the data line 171 to the second liquid crystal capacitor Clcb. The other side of the second liquid crystal capacitor Clcb can be connected to a common voltage line (not shown) that transmits a common voltage Vcom.

[0037] Similar to the first transistor Qa, the third transistor Qc includes a gate electrode connected to the gate line 121, a source electrode connected to the drain electrode of the second transistor Qb, and a reference voltage line 131 (see FIG. 1 ) connected to the transmission reference voltage Vref. Figure 2 ). The third transistor Qc is controlled according to a gate signal transmitted from the gate line 121. When the third transistor Qc and the second transistor Qb are turned on, the data voltage transmitted from the data line 171 is divided by the second transistor Qb and the third transistor Qc and then transmitted to the second liquid crystal capacitor Clcb. The reference voltage Vref can be a predetermined constant voltage.

[0038] The first subpixel PXaa and the second subpixel PXbb can display images according to different gamma curves with respect to one image signal, or display images according to the same gamma curve. Here, the gamma curve refers to a curve showing changes in brightness or transmittance with respect to grayscale of an image signal.

[0039] The gamma curve followed by the second subpixel PXbb can be adjusted by controlling the resistance ratio of the third transistor Qc and the second transistor Qb, the reference voltage Vref, etc. The charging voltage of the second liquid crystal capacitor Clcb can be adjusted by controlling the third transistor Qc and the reference voltage Vref to differentiate the brightness of the two subpixels PXaa and PXbb. The charging voltages of the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb can be appropriately adjusted to improve the side visibility of the display device.

[0040] Will refer to Figures 2 to 6 and Figure 1 A detailed structure of a display device according to an exemplary embodiment will be described together.

[0041] Figure 2 1 is a layout diagram showing a portion of one pixel PX of a display device according to an exemplary embodiment, Figure 3 Shown Figure 2 A sectional view of the display device shown in FIG. 1 taken along line IIIa-IIIb, Figure 4 Shown Figure 2 A sectional view of the display device shown in FIG. 1 taken along line IVa-IVb, Figure 5 shows a plan layout diagram of a display area of ​​a display device according to an exemplary embodiment, Figure 6 A layout diagram illustrating a portion of one pixel PX of a display device according to an exemplary embodiment is shown.

[0042] A display device according to an exemplary embodiment, which is a liquid crystal display, may include a first display panel 100 , a second display panel 200 , and a liquid crystal layer 3 disposed between the two display panels 100 and 200 .

[0043] In the first display panel 100 , a gate conductive layer including a plurality of gate lines 121 and a reference voltage line 131 is disposed on a substrate 110 . Here, the substrate 110 may include an insulating substrate.

[0044] The gate line 121 may transmit a gate signal and may extend substantially along a first direction DR1. The gate line 121 may include a first gate electrode 124a, a second gate electrode 124b, and a third gate electrode 124c. The first gate electrode 124a, the second gate electrode 124b, and the third gate electrode 124c are connected to each other and may be included in one expansion portion 124 of the gate line 121.

[0045] The expansion portion 124 may have a shape protruding or extending in the second direction DR2 from a portion of the gate line 121 extending parallel to the first direction DR1 .

[0046] The second gate electrode 124 b may be disposed between the first gate electrode 124 a and the third gate electrode 124 c .

[0047] The reference voltage line 131 may transmit a reference voltage Vref and may be spaced apart from the gate line 121 to extend substantially parallel to the gate line 121. The reference voltage line 131 may cross a plurality of data lines 171a and 171b described later and may extend across a plurality of pixels PX together with the gate line 121.

[0048] The reference voltage line 131 may include an extension 132. The extension 132 may protrude or extend from a portion of the reference voltage line 131 extending parallel to the first direction DR1 in a direction opposite to the second direction DR2. That is, the direction in which the extension 124 protrudes from the gate line 121 and the direction in which the extension 132 protrudes from the reference voltage line 131 may be opposite to each other. In other words, the extension 124 of the gate line 121 and the extension 132 of the reference voltage line 131 are disposed between the portion of the gate line 121 extending in the first direction DR1 and the portion of the reference voltage line 131 extending in the first direction DR1, and the extension 124 and the extension 132 may face each other.

[0049] The gate insulating layer 140 may be provided on the gate conductive layer. The gate insulating layer 140 may include silicon nitride (SiN x ), silicon oxide (SiO x ), insulating materials such as silicon oxynitride.

[0050] A semiconductor layer 151 including a first semiconductor 154a, a second semiconductor 154b, and a third semiconductor 154c is provided on the gate insulating layer 140. The first semiconductor 154a is provided on the first gate electrode 124a to overlap with the first gate electrode 124a, the second semiconductor 154b is provided on the second gate electrode 124b to overlap with the second gate electrode 124b, and the third semiconductor 154c is provided on the third gate electrode 124c to overlap with the third gate electrode 124c. The first semiconductor 154a, the second semiconductor 154b, and the third semiconductor 154c may be connected to each other, and the second semiconductor 154b may be provided between the first semiconductor 154a and the third semiconductor 154c.

[0051] The semiconductor layer 151 may include amorphous silicon, polysilicon, or metal oxide.

[0052] An ohmic contact layer 161 including a plurality of ohmic contact members 163 a and 165 a may be disposed on the semiconductor layer 151 .

[0053] A data conductive layer including a plurality of data lines 171 a and 171 b , a first source electrode 173 a , a second source electrode 173 b , a third source electrode 173 c , a first drain electrode 175 a , a second drain electrode 175 b , and a third drain electrode 175 c is disposed on the ohmic contact layer 161 .

[0054] The first source electrode 173a and the second source electrode 173b are connected to each other, and the first source electrode 173a is connected to one data line 171a. The first drain electrode 175a may include an end facing the first source electrode 173a and surrounded by the first source electrode 173a, and an expansion portion 177a provided on the other side of the first drain electrode 175a. The second drain electrode 175b may include an end facing the second source electrode 173b and extending parallel to the second source electrode 173b, and an expansion portion 177b provided on the other side of the second drain electrode 175b. At least a portion of the second drain electrode 175b may be the third source electrode 173c. The third drain electrode 175c may include one end facing the third source electrode 173c and another end 176. The third drain electrode 175c extends from the one end facing the third source electrode 173c in the second direction DR2, bends to extend in the first direction DR1, and then bends to extend in the second direction DR2, thereby forming the other end 176.

[0055] The data conductive layer may further include an auxiliary electrode 174c disposed between the third source electrode 173c and the third drain electrode 175c. The auxiliary electrode 174c having an island shape overlaps the third semiconductor 154c and the third gate electrode 124c.

[0056] The expansion 177 a of the first drain electrode 175 a , the expansion 177 b of the second drain electrode 175 b , and the end 176 of the third drain electrode 175 c are disposed at one side based on the gate line 121 and may be arranged substantially in the first direction DR1 .

[0057] For example, Figure 2 As shown in , the expansion portion 177a of the first drain electrode 175a, the expansion portion 177b of the second drain electrode 175b, and the end portion 176 of the third drain electrode 175c can be disposed on the upper side of the gate line 121 and can be arranged along the first direction DR1 from the left in the order of the expansion portion 177a, the expansion portion 177b, and the end portion 176 of the third drain electrode 175c.

[0058] At least a portion of each of the expansion 177 a , the expansion 177 b , and the end portion 176 of the third drain electrode 175 c may overlap the expansion 132 of the reference voltage line 131 .

[0059] Data lines 171a and 171b extend substantially in the second direction DR2 and may each transmit a data voltage. Data line 171a may include a first protrusion 172a that protrudes in the first direction DR1, and data line 171b may include a second protrusion 172b that protrudes in a direction opposite to the first direction DR1. In other words, data line 171a and data line 171b may include a first protrusion 172a and a second protrusion 172b that protrude in opposite directions, respectively. When viewed based on a pixel PX, data line 171a positioned on the left may include a first protrusion 172a that protrudes toward data line 171b adjacent to the right, and data line 171b may include a second protrusion 172b that protrudes toward data line 171a adjacent to the left.

[0060] like Figure 2 As shown in FIG, the first protrusion 172a and the second protrusion 172b are not arranged in the first direction DR1 but may be slightly offset. Alternatively, the first protrusion 172a and the second protrusion 172b may be arranged and disposed to correspond to each other in the first direction DR1.

[0061] The first source electrode 173 a may be connected to the data line 171 a through the first protrusion 172 a .

[0062] The gate conductive layer and the data conductive layer may include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof.

[0063] The planar shapes of the data conductive layer and the ohmic contact layer 161 may be substantially the same. In areas other than the area between the first source electrode 173a and the first drain electrode 175a, the area between the second source electrode 173b and the second drain electrode 175b, the area between the third source electrode 173c and the auxiliary electrode 174c, and the area between the auxiliary electrode 174c and the third drain electrode 175c, the planar shapes of the data conductive layer and the semiconductor layer 151 may be substantially the same. Figure 2 As shown in FIG, the planar area of ​​the semiconductor layer 151 may be slightly larger than the planar area of ​​the data conductive layer.

[0064] The first gate electrode 124a, the first source electrode 173a and the first drain electrode 175a together with the first semiconductor 154a form a first transistor Qa; the second gate electrode 124b, the second source electrode 173b and the second drain electrode 175b together with the second semiconductor 154b form a second transistor Qb; the third gate electrode 124c, the third source electrode 173c, the auxiliary electrode 174c and the third drain electrode 175c together with the third semiconductor 154c form a third transistor Qc.

[0065] The channels of the first transistor Qa, the second transistor Qb, and the third transistor Qc are respectively formed in a first semiconductor 154a disposed between the first source electrode 173a and the first drain electrode 175a, a second semiconductor 154b disposed between the second source electrode 173b and the second drain electrode 175b, and a third semiconductor 154c disposed between the third source electrode 173c and the third drain electrode 175c. An auxiliary electrode 174c may be formed to extend the channel of the third transistor Qc, but the auxiliary electrode 174c may be omitted.

[0066] The first transistor Qa, the second transistor Qb, and the third transistor Qc may overlap the expansion portion 124 of the gate line 121 and be arranged along the first direction DR1. Figure 2 As shown in FIG, the first transistor Qa, the second transistor Qb, and the third transistor Qc may be sequentially arranged along the first direction DR1.

[0067] The first insulating layer 180a is disposed on the data conductive layer and the exposed portions of the semiconductors 154a, 154b, and 154c. The first insulating layer 180a may include an organic insulating material or an inorganic insulating material.

[0068] A color filter layer including a plurality of color filters 230, 230d, and 230e may be disposed on the first insulating layer 180a. The color filters 230, 230d, and 230e may display one of three primary colors, such as red, green, and blue, or one of four primary colors. A set of color filters displaying different primary colors may be repeatedly disposed along the first direction DR1.

[0069] At least two of the color filters 230, 230d, and 230e adjacent to the data lines 171a and 171b may overlap each other in a third direction DR3 perpendicular to the substrate 110. The overlapping color filters 230, 230d, and 230e may prevent light leakage near the data lines 171a and 171b disposed in adjacent pixels.

[0070] The second insulating layer 180b may be provided on the color filters 230, 230d, and 230e. The second insulating layer 180b may include an inorganic insulating material or an organic insulating material, and specifically, may have a substantially flat upper surface by including an organic insulating material. The second insulating layer 180b serves as an outer coating for the color filters 230, 230d, and 230e to prevent the color filters 230, 230d, and 230e from being exposed and to prevent impurities such as pigments from flowing into the liquid crystal layer 3.

[0071] The first insulating layer 180a and the second insulating layer 180b may have a contact hole 185a disposed on the expansion 177a of the first drain electrode 175a, a contact hole 185b disposed on the expansion 177b of the second drain electrode 175b, and a contact hole 188 disposed on the end portion 176 of the third drain electrode 175c and on a portion of the expansion 132 of the reference voltage line 131 adjacent to the end portion 176.

[0072] like Figure 2 As shown in FIG, contact holes 185a, 185b, and 188 may be disposed on the same side relative to gate line 121, eg, on an upper side relative to gate line 121. Contact holes 185a, 185b, and 188 may be sequentially arranged from the left along the first direction DR1.

[0073] In each pixel PX, since the distance between the three contact holes 185a, 185b, and 188 arranged substantially in a row along the first direction DR1 and the distance between the contact holes 185a and 188 adjacent to the data lines 171a and 171b and the data lines 171a and 171b are insufficient, when openings corresponding to the contact holes 185a, 185b, and 188 are formed in the color filters 230, 230d, and 230e, the color filters 230, 230d, and 230e remaining between the contact holes 185a, 185b, and 188 or the color filters 230, 230d, and 230e remaining between the data lines 171a and 171b and the contact holes 185a and 188 may be formed narrow. In this case, the color filters 230, 230d, and 230e remaining with insufficient thickness may fall off, resulting in display defects.

[0074] In the present embodiment, the color filters 230 , 230 d , and 230 e corresponding to at least three contact holes 185 a , 185 b , and 188 may be removed to form the opening 235 to prevent the above-mentioned problem.

[0075] In a plan view, the opening 235 may overlap with the light blocking member 220 described later. Specifically, the opening 235 may not overlap with the transistors Qa, Qb, and Qc (eg, Figure 2 ), or may be stacked with some of transistors Qa, Qb, and Qc.

[0076] Reference Figure 2 The opening 235 extends substantially in the first direction DR1 , and the opening 235 may cross the plurality of data lines 171 a and 171 b without being limited to one pixel PX to extend across the plurality of pixels PX in the first direction DR1 .

[0077] In a plan view, the contact holes 185a, 185b, and 188 overlap with the opening 235 of the color filter 230 and may be disposed in the opening 235. As described above, the color filter 230 may have an opening 235 that overlaps with three or more contact holes 185a, 185b, and 188 that are arranged in a row and disposed in at least one insulating layer disposed below the color filter 230.

[0078] Reference Figure 5 and Figure 2 The display device 1000 according to the embodiment may include a display area DA capable of displaying an image. The display area DA may include a plurality of pixels PX, and the plurality of pixels PX may be arranged substantially in a matrix form.

[0079] A plurality of color filters 230a, 230b, and 230c capable of displaying different primary colors may be alternately arranged along the first direction DR1. The above-mentioned color filters 230, 230d, and 230e may correspond to the plurality of color filters 230a, 230b, and 230c, respectively.

[0080] The openings 235 formed in the plurality of color filters 230a, 230b, and 230c may extend continuously along the first direction DR1 in the display area DA. Furthermore, each opening 235 may pass through pixels PX adjacently arranged along the first direction DR1 in the first direction DR1. The plurality of openings 235 may be arranged along the second direction DR2. Therefore, throughout the entire display area DA, the respective color filters 230a, 230b, and 230c may be arranged along the second direction DR2 and may include a plurality of portions spaced apart from one another. The color filters 230a, 230b, and 230c corresponding to each pixel column may include portions spaced apart from one another in the second direction DR2, with the openings 235 located between the portions.

[0081] The intervals between the plurality of openings 235 arranged along the second direction DR2 in the second direction DR2 may be the same as or similar to the intervals between the plurality of gate lines 121 in the second direction DR2 .

[0082] In contrast, refer to Figure 6 , each color filter 230, 230d, and 230e corresponding to a pixel column may have a plurality of openings 235a. Each opening 235a may overlap at least three contact holes 185a, 185b, and 188 of a pixel PX. Each opening 235a may be limited to a pixel PX and be limited between two adjacent data lines 171a and 171b. That is, one opening 235a may be provided in each pixel PX.

[0083] The width W1 of the opening 235 or 235a in the second direction DR2 may be about half or less of the width of the light blocking member 220 in the second direction DR2. For example, when the width of the light blocking member 220 in the second direction DR2 is about 40 to 70 micrometers, the width W1 of the opening 235 in the second direction DR2 may be about 20 to 35 micrometers.

[0084] A pixel electrode layer including a plurality of first and second subpixel electrodes 191 a and 191 b , a shielding electrode 190 , and a connecting member 90 may be disposed on the second insulating layer 180 b .

[0085] The first subpixel electrode 191a may be disposed at one side based on a region in which the gate line 121, the reference voltage line 131, and the transistors Qa, Qb, and Qc are disposed in each pixel PX, and the second subpixel electrode 191b may be disposed at an opposite side thereto. Figure 2 In the embodiment shown in , the first subpixel electrode 191a may be disposed below the gate line 121, and the second subpixel electrode 191b may be disposed above the gate line 121. Specific shapes of the first subpixel electrode 191a and the second subpixel electrode 191b will be described later.

[0086] The first subpixel electrode 191a may include an extension portion 196a protruding toward the expanded portion 177a of the first drain electrode 175a and a contact portion 197a connected to one end of the extension portion 196a. The second subpixel electrode 191b may include an extension portion 196b protruding toward the expanded portion 177b of the second drain electrode 175b and a contact portion 197b connected to one end of the extension portion 196b. The contact portion 197a is electrically connected to the expanded portion 177a of the first drain electrode 175a through the contact hole 185a, and the contact portion 197b is electrically connected to the expanded portion 177b of the second drain electrode 175b through the contact hole 185b.

[0087] The extension portion 196a may protrude upward from the upper left edge portion of the first subpixel electrode 191a and may extend upward to intersect the first protrusion 172a of the data line 171a. The extension portion 196a may extend between a portion of the data line 171a extending in the second direction DR2 and the first transistor Qa. The extension portion 196a may overlap an edge portion of the expansion portion 124 of the gate line 121, or may extend upward to intersect the first protrusion 172a of the data line 171a. Figure 2 The gate line 121 may not overlap with the edge portion of the expansion 124 as shown in FIG.

[0088] The extension portion 196 b may protrude from a substantially central portion of a lower portion of the second subpixel electrode 191 b .

[0089] First subpixel electrode 191a may further include an extension portion 196aa disposed on an opposite side of extension portion 196a. That is, extension portion 196aa may protrude upward from the upper right edge portion of first subpixel electrode 191a. Extension portion 196aa may extend upward to intersect with second protrusion 172b, which protrudes to the left of another data line 171b adjacent to data line 171a. The area where extension portion 196a and first protrusion 172a intersect and overlap with each other, and the area where extension portion 196aa and second protrusion 172b intersect and overlap with each other, may be the same or similar.

[0090] The connection member 90 contacts and electrically connects the end portion 176 of the third drain electrode 175 c and the portion of the extension 132 of the reference voltage line 131 adjacent to the connection member 90 through the contact hole 188. Thus, the end portion 176 of the third drain electrode 175 c can be electrically connected to the extension 132 of the reference voltage line 131 through the conductive connection member 90 to receive the reference voltage Vref. Therefore, the third drain electrode 175 c of the third transistor Qc can receive the reference voltage Vref.

[0091] The shielding electrode 190 extends substantially along the second direction DR2 and may be disposed between two adjacent pixels PX. The shielding electrode 190 may overlap the data lines 171a and 171b to shield the electric field from the data lines 171a and 171b, and may prevent capacitive coupling between the data lines 171a and 171b and the first and second sub-pixel electrodes 191a and 191b, thereby preventing light leakage due to the capacitive coupling.

[0092] The pixel electrode layer may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), a metal thin film, or the like.

[0093] The alignment layer 11 may be disposed on the pixel electrode layer and the second insulating layer 180b. The alignment layer 11 may be a vertical alignment layer. The alignment layer 11 may be rubbed in at least one direction, or may be a photo-alignment layer including a photoreactive material.

[0094] In the second display panel 200, the light blocking member 220 (at Figure 3 and Figure 4 The substrate 210 may be disposed on the substrate 210. Here, the substrate 210 may include an insulating substrate. Figure 2 As shown in , the light blocking member 220 may include a portion extending in the first direction DR1 in a plan view, and may overlap the expansion 124 of the gate line 121, the expansion 132 of the reference voltage line 131, and the transistors Qa, Qb, and Qc (the expansion 177a of the first drain electrode 175a, the expansion 177b of the second drain electrode 175b, and the end 176 of the third drain electrode 175c). That is, the light blocking member 220 may extend between the first subpixel electrode 191a and the second subpixel electrode 191b while crossing over the first subpixel electrode 191a and the second subpixel electrode 191b, and may extend while overlapping the gate line 121 and the reference voltage line 131.

[0095] According to another embodiment, the light blocking member 220 may be disposed on the first display panel 100 instead of the second display panel 200 .

[0096] Common electrode 270 (at Figure 3 and Figure 4 The common electrode 270 may be formed as a single plate on the entire surface of the substrate 210. In other words, the common electrode 270 may not have any removed portions such as slits. The common electrode 270 may transmit a common voltage Vcom having a constant amplitude.

[0097] The reference voltage Vref transmitted from the reference voltage line 131 may be equal to or different from the common voltage Vcom. When there is a difference, the reference voltage Vref may have a potential of approximately -2V or +2V of the common voltage Vcom.

[0098] The common electrode 270 may include a transparent conductive material such as ITO, IZO, or a metal thin film.

[0099] Orientation layer 21 (in Figure 3 and Figure 4 The alignment layer 21 may be a vertical alignment layer. The alignment layer 21 may be rubbed in at least one direction or may be a photo-alignment layer including a photoreactive material.

[0100] The liquid crystal layer 3 includes a plurality of liquid crystal molecules 31. The liquid crystal molecules 31 may have negative dielectric anisotropy and may be aligned in a direction substantially perpendicular to the substrates 110 and 210 in a state in which no electric field is generated in the liquid crystal layer 3. When no electric field is generated in the liquid crystal layer 3, the liquid crystal molecules 31 may have a pretilt in a specific direction.

[0101] The first sub-pixel electrode 191a can form a first liquid crystal capacitor Clca together with the common electrode 270 and the liquid crystal layer 3, and the liquid crystal layer 3 is located between the first sub-pixel electrode 191a and the common electrode 270. The second sub-pixel electrode 191b can form a second liquid crystal capacitor Clcb together with the common electrode 270 and the liquid crystal layer 3, and the liquid crystal layer 3 is located between the second sub-pixel electrode 191b and the common electrode 270.

[0102] A plurality of spacers may be provided between the first display panel 100 and the second display panel 200. The spacers may be arranged to primarily overlap transistors Qa, Qb, and Qc in a plan view. When the pixel electrode layer overlaps the spacers, cracks may occur in the pixel electrode layer, thereby preventing the pixel electrode layer from overlapping the spacers. Therefore, the extensions 196a and 196aa of the first subpixel electrode 191a may be arranged to protrude from the left and right edges of the first subpixel electrode 191a adjacent to the data lines 171a and 171b.

[0103] According to an embodiment, the contact holes 185a, 185b, and 188 included in one pixel PX are disposed on the same side relative to the gate line 121 and arranged in parallel along the first direction DR1. Therefore, since the space occupied by the contact holes 185a, 185b, and 188 is smaller than that in the case where the contact holes 185a, 185b, and 188 are dispersed and disposed above and below the gate line 121, the width of the light blocking member 220 in the second direction DR2 can be further reduced, so that the aperture ratio and transmittance of the pixel PX can be increased.

[0104] Since the contact holes 185a, 185b, and 188 are provided on the same side with respect to the gate line 121 in one pixel PX, one of the extension 196a of the first subpixel electrode 191a and the extension 196b of the second subpixel electrode 191b should cross one of the first protrusion 172a of the data line 171a and the second protrusion 172b of the data line 171b. Figure 2In the embodiment shown in FIG, since the contact holes 185a, 185b, and 188 are provided above the gate line 121, the extension portion 196a of the first subpixel electrode 191a provided above the gate line 121 crosses the first protrusion 172a of the data line 171a. In this case, due to the parasitic capacitance between the first subpixel electrode 191a and the data line 171a, light spots due to vertical crosstalk may be observed. However, in this embodiment, the extension portion 196aa provided on the opposite side of the extension portion 196a of the first subpixel electrode 191a crosses the data line 171b adjacent to the data line 171a to form an additional parasitic capacitance, thereby compensating for the vertical crosstalk between the first subpixel electrode 191a and the data line 171a.

[0105] In the following, reference will be made to Figure 7 and Figure 8 With the above Figure 1 Now, a display device according to an embodiment will be described.

[0106] Figure 7 1 shows a layout diagram of three pixels PX1, PX2, and PX3 of a display device according to an embodiment, Figure 8 A layout diagram of three color filters of three pixels PX1 , PX2 , and PX3 of a display device according to an embodiment is shown.

[0107] Among the shapes of the first and second subpixel electrodes 191 a and 191 b provided in the pixels PX1 , PX2 , and PX3 , the overall shape of each of the first and second subpixel electrodes 191 a and 191 b may be a quadrangular shape.

[0108] The first subpixel electrode 191a may include a cross-shaped stem including a horizontal stem 192a and a vertical stem 193a; a plurality of branches 194a extending outward from the cross-shaped stem; an edge portion 195a defining a side of an outer edge; and the aforementioned extension portion 196a and contact portion 197a.

[0109] The second subpixel electrode 191b may include a cross-shaped stem including a horizontal stem 192b and a vertical stem 193b; a plurality of branches 194b extending outward from the cross-shaped stem; an edge portion 195b defining a side of an outer edge; and the aforementioned extension portion 196b and contact portion 197b.

[0110] A planar area of ​​the first subpixel electrode 191 a may be smaller than a planar area of ​​the second subpixel electrode 191 b .

[0111] The primary colors of the color filter 230 corresponding to the pixel column in which the pixel PX1 is disposed, the primary colors of the color filter 230 corresponding to the pixel column in which the pixel PX2 is disposed, and the primary colors of the color filter 230 corresponding to the pixel column in which the pixel PX3 is disposed may be different. For example, the pixel PX1 may correspond to a red color filter, the pixel PX2 may correspond to a green color filter, and the pixel PX3 may correspond to a blue color filter.

[0112] The reference voltage line 131 may include, in addition to a portion extending in the first direction DR1 in which the expansion portion 132 is provided, a vertical portion 133 extending in the second direction DR2, a horizontal portion 134 connected to the vertical portion 133, and vertical portions 135a and 135b connected to the horizontal portion 134. The vertical portions 135a and 135b are provided on the left and right sides of the first subpixel electrode 191a and extend in the second direction DR2. The horizontal portion 134 may be provided to correspond to a boundary between two adjacent pixels in the second direction DR2.

[0113] The vertical portion 133 is not provided in all pixels PX1, PX2, and PX3, but may be provided in pixel PX3. For example, the vertical portion 133 may extend while overlapping the vertical trunk 193b of the second subpixel electrode 191b of pixel PX3. The vertical portions 135a and 135b may be provided in all three pixels PX1, PX2, and PX3.

[0114] Reference Figure 7 In the display device according to the embodiment, the structure of at least one pixel PX3 among the plurality of adjacent pixels PX1, PX2, and PX3 may be partially different from the structures of the remaining pixels PX1 and PX2. For example, the data conductive layer may further include a vertical reference voltage line 178 overlapping the pixel PX3.

[0115] Vertical reference voltage line 178 may transmit a reference voltage Vref. Vertical reference voltage line 178 may include a vertical portion 178a that overlaps and intersects a first subpixel electrode 191a of at least one pixel PX3 among the plurality of pixels PX1, PX2, and PX3, and a vertical portion 178b that overlaps and intersects a second subpixel electrode 191b of at least one pixel PX3 among the plurality of pixels PX1, PX2, and PX3. Vertical portions 178a and 178b of vertical reference voltage line 178 may extend substantially along a second direction DR2.

[0116] The vertical reference voltage line 178 may include a third drain electrode 175c. In other words, the end 176 of the third drain electrode 175c may further extend upward to connect to the vertical portion 178b of the vertical reference voltage line 178, and the lower end of the third drain electrode 175c may further extend downward to connect to the vertical portion 178a of the vertical reference voltage line 178.

[0117] A vertical portion 178a of vertical reference voltage line 178 may extend while overlapping a vertical stem 193a of a first subpixel electrode 191a of pixel PX3, and a vertical portion 178b of vertical reference voltage line 178 may extend while overlapping a vertical stem 193b of a second subpixel electrode 191b of pixel PX3. Vertical reference voltage line 178 may transmit a reference voltage Vref along a second direction DR2 in the display device.

[0118] Therefore, by transmitting the reference voltage Vref in the first direction DR1 via the reference voltage line 131 and transmitting the reference voltage Vref in the second direction DR2 via the vertical reference voltage line 178, the resistance value of the wiring used to transmit the reference voltage Vref can be reduced, so that the voltage drop of the reference voltage Vref can be reduced, thereby preventing the occurrence of plane horizontal crosstalk.

[0119] The vertical reference voltage line 178 may be spaced apart from the adjacent data line 171 and may not cross the data line 171 .

[0120] Since the vertical reference voltage lines 178 are provided to correspond to only some of the pixels PX3, the pitch of the vertical reference voltage lines 178 in the first direction DR1 may be greater than the pitch of the pixels PX1, PX2, and PX3 in the first direction DR1. More specifically, the pitch of the vertical reference voltage lines 178 in the first direction DR1 may be approximately three times or more the pitch of the pixels PX1, PX2, and PX3 in the first direction DR1 (or the pitch of the first subpixel electrode 191a or the second subpixel electrode 191b in the first direction DR1).

[0121] Among the plurality of pixels PX1, PX2, and PX3, a width PW3 of a pixel electrode (first subpixel electrode 191a or second subpixel electrode 191b) in pixel PX3 in the first direction DR1 may be greater than the widths PW1 and PW2 of the pixel electrodes (first subpixel electrode 191a or second subpixel electrode 191b) in the remaining pixels PX1 and PX2 in the first direction DR1. Specifically, a difference between width PW3 of the pixel electrode in pixel PX3 in the first direction DR1 and widths PW1 and PW2 of the pixel electrodes in pixels PX1 and PX2 in the first direction DR1 may be approximately equal to or similar to width WW of vertical reference voltage line 178 in the first direction DR1. Therefore, an effective opening area, which is an area through which light can pass in pixel PX3 overlapping vertical reference voltage line 178, may be similar to the effective opening areas of pixels PX1 and PX2 that do not overlap vertical reference voltage line 178.

[0122] For example, when the width WW of the vertical reference voltage line 178 in the first direction DR1 is approximately 3 micrometers and the widths PW1 and PW2 of the pixel electrodes in pixels PX1 and PX2 in the first direction DR1 are approximately 104 micrometers, the width PW3 of the pixel electrode in the first direction DR1 in the pixel PX3 may be approximately 107 micrometers.

[0123] As described above, taking into account the aperture ratio reduced by the vertical reference voltage line 178 passing through the pixel PX3, by relatively increasing the width PW3 of the pixel electrode of the pixel PX3 in the first direction DR1, the total aperture ratio and transmittance of the pixel PX3 can be substantially equal to the total aperture ratio and transmittance of the remaining pixels PX1 and PX2. Therefore, even when the vertical reference voltage line 178 is additionally overlapped with the pixel PX3 among the plurality of pixels PX1, PX2, and PX3, it is possible to prevent defects in color expression that may occur due to the reduction in the aperture ratio and transmittance of the pixel PX3 (which corresponds to some pixels).

[0124] In the present embodiment, a distance between two adjacent data lines 171 disposed at opposite sides of the pixel PX3 may be greater than a distance between two adjacent data lines 171 disposed at opposite sides of the remaining pixels PX1 and PX2. An area of ​​the first subpixel electrode 191a and the second subpixel electrode 191b included in the pixel PX3 may be greater than an area of ​​the first subpixel electrode 191a and the second subpixel electrode 191b included in the other pixels PX1 and PX2.

[0125] Reference Figure 8At least two adjacent color filters among the plurality of color filters 230 a , 230 b , and 230 c overlap each other in a region overlapping the data line 171 to form an overlapping portion 230 p .

[0126] When the effective opening area of ​​each of the pixels PX1, PX2, and PX3 is defined as the area between two adjacent overlapping portions 230p, the effective opening area of ​​the pixel PX3 among the plurality of pixels PX1, PX2, and PX3 may be the same as or similar to the sum of the width OW3a of the left portion and the width OW3b of the right portion (where the width WW of the vertical reference voltage line 178 in the first direction DR1 is subtracted from the width OW3 between the two adjacent overlapping portions 230p in the first direction DR1). The width of the effective opening area of ​​the pixel PX3 in the first direction DR1 may be similar to the widths OW1 and OW2 of the effective opening areas of the pixels PX1 and PX2 in the first direction DR1, respectively.

[0127] The pixel PX3 through which the vertical reference voltage line 178 passes may be a pixel for displaying blue, but the vertical reference voltage line 178 is not limited thereto and may pass through a pixel for displaying red or green. Furthermore, among the plurality of pixels PX1, PX2, and PX3 repeated in a group, the number of pixels PX3 through which the vertical reference voltage line 178 passes may be one, but is not limited thereto and may be two.

[0128] In a comparative display, the first and second subpixel electrodes are spaced apart from the gate line, and transistors are disposed between the first subpixel electrode and the gate line, and between the second subpixel electrode and the gate line, resulting in contact holes dispersed on both sides relative to the gate line. According to the inventive concept, the contact holes for the pixel disposed between the first and second subpixel electrodes can be arranged in a row, so that the light-blocking member can have a reduced width. In addition, an opening corresponding to the aligned contact holes can be provided in the color filter, so that defects caused by a small piece of color filter when multiple openings are formed for each contact hole can be prevented.

[0129] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, comprising: substrate; a gate line disposed on the substrate and configured to transmit a gate signal; a first reference voltage line spaced apart from the gate line and configured to transmit a reference voltage; a second reference voltage line, disposed on the gate line and the first reference voltage line, and electrically connected to the first reference voltage line; a plurality of data lines crossing the gate line and the first reference voltage line and including a first data line and a second data line spaced apart from each other, an insulating layer, disposed on the second reference voltage line; as well as A pixel electrode layer is provided on the insulating layer, The pixel electrode layer includes a first pixel electrode, the first pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode is arranged at a first side relative to the gate line in a plan view, and the second sub-pixel electrode is arranged at a second side relative to the gate line opposite to the first side in the plan view, and The second reference voltage line overlaps the first pixel electrode and crosses the first pixel electrode. Wherein, the gate line includes a first gate electrode, a second gate electrode and a third gate electrode, The display device further includes: a first transistor including the first gate electrode, a first source electrode, and a first drain electrode; a second transistor including the second gate electrode, a second source electrode, and a second drain electrode; and a third transistor including the third gate electrode, a third source electrode, and a third drain electrode. The insulating layer has a first contact hole provided on the first drain electrode, a second contact hole provided on the second drain electrode, and a third contact hole provided on the third drain electrode. The first sub-pixel electrode is electrically connected to the first drain electrode through the first contact hole, The second sub-pixel electrode is electrically connected to the second drain electrode through the second contact hole, and The first contact hole, the second contact hole, and the third contact hole are arranged at the same side relative to the gate line and are arranged in a row, The display device further includes a color filter overlapping the first pixel electrode, the color filter having an opening that overlaps all of the first contact hole, the second contact hole, and the third contact hole, and the opening continuously extends across the first contact hole, the second contact hole, and the third contact hole. wherein the first data line includes a first protrusion protruding in a first direction, and the second data line includes a second protrusion protruding in a direction opposite to the first direction, wherein the first sub-pixel electrode includes a first extension portion protruding toward the first drain electrode and a second extension portion at an opposite side of the first extension portion, wherein the first extension overlaps the first protrusion, and the second extension overlaps the second protrusion, wherein a plurality of second reference voltage lines are arranged along the first direction, a plurality of first pixel electrodes are arranged along the first direction, and the plurality of second reference voltage lines respectively overlap with some of the plurality of first pixel electrodes, and The width of the first pixel electrode overlapping the second reference voltage line in the first direction is greater than the width of the first pixel electrode where the second reference voltage line is not provided.

2. The display device according to claim 1, wherein The second reference voltage line is spaced apart from each data line and does not cross the plurality of data lines.

3. The display device according to claim 2, wherein: The second reference voltage line and the plurality of data lines are disposed in the same conductive layer.

4. The display device according to claim 1, wherein The first reference voltage line includes a first extension portion overlapping the third contact hole, The third contact hole overlaps a portion of the third drain electrode and a portion of the first expansion, and The pixel electrode layer further includes a connecting member, and the connecting member electrically connects the third drain electrode and the first expansion portion through the third contact hole.

5. The display device according to claim 4, wherein The second reference voltage line includes the third drain electrode and is disposed in the same conductive layer as the third drain electrode. The display device according to claim 5 , wherein: The first sub-pixel electrode further includes a stem overlapping the second reference voltage line and extending parallel to the second reference voltage line in the plan view; and a plurality of branches connected to the stem.

7. The display device according to claim 1, wherein The opening crosses the plurality of data lines.

8. The display device according to claim 1, wherein A spacing between the plurality of second reference voltage lines in the first direction is greater than a spacing between the plurality of first pixel electrodes in the first direction.

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