A non-volatile latch and integrated circuit based on RRAM

Abstract

The present invention discloses a non-volatile latch based on RRAM, including: a power supply, a dual interlock storage module, a storage node, a backup module and a plurality of switch control nodes, wherein the dual interlock storage module includes a first latch unit, a first feedback unit, a second latch unit and a second feedback unit; the storage node is arranged at the connection of the first latch unit, the first feedback unit, the second latch unit and the second feedback unit; the backup module includes a plurality of 1T1R structures, the third terminal of each 1T1R structure is connected to the corresponding storage node, and the fourth terminal of each 1T1R structure is connected in common; the latch can be powered off when the circuit does not need to work, thereby reducing static power consumption, and in the event of an unexpected power failure, it can be ensured that the working state before the power failure can be restored after powering on again; at the same time, the reinforcement method of the dual interlock storage module is applied to improve the single particle resistance performance of the non-volatile circuit, and avoid circuit damage and data transmission and storage errors. The present invention also provides an integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a non-volatile latch and an integrated circuit based on RRAM (resistive random access memory). Background Art

[0002] The energy of aerospace electronic equipment mainly comes from solar energy, that is, solar energy is converted into electrical energy through the corresponding power control module, but its conversion efficiency is low; in addition, the space radiation environment is harsh. When high-energy particles enter semiconductor devices, they will ionize to produce electron-hole pairs and deposit charges, which are collected by PN junctions or electrical contacts. If the amount of collected charge exceeds the amount of charge stored in the information, a single particle effect will occur; the stored information will be destroyed, and incorrect system operation may cause permanent damage to the circuit.

[0003] In view of the above problems, those skilled in the art have developed a non-volatile latch based on RRAM, which usually integrates RRAM storage units into traditional latches to ensure that the data on the latch is saved in the RRAM during power failure, and after power is restored, the data can be returned to the latch, so that the circuit can return to the working state before power failure, which has the advantage of low power consumption, and RRAM itself has good single particle resistance performance, and it is not easy to cause the information stored in it to be destroyed. However, the single particle resistance performance of traditional latch circuits is poor. When bombarded by high-energy particles, it is easy to cause circuit output errors, thereby reducing the single particle resistance performance of the overall circuit.

[0004] As the complexity and integration of aerospace electronic equipment become higher and higher, the interference of single event effects on electronic equipment becomes more and more serious. Therefore, how to realize a latch with low power consumption, single event resistance and good non-volatility has become an urgent problem to be solved. Summary of the invention

[0005] In order to overcome the technical problem that the existing non-volatile latch has poor single particle resistance performance and is prone to circuit output errors when bombarded by high-energy particles, the present invention provides a non-volatile latch and integrated circuit based on RRAM.

[0006] The RRAM-based nonvolatile latch of the present invention comprises: a power supply,

[0007] A dual interlocking module, the dual interlocking module comprises a first latch unit, a first feedback unit, a second latch unit and a second feedback unit; the first terminals of the first latch unit, the first feedback unit, the second latch unit and the second feedback unit are all connected to a power supply, and the second terminals are all grounded; the first latch unit and the second latch unit are connected via the first feedback unit and the second feedback unit;

[0008] A storage node, the storage node is arranged at the connection of the first latch unit, the first feedback unit, the second latch unit and the second feedback unit, and the storage node is used for temporarily storing write data;

[0009] A backup module, the backup module includes a plurality of 1T1R (1Transistor and 1RRAM, 1 transistor and 1 resistive memory) structures, the third terminal of each 1T1R structure is connected to the corresponding storage node, and the fourth terminal of each 1T1R structure is connected in common, and is used to back up the temporarily stored write data of the storage node in the case of power failure or non-operation;

[0010] A plurality of switch control nodes, wherein the plurality of switch control nodes are used to control the working state of the backup module.

[0011] Preferably, the first latch unit includes a first NMOS (N Metal Oxide Semiconductor) transistor and a first PMOS (P Metal Oxide Semiconductor) transistor;

[0012] The source of the first NMOS transistor is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor is connected to the source of the first PMOS transistor, the drain of the first NMOS transistor is grounded, and the drain of the first PMOS transistor is connected to a power supply.

[0013] Preferably, the second latch unit includes a second NMOS transistor and a second PMOS transistor;

[0014] The source of the second NMOS transistor is connected to the gate of the second PMOS transistor, the gate of the second NMOS transistor is connected to the source of the second PMOS transistor, the drain of the second NMOS transistor is grounded, and the drain of the second PMOS transistor is connected to the power supply.

[0015] Preferably, the first feedback unit includes a third NMOS transistor and a third PMOS transistor;

[0016] The source of the third NMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third NMOS transistor is connected to the source of the third PMOS transistor, the drain of the third NMOS transistor is grounded, and the drain of the third PMOS transistor is connected to the power supply.

[0017] Preferably, the second feedback unit includes a fourth NMOS transistor and a fourth PMOS transistor;

[0018] The source of the fourth NMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth NMOS transistor is grounded, and the drain of the fourth PMOS transistor is connected to the power supply.

[0019] Preferably, the storage nodes include a first storage node, a second storage node, a third storage node and a fourth storage node;

[0020] The switch control nodes include a first switch control node, a second switch control node, a third switch control node and a fourth switch control node;

[0021] The backup module includes a first 1T1R structure, a second 1T1R structure, a third 1T1R structure and a fourth 1T1R structure.

[0022] Preferably, the source of the first NMOS transistor, the gate of the first PMOS transistor, the gate of the fourth NMOS transistor and the source of the fourth PMOS transistor are connected via the first storage node;

[0023] The gate of the first NMOS transistor, the source of the first PMOS transistor, the source of the third NMOS transistor, and the gate of the third PMOS transistor are connected via a second storage node;

[0024] The source of the second NMOS transistor, the gate of the second PMOS transistor, the gate of the third NMOS transistor and the source of the third PMOS transistor are connected via a third storage node;

[0025] The gate of the second NMOS transistor, the source of the second PMOS transistor, the source of the fourth NMOS transistor, and the gate of the fourth PMOS transistor are connected through a fourth storage node.

[0026] Preferably, the first 1T1R structure includes a fifth NMOS transistor and a first RRAM; the drain of the fifth NMOS transistor is connected to the first end of the first RRAM, the source of the fifth NMOS transistor is connected to the first storage node, and the gate of the fifth NMOS transistor is connected to the first switch control node;

[0027] The second 1T1R structure includes a sixth NMOS transistor and a second RRAM; the drain of the sixth NMOS transistor is connected to the first end of the second RRAM, the source of the sixth NMOS transistor is connected to the second storage node, and the gate of the sixth NMOS transistor is connected to the second switch control node;

[0028] The third 1T1R structure includes a seventh NMOS transistor and a third RRAM; the drain of the seventh NMOS transistor is connected to the first end of the third RRAM, the source of the seventh NMOS transistor is connected to the third storage node, and the gate of the seventh NMOS transistor is connected to the third switch control node;

[0029] The fourth 1T1R structure includes an eighth NMOS transistor and a fourth RRAM; the drain of the eighth NMOS transistor is connected to the first end of the fourth RRAM, the source of the eighth NMOS transistor is connected to the fourth storage node, and the gate of the eighth NMOS transistor is connected to the fourth switch control node;

[0030] The second end of the first RRAM, the second end of the second RRAM, the second end of the third RRAM, and the second end of the fourth RRAM are connected in common.

[0031] The present invention also provides an integrated circuit, comprising any one of the above-mentioned RRAM-based non-volatile latches.

[0032] In summary, the non-volatile latch based on RRAM provided by the present invention integrates the 1T1R structure into the latch to ensure that the written data on the latch can be saved in the RRAM during power failure, and after the power is re-supplied, the written data can be returned to the latch, so that the circuit can return to the working state before the power failure. The backup module includes a plurality of 1T1R structures, and the third terminal of the 1T1R structure is connected to the corresponding storage node. When the transistor in the backup module is turned on, the written data of the storage node is backed up. When the power is off, the written data can be saved in a resistance state. In the data recovery stage of the storage node, due to the difference in high and low resistance values ​​of RRAM, the original correct data can be restored at the storage node, so that the working state before the power failure can be restored. At the same time, a dual interlocked latch is adopted, and the written data is temporarily stored in the storage node through the parasitic capacitance of the storage node and the interlocking feedback mechanism, and the critical charge can be increased, and the influence of the single particle effect on the storage node and the 1T1R structure can be weakened. When a high-energy particle strikes point X (a single-particle strike point) during the backup phase, the resistance of the first RRAM is affected. If the resistance of the first RRAM after the strike is still greater than the low-resistance state resistance, the data can be correctly restored in the subsequent recovery phase. If the resistance of the first RRAM after the strike is lower than the low-resistance state resistance, the erroneous storage data will be transmitted to the storage node connected to the dual interlock memory module in the subsequent recovery phase. Due to the redundant characteristics of the dual interlock memory module, the erroneous data can be corrected through the adjacent storage nodes, thereby realizing the overall single-particle resistance of the non-volatile latch through the dual interlock memory module.

[0033] Compared with the prior art, the RRAM-based non-volatile latch provided by the present invention can be powered off when the circuit does not need to work to reduce static power consumption, and in the event of an unexpected power outage, it can be ensured that the working state before power failure can be restored after power is restored to avoid data loss; at the same time, the reinforcement method of the dual interlocking storage module is applied to improve the single particle resistance of the overall circuit, avoid circuit damage and data transmission and storage errors.

[0034] The integrated circuit provided by the present invention also has the advantages of low power consumption and high single particle resistance performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a structure of a non-volatile latch based on RRAM involved in an embodiment of the present invention;

[0036] Figure 2 Schematic diagram of the structure of a dual interlock storage module according to an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of the structure of a backup module involved in an embodiment of the present invention.

[0038] Among them, 1 is a dual interlock module, 10 is a first latch unit, 100 is a first NMOS transistor, 101 is a first PMOS transistor, 11 is a first feedback unit, 110 is a third NMOS transistor, 111 is a third PMOS transistor, 12 is a second latch unit, 120 is a second NMOS transistor, 121 is a second PMOS transistor, 13 is a second feedback unit, 130 is a fourth NMOS transistor, 131 is a fourth PMOS transistor, 2 is a storage node, 20 is a first storage node, 21 is a second storage node, 22 is a third storage node, 23 is a fourth storage node, 3 is a backup node, Module, 30 is a first 1T1R structure, 300 is a fifth NMOS transistor, 301 is a first RRAM, 31 is a second 1T1R structure, 310 is a sixth NMOS transistor, 311 is a second RRAM, 32 is a third 1T1R structure, 320 is a seventh NMOS transistor, 321 is a third RRAM, 33 is a fourth 1T1R structure, 330 is an eighth NMOS transistor, 331 is a fourth RRAM, 4 is a switch control node, 40 is a first switch control node, 41 is a second switch control node, 42 is a third switch control node, 43 is a fourth switch control node, and 5 is an X point. DETAILED DESCRIPTION

[0039] The specific implementation methods according to the present invention are described below with reference to the accompanying drawings.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0041] In order to overcome the technical problem that the existing non-volatile latch has poor single particle resistance performance and is prone to circuit output errors when bombarded by high-energy particles, the present invention provides a non-volatile latch and integrated circuit based on RRAM.

[0042] The RRAM-based nonvolatile latch of the present invention is as follows: Figures 1 to 3 As shown, including: power supply VDD,

[0043] The dual interlocking module 1 includes a first latch unit 10, a first feedback unit 11, a second latch unit 12, and a second feedback unit 13; the first terminals of the first latch unit 10, the first feedback unit 11, the second latch unit 12, and the second feedback unit 13 are all connected to a power supply, and the second terminals are all grounded; the first latch unit 10 and the second latch unit 12 are connected via the first feedback unit 11 and the second feedback unit 13;

[0044] A storage node 2, which is disposed at the connection between the first latch unit 10, the first feedback unit 11, the second latch unit 12 and the second feedback unit 13, and is used for temporarily storing write data;

[0045] The backup module 3 includes a plurality of 1T1R structures, wherein the third terminal of each 1T1R structure is connected to the corresponding storage node 2, and the fourth terminal of each 1T1R structure is connected in common, and is used to back up the temporarily stored write data on the storage node 2 in case of power failure or non-operation;

[0046] A plurality of switch control nodes 4 are used to control the working state of the backup module 3 .

[0047] In this embodiment, the first latch unit 10 and the second latch unit 12 are connected through the first feedback unit 11 and the second feedback unit 13; that is, the two ends of the first latch unit 10 are respectively connected to one end of the first feedback unit 11 and one end of the second feedback unit 13, the other end of the first feedback unit 11 is connected to one end of the second latch unit 12, and the other end of the second latch unit 12 is connected to the other end of the second feedback unit 13.

[0048] In this embodiment, the working process of the RRAM-based non-volatile latch can be divided into four stages: normal working stage, backup stage, power-off stage and recovery stage;

[0049] In the normal working stage, the CLK clock signal controls the data to be written into the storage node 2 connected to the dual interlock storage module 1;

[0050] In the backup phase, the switch control node 4 controls the transistors in each 1T1R structure to be turned on, and the write data is written from the dual interlock memory module 1 to each 1T1R structure by using the voltage difference between the storage node 2 and the fourth terminal of each 1T1R structure at CL;

[0051] In the power-off stage, that is, the voltage value of the power supply VDD is 0, the written data stored in the dual interlock memory module 1 is lost, but the written data has been stored in each 1T1R structure as the resistance state of each 1T1R structure;

[0052] In the recovery phase, the switch control node 4 controls the transistors in each 1T1R structure to be turned on for a short time. Due to the difference in resistance state of each 1T1R structure acting on the circuit, the written data is restored in the storage node 2 of the dual interlock memory module 1, thereby ensuring that the circuit can be restored to the working state before power failure.

[0053] By adopting the above technical scheme, the RRAM-based non-volatile latch provided by the present invention can be powered off when the circuit does not need to work to reduce static power consumption, and can ensure that when an unexpected power outage occurs, it can be restored to the working state before power failure after power is restored to avoid data loss; at the same time, the reinforcement method of the dual interlock memory module 1 is applied to improve the single particle resistance of the overall circuit and avoid circuit damage.

[0054] Further, the first latch unit 10 includes a first NMOS transistor 100 and a first PMOS transistor 101;

[0055] The source of the first NMOS transistor 100 is connected to the gate of the first PMOS transistor 101 , the gate of the first NMOS transistor 100 is connected to the source of the first PMOS transistor 101 , the drain of the first NMOS transistor 100 is grounded, and the drain of the first PMOS transistor 101 is connected to the power supply VDD.

[0056] Further, the second latch unit 12 includes a second NMOS transistor 120 and a second PMOS transistor 121;

[0057] The source of the second NMOS transistor 120 is connected to the gate of the second PMOS transistor 121 , the gate of the second NMOS transistor 120 is connected to the source of the second PMOS transistor 121 , the drain of the second NMOS transistor 120 is grounded, and the drain of the second PMOS transistor 121 is connected to the power supply VDD.

[0058] Further, the first feedback unit 11 includes a third NMOS transistor 110 and a third PMOS transistor 111;

[0059] The source of the third NMOS transistor 110 is connected to the gate of the third PMOS transistor 111 , the gate of the third NMOS transistor 110 is connected to the source of the third PMOS transistor 111 , the drain of the third NMOS transistor 110 is grounded, and the drain of the third PMOS transistor 111 is connected to the power supply VDD.

[0060] Further, the second feedback unit 13 includes a fourth NMOS transistor 130 and a fourth PMOS transistor 131;

[0061] The source of the fourth NMOS transistor 130 is connected to the gate of the fourth PMOS transistor 131 , the gate of the fourth NMOS transistor 130 is connected to the source of the fourth PMOS transistor 131 , the drain of the fourth NMOS transistor 130 is grounded, and the drain of the fourth PMOS transistor 131 is connected to the power supply VDD.

[0062] Further, the storage node 2 includes a first storage node 20, a second storage node 21, a third storage node 22 and a fourth storage node 23;

[0063] The switch control node 4 includes a first switch control node 40, a second switch control node 41, a third switch control node 42 and a fourth switch control node 43;

[0064] The backup module 3 includes a first 1T1R structure 30 , a second 1T1R structure 31 , a third 1T1R structure 32 and a fourth 1T1R structure 33 .

[0065] Further, the source of the first NMOS transistor 100, the gate of the first PMOS transistor 101, the gate of the fourth NMOS transistor 130 and the source of the fourth PMOS transistor 131 are connected via the first storage node 20;

[0066] The gate of the first NMOS transistor 100, the source of the first PMOS transistor 101, the source of the third NMOS transistor 110 and the gate of the third PMOS transistor 111 are connected via a second storage node 21;

[0067] The source of the second NMOS transistor 120, the gate of the second PMOS transistor 121, the gate of the third NMOS transistor 110, and the source of the third PMOS transistor 111 are connected via a third storage node 22;

[0068] The gate of the second NMOS transistor 120 , the source of the second PMOS transistor 121 , the source of the fourth NMOS transistor 130 , and the gate of the fourth PMOS transistor 131 are connected through a fourth storage node 23 .

[0069] Further, the first 1T1R structure 30 includes a fifth NMOS transistor 300 and a first RRAM 301; the drain of the fifth NMOS transistor 300 is connected to the first end of the first RRAM 301, the source of the fifth NMOS transistor 300 is connected to the first storage node 20, and the gate of the fifth NMOS transistor 300 is connected to the first switch control node 40;

[0070] The second 1T1R structure 31 includes a sixth NMOS transistor 310 and a second RRAM 311; the drain of the sixth NMOS transistor 310 is connected to the first end of the second RRAM 311, the source of the sixth NMOS transistor 310 is connected to the second storage node 21, and the gate of the sixth NMOS transistor 310 is connected to the second switch control node 41;

[0071] The third 1T1R structure 32 includes a seventh NMOS transistor 320 and a third RRAM 321; the drain of the seventh NMOS transistor 320 is connected to the first end of the third RRAM 321, the source of the seventh NMOS transistor 320 is connected to the third storage node 22, and the gate of the seventh NMOS transistor 320 is connected to the third switch control node 42;

[0072] The fourth 1T1R structure 33 includes an eighth NMOS transistor 330 and a fourth RRAM 331; the drain of the eighth NMOS transistor 330 is connected to the first end of the fourth RRAM 331, the source of the eighth NMOS transistor 330 is connected to the fourth storage node 23, and the gate of the eighth NMOS transistor 330 is connected to the fourth switch control node 43;

[0073] The second end of the first RRAM 301 , the second end of the second RRAM 311 , the second end of the third RRAM 321 , and the second end of the fourth RRAM 331 are connected in common.

[0074] Using the above technical solution, each 1T1R structure is composed of a transistor and an RRAM connected. Different from the traditional way of using charge to store information, the non-volatile element RRAM stores data through high and low resistance states. Therefore, RRAM has "normally off" properties, that is, data can still be saved during planned or accidental power outages, so that the RRAM-based non-volatile latch can completely turn off the power in standby mode, and can switch to the state before standby when the circuit needs to work again, thereby achieving zero static power consumption and further reducing overall power consumption.

[0075] In order to better understand the RRAM-based nonvolatile latch provided by the present invention, the working process of the RRAM-based nonvolatile latch is further explained below:

[0076] In the normal working stage, the clock signal CLK controls the writing of the data into the first storage node 20, the second storage node 21, the third storage node 22 and the fourth storage node 23 connected to the dual interlock memory module.

[0077] In the backup stage, a plurality of switch control nodes 4 control the transistors in each 1T1R structure to be turned on, and the write data is written from the first storage node 20, the second storage node 21, the third storage node 22, and the fourth storage node 23 to the first RRAM 301, the second RRAM 311, the third RRAM 321, and the fourth RRAM 331, respectively, by using the voltage difference between the first storage node 20, the second storage node 21, the third storage node 22, and the fourth storage node 23 and the voltage difference at CL.

[0078] In the power-off stage, the power supply VDD=0, and the written data stored in each storage node 2 is lost, but the written data has been stored in the 1T1R structure as the resistance state of the RRAM.

[0079] In the recovery stage, a number of switch control nodes 4 control the fifth NMOS transistor 300, the sixth NMOS transistor 310, the seventh NMOS transistor 320 and the eighth NMOS transistor 330 to be turned on for a short time. Due to the difference in the states of each RRAM acting on the circuit, the written data is restored on the first storage node 20, the second storage node 21, the third storage node 22, and the fourth storage node 23, thereby ensuring that the circuit can be restored to the working state before power failure, thereby having good non-volatility.

[0080] In the normal working stage, when high-energy particles strike any storage node 2, the unique interlocking feedback mechanism of the dual interlock register can ensure that the data is not affected by the high-energy particles.

[0081] In the normal working stage, after the data to be written is written into the dual interlock memory module 1, if the X point 5 is bombarded with particles, the written data temporarily stored in the dual interlock memory module 1 after the bombardment will not be wrong, because the transistors in each 1T1R structure are not turned on in the normal working stage, so the state of the transistors in each 1T1R structure is not affected, but the resistance of the first RRAM 301 is affected by the particle bombardment, and the degree of change is affected by the device set voltage and the deposited charge. However, even if the resistance of the first RRAM 301 is destroyed due to the influence of the particle bombardment, in the next stage, that is, in the backup stage, the first RRAM 301 can still be correctly backed up according to the temporarily stored write data on each storage node 2 connected to the dual interlock memory module 1.

[0082] Specifically, Figures 1 to 3 As shown, the first 1T1R structure 30 is connected to the first storage node 20. In the backup stage, the switch control node 4 controls the transistors in each 1T1R structure to be turned on. After the data to be written is written into the first RRAM 301, the fifth NMOS transistor 300 is turned off. After the particle bombardment X point 5, the temporarily stored write data in the dual interlock storage module 1 is not wrong, but the resistance value of the first RRAM 301 is affected, and the degree of change is affected by the device set voltage and the deposited charge; wherein, if the resistance value of the first RRAM 301 is still greater than the low resistance value after the particle bombardment, in the recovery stage In the recovery phase, the written data can be recovered after power is turned on again, and the state of the first RRAM 301 can be recovered; if the resistance value of the first RRAM 301 after the particle bombardment is lower than the resistance value of the low resistance state, in the recovery phase, the state of the first RRAM 301 cannot be recovered after power is turned on again, and the erroneous backup data will be transmitted to each storage node 2 connected to the dual interlock memory module 1 in the next phase, that is, in the recovery phase. However, due to the redundant latch structure in the dual interlock memory module 1, even if the data recovered on the first storage node 20 is erroneous, the storage node 2 adjacent to it can pull it back to the correct level.

[0083] In the recovery phase, each switch control node 4 controls the transistor in the corresponding 1T1R structure to be turned on for a short time. After the data in the dual interlock storage module 1 is restored, each switch control node 4 is turned off. At this time, the dual interlock storage module 1 is isolated from the backup module 3. After the particle bombardment X point 5, the restored data in the dual interlock storage module 1 will not be affected, but the resistance value in the first RRAM 301 will be affected. The degree of change is affected by the device set voltage and the deposited charge, and it cannot be restored within the clock cycle.

[0084] It can be seen that when particles bombard point X 5, the resistance of the first RRAM 301 will be affected; however, this influence will not interfere with the data on each storage node 2 under the robust structure of the dual interlock module 1 and the proper isolation of the transistors; thereby ensuring that the RRAM-based non-volatile latch provided by the present invention can have good single-particle resistance performance under the premise of realizing the "normally off" state of the latch and reducing static power consumption.

[0085] It should be noted that the above only shows that after the particle bombardment on the first storage node 20 and a point in the first 1T1R structure 30, no interference will be caused to the data on each storage node 2; for particle bombardment on other storage nodes 2, or a point on other 1T1R structures in the latch, the working principle is the same, so it will not be repeated here.

[0086] At the same time, the present invention also provides an integrated circuit, including the RRAM-based non-volatile latch provided by the present invention.

[0087] In summary, the RRAM-based nonvolatile latch provided by the present invention has a dual interlock storage module 1, which temporarily stores the written data in the storage node 2 through the parasitic capacitance of the storage node 2 and the interlock feedback mechanism, and can increase the critical charge and weaken the influence of the single particle effect; at the same time, the backup module 3 includes a plurality of 1T1R structures, and the third terminal of the 1T1R structure is connected to the corresponding storage node 2. When it is turned on, the written data is backed up, and when the power is off, the written data can be saved in a resistance state. When it is turned on for a short time, the resistance difference of the 1T1R structure acts on the circuit, and the written data can be restored at the storage node 2, thereby being able to restore to the working state before the power is off.

[0088] Compared with the prior art, the RRAM-based non-volatile latch provided by the present invention can be powered off when the circuit does not need to work to reduce static power consumption, and can ensure that when an unexpected power outage occurs, it can be restored to the working state before power outage after power is restored to avoid data loss; at the same time, the reinforcement method of the dual interlock storage module 1 is applied to improve the overall single-particle resistance of the circuit and avoid data damage.

[0089] The integrated circuit provided by the present invention also has the advantages of low power consumption and high single particle resistance performance.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A non-volatile latch based on RRAM, characterized in that: include: power supply, A dual interlocking module, the dual interlocking module comprising a first latch unit, a first feedback unit, a second latch unit and a second feedback unit; the first terminals of the first latch unit, the first feedback unit, the second latch unit and the second feedback unit are all connected to the power supply, and the second terminals are all grounded; the first latch unit and the second latch unit are connected through the first feedback unit and the second feedback unit; the first latch unit comprises a first NMOS transistor and a first PMOS transistor; the second latch unit comprises a second NMOS transistor and a second PMOS transistor; the first feedback unit comprises a third NMOS transistor and a third PMOS transistor; the second feedback unit comprises a fourth NMOS transistor and a fourth PMOS transistor; A storage node, the storage node is arranged at the connection between the first latch unit, the first feedback unit, the second latch unit and the second feedback unit, and the storage node is used to temporarily store write data; A backup module, the backup module comprising a plurality of 1T1R structures, the third terminal of each of the 1T1R structures being connected to the corresponding storage node, and the fourth terminal of each of the 1T1R structures being connected in common, for backing up the temporarily stored written data in the storage node in the event of power failure or non-operation; A plurality of switch control nodes, wherein the plurality of switch control nodes are used to control the working state of the backup module; The storage nodes include a first storage node, a second storage node, a third storage node and a fourth storage node; the switch control nodes include a first switch control node, a second switch control node, a third switch control node and a fourth switch control node; the backup module includes a first 1T1R structure, a second 1T1R structure, a third 1T1R structure and a fourth 1T1R structure; The source of the first NMOS transistor, the gate of the first PMOS transistor, the gate of the fourth NMOS transistor and the source of the fourth PMOS transistor are connected through the first storage node; the gate of the first NMOS transistor, the source of the first PMOS transistor, the source of the third NMOS transistor and the gate of the third PMOS transistor are connected through the second storage node; the source of the second NMOS transistor, the gate of the second PMOS transistor, the gate of the third NMOS transistor and the source of the third PMOS transistor are connected through the third storage node; the gate of the second NMOS transistor, the source of the second PMOS transistor, the source of the fourth NMOS transistor and the gate of the fourth PMOS transistor are connected through the fourth storage node; The first 1T1R structure includes a fifth NMOS transistor and a first RRAM; the drain of the fifth NMOS transistor is connected to the first end of the first RRAM, the source of the fifth NMOS transistor is connected to the first storage node, and the gate of the fifth NMOS transistor is connected to the first switch control node; the second 1T1R structure includes a sixth NMOS transistor and a second RRAM; the drain of the sixth NMOS transistor is connected to the first end of the second RRAM, the source of the sixth NMOS transistor is connected to the second storage node, and the gate of the sixth NMOS transistor is connected to the second switch control node; the third 1T1R structure includes a seventh NMOS transistor and a third RRAM; the drain of the seventh NMOS transistor is connected to the first end of the third RRAM, the source of the seventh NMOS transistor is connected to the third storage node, and the gate of the seventh NMOS transistor is connected to the third switch control node; the fourth 1T1R structure includes an eighth NMOS transistor and a fourth RRAM; the drain of the eighth NMOS transistor is connected to the first end of the fourth RRAM, the source of the eighth NMOS transistor is connected to the fourth storage node, and the gate of the eighth NMOS transistor is connected to the fourth switch control node; the second end of the first RRAM, the second end of the second RRAM, the second end of the third RRAM, and the second end of the fourth RRAM are connected in common.

2. The RRAM-based nonvolatile latch according to claim 1, wherein: The source of the first NMOS transistor is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor is connected to the source of the first PMOS transistor, the drain of the first NMOS transistor is grounded, and the drain of the first PMOS transistor is connected to the power supply.

3. The RRAM-based nonvolatile latch according to claim 2, characterized in that: The source of the second NMOS transistor is connected to the gate of the second PMOS transistor, the gate of the second NMOS transistor is connected to the source of the second PMOS transistor, the drain of the second NMOS transistor is grounded, and the drain of the second PMOS transistor is connected to the power supply.

4. The RRAM-based nonvolatile latch according to claim 3, characterized in that: The source of the third NMOS transistor is connected to the gate of the third PMOS transistor, the gate of the third NMOS transistor is connected to the source of the third PMOS transistor, the drain of the third NMOS transistor is grounded, and the drain of the third PMOS transistor is connected to the power supply.

5. The RRAM-based nonvolatile latch according to claim 4, characterized in that: The source of the fourth NMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the fourth NMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth NMOS transistor is grounded, and the drain of the fourth PMOS transistor is connected to the power supply.

6. An integrated circuit, characterized in that: The RRAM-based nonvolatile latch comprises the RRAM-based nonvolatile latch as claimed in any one of claims 1 to 5.

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