Insulated gate type semiconductor device and method for manufacturing the same

Abstract

The present invention provides an insulated gate type semiconductor device and a manufacturing method thereof, which can suppress the increase of working hours and can screen the gate insulating film of the dummy groove independently of the gate insulating film of the gate groove. The method comprises the following steps: digging a gate groove (51) and a dummy groove (42); burying a dummy electrode (72) in the dummy groove (42) through a gate insulating film (6), and burying a gate electrode (71) in the gate groove (51) through a gate insulating film (6); selectively forming an inspection insulating film (11) in a manner that exposes the dummy electrode (72) and covers the gate electrode (71); depositing an inspection conductive film (20) on the dummy electrode (72) and the inspection insulating film (11); and applying a voltage between the inspection conductive film (20) and a charge transfer region (1), thereby selectively inspecting the insulation characteristics of the gate insulating film (6) in the dummy groove (51).

Description

Technical Field

[0001] The present invention relates to an insulated gate type semiconductor device having a trench gate structure and a manufacturing method thereof. Background Art

[0002] In an insulated gate bipolar transistor (IGBT) having a trench gate structure, the following structure is known: a dummy electrode is buried in a portion of the trenches (dummy trenches) among a plurality of trenches, and the dummy electrode is electrically connected to the emitter electrode to reduce the gate-collector capacitance that causes switching loss.

[0003] Patent Document 1 discloses a method of performing screening for gate insulating film defects over the entire trench to ensure the quality of the gate insulating film of the dummy trench before the gate trench and the dummy trench are separated in the device structure.

[0004] However, in the method of Patent Document 1, since the gate insulating film is tested simultaneously throughout the entire trench, a relatively large voltage needs to be applied during the test, thereby generating a large number of particles when a defective element is damaged. Therefore, a screening condition matching the required resistance of the gate insulating film of the dummy trench is set to suppress the generation of particles. However, the gate insulating film of the gate trench needs to be tested again after the manufacturing process is completed, and the time-dependent dielectric breakdown (TDDB) resistance of the gate insulating film is reduced.

[0005] On the other hand, if screening is not performed after the manufacturing process is completed, it is impossible to screen for process damage after screening in the middle of manufacturing.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent No. 6304445 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] In view of the above problems, an object of the present invention is to provide an insulated gate semiconductor device and a method for manufacturing the same, which can suppress an increase in man-hours and can screen for defects in a gate insulating film of a dummy trench independently of a gate insulating film of a gate trench.

[0011] Solutions for solving problems

[0012] The main purpose of one embodiment of the present invention is an insulated gate type semiconductor device, comprising: (a) a charge transfer region of a first conductivity type; (b) an injection control region of a second conductivity type on the charge transfer region; (c) a main charge supply region of the first conductivity type on the injection control region; (d) a dummy electrode, which is buried in a dummy trench that penetrates the main charge supply region and the injection control region and reaches the charge transfer region through a gate insulating film; (e) a gate electrode, which is buried in a gate trench that penetrates the main charge supply region and the injection control region and reaches the charge transfer region through a gate insulating film; (f) a first interlayer insulating film on the gate electrode; and (g) a second interlayer insulating film on the dummy electrode, wherein the first interlayer insulating film has a stacked structure of multiple insulating films, and the insulating film of the first interlayer insulating film is one or more layers more than the insulating film of the second interlayer insulating film.

[0013] The main purpose of another embodiment of the present invention is a method for manufacturing an insulated gate type semiconductor device, comprising the following steps: (a) forming an injection control region of a second conductivity type on a charge transfer region of a first conductivity type; (b) forming a main charge supply region of a first conductivity type on the injection control region; (c) digging a gate trench and a dummy trench in a manner that penetrates the main charge supply region and the injection control region; (d) burying a dummy electrode in the dummy trench through a gate insulating film, and burying a gate electrode in the gate trench through the gate insulating film; (e) selectively forming an inspection insulating film in a manner that exposes the dummy electrode and covers the gate electrode; (f) depositing an inspection conductive film on the dummy electrode and the inspection insulating film; and (g) applying a voltage between the inspection conductive film and the charge transfer region, thereby selectively inspecting the insulating properties of the gate insulating film in the dummy trench.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide an insulated gate semiconductor device and a method for manufacturing the same, which can suppress an increase in man-hours and can screen for defects in a gate insulating film of a dummy trench independently of a gate insulating film of a gate trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a plan view showing an example of an insulated gate semiconductor device according to the embodiment.

[0017] Figure 2 is from Figure 1 The cross-sectional view is obtained by observing from the AA′ direction.

[0018] Figure 3 is from Figure 1 Cross-sectional view obtained by observing from the BB′ direction.

[0019] Figure 4The diagram is a cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to the embodiment.

[0020] Figure 5 Then Figure 4 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0021] Figure 6 Then Figure 5 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0022] Figure 7 Then Figure 6 A plan view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0023] Fig. 8A Then Figure 7 A plan view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0024] Figure 8B is from Fig. 8A This is a process cross-sectional view obtained by observing from the AA′ direction.

[0025] Fig. 9 Then Fig. 8A and Figure 8B A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0026] Fig.10 Then Fig. 9 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0027] Fig.11 Then Fig.10 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0028] Fig.12 Then Fig.11 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0029] Fig.13 Then Fig.12 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0030] Fig.14 Then Fig.13A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0031] Fig.15 Then Fig.14 A cross-sectional view showing a process of an example of a method for manufacturing an insulated gate semiconductor device according to an embodiment.

[0032] Fig.16 The diagram is a cross-sectional view showing a process of manufacturing an insulated gate semiconductor device according to a comparative example.

[0033] Fig.17 Then Fig.16 4 is a cross-sectional view showing a process of a method for manufacturing an insulated gate semiconductor device according to a comparative example.

[0034] Description of Reference Numerals

[0035] 1: semiconductor substrate (charge transfer area); 2: injection control area; 3a, 3b, 3c, 3d: main charge supply area (emitter area); 3A, 3B: electrode area predetermined layer; 6: gate insulating film; 8: field stop layer; 9: main charge receiving area (collector area); 10: main charge receiving electrode (collector electrode); 11: inspection insulating film; 12: connection insulating film; 13: upper insulating film; 14: gate surface wiring; 14a~14d: connection area; 15: main charge supply electrode (emitter electrode); 16: etching Protective film; 20: Conductive film for inspection; 21: Power supply; 22: Stage; 23: Probe; 31a~31j, 32a~32h: Contact holes; 41~44: Dummy grooves; 51, 52: Gate grooves; 71: Gate electrode; 72: Dummy electrode; 100: Semiconductor substrate; 101: Gate groove; 102: Dummy groove; 103: Gate insulating film; 104: Conductive film; 111: Gate electrode; 112: Dummy electrode; 511, 512, 521, 522: Strip portions; 513, 523: Connecting portions. DETAILED DESCRIPTION

[0036] The following is an explanation of the implementation mode with reference to the accompanying drawings. In the description of the accompanying drawings referred to in the following description, the same or similar parts are marked with the same or similar symbols. However, it should be noted that the accompanying drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are different from the actual situation. Therefore, the specific thickness and size should be determined with reference to the following description. In addition, it goes without saying that the accompanying drawings also include parts with different size relationships and ratios.

[0037] In this specification, the "main charge supply region" of an insulated gate semiconductor device refers to a region for supplying carriers constituting the main current, and refers to a semiconductor region that serves as either the emitter region or the collector region in an insulated gate bipolar transistor (IGBT). In an insulated gate field effect transistor (MISFET) or an insulated gate static induction transistor (MISSIT), it refers to a semiconductor region that serves as either the source region or the drain region. In addition, in an insulated gate thyristor such as a MIS-controlled static induction thyristor (SI thyristor), it refers to a semiconductor region that serves as either the anode region or the cathode region. "Main charge receiving region" refers to a region that receives the majority carriers constituting the main current, and refers to a semiconductor region that serves as either the source region or the drain region in a MISFET or a MISSIT, but does not serve as the above-mentioned main charge supply region. In an IGBT, it refers to a region that serves as either the emitter region or the collector region, but does not serve as the above-mentioned main charge supply region. In a MIS-controlled SI thyristor, etc., it refers to a semiconductor region that serves as either the anode region or the cathode region, but does not serve as the above-mentioned main charge supply region. Furthermore, in a semiconductor device that performs bipolar operation such as an IGBT, minority carriers having charges opposite to those of majority carriers constituting a main current may be supplied from a “main charge receiving region”.

[0038] Like this, if the "main charge supply region" is the source region, the "main charge receiving region" refers to the drain region, and the "main current" flows between the main charge supply region and the main charge receiving region. For example, in the case of IGBT, the collector current is equivalent to the main current, and if the "main charge supply region" is the emitter region, the "main charge receiving region" refers to the collector region. If the "main charge supply region" is the anode region, the "main charge receiving region" refers to the cathode region. There is the following situation: if the bias relationship is interchanged, in the case of MISFET, etc., the function of the "main charge supply region" and the function of the "main charge receiving region" can be interchanged. Moreover, the electrode electrically connected to the main charge supply region through an ohmic contact or the like is defined as a "main charge supply electrode", and the electrode electrically connected to the main charge receiving region through an ohmic contact or the like is defined as a "main charge receiving electrode". In addition, a plug (Plug) and a silicide layer for connection may be included between the main charge supply region and the main charge supply electrode, and between the main charge receiving region and the main charge receiving electrode.

[0039] In addition, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type is exemplified. However, the conductivity type can also be selected to be in an opposite relationship, with the first conductivity type being set to p-type and the second conductivity type being set to n-type. In addition, the "+" and "-" attached to "n" and "p" respectively refer to semiconductor regions with relatively high or relatively low impurity concentrations compared to semiconductor regions without "+" and "-". However, even if the semiconductor regions are marked with the same "n" and "n", it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0040] In addition, the definitions of up and down directions in the following description are only for convenience of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, up and down are converted to left and right to read, and if it is rotated 180° to observe, up and down are reversed to read, which is self-evident.

[0041] <Insulated Gate Type Semiconductor Device>

[0042] An IGBT having a trench gate structure is exemplified as the insulated gate semiconductor device according to the embodiment. The insulated gate semiconductor device according to the embodiment may be, for example, a reverse conducting IGBT (RC-IGBT) in which an IGBT and a freewheeling diode (FWD) are integrated into one chip.

[0043] like Figure 1 As shown in FIG. 1 , the insulated gate semiconductor device according to the embodiment includes gate trenches 51 and 52 and dummy trenches 41, 42, 43, and 44. Figure 1 In FIG. 1 , for convenience, the interlayer insulating film, the main charge supply electrode (emitter electrode), the protective film, etc., which are arranged on the gate trenches 51 and 52 and the dummy trenches 41 to 44 are omitted. Figure 1 In the figure, for convenience, the gate surface wiring 14 and gate trenches 51 and 52 located under the inspection insulating film 11 are schematically shown by dotted lines. In addition, dummy trenches 41, 42, 43 and 44 located under the connection regions 14a, 14b, 14c and 14d are schematically shown by dotted lines.

[0044] exist Figure 1 Although the lower ends of the dummy grooves 41 to 44 are omitted, the dummy grooves 41 to 44 have a flat O-shaped plane pattern formed by connecting the upper ends and lower ends of two strips extending parallel to each other. The dummy grooves 41 to 44 are periodically arranged in a manner that the two strips of each of the dummy grooves 41 to 44 are arranged parallel to each other. In addition, there is no particular limitation on the number, width, length of the strips, etc. of the dummy grooves 41 to 44. The dummy grooves 41 to 44 may also have an I-shaped plane pattern instead of the O-shaped plane pattern.

[0045] The gate trenches 51 and 52 have a flat O-shaped planar pattern so as to surround the periphery of the dummy trenches 42 and 44. The gate trench 51 has stripes 511 and 512 extending in parallel with the stripes of the dummy trenches 41 to 44, and a connecting portion 513 connecting the adjacent stripes 511 and 512. The gate trench 52 has stripes 521 and 522 extending in parallel with the stripes of the dummy trenches 41 to 44, and a connecting portion 523 connecting the adjacent stripes 521 and 522.

[0046] In addition, there is no particular limitation on the number and width of the gate trenches 51 and 52, and the lengths of the strips 511, 512, 521, and 522 of the gate trenches 51 and 52. The widths of the gate trenches 51 and 52 may be the same as or different from the widths of the dummy trenches 41 to 44. The gate trenches 51 and 52 may also be formed as a zigzag line that snakes between the dummy trenches 41 to 44 instead of an O-shaped plane pattern, and the zigzag line is formed by connecting the U-shaped plane pattern in reverse.

[0047] The gate surface wiring 14 is arranged on the connection parts 513 and 523 of the gate trenches 51 and 52. At the ends of each of the dummy trenches 41 to 44, connection regions 14a to 14d are provided in a manner separated from the gate surface wiring 14. The gate surface wiring 14 and the connection regions 14a to 14d are formed of, for example, polysilicon (doped polysilicon (DOPOS)) to which impurities such as phosphorus (P) are added at a high impurity concentration.

[0048] Figure 2 is from Figure 1 The cross-sectional view is obtained by observing the AA′ direction. Figure 2 As shown, the insulated gate semiconductor device according to the embodiment includes a first conductivity type (n - The charge transport region 1 is a semiconductor region that can transport carriers (electrons) that become the main current by utilizing the drift electric field. An injection control region (base region) 2 that is a body region of the second conductivity type (p type) is provided on the upper portion of the charge transport region 1. The injection control region 2 is a semiconductor region that controls the carriers injected into the charge transport region 1. An impurity concentration higher than that of the charge transport region 1 is provided on the upper portion of the injection control region 2. + Type main charge supply regions (emitter regions) 3a, 3b, 3c, 3d.

[0049] Although not shown in the figure, a second conductivity type (p 2 ) may be provided on the upper portion of the injection control region 2 so as to be in contact with the main charge supply regions 3a to 3d. + For example, the main charge supply regions 3a to 3d and the contact regions may be connected to Figure 1The strip portions 511 , 512 , 521 , 522 of the illustrated gate trenches 51 , 52 extend in parallel and are periodically alternately arranged.

[0050] like Figure 2 As shown, dummy trenches 42 and gate trenches 51 are provided from the upper surface of the main charge supply regions 3a to 3d to penetrate the main charge supply regions 3a to 3d and the injection control region 2 and reach the upper part of the charge transfer region 1. The dummy trenches 42 and gate trenches 51 have substantially the same depth.

[0051] A gate insulating film 6 is provided on the bottom surface and the side surface of the dummy trench 42 and the gate trench 51. As the gate insulating film 6, in addition to being able to use a silicon oxide film (SiO2 film), it is also possible to use a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, or a composite film formed by stacking a plurality of these single-layer films.

[0052] The gate insulating film 6 of the gate trench 51 functions as a gate film that electrostatically controls the surface potential of the channel in the injection control region 2 directly below the main charge supply region 3a to 3d. On the other hand, the gate insulating film 6 of the dummy trench 42 does not function as a gate film, but it is necessary to ensure a certain degree of insulation in the operation of the element. The portion that is most required to be insulating is the bottom region of the dummy trench 42 where the electric field is concentrated. In the gate insulating film 6 of the dummy trench 42, as in the gate insulating film 6 of the gate trench 51, it is also necessary to ensure reliability against the TDDB phenomenon in which insulation breakdown occurs over time. By applying voltage to screen for defects such as abnormal shapes of the dummy trench 42 and the gate trench 51 and deterioration of the film quality of the gate insulating film 6 between the dummy trench 42 and the gate trench 51 and the electrode, the reliability against TDDB can be improved.

[0053] A dummy electrode 72 is embedded in the inner side of the dummy trench 42 via the gate insulating film 6. The dummy electrode 72 has a function of reducing the capacitance between the gate and the collector that causes switching loss, for example. A gate electrode 71 is embedded in the inner side of the gate trench 51 via the gate insulating film 6. As the material of the dummy electrode 72 and the gate electrode 71, for example, DOPOS can be used. In addition, Figure 2 The dummy trenches 41, 43 and 44 shown also have the same structure as the dummy trench 42. Figure 2 The gate trench 52 shown also has the same structure as the gate trench 51 .

[0054] like Figure 2 As shown in FIG. 1 , an interlayer insulating film (11, 12, 13) is provided on the gate electrode 71. The interlayer insulating film (11, 12, 13) on the gate electrode 71 has a three-layer structure including an inspection insulating film 11, a connection insulating film 12 provided on the inspection insulating film 11, and an upper insulating film 13 provided on the connection insulating film 12. On the other hand, an interlayer insulating film (12, 13) is provided on the dummy electrode 72. The interlayer insulating film (12, 13) on the dummy electrode 72 has a two-layer structure including a connection insulating film 12 and an upper insulating film 13 provided on the connection insulating film 12, without the inspection insulating film 11. That is, the interlayer insulating film (11, 12, 13) on the gate electrode 71 has a stacked structure of multiple insulating films, and the insulating film of the interlayer insulating film (11, 12, 13) on the gate electrode 71 is one or more layers greater than the insulating film of the interlayer insulating film (12, 13) on the dummy electrode 72.

[0055] For example, the thickness of the inspection insulating film 11 on the gate electrode 71 is about 50nm to 100nm, the thickness of the connection insulating film 12 on the gate electrode 71 and the dummy electrode 72 is about 50nm to 100nm, and the thickness of the upper insulating film 13 on the gate electrode 71 and the dummy electrode 72 is about 50nm to 100nm.

[0056] In addition, it is not necessary to provide the upper insulating film 13 on the gate electrode 71 and the dummy electrode 72. In the case where the upper insulating film 13 is not provided, the interlayer insulating film (11, 12) on the gate electrode 71 becomes a two-layer structure having the inspection insulating film 11 and the connection insulating film 12 provided on the inspection insulating film 11, while the interlayer insulating film 12 on the dummy electrode 72 becomes a single-layer structure having the connection insulating film 12.

[0057] The test insulating film 11 is provided to Figure 1 The gate trenches 51, 52 and the gate surface wiring 14 are shown. Figure 1 Omitted Figure 2 The illustration of the connection insulating film 12 and the upper insulating film 13 is shown, but Figure 2 The connection insulating film 12 and the upper insulating film 13 shown are provided on the entire upper surface of the semiconductor substrate 1. Figure 1 The illustration of the connecting insulating film 12 and the upper insulating film 13 is omitted, but Figure 1 As schematically shown by the single-dot chain lines in FIG. 1 , contact holes 31 a to 31 j and contact holes 32 a to 32 h are formed in the connection insulating film 12 and the upper insulating film 13 .

[0058] As the test insulating film 11, the connection insulating film 12, and the upper insulating film 13, a high temperature oxide film (HTO film), a non-doped silicon oxide (SiO2) film called "NSG" that does not contain phosphorus (P) and boron (B) can be used. In addition, as the test insulating film 11, the connection insulating film 12, and the upper insulating film 13, a phosphorus-added silicon oxide (PSG) film, a boron-added silicon oxide (BSG) film, a boron- and phosphorus-added silicon oxide (BPSG) film, and a silicon nitride (Si3N4) film can also be used. In addition, as the test insulating film 11, the connection insulating film 12, and the upper insulating film 13, a stack of these films that can be used can also be used. The materials of the test insulating film 11, the connection insulating film 12, and the upper insulating film 13 can be the same as each other, or different from each other. For example, the test insulating film 11 and the connection insulating film 12 can be formed of an HTO film, and the upper insulating film 13 can be a BPSG film that can be reflowed.

[0059] A main charge supply electrode (emitter electrode) 15 is disposed on the upper insulating film 13. The main charge supply electrode 15 is electrically connected or metallically bonded to the main charge supply regions 3a to 3d and the like via contact holes 31a to 31j opened in the connecting insulating film 12 and the upper insulating film 13.

[0060] like Figure 1 As shown, connection areas 14a, 14b, 14c, and 14d are arranged at the ends of the dummy trenches 41 to 44. The dummy trenches 41 to 44 are electrically connected to the main charge supply electrode 15 via contact holes 32a to 32h opened in the connection insulating film 12 and the upper insulating film 13 located on the connection areas 14a to 14d. Figure 1 In FIG. 1 , the positions of the contact holes 32 a to 32 h are schematically shown by single-dot chain lines.

[0061] Gate surface wiring 14 is disposed on connection portions 513, 523 of gate trenches 51, 52 so as to be in contact with connection portions 513, 523. Gate surface wiring 14 is electrically insulated and separated from dummy trenches 41-44, and dummy trenches 41-44 do not contribute to channel formation.

[0062] Figure 3 is from Figure 1 The cross-sectional view is obtained by observing the BB′ direction. Figure 3 As shown, on the injection control region 2, the gate surface wiring 14 is provided separately from the connection region 14c. The inspection insulating film 11 is provided to cover the gate surface wiring 14. The connection insulating film 12 and the upper insulating film 13 are provided on the inspection insulating film 11 and the connection region 14c.

[0063] exist Figure 2 The charge transport region 1 shown is provided with n+ A field stop layer 8 of the type may be provided. In addition, a buffer layer may be provided instead of the field stop layer 8, or a non-penetrating structure may be provided without the field stop layer 8. A p + A main charge receiving region (collector region) 9 of the type is provided, and a main charge receiving electrode (collector electrode) 10 is arranged under the collector region 9. As the main charge receiving electrode 10, for example, a single layer film formed of gold (Au) or a metal film in which Al, nickel (Ni), and Au are stacked in this order can be used.

[0064] When the insulated gate semiconductor device according to the embodiment operates, a positive voltage is applied to the main charge receiving electrode 10, and a positive voltage above the threshold is applied to the gate electrode 71 while the main charge supply electrode 15 is grounded. As a result, the surface potential of the injection control region 2 facing the gate trench 51 is electrostatically controlled via the gate insulating film 6, thereby forming a channel and the IGBT is turned on. In the on state, electrons as majority carriers are injected from the main charge supply regions 3a to 3d into the charge transfer region 1, and holes as minority carriers are injected from the collector region 9 into the charge transfer region 1. The holes and electrons injected into the charge transfer region 1 cause conductivity modulation, and the resistance in the charge transfer region 1 decreases. At this time, since the dummy electrode 72 is disposed adjacent to the gate electrode 71 and grounded, a part of the gate-collector capacitance (feedback capacitance) is replaced by the collector-emitter capacitance, so that the feedback capacitance is reduced and the switching speed is improved.

[0065] On the other hand, when the voltage applied to the gate electrode 71 is less than the threshold value, the channel of electrons formed in the injection control region 2 disappears, and the IGBT becomes off. In the off state, the electrons accumulated in the charge transfer region 1 are discharged from the collector region 9, and the holes accumulated in the charge transfer region 1 are discharged from the contact region.

[0066] <Method for Manufacturing Insulated Gate Type Semiconductor Device>

[0067] Next, refer to Figures 4 to 15 An example of a method for manufacturing an insulated gate type semiconductor device according to an embodiment including a screening method for an insulated gate type semiconductor device according to an embodiment is described below. Figure 2 A cross section showing the dummy trench 42 and the gate trench 51 is shown for illustration.

[0068] First, prepare n - A semiconductor substrate 1 formed of Si of type 1 is used as a base portion (refer to Figure 2). Next, p-type impurity ions are ion-implanted into the entire upper surface of the semiconductor substrate 1. Thereafter, heat treatment is performed to activate the p-type impurity ions and turn them into p-type impurities, and the p-type impurities are thermally diffused to the diffusion depth required to serve as the injection control region 2. In addition, the injection control region 2 can also be formed by epitaxial growth on the upper surface of the semiconductor substrate 1. Next, a photoresist film is coated on the upper surface of the injection control region 2, and the photoresist film is patterned using photolithography technology. The patterned photoresist film is used as a mask for ion implantation, and n-type impurity ions are selectively ion-implanted into the upper surface of the injection control region 2. Thereafter, heat treatment is performed to activate the n-type impurity ions and thermally diffuse them. As a result, as shown in FIG. Figure 4 As shown, n is formed on the upper part of the injection control region 2. + The electrode area of ​​the type is predetermined with layers 3A and 3B.

[0069] Next, an etching protection film 16 such as an oxide film is formed on the upper surface of the injection control region 2 and the electrode region predetermined layers 3A and 3B by chemical vapor deposition (CVD) or the like. Then, the etching protection film 16 is patterned using photolithography and dry etching such as reactive ion etching (RIE). The patterned etching protection film 16 is used as an etching mask, such as Figure 5 As shown, the dummy trench 42 and the gate trench 51 are selectively formed by dry etching such as RIE. Figure 4 The electrode area predetermined layers 3A, 3B are shown separated into Figure 5 The main charge supply regions (emitter regions) 3a to 3d are shown. The dummy trenches 42 and the gate trenches 51 penetrate the main charge supply regions 3a to 3d and the injection control region 2 and reach the upper part of the semiconductor substrate 1. At this time, similarly to the dummy trenches 42 and the gate trenches 51, Figure 1 The dummy trenches 41, 43, 44 and the gate trench 52 are shown. Afterwards, the etching protection film 16 is removed.

[0070] Next, a gate insulating film 6 such as a SiO2 film is formed on the bottom and side surfaces of the dummy trench 42 and the gate trench 51, and the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d by a thermal oxidation method or a CVD method. Next, a conductive film (embedded conductive film) such as a DOPOS layer (first DOPOS film) is deposited by a CVD method to fill the dummy trench 42 and the gate trench 51. Thereafter, the embedded conductive film and the gate insulating film 6 on the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d are removed by etch back or chemical mechanical polishing (CMP), thereby exposing the upper surfaces of the injection control region 2 and the main charge supply regions 3a to 3d. As a result, Figure 6As shown, a dummy electrode 72 and a gate electrode 71 formed of an embedding conductive film are embedded in the dummy trench 42 and the gate trench 51 via the gate insulating film 6 .

[0071] Next, a pattern-forming conductive film formed of a new DOPOS film (second DOPOS film) is deposited by CVD or the like. Then, the pattern-forming conductive film is patterned using photolithography and dry etching such as RIE, thereby forming a conductive film. Figure 7 As shown, the gate surface wiring 14 and the connection areas 14a to 14d are formed. The connection areas 14a to 14d are partially formed on the ends of the dummy trenches 41 to 44 in such a manner as to be in contact with the dummy trenches 41 to 44. The gate surface wiring 14 is formed to be separated from the connection areas 14a to 14d and to be in contact with the connection parts 513 and 523 on the connection parts 513 and 523 of the gate trenches 51 and 52.

[0072] Next, a test insulating film 11 such as an HTO film is deposited on the upper surfaces of the dummy electrode 72, the gate electrode 71, the injection control region 2, and the main charge supply regions 3a to 3d by CVD or the like. Then, the test insulating film 11 is patterned by photolithography and dry etching. As a result, Fig. 8A As shown, the test insulating film 11 is formed to cover the gate surface wiring 14 and the gate trenches 51 and 52. The upper surfaces of the connection regions 14a to 14d and the dummy trenches 41 to 44 are exposed from the opening of the test insulating film 11.

[0073] Figure 8B is from Fig. 8A The process cross-sectional view is obtained by observing the AA' direction. Figure 8B As shown, the upper surface of the gate electrode 71 is covered with the test insulating film 11. The upper surface of the dummy electrode 72 is not covered with the test insulating film 11 and is exposed.

[0074] Then, if Fig. 9 As shown, the inspection conductive film 20 formed of a third DOPOS film or the like is formed by CVD or the like on the entire upper surface of the dummy electrode 72 , the injection control region 2 , and the main charge supply regions 3 a to 3 d .

[0075] Next, the insulating property of the gate insulating film 6 of the dummy trench 42 is inspected independently of the gate insulating film 6 of the gate trench 51 by using the inspection conductive film 20 deposited on the entire surface, thereby screening only the gate insulating film 6 of the dummy trench 42. Specifically, Fig.10As shown, the lower surface of the semiconductor substrate 1 is arranged on a conductive stage 22. Then, the negative side of the power supply 21 is electrically connected to the stage 22, and the tip of the probe 23 electrically connected to the positive side of the power supply 21 is crimped to the conductive film 20 for inspection. In this state, the power supply applies a voltage higher than that in normal operation between the conductive film 20 for inspection and the lower surface of the semiconductor substrate 1 to perform a dummy gate impact test. The dummy gate impact test is an accelerated test for evaluating the TDDB phenomenon. The dummy gate impact test is performed by applying a voltage (for example, about 4MV / cm) higher than the normal voltage (for example, about 2MV / cm) applied between the conductive film 20 for inspection and the lower surface of the semiconductor substrate 1. Thereafter, the current flowing between the conductive film 20 for inspection and the lower surface of the semiconductor substrate 1 is measured. When the leakage current between the conductive film 20 for inspection and the lower surface of the semiconductor substrate 1 is greater than the reference value, it can be determined that the gate insulating film 6 has deteriorated in film quality, so the insulation characteristics of the gate insulating film 6 can be inspected.

[0076] Next, the inspection conductive film 20 is removed. Fig.11 As shown, a connection insulating film 12 such as an HTO film is deposited on the entire upper surface of the semiconductor substrate 1, that is, the upper surfaces of the dummy electrode 72, the inspection insulating film 11, the injection control region 2, and the main charge supply regions 3a to 3d by a CVD method or the like. The material of the connection insulating film 12 may be the same as or different from that of the inspection insulating film 11. In addition, the inspection insulating film 11 may be removed before the connection insulating film 12 is deposited.

[0077] Then, if Fig.12 As shown, an upper insulating film 13 such as a BPSG film is deposited on the entire upper surface of the connecting insulating film 12 by a CVD method or the like. The material of the upper insulating film 13 may be the same as or different from that of the inspection insulating film 11 and the connecting insulating film 12. In addition, the upper insulating film 13 may not necessarily be formed.

[0078] Next, a portion of the connection insulating film 12 and the upper insulating film 13 is selectively removed by photolithography and dry etching. Thus, contact holes are formed in the connection insulating film 12 and the upper insulating film 13, exposing the upper surfaces of the main charge supply regions 3a to 3d. Alternatively, contact holes may be formed only in the connection insulating film 12 without forming the upper insulating film 13. Alternatively, contact holes may be formed in the connection insulating film 12 and the upper insulating film 13, exposing the upper surfaces of the main charge supply regions 3a to 3d. Fig. 8A The upper surfaces of the connection areas 14a-14d are shown exposed.

[0079] Next, a metal layer such as an Al film is deposited on the entire surface of the upper insulating film 13, the main charge supply regions 3a to 3d, and the connection regions 14a to 14d by sputtering or evaporation. Then, the Al film or other metal layer is patterned by photolithography and dry etching such as RIE. Fig.14 As shown, a main charge supply electrode 15 is formed to make ohmic contact with the main charge supply regions 3a to 3d via the contact hole.

[0080] Next, the thickness of the semiconductor substrate 1 is adjusted by CMP or the like. Then, p-type impurity ions are ion-implanted into the lower surface of the semiconductor substrate 1. In addition, n-type impurity ions are ion-implanted into the lower surface of the semiconductor substrate 1 with a projection range deeper than that of the ion implantation of p-type impurity ions. After that, the implanted impurity ions are activated and thermally diffused by heat treatment, thereby Fig.15 As shown, forming n + Type field stop layer 8 and p + In addition, the field stop layer 8 and the collector region 9 may also be formed by epitaxial growth in sequence on the lower surface of the semiconductor substrate 1.

[0081] Then, if Figure 2 As shown, a main charge receiving electrode 10 made of Au or the like is formed on the lower surface of the collector region 9 by sputtering or evaporation. Thereafter, the semiconductor wafer is divided into a plurality of semiconductor chips by dicing, and the insulated gate semiconductor device according to the embodiment is completed.

[0082] After that, a gate impact test is performed for each semiconductor chip to check the insulation characteristics of the gate insulating film 6 in the gate trenches 51 and 52, thereby screening for defects in the gate insulating film 6 in the gate trenches 51 and 52. This screening is the first gate impact test for the gate insulating film 6 in the gate trenches 51 and 52.

[0083] According to the manufacturing method of the insulated gate type semiconductor device involved in the embodiment, by inspecting the insulation characteristics of the gate insulating film 6 of the dummy trenches 41 to 44, the quality of the gate insulating film 6 of the dummy trenches 41 to 44 can be appropriately guaranteed. At this time, by covering the gate trenches 51 and 52 with the inspection insulating film 11, the insulation characteristics of the gate insulating film 6 of the dummy trenches 41 to 44 can be inspected independently of the gate insulating film 6 of the gate trenches 51 and 52. As a result, the influence that will be caused to the gate insulating film 6 of the gate trenches 51 and 52 can be eliminated. In addition, the insulation characteristics required for the gate insulating film 6 of the dummy trenches 41 to 44 are lower than the insulation characteristics required for the gate insulating film 6 of the gate trenches 51 and 52, so the voltage value applied in the screening test can be relaxed in accordance with the resistance required for the gate insulating film 6 of the dummy trenches 41 to 44. Therefore, the defect generation rate can be reduced, and the amount of particle generation when the defect occurs can be suppressed, so that the contamination of the process environment can be suppressed. On the other hand, the gate insulating film 6 of the gate trenches 51 and 52 can be inspected for insulation properties by a gate impact test after the process is completed, thereby also screening for damage during the process.

[0084] <Comparative Example>

[0085] Next, a screening method for an insulated gate type semiconductor device according to a comparative example is described. In the screening method for an insulated gate type semiconductor device according to the comparative example, Fig.16 As shown, a gate trench 101 and a dummy trench 102 are formed on an upper portion of a semiconductor substrate 100. Then, a gate electrode 111 is embedded in the gate trench 101 via a gate insulating film 103. A dummy electrode 112 is embedded in the dummy trench 102 via a gate insulating film 103.

[0086] Then, if Fig.17As shown, the conductive film 104 is formed over the entire surface of the gate electrode 111 and the dummy electrode 112. Then, the lower surface of the semiconductor substrate 100 is arranged on the conductive stage 22. Then, the negative side of the power supply 21 is electrically connected to the stage 22, and the tip of the probe 23 electrically connected to the positive side of the power supply 21 is pressed against the conductive film 104. In this state, the power supply applies a voltage higher than that in the normal operation between the conductive film 104 and the lower surface of the semiconductor substrate 1 to perform the gate impact test. That is, the gate insulating film 6 is tested simultaneously over the entire trenches of the gate trench 101 and the dummy trench 102, so it is necessary to apply a relatively large voltage during the test, and a large amount of particles are generated when a defective element is broken. In contrast, in the screening method of the insulated gate type semiconductor device involved in the embodiment of the present invention, since the inspection insulating film 11 covers the gate trenches 51 and 52, it is possible to independently screen only the gate insulating film 6 of the dummy trenches 41 to 44, and the amount of particles generated can be suppressed.

[0087] (Other embodiments)

[0088] As described above, the present invention is described through the embodiments, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application technologies can be clearly identified by those skilled in the art.

[0089] For example, although a trench gate IGBT is exemplified as the insulated gate semiconductor device according to the embodiment, the present invention is not limited thereto and can be applied to various insulated gate semiconductor devices such as a trench gate MISFET.

[0090] In the description of the insulated gate type semiconductor device involved in the embodiment, an insulated gate type semiconductor device using Si is exemplified. However, in addition to being applicable to the insulated gate type semiconductor device using Si, it can also be applied to an insulated gate type semiconductor device using a semiconductor material (wide bandgap semiconductor) having a wider bandgap width than Si, such as silicon carbide (SiC), gallium nitride (GaN), diamond or aluminum nitride (AlN).

[0091] As described above, it is needless to say that the present invention includes various embodiments and the like that are not described here. Therefore, the technical scope of the present invention is determined only by the inventive features according to the claims that are appropriately derived from the above description.

Claims

1. An insulated gate semiconductor device, characterized in that: have: a charge transport region of a first conductivity type; an injection control region of the second conductivity type on the charge transport region; a main charge supply region of the first conductivity type on the injection control region; a dummy electrode embedded in a dummy trench penetrating the injection control region and reaching the charge transfer region via a gate insulating film; a gate electrode embedded in a gate trench penetrating the main charge supply region and the injection control region and reaching the charge transfer region via the gate insulating film; a first interlayer insulating film on the gate electrode; as well as The second interlayer insulating film on the dummy electrode, The first interlayer insulating film has a stacked structure of a plurality of insulating films, and the insulating film of the first interlayer insulating film has one or more layers than the insulating film of the second interlayer insulating film. The first interlayer insulating film is formed of a stacked structure including an inspection insulating film on the gate electrode and a connection insulating film on the inspection insulating film, and the second interlayer insulating film includes the connection insulating film on the dummy electrode. The connecting insulating film that is the first layer of the second interlayer insulating film from the dummy electrode side is in contact with the upper surface of the dummy electrode and is shared with the connecting insulating film that is the second layer of the first interlayer insulating film from the gate electrode side.

2. The insulated gate semiconductor device according to claim 1, wherein: The stacked structure of the first interlayer insulating film further includes an upper insulating film on the connecting insulating film. The second interlayer insulating film is formed of a stacked structure of the connecting insulating film and the upper insulating film on the dummy electrode.

3. The insulated gate semiconductor device according to claim 2, wherein: The inspection insulating film and the connection insulating film are formed of the same material as each other.

4. A method for manufacturing an insulated gate type semiconductor device, characterized in that: Including the following processes: forming an injection control region of a second conductivity type on the charge transport region of the first conductivity type; forming a main charge supply region of a first conductivity type on the injection control region; digging a gate trench in a manner penetrating the main charge supply region and the injection control region, and digging a dummy trench in a manner penetrating the injection control region; burying a dummy electrode in the dummy trench via a gate insulating film, and burying a gate electrode in the gate trench via the gate insulating film; selectively forming an inspection insulating film so as to expose the dummy electrode and cover the gate electrode; depositing a conductive film for inspection on the dummy electrode and the insulating film for inspection; as well as A voltage is applied between the inspection conductive film and the charge transfer region, thereby selectively inspecting the insulation characteristics of the gate insulating film in the dummy trench.

5. The method for manufacturing an insulated gate semiconductor device according to claim 4, wherein: After the inspection step, the method further includes removing the inspection conductive film.

6. The method for manufacturing an insulated gate semiconductor device according to claim 5, wherein: After the step of removing the conductive film for inspection, the following step is further included: depositing a connection insulating film so as to cover the inspection insulating film; Opening a contact hole in the connecting insulating film; as well as A main charge supply electrode is formed to be electrically connected to the main charge supply region via the contact hole.

7. The method for manufacturing an insulated gate semiconductor device according to claim 5, wherein: After the step of removing the conductive film for inspection, the following step is further included: depositing a connection insulating film so as to cover the inspection insulating film; depositing an upper insulating film so as to cover the connecting insulating film; Opening contact holes in the connection insulating film and the upper insulating film; as well as A main charge supply electrode is formed to be electrically connected to the main charge supply region via the contact hole.

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