A negative charge compensation circuit for an integrating capacitor

Abstract

The present invention discloses an integrating capacitor negative charge compensation circuit. The circuit includes an integrator circuit, a first integrating capacitor switch and a first preset bias circuit; the first integrating capacitor switch is connected in series with the integrating capacitor in the integrator circuit, and the first preset bias circuit is connected in parallel to both ends of the integrating capacitor. The first integrating capacitor switch is used to isolate the integrating capacitor from the amplifier in the integrator circuit when there is no input charge, and to connect the integrating capacitor to the amplifier in the integrator circuit when there is input charge; the first preset bias circuit is used to apply negative charge to the integrating capacitor when there is no input charge. By adopting the circuit of the present invention, by pre-biasing the integrating capacitor and pre-storing negative charge on the capacitor, a smaller integrating capacitor under the same input dynamic range or a larger input dynamic range under the same size of integrating capacitor can be realized, and an integrator with a larger input dynamic range can be realized when the size of the capacitor is limited by the area of ​​the integrated circuit layout.

Description

Technical Field

[0001] The invention relates to the technical field of integrator circuits, and in particular to an integrating capacitor negative charge compensation circuit. Background Art

[0002] Active integrator is a circuit that relies on capacitors to convert charge into voltage through charge integration, thereby realizing charge detection. The traditional integrator circuit consists of an operational amplifier and an integrating capacitor connected between the input and output terminals of the operational amplifier, such as Figure 1 shown. Figure 1 In the figure, the integral capacitor value in the integrator circuit is Cf, and the open-loop gain of the operational amplifier is Af. The input charge is Qin, and the change in output voltage relative to the baseline is taken as ΔUout. If the op amp is an ideal op amp, ΔUout = Qin / Cf. The relationship between the maximum charge input, i.e., the input dynamic range Qin,max, and the output swing ΔUout,max is ΔUout,max = Qin,max / Cf. The output voltage swing is usually limited by the power supply voltage. If you want to increase the input range Qin,max, you can only increase the integral capacitor Cf. However, increasing the capacitance is limited in many cases, especially when the integrated circuit layout area is tight. Summary of the invention

[0003] The purpose of the present invention is to provide an integrating capacitor negative charge compensation circuit, which can achieve a smaller integrating capacitor under the same input dynamic range, or a larger input dynamic range under the same size of integrating capacitor by pre-biasing the integrating capacitor and pre-storing negative charge on the capacitor, and can achieve an integrator with a larger input dynamic range when the size of the capacitor is limited by the area of ​​the integrated circuit layout.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] An integral capacitor negative charge compensation circuit, comprising:

[0006] an integrator circuit, a first integrating capacitor switch and a first preset bias circuit;

[0007] The first integral capacitor switch is connected in series with the integral capacitor in the integrator circuit, and the first integral capacitor switch is used to isolate the integral capacitor from the amplifier in the integrator circuit when there is no input charge, and to connect the integral capacitor to the amplifier in the integrator circuit when there is input charge;

[0008] The first preset bias circuit is connected in parallel to both ends of the integration capacitor, and the first preset bias circuit is used to apply negative charge to the integration capacitor when there is no input charge.

[0009] Optionally, the first integral capacitor switch specifically includes:

[0010] a first switch and a second switch;

[0011] One end of the first switch is connected to the inverting input end of the amplifier, and the other end of the first switch is connected to the first end of the integrating capacitor;

[0012] The second end of the integrating capacitor is connected to one end of the second switch, and the other end of the second switch is connected to the output end of the amplifier;

[0013] The first switch and the second switch are both opened when there is no input charge, and the first switch and the second switch are both closed when there is input charge.

[0014] Optionally, the first preset bias circuit specifically includes:

[0015] A first plate, a second plate, a third switch and a fourth switch;

[0016] One end of the third switch is connected to the first electrode plate, and the other end of the third switch is connected to the first end of the integral capacitor;

[0017] One end of the fourth switch is connected to the second electrode plate, and the other end of the fourth switch is connected to the second end of the integral capacitor;

[0018] The third switch and the fourth switch are both closed when there is no input charge, and the third switch and the fourth switch are both opened when there is input charge.

[0019] Optionally, the positive input terminal of the amplifier is grounded.

[0020] Optionally, the bias voltage of the first electrode plate is smaller than the bias voltage of the second electrode plate.

[0021] The present invention also provides an integral capacitor negative charge compensation circuit, comprising:

[0022] an integrator circuit, an incremental range integrating capacitor, a second integrating capacitor switch, and a second preset bias circuit;

[0023] The incremental range integrating capacitor is connected between the inverting input terminal and the output terminal of the amplifier in the integrator circuit; the incremental range integrating capacitor is used to increase the range of charge measurement of the integrator circuit;

[0024] The second integral capacitor switch is connected in series with the incremental range integral capacitor, and the second integral capacitor switch is used to isolate the incremental range integral capacitor from the amplifier when the incremental range is not increased, and to connect the incremental range integral capacitor to the amplifier when the incremental range is increased;

[0025] The second preset bias circuit is connected in parallel to both ends of the incremental range integrating capacitor, and the second preset bias circuit is used to apply negative charge to the integrating capacitor when the incremental range is not increased.

[0026] Optionally, the second integral capacitor switch specifically includes:

[0027] a fifth switch and a sixth switch;

[0028] One end of the fifth switch is connected to the inverting input end of the amplifier, and the other end of the fifth switch is connected to the first end of the incremental range integrating capacitor;

[0029] The second end of the incremental range integrating capacitor is connected to one end of the sixth switch, and the other end of the sixth switch is connected to the output end of the amplifier;

[0030] The fifth switch and the sixth switch are both opened when the range is not increased, and the fifth switch and the sixth switch are both closed when the range is increased.

[0031] Optionally, the second preset bias circuit specifically includes:

[0032] a third plate, a fourth plate, a seventh switch, and an eighth switch;

[0033] One end of the seventh switch is connected to the third electrode plate, and the other end of the seventh switch is connected to the first end of the incremental range integrating capacitor;

[0034] One end of the eighth switch is connected to the fourth electrode plate, and the other end of the eighth switch is connected to the second end of the incremental range integrating capacitor;

[0035] The seventh switch and the eighth switch are both closed when the range is not increased, and the seventh switch and the eighth switch are both opened when the range is increased.

[0036] Optionally, the positive input terminal of the amplifier is grounded.

[0037] Optionally, the bias voltage of the third electrode plate is smaller than the bias voltage of the fourth electrode plate.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention proposes an integrating capacitor negative charge compensation circuit, including an integrator circuit, a first integrating capacitor switch and a first preset bias circuit; the first integrating capacitor switch is connected in series with the integrating capacitor in the integrator circuit, and the first preset bias circuit is connected in parallel to both ends of the integrating capacitor. The first integrating capacitor switch is used to isolate the integrating capacitor from the amplifier in the integrator circuit when there is no input charge, and to connect the integrating capacitor to the amplifier in the integrator circuit when there is input charge; the first preset bias circuit is used to apply negative charge to the integrating capacitor when there is no input charge. The present invention can achieve a smaller integrating capacitor under the same input dynamic range, or a larger input dynamic range under the same size of integrating capacitor by pre-biasing the integrating capacitor and pre-storing negative charge on the capacitor, and can achieve an integrator with a larger input dynamic range when the size of the capacitor is limited by the integrated circuit layout area.

[0040] The present invention also proposes an integral capacitor negative charge compensation circuit, including an integrator circuit, an incremental range integral capacitor, a second integral capacitor switch and a second preset bias circuit; the incremental range integral capacitor is connected between the reverse input terminal and the output terminal of the amplifier in the integrator circuit, the second integral capacitor switch is connected in series with the incremental range integral capacitor, and the second preset bias circuit is connected in parallel to both ends of the incremental range integral capacitor; the incremental range integral capacitor is used to increase the range of charge measurement of the integrator circuit, the second integral capacitor switch is used to isolate the incremental range integral capacitor from the amplifier when the range is not increased, and to connect the incremental range integral capacitor to the amplifier when the range is increased, and the second preset bias circuit is used to apply negative charge to the integral capacitor when the range is not increased. When the integrator circuit is used for multi-range charge measurement, the present invention can increase the output swing, isolate and pre-bias the integral capacitor before charge input, and pre-store negative charge on the capacitor, thereby achieving the purpose of increasing the input dynamic range or reducing the integral capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 It is a circuit diagram of an integrator in the prior art;

[0043] Figure 2 This is a circuit diagram of the negative charge compensation circuit of the integral capacitor in the first embodiment of the present invention;

[0044] Figure 3 This is a circuit diagram of the negative charge compensation circuit of the integral capacitor in the second embodiment of the present invention;

[0045] Figure 4This is a circuit diagram of a multi-range integrator in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The purpose of the present invention is to provide an integrating capacitor negative charge compensation circuit, which can achieve a smaller integrating capacitor under the same input dynamic range, or a larger input dynamic range under the same size of integrating capacitor by pre-biasing the integrating capacitor and pre-storing negative charge on the capacitor, and can achieve an integrator with a larger input dynamic range when the size of the capacitor is limited by the area of ​​the integrated circuit layout.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Embodiment 1

[0050] Figure 1 is the integrator circuit diagram, Figure 2 The circuit diagram of the negative charge compensation of the integral capacitor is as follows: Figure 1-2 As shown, an integral capacitor negative charge compensation circuit includes: an integrator circuit, a first integral capacitor switch and a first preset bias circuit. The first integral capacitor switch is connected in series with the integral capacitor in the integrator circuit, and the first integral capacitor switch is used to isolate the integral capacitor from the amplifier in the integrator circuit when there is no input charge, and connect the integral capacitor to the amplifier in the integrator circuit when there is input charge; the first preset bias circuit is connected in parallel at both ends of the integral capacitor, and the first preset bias circuit is used to apply negative charge to the integral capacitor when there is no input charge. The integral capacitor value is Cf.

[0051] The first integral capacitor switch specifically includes: a first switch S1 and a second switch S2. One end of the first switch S1 is connected to the reverse input end of the amplifier, and the other end of the first switch S1 is connected to the first end of the integral capacitor; the second end of the integral capacitor is connected to one end of the second switch S2, and the other end of the second switch S2 is connected to the output end of the amplifier; the first switch S1 and the second switch S2 are both disconnected when there is no input charge, and the first switch S1 and the second switch S2 are both closed when there is input charge. The positive input end of the amplifier is grounded.

[0052] The first preset bias circuit specifically includes: a first electrode plate, a second electrode plate, a third switch S3, and a fourth switch S4. One end of the third switch S3 is connected to the first electrode plate, the other end of the third switch S3 is connected to the first end of the integrating capacitor, and the bias voltage of the first electrode plate is Vb1. One end of the fourth switch S4 is connected to the second electrode plate, the other end of the fourth switch S4 is connected to the second end of the integrating capacitor, and the bias voltage of the second electrode plate is Vb2, where Vb1 < Vb2. Both the third switch S3 and the fourth switch S4 are closed when there is no input charge amount, and both the third switch S3 and the fourth switch S4 are opened when there is an input charge amount.

[0053] The integrating capacitor negative charge compensation circuit works as follows:

[0054] (1) Preset bias

[0055] Before the input charge arrives, that is, in the initial state of the circuit, switches S1 and S2 are opened to isolate the integrating capacitor from other parts of the circuit. Switches S3 and S4 are closed to reset both ends of the capacitor to a determined voltage. As Figure 2 shown, the bias voltage of the left electrode plate of the capacitor is Vb1, the bias voltage of the right electrode plate is Vb2, and it is ensured that Vb1 < Vb2, that is, the bias voltage of the left electrode plate is lower than that of the right electrode plate. Since the voltage at the output end of the integrator flips downward, this is equivalent to pre-storing negative charge on the capacitor, and the pre-stored charge amount Q0 = Cf(Vb1 - Vb2).

[0056] (2) Charge integration

[0057] When the circuit enters the amplification stage, the input charge amount is Qin, the output voltage is Uout, switches S3 and S4 are opened, and switches S1 and S2 are closed. The integrating capacitor is disconnected from the preset bias and connected to the circuit to start the charge integration process. At this time, the relationship between the output voltage and the input charge amount is:

[0058] Qin + Q0 = Cf * ΔUout

[0059] In the formula, Cf is the value of the integrating capacitor, and ΔUout is the change amount of the output voltage relative to the baseline.

[0060] The relationship between the input dynamic range Qin,max and the output swing ΔUout,max is:

[0061] Qin,max + Q0 = Cf * ΔUout,max

[0062] Qin,max + Cf(Vb1 - Vb2) = CfΔUout,max

[0063] That is:

[0064] Cf = Qin,max / (ΔUout,max + Vb2 - Vb1)

[0065] Since Vb2>Vb1, when the input dynamic range and the output swing are the same, the integral capacitance value is smaller than the integral capacitance value in the prior art integrator, thereby achieving the purpose of reducing the integral capacitance. Equivalently, when the integral capacitance value and the output swing are the same, the input dynamic range of the present invention is greater than the input dynamic range of the classical integrator.

[0066] The present invention proposes an integral capacitor negative charge compensation circuit, which achieves the purpose of increasing the output dynamic range or reducing the capacitance by pre-biasing the capacitor voltage. That is, when the integral capacitor and the output swing are constant, the input dynamic range Qin,max can be increased. When the input dynamic range and the output swing are constant, the integral capacitor value Cf can be reduced.

[0067] Embodiment 2

[0068] Figure 3 This is the circuit diagram of the negative charge compensation of the integral capacitor. Figure 4 For the multi-range integrator circuit diagram, Figure 3-4 As shown, a negative charge compensation circuit of an integral capacitor includes: an integrator circuit, an incremental range integral capacitor, a second integral capacitor switch, and a second preset bias circuit. The number of incremental range integral capacitors can be set to one or more according to the needs of the range. The incremental range integral capacitor is connected between the reverse input terminal and the output terminal of the amplifier in the integrator circuit; the incremental range integral capacitor is used to increase the range of charge measurement of the integrator circuit; the second integral capacitor switch is connected in series with the incremental range integral capacitor, and the second integral capacitor switch is used to isolate the incremental range integral capacitor from the amplifier when the range is not increased, and connect the incremental range integral capacitor to the amplifier when the range is increased; the second preset bias circuit is connected in parallel at both ends of the incremental range integral capacitor, and the second preset bias circuit is used to apply negative charge to the integral capacitor when the range is not increased. The integral capacitor value in the integrator circuit is Cf1, and the incremental range integral capacitor value is Cf2.

[0069] The second integral capacitor switch specifically includes: a fifth switch S5 and a sixth switch S6. One end of the fifth switch S5 is connected to the reverse input end of the amplifier, and the other end of the fifth switch S5 is connected to the first end of the incremental range integral capacitor; the second end of the incremental range integral capacitor is connected to one end of the sixth switch S6, and the other end of the sixth switch S6 is connected to the output end of the amplifier; the fifth switch S5 and the sixth switch S6 are both disconnected when the incremental range is not increased, and the fifth switch S5 and the sixth switch S6 are both closed when the incremental range is increased. The positive input end of the amplifier is grounded.

[0070] The second preset bias circuit specifically includes: a third plate, a fourth plate, a seventh switch S7 and an eighth switch S8. One end of the seventh switch S7 is connected to the third plate, and the other end of the seventh switch S7 is connected to the first end of the incremental range integrating capacitor; one end of the eighth switch S8 is connected to the fourth plate, and the other end of the eighth switch S8 is connected to the second end of the incremental range integrating capacitor; the seventh switch S7 and the eighth switch S8 are both closed when the range is not increased, and the seventh switch S7 and the eighth switch S8 are both opened when the range is increased. The bias voltage of the third plate is Vb3, the bias voltage of the fourth plate is Vb4, and Vb3 <Vb4。

[0071] Normally, the output swing of the integrator is limited by the output baseline and the power supply voltage, and the negative charge compensation of the present invention cannot increase the output swing. However, in multi-range charge measurement, for example, the present invention can increase the output swing to a certain extent.

[0072] When the integrator is used for multi-range charge measurement, more than one incremental range integrating capacitor will be connected between the input and output terminals of the operational amplifier to increase the range by connecting more capacitors in parallel. Figure 4 When negative charge compensation is not used, the low range integral capacitor is Cf1, and the high range integral capacitor value is Cf1+Cf2. Assuming that the minimum input charge of the high range is Qh, the corresponding output voltage is:

[0073] ΔUout=Qh / (Cf1+Cf2)

[0074] like Figure 3 As shown, before the range is switched from low to high, switches S5 and S6 are disconnected, S7 and S8 are closed, and negative charge is pre-stored on the integral capacitor Cf2, and the charge amount Q0 = Cf2 (Vb1-Vb2). When the range is switched from low to high, switches S5 and S6 are closed, and S7 and S8 are disconnected. The output voltage at this time is:

[0075] ΔUout=(Qh+Q0) / (Cf1+Cf2)

[0076] Since Q0 is a negative value, the same high-range minimum input charge Qh corresponds to a smaller output voltage after the improvement of the present invention, that is, corresponds to a larger high-range output swing.

[0077] The key point of the negative charge compensation circuit of the integral capacitor proposed by the present invention is to isolate and pre-bias the integral capacitor before the charge input, and pre-store negative charge on the capacitor, so as to achieve the purpose of increasing the input dynamic range or reducing the integral capacitor. The operational amplifier, switch and capacitor in the circuit can have many different implementation forms.

[0078] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An integral capacitor negative charge compensation circuit, characterized in that: include: an integrator circuit, a first integrating capacitor switch and a first preset bias circuit; The first integral capacitor switch is connected in series with the integral capacitor in the integrator circuit, and the first integral capacitor switch is used to isolate the integral capacitor from the amplifier in the integrator circuit when there is no input charge, and to connect the integral capacitor to the amplifier in the integrator circuit when there is input charge; The first preset bias circuit is connected in parallel to both ends of the integration capacitor, and the first preset bias circuit is used to apply negative charge to the integration capacitor when there is no input charge; The first preset bias circuit: before the input charge arrives, that is, in the initial state of the circuit, opens switches S1 and S2 to isolate the integral capacitor from other parts of the circuit, and closes switches S3 and S4 to reset both ends of the capacitor to a certain voltage; The integrator circuit: when the circuit enters the amplification stage, the input charge is Qin, the output voltage is Uout, switches S3 and S4 are opened, switches S1 and S2 are closed, the integration capacitor is disconnected from the preset bias and connected to the circuit, and the charge integration process begins.

2. The integral capacitor negative charge compensation circuit according to claim 1, characterized in that: The first integral capacitor switch specifically comprises: a first switch and a second switch; One end of the first switch is connected to the inverting input end of the amplifier, and the other end of the first switch is connected to the first end of the integrating capacitor; The second end of the integrating capacitor is connected to one end of the second switch, and the other end of the second switch is connected to the output end of the amplifier; The first switch and the second switch are both opened when there is no input charge, and the first switch and the second switch are both closed when there is input charge.

3. The integral capacitor negative charge compensation circuit according to claim 1, characterized in that: The first preset bias circuit specifically comprises: A first plate, a second plate, a third switch and a fourth switch; One end of the third switch is connected to the first electrode plate, and the other end of the third switch is connected to the first end of the integral capacitor; One end of the fourth switch is connected to the second electrode plate, and the other end of the fourth switch is connected to the second end of the integral capacitor; The third switch and the fourth switch are both closed when there is no input charge, and the third switch and the fourth switch are both opened when there is input charge.

4. The integral capacitor negative charge compensation circuit according to claim 1, characterized in that: The non-inverting input terminal of the amplifier is grounded.

5. The integral capacitor negative charge compensation circuit according to claim 3, characterized in that: The bias voltage of the first plate is smaller than the bias voltage of the second plate.

6. An integral capacitor negative charge compensation circuit, characterized in that: include: an integrator circuit, an incremental range integrating capacitor, a second integrating capacitor switch, and a second preset bias circuit; The incremental range integrating capacitor is connected between the inverting input terminal and the output terminal of the amplifier in the integrator circuit; the incremental range integrating capacitor is used to increase the range of charge measurement of the integrator circuit; When the integrator in the integrator circuit is used for multi-range charge measurement, more than one incremental range integrating capacitor is connected across the input and output terminals of the operational amplifier, and the range is increased by connecting more capacitors in parallel; The second integral capacitor switch is connected in series with the incremental range integral capacitor, and the second integral capacitor switch is used to isolate the incremental range integral capacitor from the amplifier when the incremental range is not increased, and to connect the incremental range integral capacitor to the amplifier when the incremental range is increased; The second preset bias circuit is connected in parallel to both ends of the incremental range integrating capacitor, and the second preset bias circuit is used to apply negative charge to the integrating capacitor when the incremental range is not increased.

7. The integral capacitor negative charge compensation circuit according to claim 6, characterized in that: The second integral capacitor switch specifically comprises: a fifth switch and a sixth switch; One end of the fifth switch is connected to the inverting input end of the amplifier, and the other end of the fifth switch is connected to the first end of the incremental range integrating capacitor; The second end of the incremental range integrating capacitor is connected to one end of the sixth switch, and the other end of the sixth switch is connected to the output end of the amplifier; The fifth switch and the sixth switch are both opened when the range is not increased, and the fifth switch and the sixth switch are both closed when the range is increased.

8. The integral capacitor negative charge compensation circuit according to claim 6, characterized in that: The second preset bias circuit specifically comprises: a third plate, a fourth plate, a seventh switch, and an eighth switch; One end of the seventh switch is connected to the third electrode plate, and the other end of the seventh switch is connected to the first end of the incremental range integrating capacitor; One end of the eighth switch is connected to the fourth electrode plate, and the other end of the eighth switch is connected to the second end of the incremental range integrating capacitor; The seventh switch and the eighth switch are both closed when the range is not increased, and the seventh switch and the eighth switch are both opened when the range is increased.

9. The integral capacitor negative charge compensation circuit according to claim 6, characterized in that: The non-inverting input terminal of the amplifier is grounded.

10. The integral capacitor negative charge compensation circuit according to claim 8, characterized in that: The bias voltage of the third electrode plate is smaller than the bias voltage of the fourth electrode plate.

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