Devices and methods

Abstract

The present invention describes a Schottky barrier thin film transistor. The Schottky barrier thin film transistor includes a Schottky source contact electrode on an oxide semiconductor. The Schottky barrier thin film transistor has an intrinsic gain of at least 500. The present invention also describes a method for preparing a Schottky barrier thin film transistor with a Schottky source contact electrode formed on an oxide semiconductor channel.

Description

Technical Field

[0001] The present invention relates to a Schottky barrier thin film transistor, in particular to a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel, and a method for preparing a Schottky source contact on an oxide semiconductor channel in the Schottky barrier transistor. Background Art

[0002] Generally speaking, a Schottky Barrier Thin-Film Transistor (SBTFT) (also known as a source-gate transistor, Source-Gated Transistor, SGT, or Schottky Source Transistor, Schottky Source Transistor, SST) consists of a gate insulating layer, a semiconductor channel covering the gate insulating layer, a source contact electrode covering at least a portion of the semiconductor channel layer, a drain contact electrode, and a gate contact electrode stack. The source contact electrode, the gate contact electrode, and the drain contact electrode are separated from each other. The portion where the source contact electrode intersects with the semiconductor channel layer is the source region of the semiconductor layer, which defines the Schottky barrier at the interface between the source contact electrode and the semiconductor source region. When the source region of the semiconductor layer is depleted, the gate contact electrode can control the transport of carriers from the source contact electrode to the source region of the semiconductor channel across the Schottky barrier.

[0003] Oxide semiconductors, especially indium-gallium-zinc oxide (IGZO), have become mature in the field of thin-film electronic devices. However, the relatively low intrinsic gain, short channel effect and negative bias light temperature stress (NBITS) of oxide semiconductor thin-film transistors (TFTs) still limit their development in the display field.

[0004] Therefore, oxide semiconductor TFTs need further improvement. Summary of the invention

[0005] One of the purposes of the present invention is to provide a Schottky barrier thin film transistor that uses a source contact electrode to cover a portion of an oxide semiconductor channel layer, thereby providing a device that can eliminate or mitigate the disadvantages mentioned in this document or other documents. For example, one of the purposes of the present invention is to further improve the intrinsic gain of the device, improve the short channel effect, and / or improve the negative bias light temperature pressure effect by using a Schottky barrier thin film transistor that uses a source contact electrode to cover a portion of an oxide semiconductor channel layer. For example, one of the purposes of the present invention is to propose a method for forming a Schottky source contact electrode on an oxide semiconductor channel layer to improve the intrinsic gain of the device, improve the short channel effect, and improve the negative bias light temperature pressure effect.

[0006] According to a first aspect, the present invention provides a Schottky barrier thin film transistor having an intrinsic gain exceeding 500, formed by a Schottky source contact electrode on an oxide semiconductor channel layer.

[0007] According to a second aspect, the present invention provides an inverter, a logic gate, an integrated circuit, an analog circuit, and a display circuit composed of the Schottky barrier thin film transistor proposed in the first aspect.

[0008] According to a third aspect, the present invention provides a method for forming a Schottky contact on an oxide semiconductor channel for preparing a Schottky barrier thin film transistor, the method comprising: depositing a source contact electrode on the oxide semiconductor channel in an oxygen-containing gas environment. DETAILED DESCRIPTION

[0009] As stated in the claims, the present invention provides a Schottky barrier thin film transistor. The present invention also provides a method for forming a Schottky source contact on an oxide semiconductor channel for making a Schottky barrier thin film transistor. Other contents proposed in the present invention are included in the claims, and the details will be given below.

[0010] Schottky barrier thin film transistor with Schottky source contact formed on oxide semiconductor channel

[0011] The first part of the present invention proposes a Schottky barrier thin film transistor having a Schottky source contact formed on an oxide semiconductor channel layer, wherein the intrinsic gain of the Schottky barrier thin film transistor exceeds 500.

[0012] Therefore, since Schottky barrier thin film transistors have a relatively high (over 500) intrinsic gain, Schottky barrier thin film transistors are suitable for applications such as inverters, logic circuits, analog circuits, and large-area displays. In addition, Schottky barrier thin film transistors can better improve the short channel effect and the influence of negative bias light temperature stress effect, as shown in more details below.

[0013] The transistor is the cornerstone of the recent technological revolution in society, and its discovery has reshaped modern society. To achieve further progress, people must design new transistors to meet industrial needs. By combining thin-film transistors with another basic electronic device (Schottky diode), people have achieved an unconventional transistor design. The advantages of this new Schottky barrier thin-film transistor (Schottky barrier thin-film transistor) include high intrinsic gain, low voltage saturation, insensitivity to channel length, and better stability.

[0014] In the literature, Schottky barrier thin film transistors with similar design and characteristics are given different names, such as Schottky barrier thin film transistor, source-gate transistor and tunneling contact transistor. Behind the different names, there are various conflicting theories that have been proposed. For example, the reduction of the source barrier height, the increase of the tunneling current or the modulation of the effective source length have been considered to be the reasons for the current and gate dependence. Similarly, there are different reports on the effect of the Schottky drain contact. Similarly, the diode reverse saturation current, the tunneling current and the source-induced semiconductor layer depletion have been considered to be the reasons for the current saturation.

[0015] While Schottky barrier thin film transistors were developing, breakthroughs in oxide semiconductor devices ushered in a new era in the field of microelectronics, especially in large-area, flexible, and transparent applications. The wide bandgap of oxide semiconductors (generally >3eV) ensures high optical transparency, while room temperature processability provides compatibility with flexible substrates. Although research on oxide semiconductors, especially indium-gallium-zinc oxide (IGZO), is close to maturity, there are still many obstacles in large-area applications. The most important of these is negative bias illumination temperature stress (NBITS). When the IGZO TFT is under negative gate bias, the increase in temperature and the absorption of photons with energy close to the bandgap cause the turn-on voltage to shift to the negative direction. At present, NBITS is still an important factor hindering IGZO from replacing polysilicon and amorphous silicon in displays.

[0016] Equally important is the issue of device size. To maintain the development of electronic circuits, the density of transistors must be continuously increased; therefore, the size of transistors must be reduced. However, after the channel length between the source and the drain is reduced to a certain extent, the performance of the transistor will be significantly reduced. In particular, the reduction in the on-off ratio and the intrinsic gain will prevent short-channel devices from being used as driver devices in displays.

[0017] In this work, we designed TFTs based on a new theory of reverse-biased thin-film Schottky diodes and fabricated TFTs that exhibited extremely high gain. Based on these designs and theoretical analysis, the intrinsic gain of the gate-source transistors generally exceeded 10,000, with a peak gain of 29,000. In addition, this is the first time that an oxide semiconductor thin-film transistor has been invented that is not affected by NBITS. At the same time, there is no obvious short channel effect when the channel length of such devices is reduced to 360nm. Finally, in our design, the channel layer no longer has to be a semiconductor, for example, an oxide conductor such as indium tin oxide (ITO) can be used.

[0018] In the classic model of Schottky barrier thin film transistor, under zero bias, the conduction band energy EC in the semiconductor at the interface between the Schottky source contact and the semiconductor channel is at its maximum value (i.e., the source barrier height ΦB). The conduction band energy EC decreases in the semiconductor channel as it moves away from the interface. Generally speaking, Schottky barrier thin film transistors require a source barrier height of about 0.3eV-0.5eV to deplete the channel layer of the semiconductor while generating a high enough current to meet application needs.

[0019] The traditional model assumes that the Schottky source contact and the semiconductor layer are uniform. Because of the intrinsic heterogeneity (also considered as inhomogeneity) of oxide semiconductors, the inventors believe that this traditional model is not applicable to Schottky source contacts on oxide semiconductors. This heterogeneity may be nanoscale, for example, it may be caused by the inhomogeneity of the intrinsic components of the oxide semiconductor and / or the source contact electrode, it may be caused by the depletion of oxygen components in the near-interface region of the oxide semiconductor, it may be caused by changes in the morphology of polycrystalline, single crystal or amorphous and / or the work function changes caused by different crystals of the source contact electrode.

[0020] Contrary to the conventional model, for a Schottky barrier thin film transistor with a source contact covering an oxide semiconductor channel, the conduction band energy level EC in the oxide semiconductor increases as it moves away from the interface between the source contact electrode and the oxide semiconductor channel. Therefore, the effective source barrier height in the oxide semiconductor channel is It will be higher than the barrier height on the interface. In the interface, in the direction perpendicular to the Schottky source contact and the semiconductor layer, when the low barrier region at the source is surrounded by the high barrier region, the minimum EC of the oxide semiconductor conduction band increases. Therefore, a barrier saddle point (Saddle Point, SP) may be formed in the conduction band minimum. The barrier saddle point provides the most preferred current flow path and also affects the effective source barrier height. The uneven barrier distribution at the nanoscale may cause multiple barrier saddle points to simultaneously determine the effective source barrier height. The present invention proposes that under general conditions, the barrier saddle point will change with the voltage, resulting in the effective barrier height being directly related to the voltage. When the drain voltage increases, the barrier saddle point becomes lower so that more current can cross the barrier, and the specific details will be described in detail below. The current that increases with the increase in drain voltage reduces the intrinsic gain. In other words, the non-uniformity of the device determines the characteristics of the Schottky barrier thin film transistor, at least in part, by increasing or decreasing the effective barrier height. In particular, the low barrier region caused by the non-uniformity is a decisive factor for the characteristics of the Schottky barrier thin film transistor, and the specific details will be described in detail below.

[0021] In order to improve the properties of the source contact electrode to the desired level, the inventors have confirmed that the effective barrier height of the Schottky contact should be lower than the source barrier height at the interface. The inventors have also confirmed that this may be achieved by (at least partially) controlling the thickness of the oxide semiconductor (that is, the oxide semiconductor channel thickness H) and / or its non-uniformity, thereby controlling the performance of the Schottky barrier thin film transistor or reducing the impact of its non-uniformity.

[0022] A more ideal situation is to remove the potential saddle point to make the effective barrier height The current is no longer affected by the applied voltage. Reducing the thickness H of the oxide semiconductor channel layer may cause the barrier saddle point to move closer to the interface between the oxide semiconductor channel and the source contact until the barrier saddle point eventually disappears completely.

[0023] The present invention has proved that the effective source barrier height can be reduced by regulating the barrier saddle point in the oxide semiconductor channel, and the specific details will be described in detail below. Controlling the barrier saddle point can be achieved in the following ways, for example, by reducing the height of the barrier saddle point and reducing the effective barrier height, and even by reducing the distance of the barrier saddle point from the interface to achieve the effect of completely eliminating the barrier saddle point. In other words, reducing the effective barrier height can be achieved not only by reducing the height of the barrier saddle point, but also by moving its position in the oxide semiconductor channel.

[0024] The present invention has proved that if the thickness of the oxide semiconductor channel layer is too large, the height of the barrier saddle point or its distance from the interface is too large, resulting in the effective barrier height of the Schottky source contact being If the thickness of the oxide semiconductor channel layer is too small, the electric field in actual application becomes very large, which may cause tunneling and other additional mechanisms that reduce the barrier to affect the saturation current of the output curve of the Schottky barrier thin film transistor. The specific details will be described in detail below.

[0025] Before depositing the source contact, the conductivity can be improved by treating the oxide semiconductor channel layer, such as annealing or plasma treating the surface area. However, even with sufficient thickness, the oxide semiconductor channel layer may be depleted by oxygen during treatment, such as annealing. The inventors have confirmed that the depletion of the semiconductor channel layer due to oxygen treatment may lead to greater non-uniformity and thus affect the semiconductor source contact, and the specific details will be described in detail below. The present invention has been confirmed that depositing a source contact electrode on the oxide semiconductor channel layer in an oxygen atmosphere may be beneficial to the oxide semiconductor to deplete the surface area with excess oxygen elements, or to form a beneficial oxygen-containing interface layer, and the specific details will be described in detail below.

[0026] By creatively exploiting the barrier height non-uniformity and the resulting dependence of the barrier height on thickness at the source contact, the inventors have overcome traditional problems associated with oxide semiconductors, such as IGZO Schottky thin film transistor process issues. Of particular note, the inventors have successfully fabricated oxide semiconductor devices, such as IGZO Schottky barrier thin film transistors, that exhibit extremely high intrinsic gain in short channels, excellent stability, and excellent stability under negative bias light temperature stress.

[0027] These Schottky barrier thin film transistors are suitable for large-area displays, logic gates, analog circuits, etc. In addition, the low voltage saturation characteristics of these Schottky barrier thin film transistors significantly reduce power consumption, making them very suitable for battery-powered wearable devices.

[0028] Typically, a conventional Schottky barrier thin film transistor (Schottky barrier thin film transistor) uses a Schottky contact (ie, Schottky source contact) at the source to adjust the drain current ID so that the drain current ID is not affected by the semiconductor channel.

[0029] In order to work like a conventional Schottky barrier thin film transistor, there are three basic design principles: (a) the gate contact area must overlap with the Schottky source contact area;

[0030] (b) The semiconductor channel must be sufficiently conductive so as not to limit the drain current ID;

[0031] (c) The semiconductor channel must be thin enough so that the channel layer can be completely depleted when a reverse voltage is applied.

[0032] Conventional Schottky barrier thin-film transistor structures have applied various semiconductor channel layers, including amorphous silicon, polycrystalline silicon, zinc oxide, zinc oxide nanosheets and zinc oxide nanowires. So far, conventional Schottky barrier transistors made using oxide semiconductors have shown very poor performance, which may be caused by poor Schottky source contacts or low channel conductivity.

[0033] Typically, in order to provide a sufficiently large current while being able to deplete the semiconductor layer, Schottky barrier thin film transistors require a source barrier height of about 0.3-0.5 eV. For oxide semiconductors, it is difficult to form a uniform Schottky contact with such a low barrier height. In addition, barrier height non-uniformity is prevalent in Schottky barrier thin film diodes made of oxide semiconductors and has been shown to significantly degrade the reverse bias current-voltage characteristics of these diodes. So far, all discussions in the literature on the working mechanism of Schottky barrier thin film transistors have assumed a uniform barrier at the source contact. Since the working mechanism of Schottky thin film transistors is critically dependent on the behavior of the Schottky barrier when reverse biased at the source, it is very important to have a deep understanding of the impact of barrier height variations on the transistor.

[0034] Here, oxide semiconductors, especially IGZO Schottky barrier thin film transistors, show extremely high gain, which shows unprecedented resistance to negative bias light temperature stress and short channel effect. First, the inventors fabricated a conductive IGZO channel by thermal annealing in an inert gas. However, Schottky junctions formed on IGZO or any other amorphous semiconductor may have non-uniform barrier heights. Barrier non-uniformity leads to the formation of saddle points at the conduction band minimum, which, as an effective barrier height, are very susceptible to changes with bias. In order to maximize the intrinsic gain, the effects of the saddle points should be removed or reduced. The inventors achieved this through two mechanisms:

[0035] 1. Through simulation of Schottky barrier thin film transistors, it was determined that the saddle point can be eliminated by reducing the semiconductor thickness;

[0036] 2. During the deposition of the source contact electrode, the sputtering power and the introduction of oxygen are used to control the non-uniformity of the potential barrier.

[0037] Through these two mechanisms, the devices produced have an intrinsic gain that is consistently above 1,000. Finally, the inventors have demonstrated that this type of Schottky barrier thin-film transistor is immune to short-channel effects at 800nm ​​and is very stable under negative bias light temperature stress.

[0038] For oxide semiconductors, oxygen defects are believed to cause non-uniformity in Schottky source contacts. The manufacturing method described in the present invention is applicable to all oxide semiconductors. In addition, the simulation of Schottky barrier thin film transistors with non-uniform Schottky source contacts has enabled the inventors to have a deeper understanding of the working principle of Schottky thin film transistors, which is also applicable to other amorphous semiconductor systems, such as organic semiconductors. The method described in the present invention can also be used in complementary metal oxide circuits. For example, Pt is used as a Schottky source contact on an n-type oxide semiconductor, so that it can be used as a contact electrode for both n-type and p-type transistors. Although the current in a Schottky barrier thin film transistor may be relatively lower than that in a standard thin film transistor, simulations show that the current generated by an oxide semiconductor such as IGZO and a Schottky thin film transistor is sufficient for use in AMOLED displays.

[0039] The inventors have identified new design principles for these Schottky thin barrier film transistors based on oxide semiconductor channels: In order to make the performance of the source Schottky contact on the oxide semiconductor channel unaffected by the drain bias voltage, the effective source barrier height It should be lower than the source barrier height ΦB at the interface. The inventors have demonstrated that this can be achieved at least by controlling the thickness of the oxide semiconductor channel (i.e., the oxide semiconductor channel thickness H) or adjusting the inhomogeneity of the channel, thereby controlling the properties of the thin film transistor or controlling the effect of inhomogeneity on the thin film transistor. In other words, for a non-uniform barrier, the thickness of the oxide semiconductor channel (i.e., the oxide semiconductor channel thickness H) should be reduced so that the barrier saddle point is removed or is close enough to the interface between the Schottky source contact and the oxide semiconductor channel, but not so thin as to generate a high enough electric field to reduce the gain or deplete the oxide semiconductor channel, thereby making the operating voltage larger. Using this new design principle, the inventors have successfully fabricated oxide semiconductors with ultra-high intrinsic gain, such as IGZO Schottky barrier thin film transistors. This result is largely due to a detailed study of the interface disorder between the Schottky source contact and the oxide semiconductor, which is also very useful for studying other disordered materials. In addition, these Schottky barrier thin film transistors also show ultra-high insensitivity to short channel effects and negative bias light temperature stress. Individually, these enhancements are remarkable improvements over existing technologies, and on a macro level, they represent a significant advance in Schottky thin-film transistor technology.

[0040] Intrinsic Gain

[0041] The intrinsic gain AV of the Schottky barrier thin film transistor can be considered as one of the parameters to measure its performance here, and the specific details will be described in detail below. The Schottky barrier thin film transistor has an intrinsic gain of at least 500. In one embodiment, the intrinsic gain is preferably at least 1000, more preferably at least 2000, and most preferably at least 3000, at least 5000, at least 8000 or 10000. In one embodiment, the intrinsic gain is preferably 50,000, at most 45,000, at most 40,000, at most 35,000, at most 30,000, at most 25,000, at most 20,000, and at most 10,000.

[0042] NBITS

[0043] Negative bias light temperature stress may cause the turn-on voltage of the conventional thin film transistor to shift negatively during operation. In one example, after irradiation with a white light emitting diode for 30 minutes, preferably after 45 minutes, at an illumination of about 2000 lx, with a light source and a device spaced 3 cm apart, a bias voltage of -20 V, a gate voltage of 20 V and a temperature of 80°C, the turn-on voltage of the Schottky thin film transistor changes by at most 10%, preferably at most 5%, and more preferably at most 1%.

[0044] Short channel effect

[0045] Since the source contact and the drain contact are too close, the short channel effect may cause the device size to be unable to be reduced. In one example, when the channel length L is reduced to 2μm, 1μm, or even 0.8μm, the thin film transistor still shows a smooth saturation region when a drain voltage of 20V is applied.

[0046] Effective barrier height

[0047] In one example, the effective barrier height of the Schottky source contact is substantially independent of the drain voltage of the Schottky transistor when the device is operating. In this case, the barrier saddle point is lowered and / or removed. It should be understood that other factors such as image force barrier reduction still cause the source-drain current to be dependent on the drain voltage, but not significantly.

[0048] In one example, the maximum potential of the conduction band minimum (i.e., saddle point) of the oxide semiconductor channel at zero bias is within 10 nm, preferably within 5 nm, or more preferably within 3 nm of the interface between the Schottky source contact and the oxide semiconductor channel. In this case, the barrier saddle point is reduced or removed.

[0049] In one example, the oxide semiconductor channel has a sufficiently small thickness so that the maximum potential of the conduction band minimum (i.e., saddle point) of the oxide semiconductor channel at zero bias is within 10 nm, preferably within 5 nm, and more preferably within 3 nm of the interface between the Schottky source contact and the oxide semiconductor channel. This is particularly true when the oxide semiconductor channel is an IGZO material.

[0050] In one example, at zero bias, the potential saddle point is reduced or removed by lowering the conduction band energy level in the oxide semiconductor channel away from the Schottky source contact electrode.

[0051] Oxide semiconductors

[0052] It should be understood that the oxide semiconductor channel includes or is formed of an oxide semiconductor and has sufficiently high conductivity when the transistor is turned on. Therefore, the source contact area of ​​the transistor largely determines the transistor current.

[0053] In one example, the oxide semiconductor is an amorphous oxide semiconductor. In one example, the oxide semiconductor is a crystalline oxide semiconductor. In one example, the oxide semiconductor includes or is an n-type oxide semiconductor. In one example, the oxide semiconductor includes or is a p-type oxide semiconductor.

[0054] In one example, the oxide semiconductor includes / or is an oxide semiconductor based on zinc oxide, preferably an oxide semiconductor based on amorphous zinc oxide. In one example, the oxide semiconductor based on zinc oxide contains at least one of hafnium, yttrium, tantalum, zirconium, titanium, copper, nickel, chromium, indium, gallium, aluminum, tin and magnesium.

[0055] In one example, the oxide semiconductor includes or is zinc oxide, zinc gallium oxide, zinc tin oxide, indium sesquioxide, indium tin oxide, indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium hafnium zinc oxide, indium silicon zinc oxide, indium zirconium zinc oxide, indium tin zinc oxide, indium gallium tin oxide, tin dioxide, aluminum zinc oxide, aluminum zinc tin oxide, or zirconium zinc tin oxide. In one example, the oxide semiconductor includes or is crystalline, such as polycrystalline zinc oxide, crystalline, such as polycrystalline zinc gallium oxide, crystalline, such as polycrystalline zinc tin oxide, crystalline, such as polycrystalline indium oxide, crystalline, such as polycrystalline indium tin oxide, crystalline, such as polycrystalline indium zinc oxide, crystalline, such as polycrystalline indium gallium oxide, crystalline, such as polycrystalline indium gallium zinc oxide, crystalline, such as polycrystalline indium hafnium zinc oxide, crystalline, such as polycrystalline indium silicon zinc oxide, crystalline, such as polycrystalline indium zirconium zinc oxide, crystalline, such as polycrystalline indium tin zinc oxide, crystalline, such as polycrystalline indium gallium tin oxide, crystalline, such as polycrystalline tin dioxide, crystalline, such as aluminum zinc oxide, crystalline, such as polycrystalline aluminum zinc tin oxide, crystalline, such as polycrystalline zirconium zinc tin oxide. For example, the oxide semiconductor includes or is amorphous zinc oxide, amorphous zinc gallium oxide, amorphous zinc tin oxide, amorphous indium oxide, amorphous indium tin oxide, amorphous indium zinc oxide, amorphous indium gallium oxide, amorphous indium gallium zinc oxide, amorphous indium hafnium zinc oxide, amorphous indium silicon zinc oxide, amorphous indium zirconium tin oxide, amorphous indium tin zinc oxide, amorphous indium gallium tin oxide, amorphous tin dioxide, amorphous aluminum zinc oxide, amorphous aluminum zinc tin oxide, or amorphous zirconium zinc tin oxide.

[0056] In a preferred example, the oxide semiconductor is InGaZnO (IGZO). The composition of the oxide semiconductor can be a(In2O3).b(Ga2O3).c(ZnO). More preferably, the oxide semiconductor is amorphous InGaZnO (IGZO). The oxide semiconductor can be amorphous a(In2O3).b(Ga2O3).c(ZnO). In one example, a, b, and c are real numbers, where a≥0, b≥0, or c>0. In one example, a, b, and c are real numbers, where a≥1, b≥1 or 0<c≤1. In one example, a = 1, b = 1, c = 2.

[0057] In one example, before depositing the Schottky source contact, the oxide semiconductor channel layer is annealed or plasma treated, and the specific details will be described in detail below.

[0058] In one example, the oxide semiconductor includes an oxygen depletion region. In one example, the oxide semiconductor includes an oxygen depletion region near the oxide semiconductor channel and the Schottky source contact or at the interface between the oxide semiconductor channel and the Schottky source contact. In one example, the oxygen depletion region is within 5 nm of the interface, preferably within 3 nm. In one example, the oxygen depletion region is formed during annealing before depositing the Schottky source contact. Preferably, the oxide semiconductor is IGZO, and more preferably, the oxide semiconductor is amorphous IGZO.

[0059] Oxide semiconductor channel thickness H

[0060] If the oxide semiconductor channel thickness is too large, the height of the saddle point or the distance from the saddle point to the interface may be too large, so for the expected Schottky source contact electrode properties, that is, no change with bias, the effective source barrier height However, the inventors have determined that if the oxide semiconductor channel thickness is too small, the electric field during device operation becomes so large that tunneling and other barrier lowering mechanisms also affect the saturation current in the output curve of the thin film transistor, as will be described in detail below.

[0061] In one example, the thickness H of the oxide semiconductor channel is in the range of 5 nm to 50 nm, preferably in the range of 10 nm to 40 nm, more preferably in the range of 15 nm to 30 nm, for example 20 nm or 25 nm. It should be clear that the thickness H of the oxide semiconductor channel is measured in a direction perpendicular to the interface plane between the oxide semiconductor channel and the Schottky source contact.

[0062] Schottky source contact

[0063] In one example, the Schottky source contact needs to be formed of a material with a work function of at least 4.5 eV, or preferably at least 5 eV, such as a metal, alloy, or non-metal (Table 1). In one example, the Schottky source contact is typically made of platinum, palladium, nickel, gold, or indium tin oxide.

[0064] In one example, the Schottky source contact is deposited on the oxide semiconductor channel by evaporation or sputtering in the presence of an oxygen atmosphere, such as by sputtering in an atmosphere containing oxygen.

[0065] In one example, the thickness of the Schottky source contact is in the range of 10 nm to 250 nm, preferably in the range of 25 nm to 150 nm, more preferably in the range of 50 nm to 100 nm, such as 70 nm.

[0066] Table 1 Work function of each element (eV)

[0067]

[0068] In one example, the Schottky source contact includes a multilayer Schottky source contact with a graded composition or a single layer Schottky source contact. For example, the multilayer Schottky source contact may be a 5 nm thick Pt layer deposited on the oxide semiconductor channel and an Au layer covering the Pt layer.

[0069] Interface layer

[0070] In one example, the Schottky thin film transistor includes an interface layer disposed between the Schottky source contact and the oxide semiconductor channel. For example, the interface layer may be composed of an oxide, such as AgOx, a two-dimensional material, such as graphene, or an organic self-assembled monolayer, such as octadecyltrichlorosilane. In one example, the thickness of the interface layer is in the range of 0.1 nm to 5 nm, preferably in the range of 0.5 nm to 2 nm.

[0071] Drain contact

[0072] In one example, the drain contact material may be formed of a material such as a metal, an alloy, a non-metal, a conductive oxide, etc. In one example, the drain contact is formed of a metal such as molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), chromium (Cr), gold (Au), or an alloy thereof, or a conductive oxide such as indium zinc oxide (IZO), indium tin oxide (ITO), or a mixture thereof.

[0073] Gate contact

[0074] In one example, the gate contact may be formed of materials such as metals, alloys, non-metals, conductive oxides, etc. In one example, the gate contact may be formed of (or include) metals such as molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), chromium (Cr), gold (Au) or alloys thereof, doped semiconductors such as doped silicon (Si) or conductive oxides such as indium zinc oxide (IZO), indium tin oxide (ITO) or mixtures thereof.

[0075] Schottky barrier thin film transistor structure

[0076] In one example, the Schottky thin film transistor structure comprises a gate insulating layer, an oxide semiconductor channel covering the gate insulating layer, a Schottky source contact covering a first portion of the oxide semiconductor channel, a gate contact covering a second portion of the oxide semiconductor channel, and a stack formed by a drain contact, wherein the source contact, the gate contact, and the drain contact are spaced apart from each other.

[0077] Preferred Examples

[0078] In one embodiment, the Schottky thin film transistor structure comprises:

[0079] a stack formed of a gate insulating layer, wherein the gate insulating layer is silicon dioxide;

[0080] an oxide semiconductor channel covering the gate insulating layer, wherein the oxide semiconductor channel layer is annealed amorphous a(In2O3).b(Ga2O3).c(ZnO), wherein a=1, b=1 and c=2, wherein the oxide semiconductor includes an oxygen depletion region formed during annealing prior to depositing the source contact, and wherein the oxide semiconductor channel has a thickness H in the range of 5 nm to 50 nm, preferably in the range of 10 nm to 40 nm, more preferably in the range of 15 nm to 30 nm, for example 20 nm or 25 nm;

[0081] A Schottky source contact region covers at least a first portion of the oxide semiconductor channel, wherein the source contact electrode is formed by sputtering Pt onto an annealed oxide semiconductor in an atmosphere containing oxygen;

[0082] The second portion covering the oxide semiconductor channel is a drain contact region, wherein the material used for the drain contact electrode is Pt;

[0083] and a gate contact located under the third portion of the insulating layer, wherein the material used for the gate contact is doped silicon; wherein the source contact, the gate contact and the drain contact are separated from each other.

[0084] A preferred embodiment provides a Schottky thin film transistor, which includes a Schottky source contact on an oxide semiconductor channel, the Schottky barrier thin film transistor having an intrinsic gain of at least 500, preferably at least 1000, more preferably at least 2000, and most preferably at least 3000, wherein the oxide semiconductor channel layer is amorphous IGZO, specifically a(In2O3).b(Ga2O3).c(ZnO), wherein a=1, b=1 and c=2, and wherein the thickness H of the oxide semiconductor channel is in the range of 5nm to 50nm, preferably in the range of 10nm to 40nm, more preferably in the range of 15nm to 30nm, for example 16nm to 28nm, for example 20nm to 25nm.

[0085] And wherein the source contact is a Schottky source contact formed of a material (e.g., metal, alloy, non-metal, preferably platinum) having a work function of at least 4.5 eV. Under zero bias, the highest point of the minimum conduction band of the oxide semiconductor channel in the Schottky thin film transistor is within 10 nm of the interface between the Schottky source contact and the oxide semiconductor channel, preferably within 5 nm, and more preferably within 3 nm.

[0086] The second aspect includes an inverter, a logic gate, an integrated circuit, an analog circuit or a display circuit composed of the Schottky barrier transistor of the first aspect.

[0087] Method for forming a Schottky source contact electrode on an oxide semiconductor channel

[0088] According to a third aspect, a method for forming a Schottky source contact on an oxide semiconductor channel of a Schottky barrier thin film transistor is proposed, the method comprising: depositing a source contact on an oxide semiconductor channel layer in an atmosphere containing oxygen.

[0089] The Schottky source contact, the oxide semiconductor channel and the Schottky barrier transistor may refer to the first aspect.

[0090] Deposition power

[0091] In one example, depositing a source contact electrode on the oxide semiconductor channel includes evaporating a source contact on the oxide semiconductor channel.

[0092] In one example, the sputtering power ranges from 0.4W / cm2 to 3W / cm2 when depositing the source electrode contact, preferably from 0.6W / cm2 to 1.7W / cm2, such as 0.88W / cm2 or 1.32W / cm2. These sputtering powers correspond to sputtering powers in the range of 20W to 150W, preferably in the range of 30W to 80W, for example, for a sputtering target with a diameter of 3 inches used in this patent, the optimal power is 40W or 60W.

[0093] In one instance, the thickness range when depositing the source contact is from 10nm to 250nm, preferably from 25nm to 150nm, and most preferably from 50nm to 100nm, for example 70nm, when the sputtering power is from 0.4W / cm2 to 3W / cm2, preferably from 0.6W / cm2 to 1.7W / cm2, for example 0.88W / cm2 or 1.32W / cm2.

[0094] Since higher sputtering powers may result in faster source contact deposition rates, less oxygen may be mixed into the interface formed between the oxide semiconductor channel and the source contact during the sputtering process. For example, for IGZO oxide semiconductors, more In3+ can be reduced when higher sputtering powers are used, resulting in lower barrier regions (with a greater likelihood of non-uniformity in barrier height) and higher reverse currents. As power increases, the greater density is due to the reduced differences in oxygen content, and this effect may tend to saturate.

[0095] Gas atmosphere

[0096] In one embodiment, the inert gas contains oxygen, and the inert gas is preferably argon, with an oxygen content ranging from 0.1% to 10%, preferably ranging from 1% to 5%, such as 3% by volume partial pressure.

[0097] In one example, the gas pressure ranges from 1x10-5 mbar to 1x10-1 mbar, preferably ranges from 1x10-4 mbar to 1x10-2 mbar, such as 5x10-3 mbar.

[0098] In one embodiment, the basic oxygen pressure range of the atmosphere is 1x10-8 mbar to 1x10-2 mbar, preferably in the range of 1x10-7 mbar to 1x10-2 mbar, and optimally in the range of 1x10-6 mbar to 1x10-3 mbar, for example 1x10-5 mbar to 1x10-4 mbar.

[0099] Annealing conditions

[0100] In one example, the method includes treating the oxide semiconductor channel before depositing the source contact to increase the conductivity of the oxide semiconductor channel, improve the operating voltage and / or increase the carrier mobility. Treating the oxide semiconductor channel can be performed by annealing (also known as thermal annealing) and / or plasma treatment, such as Ar plasma treatment.

[0101] In one example, the method includes annealing the oxidized semiconductor channel prior to depositing the source electrode thereon.

[0102] In one example, annealing is preferably performed in a nitrogen atmosphere at a temperature ranging from 200°C to 400°C, preferably ranging from 250°C to 350°C, for example at 300°C for at least 15 minutes, more preferably at least 30 minutes, and most preferably at least 60 minutes. Annealing can improve the conductivity of the semiconductor channel, improve the operating voltage and increase the mobility of carriers. Annealing may also act on the surface area, and / or the entire thickness of the oxide semiconductor due to oxygen depletion.

[0103] Semiconductor channel materials

[0104] In one example, the oxide semiconductor material is prepared by sputtering, pulsed laser deposition, solution processing, combustion synthesis or spin coating. In one example, the oxide semiconductor channel is prepared by sputtering.

[0105] Preferred Examples

[0106] In one example, the method includes:

[0107] wherein the oxide semiconductor is annealed before the source contact is deposited on the oxide semiconductor channel layer and the source contact is deposited on the oxide semiconductor channel in a gas atmosphere containing oxygen;

[0108] Wherein, the annealing conditions are: in an inert atmosphere (preferably nitrogen), at a temperature ranging from 200° C. to 400° C., preferably ranging from 250° C. to 350° C., for example, 300° C., for at least 30 minutes, preferably about 60 minutes;

[0109] The inert gas in the sputtering gas atmosphere composed of oxygen is preferably argon, and the oxygen content ranges from 0.1% to 10%, preferably from 1% to 5%, for example, 3% by volume partial pressure;

[0110] The gas pressure ranges from 1x10-5 mbar to 1x10-1 mbar, preferably from 1x10-4 mbar to 1x10-2 mbar, for example, 5x10-3 mbar.

[0111] Wherein, the oxide semiconductor channel is amorphous IGZO, preferably a(In2O3)b(Ga2O3).c(ZnO), a=1, b=1, c=2. The thickness H ranges from 5nm to 50nm, preferably from 10nm to 40nm, most preferably from 15nm to 30nm, for example, 20nm to 25nm among 16nm to 28nm, for example, 20nm or 25nm;

[0112] The source contact metal is Pt.

[0113] Related definitions

[0114] In this specification, the word "consisting of" means including the specified components but does not exclude the presence of other components. The word "consisting mainly of" or "consisting mainly of" means including the specified components but excluding other components, except those present as impurities when making these components, materials inevitably added during processing, and components added for purposes other than achieving the technical performance of the present invention, such as colorants, etc.

[0115] Where appropriate, the optional features described herein may be used alone or in combination with each other, particularly in the combinations described in the accompanying claims. Where appropriate, the content of each aspect or exemplary embodiment of the invention also applies to all other aspects or instances of the invention. In other words, a technician reading this specification should regard the content of each aspect or instance of the invention as interchangeable and combinable between different aspects and instances. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] For a better understanding of the invention and to show how exemplary embodiments of the invention may be implemented, reference is made, by way of example only, to the accompanying drawings, in which:

[0117] Figure 1A The diode is explained according to the diagram based on the example; Figure 1BA Schottky barrier thin film transistor is explained according to the example and the diagram; Figure 1C A Schottky barrier thin film transistor is explained according to the example and the diagram;

[0118] Figures 2A to 2M According to the example, the design and optimization of Schottky barrier thin film transistor by adjusting the source contact deposition conditions and semiconductor thickness is described; Figure 2A The structure and current transmission path of a TFT with an ohmic contact are described in the figure; Figure 2B The structure and current transmission path in a TFT having a Schottky contact are described according to the diagram according to the example; Figure 2C The output characteristic curve of TFT is described according to the example. Figure 2D The output characteristic curve of the Schottky barrier thin film transistor is shown in the example: the saturation voltage shows a significant difference (with Figure 2C Compared to the Schottky barrier thin film transistor, it is easy to be depleted under the source; Figure 2E Shown are XPS results at 60 W in argon (top), 60 W in 3% O2 / Ar (middle), and 40 W in 3% O2 / Ar (bottom); Figure 2F |I|-V curves of Schottky diodes at different powers and different oxygen contents during Pt deposition (device structure is shown in the inset); Figure 2G The output characteristic curves of Schottky barrier thin film transistors with different powers and oxygen contents during Pt deposition are given (the device structure is shown in the inset); Figures 2H to 2J It shows that IGZO TFTs( Figure 2H ) thickness dependence at VD = 1V (the inset is the device structure), Schottky barrier thin film transistor at VD = 1V ( Fig.2I ) and Schottky barrier thin film transistor at VD = 10V ( Figure 2J )’s output characteristic curve; Figures 2K to 2M The thickness of IGZO is 50nm ( Figure 2K )、30nm( Figure 2L ) and 20nm( Figure 2M ) Output characteristics of Schottky barrier thin film transistor;

[0119] Figure 3A The model of Schottky barrier thin film transistor is described according to the example and the figure; Figure 3B The model of Schottky barrier thin film transistor is described according to the example and the figure; Figure 3C The ID-VD output curve of the Schottky barrier thin film transistor is described according to the example. Figure 3D The ID-VD output curve of the Schottky barrier thin film transistor is described according to the example. Figure 3E Schottky barrier thin film transistors are described; Figure 3DAccording to the example, the current density distribution diagram of the source of the Schottky barrier thin film transistor when VG = 10V, VD = 1V and the IGZO thickness is 100nm is described according to the figure; Figure 3F Describes Figure 3D The current density at the source of the Schottky barrier thin film transistor; Figure 3G Describes Figure 3D Distribution of conduction band minimum Ec of Schottky barrier transistor with depth z; Figure 3H and 3I The device simulation ( Figure 3H ) and experiments ( Fig. 3I ) Output curves of Schottky barrier thin film transistors under different semiconductor thicknesses; Figure 3H , the average barrier height, ФB0 is 0.5 eV and the barrier height non-uniformity is ФB=ФB0-Δ=0.2 eV. The non-uniformity width L0 is 10 nm and the distance from the source edge P is 100 nm; Figure 3J and 3K The Schottky barrier thin film transistor model is described according to the example and the figure when the barrier is not uniform. D |-VG transfer curve, VD=1V( Figure 3J ) and VD=10V( Figure 3K ), where IGZO thickness is 10, 20, 30, 50 and 100 nm, Δ = 0.3 eV and P = 1 μm. The experimental results are shown in Fig.2I and 2J As shown; similar results can be seen with different P values ​​and Δ values; Figure 3L The depth distribution diagram of the conduction band minimum EC-z of the Schottky barrier thin film transistor is described according to the example; Figure 3M It shows that when VD=0-2V, Figure 3H Figure 3. Conduction band minimum contour below the inhomogeneity center of the Schottky barrier thin-film transistor when the IGZO thickness is 20 nm.

[0120] Figure 4A and 4B It explains that there is no obvious barrier non-uniformity in the Schottky barrier thin film transistor in theory; Figure 4A Describes the conduction band between the source and semiconductor interface, showing the mechanism of current injection; Figure 4B Schematic diagram depicting the structure of a Schottky barrier thin-film transistor, showing the shape of the depletion region before and after current saturation. Figure 4C , 4D The measured transfer curve when VD = 10V ( Figure 4C ) and the measured output curves when VG=20, 26, 30V ( Figure 4D )’s fit.

[0121] Figures 5A to 5DThe intrinsic gain measurement of Schottky barrier thin film transistor is described according to the example and the figure; Figure 5A The amplified output curves of the Schottky barrier thin film transistor with IGZO thickness of 20nm at VG = 10V, 20V, and 30V. When very small current fluctuations fall within the tolerance range of the measured device, the raw data is linearly fitted; Figure 5B The intrinsic gain of the Schottky barrier thin film transistor with IGZO thickness of 20nm is shown when VG = 10V, 20V, and 30V, and the intrinsic gain value obtained by linear fitting and 15-point smoothing of the output curve is shown; Figure 5C shows the measured intrinsic gain of the inverter with a current source (Keysight E5270B) as load; the measurement setup is shown in the inset; Figure 5D Schematic diagram describing the relationship between the intrinsic gain and VD of Schottky barrier thin film transistors with different IGZO thicknesses.

[0122] Figures 6A to 6D The advantages of Schottky barrier thin film transistors using oxide materials are shown; Fig. 6A Scanning electron microscope (SEM) images of three short channel length Schottky barrier thin film transistors are shown; Figures 6B to 6D The channel length is shown to be 1640nm ( Figure 6B )、602nm( Figure 6C ) and 360nm( Fig.6D ) output curves of short-channel Schottky contact transistors. It can be seen that all devices are not affected by the short-channel effect.

[0123] Figure 7 The negative bias and light effects of Schottky barrier thin film transistors are described; Figure 7 The transfer curve of the device under NBITS for 20 hours is shown. The device was exposed to heating conditions at 60°C with a 2000lx white LED at a bias of VG = -20V.

[0124] Fig. 8A Schematic diagram of ID-VG curve of TFT with Ti-ITO channel material; Figure 8B The ID-VG curves of Schottky barrier thin film transistors with Pt-ITO channel material are described.

[0125] Fig.9A The |J|-V curves of Pt-IGZO diodes at different temperatures from 220K to 300K are shown, where Pt is in 3% O2 / Ar gas and the deposition power is 60W; Fig. 9B for Fig.9ABarrier height and ideality coefficient plotted against 1 / T, where the temperature dependence of the barrier height (standard deviation from the average barrier height is σ=0.08 eV) indicates the presence of barrier inhomogeneity; Fig. 9C is a graph of barrier height and ideality factor as a function of Pt deposition power, where the error bars are standard deviations from the mean;

[0126] Fig.10 The statistical data of the iID-VG curve of the Schottky barrier thin film transistor with IGZO thickness of 20nm and Pt deposited under 60W and 3% O2 / Ar conditions are given (the error bars show the standard deviation from the mean);

[0127] Figures 11A to 11D The effect of the location of the non-uniformity on the characteristics of a Schottky barrier thin film transistor with a semiconductor layer thickness of 100 nm is shown, where the non-uniformity is 10 nm wide and VG = 10 V; Fig.11A : Output curve when Δ=0.1eV; Fig. 11B : Output curve when Δ=0.2eV; Fig. 11C : Output curve when Δ=0.3eV; Fig.11D : The potential of the semiconductor-dielectric interface at different VD values ​​at the source boundary z = 5um;

[0128] Fig.12 A method for forming a Schottky source contact on an oxide semiconductor channel according to a proposed process is described;

[0129] Fig.13 A method of forming a Schottky source contact on an oxide semiconductor channel according to a proposed process is described.

[0130] Detailed explanation of drawings

[0131] Source Barrier Control

[0132] Figure 1A The diode 10 is described according to an example. Figure 1A A cross-sectional view of the structure of an IGZO-Pt Schottky diode 10 on a Si / SiO2 substrate is shown. The diode 10 consists of a gate contact 11 made of silicon, a dielectric layer 12 made of silicon dioxide, an ohmic contact layer 13 made of titanium, covering an IGZO oxide semiconductor layer 14, covering the dielectric layer 12, and a Pt Schottky source contact electrode 15, covering a portion of the oxide semiconductor 14.

[0133] The oxide semiconductor channel layer thickness H of the diode 10 is 150nm, wherein the oxide semiconductor is IGZO. The diode 10 has a Schottky source contact thickness h of 70nm, and the Schottky source contact is Pt (metal). The diode 10 has a Ti ohmic contact electrode with a thickness of 70nm. All metal layers are deposited by radio frequency sputtering. Other materials for the gate contact 11, the dielectric layer 12, the ohmic contact layer 13 and the Schottky source contact 15 are known. The material of the oxide semiconductor 14 has been given above.

[0134] Figure 1B The Schottky barrier thin film transistor 100 is described. Figure 1B The structure cross-sectional view of the Schottky barrier thin film transistor 100 formed by IGZO-Pt on a Si / SiO2 substrate is shown. The Schottky barrier thin film transistor 100 is composed of a gate contact electrode formed by a highly doped silicon wafer, a gate insulating layer formed by SiO2, and an oxide semiconductor channel formed by IGZO. The Schottky source contact electrode is composed of Pt, which covers the first part of the oxide semiconductor channel, and the drain contact is composed of Pt, which covers the second part of the oxide semiconductor channel. The distance between the Schottky source contact electrode 150 and the drain contact electrode 160 is L. The thickness of the oxide semiconductor channel is H. The thickness of the Schottky source contact electrode 50 is h. In this example, the Si / SiO2 substrate forms a gate contact electrode 110 (also called a gate electrode) and a gate insulating layer 120. However, the Schottky barrier thin film transistor 100 can also be prepared on an insulating substrate such as glass or plastic. In this case, a gate contact electrode 110 (e.g., metal or conductive oxide such as ITO) is deposited on an insulating substrate, and then a gate insulating layer (e.g., SiO2 or HfO2) is deposited thereon. The materials of the gate contact electrode 110, the gate insulating layer 120, the Schottky source contact electrode 150, and / or the drain contact electrode 160 are known. The material of the oxide semiconductor channel 140 has been given above.

[0135] The oxide semiconductor channel thickness H of the Schottky barrier thin film transistor 100 is 20nm, and its material is IGZO. Generally speaking, the oxide semiconductor channel thickness H of the Schottky barrier thin film transistor 100 ranges from 5 to 100nm. The length of the source S of the Schottky barrier thin film transistor 100 is 600μm, and the channel length L is 60μm. The width W of the Schottky barrier thin film transistor 100 is 2mm. The Schottky source contact thickness h of the Schottky barrier thin film transistor 100 is 70nm, and its material is Pt (i.e., a metal). As described below, all metal layers in the Schottky barrier thin film transistor 100 are deposited by radio frequency sputtering.

[0136] For the Schottky barrier thin film transistor mechanism, IGZO should have high conductivity so that the source region can effectively control the current. This can be achieved by annealing the oxide semiconductor in a nitrogen atmosphere at 300°C (i.e., thermal annealing). However, since In3+ is reduced to In0 at high temperatures, the Schottky contact properties on the oxide semiconductor are highly dependent on the oxygen content at the interface (i.e., the interface between the Schottky source contact and the oxide semiconductor channel, the Pt–IGZO interface). Therefore, annealing the oxide semiconductor in a nitrogen atmosphere will reduce the oxygen content, resulting in poor Schottky barrier performance.

[0137] Figure 1C The Schottky barrier thin film transistor is described according to examples. Figure 1C The structure of the IGZO-Pt Schottky barrier thin film transistor 100A made on a Si / SiO2 substrate is shown in cross-sectional view. The Schottky barrier thin film transistor 100A is substantially similar to the Schottky barrier thin film transistor 100 described above.

[0138] Compared with the Schottky barrier thin film transistor 100, the Schottky barrier thin film transistor 100A further includes a field plate 170 formed of Pt, which extends from the Schottky source contact 150 and covers another dielectric layer 180 formed of SiO2. The dielectric layer 180 covers the third portion of the oxide semiconductor channel 140 between the Schottky source contact 150 and the drain contact 160, filling a portion of the gap therebetween. The field plate 170 provides capacitive coupling between the Schottky source contact 150 and the oxide semiconductor channel 140, thereby preventing an excessively high electric field from being generated near and / or at the edge of the Schottky source contact 150.

[0139] Figures 2A to 2M According to the example, the deposition conditions of the source contact and the thickness of the oxide semiconductor are adjusted, and the Schottky barrier thin film transistor is designed and optimized. Figure 2A The structure and current transfer path of ohmic contact TFT are described. Figure 2B The structure and current transfer path of a Schottky contact thin film transistor are described based on an example, showing how the current is saturated due to depletion under the source. Figure 2C The typical output characteristic curve of Ohmic contact TFT is shown according to the example. Figure 2D The output characteristic curve of the Schottky barrier thin film transistor is shown in the example: the saturation voltage shows a significant difference (with Figure 2C This is because the Schottky barrier thin film transistor is easily depleted under the source. Figure 2E XPS results at 60 W in Argon (top), 60 W in 3% O2 / Ar (middle), and 40 W in 3% O2 / Ar (bottom) are shown. Figure 2F|I|-V curves of Schottky diodes using different powers and oxygen contents during Pt deposition. Figure 2G The transfer characteristic curves of Schottky barrier thin film transistors using different powers and oxygen contents during Pt deposition are given. Figures 2H to 2J It shows that IGZO TFTs( Figure 2H ) at VD = 1V (see the device structure in the illustration), Schottky barrier thin film transistor at VD = 1V ( Fig.2I ) and Schottky barrier thin film transistor at VD = 10V ( Figure 2J )’s transfer characteristic curve. Figure 2K to 2M The thickness of IGZO is 50nm ( Figure 2K ), 30nm( Figure 2L ) and 20nm( Figure 2M ) when the output characteristic curve of Schottky barrier thin film transistor.

[0140] The source barrier is the most important feature of the Schottky barrier thin-film transistor. Forming a Schottky source on an oxide semiconductor is challenging and depends on whether there is sufficient oxygen content at the interface. However, since oxygen vacancies are donor states in oxide semiconductors, this further increases the difficulty of preparing the conductive channel. In addition, annealing performed after the device is prepared to improve the conductivity of the conductive channel will destroy the performance of the barrier, so annealing must be performed before depositing the Schottky contact. Therefore, in order to ensure that there is sufficient oxygen content at the interface, oxygen needs to be added during the deposition of the Schottky contact. The inventors were able to effectively control the oxygen content in the Pt film in a 3% O2 / Ar atmosphere and by adjusting the deposition power. As Figure 2E The XPS results in Figure 2 show that the oxygen content in the Pt film deposited in a pure argon atmosphere is negligible. When oxygen is introduced, the ratio of the O 1s to Pt 4p3 / 2 peak area increases, and the Pt 4f5 / 2 and 4f7 / 2 peaks shift to the left, indicating that the Pt film is oxidized. In addition, the oxygen content of the Pt film can be further increased by reducing the deposition power from 60W to 40W.

[0141] Schottky Barrier Thin Film Transistor

[0142] A conventional TFT consists of a source and a drain connected by a semiconductor channel. For the TFT to work properly, the contact should be ohmic, i.e., low resistance. The semiconductor channel is capacitively coupled to the gate electrode through an insulating dielectric, so the gate voltage can control the conductivity of the channel ( Figure 2A ). In Schottky barrier thin film transistors ( Figure 2B ), the source ohmic contact is replaced by a Schottky contact. Therefore, it is the source rather than the channel that determines the current. Figure 2C and Figure 2EThe output characteristic curves of the IGZO TFT and the Schottky barrier TFT demonstrate the effect of replacing the source ohmic contact with the Schottky source contact. The TFT current is saturated only at high drain voltages, while in the Schottky barrier TFT, the voltage at which the current reaches saturation is significantly reduced in the Schottky barrier TFT because the Schottky source completely depletes the semiconductor layer ( Figure 2B ). More importantly, the better the saturation of the Schottky barrier thin film transistor, the better the intrinsic gain (an important characteristic parameter of the transistor) is, which means that the intrinsic gain is much greater than that of the TFT.

[0143] We tested the performance of Schottky contacts with different oxygen contents by fabricating Pt-IGZO Schottky diodes and Schottky barrier thin-film transistors. Figure 2F is the |I|-V curve of Schottky diode, Figure 2G The transfer characteristic curve of the Schottky barrier thin film transistor. The Pt-IGZO diode without oxygen treatment is actually close to an ohmic contact due to the formation of a lower barrier in the Schottky contact. The lower barrier is caused by the reduction of In3+ to In0 due to insufficient oxygen content at the interface. Using oxygen-rich Pt as the contact electrode, the barrier will be more uniform, thereby reducing the reverse current in the diode and the on-current in the Schottky barrier thin film transistor. The strong bias dependence of the diode reverse current and low temperature measurements prove that some barrier height non-uniformity still exists ( Fig.9A and Fig. 9B ). In addition, the barrier height extracted from the diode IV curve shows that changes in deposition power also affect the barrier non-uniformity. Higher deposition power leads to faster Pt deposition rate and less oxygen content introduced at the Pt-IGZO interface, causing the barrier height to decrease with increasing deposition power ( Fig. 9C ). Therefore, the increase in power leads to an increase in the on-current of the Schottky barrier thin film transistor and a decrease in the turn-on voltage. Although the Schottky barrier thin film transistor can have a higher on-current at a deposition power of 100W, a deposition power of 60W can provide a uniform barrier height, so 60W is selected as the optimal condition for Pt deposition. For more information on the effect of deposition conditions on the barrier, see Fig. 9C .

[0144] Figure 2F According to an example, an |I|-V curve of the Schottky diode 10 is shown. Figure 2F|I|-V curves of Schottky diodes using different sputtering powers and oxygen contents during Pt deposition. The oxide semiconductor channel thickness H of Schottky diode 10 is 150nm, and its material is IGZO. The Schottky source contact thickness h of Schottky diode 10 is 70nm, and its material is Pt. The ohmic contact layer thickness h of Schottky diode 10 is 70nm, and its material is Ti. We fabricated a series of Schottky barrier thin film transistors by depositing Schottky source contact Pt at a power of 60W in the absence of oxygen and at powers of 40W, 60W, and 100W in a 3% O2 / Ar atmosphere, respectively.

[0145] like Figure 2F As shown in Figure 1, depositing Pt in the absence of oxygen results in an ohmic IGZO-Pt contact. In order to increase the oxygen content in the interface (i.e., the interface between the Schottky source contact and the oxide semiconductor channel) without adversely affecting the conductivity of the IGZO channel (i.e., the oxide semiconductor channel), we first thermally annealed the oxide semiconductor and then deposited Pt in an atmosphere of 3% O2 / Ar. In addition, the reverse current of the diode increased with increasing Pt deposition power ( Figure 2F ). For example, when V = -1 V, the current in the diode at 100 W is two orders of magnitude greater than the current in the diode at 40 W. Increasing the deposition power above 100 W has limited effect on the current.

[0146] like Figure 2G As shown, similar results to those of the Schottky diode 10 can be observed in the transfer characteristic curve of the Schottky barrier thin film transistor 100. Comparing the Schottky barrier thin film transistor 100 prepared by depositing Pt at 40W in a 3% O2 / Ar atmosphere and depositing Pt at 60W in a 3% O2 / Ar atmosphere, the turn-on voltage of the former is 6V higher than that of the latter. The device prepared by depositing Pt at 60W in a 3% O2 / Ar atmosphere has a higher current and a turn-on voltage close to zero, so the device performance is more superior. However, when the deposition power is greater than 60W, the improvement of the turn-on current and turn-on voltage is limited.

[0147] This strong dependence of the reverse current may be related to the inhomogeneity of the barrier. Since higher deposition power leads to faster Pt deposition rate, less oxygen components are introduced at the Pt-IGZO interface during sputtering. Therefore, when using higher deposition power, more In3+ is reduced, resulting in a higher density in the low barrier region and a higher reverse current. However, at higher power, due to the reduction in the difference in oxygen content, the current variation also decreases.

[0148] Variation of Schottky barrier thin film transistor performance with thickness

[0149] The inventors have shown that the reverse current of Schottky diodes has a significant dependence on the semiconductor thickness. Therefore, the performance of Schottky barrier thin film transistors can be optimized by adjusting the thickness. To verify this hypothesis, IGZO TFTs and Schottky barrier thin film transistors (IGZO TFTs) with IGZO thicknesses of 20nm, 30nm and 50nm were fabricated simultaneously. Fig.10 Statistical analysis of the transfer characteristic curves of 20nm Schottky barrier thin film transistors is shown). All IGZO TFTs have a mobility of about 7cm2V-1s-1 and a VT of about 2V. There is no obvious thickness dependence of IGZO TFTs ( Figure 2H ). In contrast, Fig.2I and Figure 2J The transfer characteristic curve of the Schottky barrier thin film transistor in shows a strong thickness dependence.

[0150] First, when the drain voltage VD = 10V, the turn-on voltage VON increases from -18V at 50nm to 0V at 20nm. The modulation of VON can be attributed to the difficulty of depletion under the Schottky source. Thinner semiconductors are more easily depleted, so a larger positive voltage VG is required to open the channel. Secondly, Fig.2I The thinner devices in the circuit have larger on-state currents, which cannot be explained by the existing literature.

[0151] Figure 2K , there are two other trends in the output characteristic curves of 2L and 2M that cannot be explained by existing theories. First, the thinner the semiconductor, the more linear the curve at low VD. Second, in the saturation region of this device, a thinner semiconductor layer can provide a flatter saturation current. The flatness of the saturation current is particularly important for obtaining high intrinsic gain. In addition, when the IGZO thickness is reduced from 50nm to 20nm, it is observed that the intrinsic gain will increase by nearly two orders of magnitude. In order to investigate the root of this thickness dependence, we performed device simulations, which are described in detail below.

[0152] For a fully depleted non-uniform diode, its effective barrier height may be related to the thickness. By adjusting the thickness H of the oxide semiconductor channel of the Schottky barrier thin film transistor 100, we optimize the effective barrier height of the Schottky barrier thin film transistor.

[0153] Using IGZO as an oxide semiconductor, we fabricated TFTs and Schottky barrier thin film transistors 100 with semiconductor channel layers of 10nm, 20nm, 30nm and 50nm thickness, respectively. Ti deposited in pure Ar atmosphere was used as the TFT source-drain contact electrode. Pt deposited at 60W in 3% O2 / Ar atmosphere was used as the Schottky barrier thin film transistor 100 Schottky source contact electrode 150.

[0154] according to Figure 2K , 2L and 2M show the ID-VD output characteristic curve of the Schottky barrier thin film transistor 100, the saturation voltage decreases as the thickness of the oxide semiconductor channel decreases. This is consistent with the dual dielectric model:

[0155]

[0156] Where VDsat1 is the voltage required to completely deplete the oxide semiconductor channel 140 under the Schottky source contact 150 (also called the source saturation voltage), VT is the threshold voltage of the Schottky barrier thin film transistor, and CS and CG are the unit area capacitances of the oxide semiconductor channel 140 and the gate insulating layer 120, respectively. Usually, VDsat1 is much lower than the drain saturation voltage VDsat2 of conventional TFTs.

[0157] V Dsat2 =V G -V T

[0158] We also observed two unexpected trends.

[0159] First, for the Schottky barrier thin film transistor 100 with thinner oxide semiconductor channel thickness (eg, 30 nm and 50 nm), the saturation current is flatter.

[0160] Secondly, for Schottky barrier thin film transistors 100 with thinner oxide semiconductor channel thickness H (e.g., 30nm and 50nm), there is a more linear ID-VD output curve before saturation. The VD dependence of the saturation current is particularly important for achieving high intrinsic gain, which will be described in detail below.

[0161] Effect of potential barrier non-uniformity

[0162] The operating characteristics of the Schottky barrier thin film transistor can be described using a distributed network of diodes and resistors in the depletion region or envelope of the Schottky source contact (150).

[0163] Figure 3A A model of a Schottky barrier thin film transistor (100) is described according to an example. In particular, Figure 3A A cross-sectional view of a distributed diode model of a Schottky barrier thin film transistor (100) is shown.

[0164] As mentioned above about Figure 1BThe Schottky barrier thin film transistor (100) includes a gate contact (110) formed of Si, a gate insulator layer (120) formed of SiO2, an IGZO oxide semiconductor channel layer (140) covering the gate insulator layer (120) of the substrate, a Schottky source contact (150) covering a first portion of the oxide semiconductor channel (140), and a drain contact (160) covering a second portion of the oxide semiconductor channel (140). The Schottky barrier thin film transistor (100) includes a gate contact (170) on the reverse side of the substrate Si layer (110). The Schottky source contact electrode (150) and the drain contact electrode (160) are spaced apart by a length L. The thickness of the oxide semiconductor channel (140) is H. The thickness of the Schottky source contact electrode (150) is h.

[0165] The channel layer (140) of the oxide semiconductor can be regarded as a plurality of diodes D S A distributed network (in this example, four diodes are connected in parallel with each other and arranged in series with a fifth diode), and a plurality of resistors R between the depletion region or envelope of the Schottky source contact (150) SC (4 in this example) and R CH (3 in this example), where the resistor R SC The resistor R is at least partially an oxide semiconductor. CH is at least partly the resistance of the channel. In use, the drain current I D The drain current I1 is controlled by the reverse biased source barrier. In mode 1, the current I1 is controlled by adjusting the barrier height at the edge of the Schottky source electrode (150) closest to the drain contact (160). In mode 2, the current I2 is controlled by adjusting the depletion region formed under the edge of the Schottky source contact (150) similar to the JFET principle. D =I1+I2. That is, the reverse biased diode controls the drain current.

[0166] Since the oxide semiconductor channel (140) is highly conductive, vertical transport is likely dominated by a reverse biased diode at the Schottky source contact (150) rather than vertical resistance. The exponential current increase in the reverse biased diode may be attributed to a variety of reasons, including tunneling, reduced image force, and / or barrier inhomogeneity. However, if tunneling or reduced image force is the source of the exponential current increase, then the electric field will increase as the oxide semiconductor channel thickness H decreases. Therefore, I D V D The exponential dependence of will only be exacerbated by reducing the oxide semiconductor channel thickness H. Figure 2K to 2MAs shown in the experimental results, reducing the thickness H of the oxide semiconductor channel can eliminate the exponential growth, so the effects of tunneling and / or image force reduction can be considered small and / or negligible. The dependence of the reverse current on the thickness H of the oxide semiconductor channel in the Pt-IGZO Schottky diode (10) may be due to the non-uniformity of the barrier height. However, to date, there has been no research on the non-uniformity in the Schottky source contact in Schottky barrier thin film transistors.

[0167] Figure 3B The model structure of Schottky barrier thin film transistor is demonstrated based on examples. Figure 3B A model cross-sectional view of a Schottky barrier thin film transistor is shown in which a source barrier in a Schottky source contact (150) includes a non-uniformity (180) (also referred to as a barrier non-uniformity or a low barrier region).

[0168] According to the above Figure 1B and Figure 3A The Schottky barrier thin film transistor (100) includes a gate contact (110) formed of Si, a gate insulator layer (120) formed of SiO2, an IGZO oxide semiconductor channel layer (140) covering the gate insulator layer (120) of the substrate, a Schottky source contact (150) covering a first portion of the oxide semiconductor channel (140), and a drain contact (160) covering a second portion of the oxide semiconductor channel (140). The Schottky barrier thin film transistor (100) includes a gate contact (170) on the reverse side of the substrate Si layer (110). The Schottky source contact electrode (150) and the drain contact electrode (160) are spaced apart by a length L. The thickness of the oxide semiconductor channel (140) is H. The Schottky source contact electrode (150) has a thickness of h (i.e., the Schottky source contact thickness) and a length of s (i.e., the Schottky source contact length s). The barrier non-uniform region (180) has a width of 10 nm, which results in a low barrier region (LBR), and the distance between this non-uniform region and the drain end of the Schottky source contact electrode (150) is P.

[0169] The Schottky barrier thin film transistor 100 is simulated using Silvaco Atlas (RTM) provided by Silvaco Corporation (USA). Figure 3B As shown, a barrier non-uniform region 180 is inserted into the Schottky source contact electrode 150. Only the barrier height below the average barrier height is considered. 0.5 eV barrier non-uniformity, as higher non-uniform barrier regions are not expected to have a significant impact on the drain current I DTo help understand the impact of the randomly distributed non-uniformity in the Schottky source contact electrode 150 on device performance, we changed the location and size of the barrier non-uniform region 180. The contact length S of the Schottky source was fixed to 5 μm. The length L between the Schottky source 150 and the drain 160 was fixed to 2 μm (also called the channel length). The channel width was fixed to 1 μm. The width L0 of the barrier non-uniform region 180 was 10 nm.

[0170] like Figure 3B As shown, we simulated a Schottky barrier thin film transistor by using Silvaco Atlas and inserted the barrier inhomogeneity region (IH) into the Schottky source contact. Figure 3C The output characteristic curve I of the Schottky barrier thin film transistor 100 in the example is depicted. D -V D .in Figure 3C The output characteristic curve I of the Schottky barrier thin film transistor 100 with a uniform source barrier is shown. D -V D , the output characteristic curve V G Increase the voltage from 0V to 10V in steps of 1V.

[0171] In more detail, Figure 3C The output curve I of the simulated Schottky barrier thin film transistor 100 with a Schottky source 150 having a uniform barrier height is shown. D -V D , the channel thickness H of the oxide semiconductor, IGZO, is 100nm. Note that this uniform barrier Schottky source contact 150 is impossible to achieve in actual preparation, and is only used for comparison and analysis. This output characteristic curve is a typical curve of a standard Schottky barrier thin film transistor. When V G The device has a low saturation current I of 0.7nA at 10V. Dsat1 , 2.6V low saturation voltage V Dsat1 And a high output impedance r0 of 200GΩ.

[0172] Figure 3D The output curve I of the Schottky barrier thin film transistor 100 in the example is shown. D -V D .in Figure 3D The output curve I of the simulated Schottky barrier thin film transistor 100 is shown. D -V D , its gate contact voltage V GThe voltage increases gradually from 0V to 10V with a step length of 1V. The Schottky barrier thin film transistor 100 has a 100nm thick IGZO oxide semiconductor channel layer. The width P of the barrier non-uniform region is 10nm, and the amplitude Δ=0.3eV. The low barrier region (LBR) is located 100nm away from the drain contact end of the Schottky source 150.

[0173] and Figure 3C compared to, Figure 3D The output curve of the Schottky barrier thin film transistor in which the Schottky source contact electrode 150 has a non-uniform potential barrier is shown. Figure 3D and Figure 3C The other parameters of the Schottky barrier thin film transistor are the same. In this example, the low barrier region (LBR) is located 100nm away from the Schottky source 150 and drain contact ends. The barrier in this area is reduced by Δ=0.3eV. The presence of LBR leads to a significant reduction in output impedance and an increase in current by more than an order of magnitude. The nonlinear region seen in the experiment was also successfully demonstrated, indicating that the non-uniform barrier may be Figure 2D and Figure 2E The source of the undesirable characteristics shown in . Similar characteristics are also observed for different barrier lowering values ​​Δ, distance P and width L0. Before saturation, different gate contact voltages V G The output curves of the device overlap. This is because the Schottky source is only 5μm long in the device simulation. The limitation on the number of model nodes in the simulation software cannot accurately simulate the barrier non-uniform area while increasing the source length.

[0174] from Figure 3E From the current distribution, it can be seen that the current is mainly contributed by the low potential barrier inhomogeneous area.

[0175] Figure 3E Shows Figure 3D The current density of the Schottky barrier thin film transistor 100 is Figure 3E shows the gate voltage V G (from 0.2V to 2V, step size is 0.2V), Figure 3D The distribution of current density |J| at the Schottky source 150 of the Schottky barrier thin film transistor 100. Here, the Schottky barrier thin film transistor 100 has a channel of IGZO oxide semiconductor, and its thickness H is 20nm. The width L0 of the non-uniform barrier region 180 is 10nm, Δ=0.3eV. The low barrier region (LBR) is located at a distance of P=100nm from the drain contact end of the Schottky source 150.

[0176] More specifically, in order to determine Figure 3D The origin of the nonlinear current curve shown in Figure 2 is that we take the drain voltage VD The current density profile at the Schottky source contact 150 below saturation. Figure 3E It can be seen that the current density |J| mainly flows out from the potential barrier non-uniform region 180. Different from the current density |J| contributed by the Schottky source 150, when the drain voltage VD increases from 0.2V to 2V, this current density |J| increases exponentially by two orders of magnitude.

[0177] Figure 3F The current density distribution along the Schottky interface is shown, and the IGZO layer thickness H is 100nm. Different from the rest of the source, when V D When increasing from 0.2V to 2V, the current through the inhomogeneous barrier region increases exponentially by two orders of magnitude. Figure 3G The reason for its exponential growth is shown in the figure, which shows that the device barrier saddle point changes with voltage, which means that the effective barrier height also changes with voltage. Figure 3M As shown in Figure 2, when H = 20 nm, the saddle point is much lower at zero bias, and more importantly, the degree of change of the saddle point with bias is also much lower. D There is no index I D -V D Once the device is saturated, since the saddle point no longer exists, its source-drain saturation current is flatter and the gain increases by an astonishing 2 orders of magnitude.

[0178] Figure 3G Shown Figure 3D The conduction band minimum E of the Schottky barrier thin film transistor C The distribution with depth z. That is, Figure 3G Plotted as depth z and conduction band minimum E C For 10V V G , Figure 3G Shows V D The depth distribution of the minimum value of the conduction band below the center of the non-uniform barrier region when changing from 0V to 2V in steps of 0.2V. The Schottky barrier thin film transistor 100 has a 100nm thick IGZO channel. The width L0 of the non-uniform barrier region is 10nm, and the amplitude Δ=0.3eV. The low barrier region (LBR) is located at a distance of P=100nm from the drain contact end of the Schottky source 150. E C -z depth profiles show the respective potential saddle points (SP 0V -SP 2V ) (i.e., the maximum of the lowest energy level of the conduction band). For clarity, we only label the saddle point SP 0V and SP 2V .

[0179] In more detail, the above Figure 3F The reason for the exponential growth of the current density |J| can be found in Figure 3G It can be seen in. Figure 3G The contours of the lowest energy level of the conduction band from the center of the non-uniform barrier region 180 vertically downward to the semiconductor-dielectric interface are shown. These contours show that barrier saddle points are formed below the non-uniform barrier region due to the influence of the surrounding higher barrier regions. These barrier saddle points become the effective barrier height of the non-uniform region barrier, and thus further determine the effective barrier height of the entire Schottky source contact electrode 150. The degree to which the height of each saddle point varies with voltage leads to an exponential increase in current before saturation.

[0180] like Figure 3H and 3I The output curve and Figure 3J and 3K As shown in the transfer curves, the simulation results clearly reproduce the thickness dependence seen in the experiment.

[0181] Figure 3J Describes the transfer curve of the Schottky barrier thin film transistor model |I D |-V G . Figure 3J The Schottky barrier thin film transistor with a non-uniform barrier region 1 μm away from the source and drain ends is shown in V D = |I at 1V D |-V G Transfer curves, the thickness H of the oxide semiconductor channel layer of the transistor is 10nm, 20nm, 30nm, 50nm and 100nm respectively. The non-uniform barrier region has a width of 10nm and an amplitude Δ=0.3eV. Average barrier height The low barrier region (LBR) is located at a distance of 150 nm from the drain contact end of the Schottky source electrode P = 100 nm. The simulation results are compared with the experimental results. Fig.2I Different Δ values ​​and average barrier height Similar results can be obtained.

[0182] Figure 3K The Schottky barrier thin film transistor with a non-uniform barrier region 1 μm away from the source and a gate oxide thickness H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm is shown. D = Simulated transfer curve at 10V |I D |-V G The width H of the non-uniform barrier region is 10 nm, and the amplitude Δ = 0.3 eV. The average barrier height The low barrier region (LBR) is located at a distance of 150 nm from the Schottky source and drain contact terminals P = 100 nm. The simulation results are compared with the experimental results. Figure 2J Different Δ values ​​and average barrier height Similar results can be obtained.

[0183] Figure 3L The results show that for different semiconductor thicknesses, the distance from the center of the inhomogeneous barrier region to the Figure 3E The vertical dashed line in the figure shows the distribution of the conduction band minimum energy. For thicker semiconductor layers, a saddle point is formed below the inhomogeneous region due to the depletion of the surrounding higher barrier region. When IGZO becomes thinner, the electric field increases and reduces the saddle point height until it disappears completely when it is thinned to a certain thickness.

[0184] Figure 3L The depth distribution E of the conduction band minimum energy of Schottky barrier thin film transistor is described based on an example. C -z. Figure 3L The depth distribution E of the conduction band minimum energy below the center of the inhomogeneous potential barrier region under zero bias (i.e., V = 0 V) ​​is shown. C -z and the relationship between the oxide layer thickness H, where the channel thickness H is 10nm, 20nm, 30nm, 50nm and 100nm respectively. The oxide semiconductor is IGZO. The width L of the non-uniform barrier region a The lower barrier region (LBR) is 100 nm away from the drain contact end of the Schottky source contact electrode 150. The average barrier height is This shows that the effective barrier height varies with the thickness H of the oxide semiconductor channel.

[0185] For all oxide semiconductor channels with thickness H of 10 nm, 20 nm, 30 nm, 50 nm and 100 nm, the conduction band minimum energy E at the interface of the Schottky source contact 150 – oxide semiconductor 140 is C same.

[0186] The oxide semiconductor channel thickness H is 20nm, 30nm, 50nm and 100nm. C -z depth distribution with different potential saddle points (SP 20nm , S.P. 30nm , S.P. 50nm , S.P. 100nm For these oxide semiconductors with channel thickness H of 20nm, 30nm, 50nm and 100nm, the maximum value of the conduction band minimum energy is C -z depth profile analysis, conduction band minimum E CAs the distance from the interface between the Schottky source contact electrode 150 and the oxide semiconductor 140 increases, at each barrier saddle point (SP 20nm , S.P. 30nm , S.P. 50nm , S.P. 100nm ) and then decrease monotonically in the oxide semiconductor 140. Each saddle point SP 20nm , S.P. 30nm , S.P. 50nm , S.P. 100nm They are located at different positions of approximately 4nm, 6nm, 9nm and 14nm respectively.

[0187] The oxide semiconductor channel thickness H is 10nm. C -z depth profile analysis shows no potential saddle point. This means that when the oxide semiconductor channel thickness H = 10nm, the conduction band minimum energy E C The maximum value of is at the interface of the Schottky source contact electrode 150 and the oxide semiconductor 140, and the conduction band has the lowest energy E C It decreases monotonically away from the interface.

[0188] According to the experimental results, as above Figure 3H and 3I As described above, as the thickness H of the oxide semiconductor channel decreases, the exponential growth before current saturation disappears. Figure 3L The conduction band minimum energy E of different oxide semiconductor channel thicknesses H under zero bias is compared. C The distribution of the barrier saddle point is shown in the figure. The barrier saddle point changes with the thickness H of the oxide semiconductor channel layer, which is the same phenomenon observed in the Schottky diode. As the oxide semiconductor channel thickness H decreases, the electric field increases and reduces the height of the barrier saddle point. When the oxide semiconductor channel thickness H is small enough, for example, when the oxide semiconductor channel thickness H is 10nm, the barrier saddle point is finally completely removed. In the absence of the barrier saddle point, the effective barrier height of the non-uniform barrier region 180 no longer changes with voltage, and the drain current I D will no longer change with the drain voltage V D grows exponentially. In this way, the trend observed in the experiment is reproduced. This effect is valid for all non-uniform barrier regions, except for those non-uniform potential barriers at the edge of the Schottky source contact electrode 150, because these barriers cannot be affected by the surrounding high barrier regions, so there is no saddle point. If the Schottky source contact electrode 150 is long enough, the current from the edge of the Schottky source contact electrode 150 can be ignored because the contribution to the current inside the source contact is dominant. Once the barrier saddle point is lowered, since the diffusion current depends only on the change in the electric field, the relationship between the current change with voltage before saturation will become linear, that is, with the drain voltage V DLinear changes.

[0189] Once the drain voltage V D When the current is large enough to deplete the oxide semiconductor 140 under the edge of the Schottky source contact 150, the Schottky barrier thin film transistor 100 reaches saturation, regardless of whether the current was linear or exponential before. However, as in the above experiment, the output impedance will still be affected by the oxide semiconductor channel thickness H. Unlike the situation before the source is saturated, the uneven potential barriers at various locations of the Schottky source contact 150 will not seriously affect the output impedance. This is because after saturation, the potential from the drain contact electrode 160 cannot be transmitted to the inside of the source. At this time, the potential can only be transmitted to the area at the boundary of the Schottky source contact electrode 150. At this time, a slight change in the barrier height at the boundary will produce a certain current change, thereby reducing the output impedance. A slight change in the drain voltage will cause a change in the height of the barrier saddle point in the boundary region, resulting in an exponential change in the current. Similarly, by reducing the thickness H of the oxide semiconductor channel, these barrier saddle points can be removed, thereby obtaining a voltage-independent barrier height (ignoring the reduction of the mirror force and the tunneling effect) and a higher output impedance, as shown Figure 3H and 3I As shown. Fig. 3I and Figure 3J The simulated transmission characteristic curve described in further confirms that the potential barrier non-uniform region 180 is the reason for this effect.

[0190] Intrinsic Gain

[0191] As shown in the device simulation, because the saddle point of the conduction band minimum is removed or approximately removed, the intrinsic gain of our Schottky barrier thin film transistor is very high. The intrinsic gain AV is the maximum voltage gain of the thin film transistor, so it is an important indicator of the thin film transistor's ability to amplify signals. In particular, the intrinsic gain AV of the thin film transistor is therefore considered to be one of the indicators that describe the performance of the device. In applications in the display field, thin film transistors with high intrinsic gain can be used as constant current sources. At the same time, high intrinsic gain will also provide logic circuits with a greater noise safety factor and improve their noise immunity. The intrinsic gain AV can be calculated as the ratio of the transconductance gm and the output conductance gd, or as the product of the transconductance gm and the output resistance r0:

[0192]

[0193] or

[0194] A V =g m r0

[0195] in

[0196]

[0197] and

[0198]

[0199] Currently, the intrinsic gain of silicon-based metal oxide semiconductor field effect transistors is generally in the range of 20-40, but the intrinsic gain of polysilicon thin film transistors with long channels has been demonstrated to be higher than 100. Given the characteristics of the saddle point, the intrinsic gain can be maximized by reducing the thickness of the IGZO film in our device.

[0200] However, it is difficult to directly derive the intrinsic gain from the current-voltage characteristic curve of our Schottky barrier thin film transistors because the output curve is very flat. This flatness requires high-precision testing of the smallest changes in current ID, reaching the limit resolution of our test equipment.

[0201] Figure 5A The output curve of the Schottky barrier thin film transistor with 20nm thick IGZO shows that when VD changes from 15V to 60V, the current changes by only pA. The red solid line is the linear fit of the result from 15V to 60V, and the dotted line shows the degree of fluctuation.

[0202] use Figure 5A The linear fitting results show that when VG is equal to 10V, 20V and 30V, the intrinsic gain reaches 19,000, 29,000 and 11,000 respectively. The gain value obtained by 15-point smoothing of the output curve is highly consistent with the linear fitting result, and the gain value under some bias voltages is as high as 100,000 ( Figure 5B ). To further confirm the high gain characteristics, the Schottky barrier thin film transistor was connected to the inverter using a current source as a load ( Figure 5C Inset). With 60V on the drain, the voltage gain during inversion reaches 6,200.

[0203] According to the example, Figure 5D The functional relationship between the intrinsic gain AV and the drain voltage VD of the Schottky barrier thin film transistor 100 is shown. In particular, Figure 5D The relationship between the drain voltage VD and the intrinsic gain AV of the Schottky barrier thin film transistor 100 with an oxide semiconductor channel thickness H of 10 nm, 20 nm, 30 nm and 50 nm respectively when the gate voltage VG is 40 V is shown, wherein the oxide semiconductor is IGZO.

[0204] like Figure 5DAs shown, among the devices with oxide semiconductor channel thickness H of 10nm, 20nm, 30nm and 50nm, the Schottky barrier thin film transistor 100 with oxide semiconductor channel thickness H of 20nm (wherein the oxide semiconductor is IGZO) has a maximum intrinsic gain AV of 3,000 under a wide range of drain voltage VD. The Schottky barrier thin film transistor 100 with oxide semiconductor channel thickness H of 50nm has an intrinsic gain of up to 20 at a drain voltage VD of 15V. At a drain voltage VD of 15V, the Schottky barrier thin film transistor 100 with oxide semiconductor channel thickness H of 20nm and 30nm respectively has an intrinsic gain AV of up to 100. In particular, compared with standard transistors, the Schottky barrier thin film transistor 100 with semiconductor channel thickness H of 20nm has an intrinsic gain AV of 3,000, showing a huge improvement. Compared to Schottky barrier thin film transistors based on other materials, the Schottky barrier thin film transistor 100 maintains an intrinsic gain AV of more than 1,000 over a wide voltage range. Although some polysilicon Schottky barrier thin film transistors have achieved an intrinsic gain AV of 10,000 over a narrow drain voltage VD range, the intrinsic gain AV of oxide semiconductor Schottky barrier thin film transistors has been only 400 so far. It is impossible to achieve a huge improvement in the intrinsic gain AV of the Schottky barrier thin film transistor 100 by simply understanding the conventional working mechanism of the Schottky barrier thin film transistor. Rather, the theory of barrier non-uniformity, which is particularly common in oxide semiconductor Schottky junctions, is also important for achieving high-performance devices. First, source saturation makes the source unaffected by the non-uniform Schottky barrier. Second, by reducing the semiconductor channel thickness H, the barrier saddle point at the conduction band minimum EC caused at least in part by the barrier non-uniformity in the low barrier region is reduced or removed. The combination of the two effects helps to reduce the drain current variation caused by small changes in the drain voltage, thereby maintaining a nearly constant current.

[0205] like Figure 5D As shown, when the semiconductor channel thickness H is less than 10nm, the intrinsic gain AV does not increase further. More specifically, in the Schottky barrier thin film transistor 100 with such a small oxide semiconductor channel thickness H, the electric field becomes so large that tunneling and other barrier lowering mechanisms affect the saturation current of the output curve. The acquisition of the maximum intrinsic gain AV in these examples is limited by the hysteresis caused by gate contact leakage current and defects. Especially in high-gain Schottky barrier thin film transistors 100, these factors can lead to errors in gain measurement.

[0206] Short channel effect

[0207] In order to achieve high-density integration, the size of transistors must be reduced, but the short channel effect has always been the main obstacle to reducing the size of transistors. In the case of IGZO thin-film transistors, reducing the channel length to less than 5 microns will produce a high enough electric field to make the saturation current strongly dependent on VD. In contrast, Schottky barrier thin-film transistors are more resistant to short channel effects because it is the source region rather than the channel and the size of the channel that determines the source-drain current.

[0208] Using electron beam lithography, the inventors fabricated IGZO Schottky barrier thin film transistors with channel lengths of 360, 602, and 1640 nm. Scanning electron microscope (SEM) images of the devices with the three channel lengths are shown in Figure 1. Fig. 6A shown. Figure 6B , 6C and 6D show that VD remains flat at 20V with a channel length of 360nm. To our knowledge, this resistance to short channel effects has never been achieved in oxide semiconductors. In addition, the current is always consistent and is independent of the channel length, which means that Schottky barrier thin-film transistors have greater tolerance for alignment accuracy, which is very important for large-area electronic circuits.

[0209] Negative bias light temperature stress

[0210] In conventional thin film transistors, oxide semiconductors, such as IGZO, the channel is very sensitive to the effects of light and negative gate bias, an effect known as negative bias light temperature stress (NBITS). This stress causes the threshold voltage of conventional TFTs to move toward negative voltages during use, which is a difficult problem to solve for TFT applications in backlight displays. Schottky barrier thin film transistor 100 eliminates this problem because the current only depends on the source, so no additional shielding layer is required, as described in more detail below.

[0211] When a conventional IGZO thin-film transistor is irradiated with photons close to the bandgap energy and is under negative bias, the threshold voltage VT of the oxide semiconductor channel shows a large negative shift. This instability is attributed to deep energy level defects formed by oxygen vacancies. Photons close to the bandgap energy will excite electrons (holes) into the conduction band. These holes will move toward the gate contact under the action of the electric field and may be trapped in the interface or gate dielectric. When the bias disappears, these holes will still be trapped, causing electrons to accumulate on the IGZO side of the interface. Although the threshold voltage VT can be reduced by various measures, such as high-voltage annealing and the use of asymmetric source-drain contacts, it is still impractical to integrate IGZO Schottky barrier thin-film transistors into displays without taking light-shielding measures. Such light-shielding measures eliminate the transparency advantage of IGZO Schottky barrier thin-film transistors and introduce additional manufacturing steps.

[0212] In contrast, the Schottky barrier thin film transistor 100 does not have the negative drift of the threshold voltage VT of the conventional IGZO thin film transistor. The NBITS test was performed on the 20nm thick IGZO Schottky barrier thin film transistor 100. The device was placed in an environment with VG = -20V, a temperature of 60°C, and an LED white light intensity of 2000lx. After 20h of stress testing, the VON of the device had almost no change, as shown in Figure 2. Figure 7 This high stability should come from the fact that the current is independent of the channel conductivity. The high resistance of the source will mask the instability of the channel. This resistance to negative bias light temperature stress eliminates the long-standing obstacle for the widespread application of oxide semiconductors in the display industry.

[0213] Applications of other oxide materials

[0214] In this work, through further understanding of the working principle and design method, even the commonly said limitation that the channel layer can only be a semiconductor is eliminated. A semi-metal oxide ITO was tested here. It is difficult to use this material in ordinary thin-film transistors, such as the lack of gate modulation in ITO thin-film transistors. Fig. 8A However, Figure 8B As shown, the output characteristics of the ITO Schottky barrier thin film transistor are Figure 2M The output characteristics of the IGZO Schottky barrier thin film transistor in the ITO Schottky barrier thin film transistor are similar. It shows that the design of Schottky source contact can broaden the material selection range of the channel layer.

[0215] simulation

[0216] The device simulation part of the present invention uses Silvaco Atlas software. Atlas is used to solve Poisson's equation, carrier continuity equation and charge transport equation. The barrier non-uniform region 180 is introduced into the Schottky source contact 150, and we simulate the Schottky barrier thin film transistor structure. In addition to the barrier height of The non-uniform area of ​​the Schottky contact source barrier height Assumed to be 0.5eV. Because higher potential barriers do not contribute much to the current, we only consider potential barriers with a height lower than The non-uniform region. Therefore, the value of Δ changes from 0 (simulating a uniform source) to 0.3 eV. The distance P between the edge of the Schottky contact source 150 close to the drain 160 and the non-uniform region is 0, 10, 100, 1000 and 4000 nm, respectively. The width of the non-uniform region is also set to 3, 10 and 30 nm, respectively. Unless otherwise specified, the source length and channel length are set to 5μm and 2μm, respectively. The semiconductor channel thickness is 10nm, 20nm, 30nm, 50nm and 100nm, respectively. The oxide semiconductor is IGZO, and the default Atlas model of IGZO is used. The dielectric layer is SiO2, and the dielectric thickness is 100nm. The length of the drain contact 160 is 1μm, and the gate contact overlaps the entire device. The channel width LCH is 1μm.

[0217] Schottky diode preparation process

[0218] An IGZO-Pt Schottky diode 10 was fabricated using Ti as an ohmic contact. The substrates 11 and 12 were SiO2-Si wafers, which were cleaned in an ultrasonic cleaner using Decon90, deionized water, acetone, and isopropanol, respectively. Then, a 20 nm thick titanium layer was deposited on the wafer as an ohmic contact layer 13 by radio frequency sputtering. During the sputtering of titanium, the working gas atmosphere was 5×10-3 mbar of argon and the sputtering power was 150 W. A 150 nm thick IGZO layer was deposited by radio frequency sputtering, and the IGZO target material was a target with a molecular ratio of In2O3:Ga2O3:ZnO of 1:1:2 provided by Kurt J Lesker Company Ltd (UK). The working gas atmosphere during the IGZO sputtering process was 5×10-3 mbar of argon and the sputtering power was 100 W. Before Pt deposition, the structure needed to be annealed in a nitrogen atmosphere at 300°C for 1 h. Then, the 70 nm thick Pt layer as the Schottky source contact 15 is also deposited by sputtering a Pt target provided by Leybold Materials GmbH (Germany), the working gas atmosphere is 5×10-3mbar argon containing 3% oxygen, and the sputtering power is 60 W. Unless otherwise specified, the sputtering target diameter is 3 inches (i.e. 1.32 W / cm2 when sputtering at 60 W). A mask is used to define the pattern of the Schottky diode.

[0219] Preparation process of Schottky barrier thin film transistor

[0220] Both the Schottky barrier thin film transistor 100 and the thin film transistor use a silicon wafer covered with 100nm thick SiO2. The silicon wafer was cleaned in an ultrasonic cleaner using Decon90, deionized water, acetone and isopropanol. The oxide semiconductor channel layer 140 uses sputtered IGZO, and the IGZO target material uses a target material with a molecular ratio of In2O3:Ga2O3:ZnO of 1:1:2 provided by Kurt J Lesker Company Ltd (UK). The working gas atmosphere of the IGZO sputtering process is argon at 5×10-3mbar, and the sputtering power is 100W. Before Pt deposition, the structure needs to be annealed in a nitrogen atmosphere at 300°C for one hour. Then, the 70 nm thick Pt layer as the Schottky source contact 15 is also deposited by sputtering a Pt target provided by Leybold Materials GmbH (Germany), the working gas atmosphere is 5×10-3 mbar of argon containing 3% oxygen, and the sputtering power is 60 W. Unless otherwise specified, the diameter of the sputtering target is 3 inches. The preparation method of the IGZO thin film transistor is similar to that of the Schottky barrier thin film transistor, but Ti is used instead of Pt as the source and drain contacts, and the sputtering method is the same as that of the Schottky diode. Except for the channel layer, the preparation method of the ITO Schottky barrier thin film transistor is the same as that of the IGZO Schottky barrier thin film transistor, and the ITO target is deposited in the working gas atmosphere of 5×10-3 mbar of argon and the sputtering power is 100 W. Except that the short channel Schottky barrier thin film transistor 100 uses electron beam exposure to define the pattern, the pattern definition of the Schottky barrier thin film transistor 100 and the thin film transistor uses mask and photolithography technology.

[0221] Device performance test

[0222] Standard current-voltage tests for all devices were performed at room temperature using a Keysight E5270B semiconductor analyzer. Intrinsic gain was calculated using 30 averages of the output curves of the IGZO Schottky barrier thin film transistor in pulse mode with a period of 600ms using the Keysight E5270B. Low temperature tests of the IGZO Schottky diodes were performed using a Lakeshorecryogenic CRX-4K workstation. SEM images were taken using a Zeiss Sigma field emission scanning electron microscope. Bias tests were performed using an Advanced Research Systems DE-204 temperature control console.

[0223] method

[0224] Fig.12 A method of forming a Schottky source contact on an oxide semiconductor channel layer is illustrated according to an example.

[0225] At S801 , a source contact electrode is deposited on the oxide semiconductor channel layer in an oxygen-containing gas atmosphere.

[0226] The method includes all the steps described herein.

[0227] Fig.13 A method of forming a Schottky source contact on an oxide semiconductor channel layer is illustrated according to an example.

[0228] The oxide semiconductor channel layer is amorphous a(In2O3)b(Ga2O3)c(ZnO), where a=1, b=1, c=2, and the thickness H of the oxide semiconductor channel is in the range of 5nm to 50nm, preferably in the range of 10nm to 40nm, and more preferably in the range of 15nm to 30nm, for example 20nm or 25nm.

[0229] For example, Pt is used for the source contact.

[0230] At S901, before depositing the source contact, we anneal the oxide semiconductor. The annealing needs to be performed in an inert gas atmosphere at a temperature ranging from 200°C to 400°C, more preferably from 250°C to 350°C, for example, at 300°C for at least 30 minutes, preferably 60 minutes.

[0231] At S902, a source contact is deposited on the oxide semiconductor channel in an oxygen-containing gas atmosphere. The oxygen-containing gas may be an inert gas, preferably argon, containing an oxygen concentration between 0.1% and 10%, more preferably between 1% and 5%, for example, an oxygen partial pressure of 3%. The gas pressure needs to be in the pressure range of 1×10-3mbar to 1×10-1mbar, preferably in the pressure range of 1×10-4mbar to 1×10-2mbar, such as 5×10-3mbar. Depositing the source contact on the oxide semiconductor layer includes sputtering the source contact on the oxide semiconductor layer with a power range controlled in the range of 0.4W / cm2 to 3W / cm2, more preferably in the range of 0.6W / cm2 to 1.7W / cm2, for example, 0.88W / cm2 or 1.32W / cm2. These sputtering power densities correspond to sputtering powers of 20 W to 150 W, more preferably in the range of 30 W to 80 W, for example 40 W or 60 W, respectively, for a sputtering target of 3 inches in diameter.

[0232] The method comprises any of the steps described herein.

[0233] test

[0234] Room temperature testing was performed on a probe station. The diode 10 and the Schottky barrier thin film transistor 100 were tested using a probe. For the measurement of negative bias illumination temperature stress, the Schottky barrier thin film transistor was pasted on a chip carrier and connected with gold wire before being connected to a 4K cryostat temperature controller in Advanced Research Systems, Inc. The light source was a white LED lamp with an intensity of about 2000 lx, about 3 cm away from the Schottky barrier thin film transistor. The Agilent E5260B semiconductor analyzer was controlled by an internal Labview program to perform electrical performance tests.

[0235] XPS Test

[0236] XPS measurements were performed using an Axis Ultra Hybrid (Kratos, Manchester UK) at 10 mA emission current and 15 kV bias. A charge neutralizer was used to eliminate any excess charge effects. The original pressure of the device was 10-8 mbar. Test scans and high-resolution scans were performed at 80 eV and 20 eV energies, respectively. High-resolution scans were performed in two ranges of interest, around the O1s and Pt 4p3 / 2 peaks and the Pt 4f5 / 2 and f7 / 2 peaks, as well as the C 1s peak. The analysis was performed using Casa PS software. The binding energy was calibrated to the amorphous carbon peak at 284.8 eV. After calibration, the spectra were corrected using the background difference method. The spectra were fitted using the Gaussian-Lorentzian formula, except for the Pt 4f5 / 2 and f7 / 2 peaks, which used asymmetric LA functions.

[0237] XPS

[0238] When Pt is deposited in argon, no metal oxide components are detected on the O 1s peak. Pt sputtered in an argon atmosphere containing 3% oxygen forms a metal oxide signal peak at around 530eV. At 60W, the ratio of the O 1s and Pt 4p3 / 2 signal peaks is about 1:4. At 40W, this ratio increases to 4:5, indicating an increase in the degree of oxidation. When the sputtering gas atmosphere contains oxygen and the power is reduced from 60W to 40W, the Pt 4f5 / 2 and f7 / 2 signal peaks drift to the left. The leftward drift indicates an increase in the degree of oxidation, with PtO, PtO2 and Pt with higher oxygen content contributing more to the signal peak as the sputtering power decreases. The increase in the degree of oxidation at lower sputtering powers is mainly due to the introduction of more oxygen into the film due to longer deposition times.

[0239] Location of inhomogeneity

[0240] The contribution of the lower barrier region to the current depends largely on the closest distance P from the source edge to the drain. Fig.11A , 11B As shown in the output curves in 11C, the closer the non-uniformity is to the drain end of the source, the larger the ID. Fig. 11C In all cases, the current grows exponentially before saturation, except when the inhomogeneity is located at the edge of the source, i.e. P = 0 nm. At the edge, the inhomogeneity cannot be pinched off and no saddle point is formed in the conduction band. In this case, the effective barrier height is independent of the voltage and the current does not grow exponentially. The reason why the current depends so strongly on the position is the lateral resistance under the source. The further away from the source edge, the lower the potential of the interface. Therefore, the area farther away from the source edge is less reverse biased and produces less current. Since the inhomogeneity of the current dominates, the total current in the source is lower the farther away from the source edge.

[0241] For similar reasons, the output impedance also depends on the location of the inhomogeneity. When the device is saturated at the source, the potential of the semiconductor-dielectric interface below the source is fixed and independent of VD, except for the first 200nm or so of the source (e.g. Fig.11D Therefore, the non-uniformity within 200nm of the source edge is only affected by the non-uniformity of VD saturation, making it the limiting factor for output impedance and intrinsic gain.

[0242] Schottky Barrier Thin Film Transistor Theory

[0243] In addition to the simulation, an analytical theory can be derived to further understand the device behavior. In high-gain devices, the saddle point no longer has a significant effect, and Equation 1 gives the effective barrier height at the source interface:

[0244]

[0245] where Φ IFL and αqε M are the barrier lowering terms caused by the image force effect and the electric field effect. In the Schottky barrier thin film transistor, most of the current flows through the front end of the source. After detailed analysis, we found that the current I in the linear region lin It can be expressed by formula 2:

[0246]

[0247] Similarly, the current in the saturation region I sat It can be expressed by formula 3:

[0248]

[0249] Where W is the source contact width, q is the elementary charge, μ nis the electron mobility in the semiconductor, NC is the effective state density in the conduction band, VT is the threshold voltage of the Schottky barrier thin film transistor, k is the Boltzmann constant, T is the temperature, CS and CG are the unit area capacitances of the semiconductor and gate insulator, respectively. In the present experiment, μ n =10.6cm2 / Vs (obtained from IGZO TFT), W=2mm and the relative dielectric constants of SiO2 and IGZO are 3.9 and 10 respectively. Figure 4C The experimental transfer curve (circle) is in good agreement with the curve obtained according to Equation 3. By fitting, we can conclude that α = 0.73 nm, VT = 11.7 V, This is almost Fig. 9C The results of the barrier height obtained in the experiment are completely consistent. Using the same parameters, the output curves obtained are also very consistent with our theory ( Figure 4C ). The above results show that our analytical formula accurately describes the IV characteristics of Schottky barrier thin film transistors.

[0250] In more detail, this theory is only applicable to high-gain devices, that is, because the semiconductor is made thin enough or for other reasons, the effect of the saddle point can be ignored. Under reverse bias, the current flowing out of the source is diffusion controlled, as shown in Equation 4:

[0251]

[0252] Among them, J V (x) is the vertical current of the source at position x, q is the elementary charge, μ n is the electron mobility in the semiconductor, N C is the effective density of states in the conduction band, ε M (x) Electric field at the Schottky interface, φ B is the Schottky barrier height, V int (x) is the potential at the semiconductor-insulator interface at position x, k is the Boltzmann constant, and T is the temperature. Figure 4A As shown. At position x:

[0253]

[0254] in, is the average barrier height H is the thickness of the semiconductor layer. Therefore, the vertical current density of the source at position x can be given by Equation 5:

[0255]

[0256] when We assume that most of the current injection occurs at Therefore, the resistivity ρV at position x can be given by Equation 6:

[0257]

[0258] If we assume that V D <<(V G -V T ), where V G is the gate voltage of the Schottky barrier thin film transistor, V T is the threshold voltage of the Schottky barrier thin film transistor. Therefore, the resistance R along the semiconductor-insulator interface under the source L It can be expressed by formula 7:

[0259]

[0260] Among them, σ ch represents the conductivity of the channel, N ch represents the electron density in the channel, C G is the capacitance per unit area of ​​the gate dielectric, V T Represents the threshold voltage of a Schottky barrier thin-film transistor.

[0261] Therefore, the effective source length can be expressed by Equation 8:

[0262]

[0263] To calculate the threshold voltage of Schottky barrier thin film transistors, consider the average barrier height potential It is expressed by formula 9:

[0264]

[0265] Among them, C S is the capacitance per unit area of ​​the semiconductor layer, V T-TFT is the threshold voltage of the semiconductor channel. Therefore, the threshold voltage of the Schottky barrier thin film transistor can be expressed by equation 10:

[0266]

[0267] Before the device saturates, V D does not result in complete depletion of the semiconductor below the source edge ( Figure 4B ), the current can be estimated in two different cases. If the source length S>>L eff , then the current I in the linear region lin It can be expressed by formula 11 (same as formula 2):

[0268]

[0269] When Leff >>S, the linear region current can be expressed by equation 12:

[0270]

[0271] Similarly, in the saturation state, based on the series resistance model, the saturation drain voltage V Dsat It can be expressed by formula 13:

[0272]

[0273] If the source length S>>L eff , the saturation current can be expressed by equation 14:

[0274]

[0275] If the source length L eff >>S, the saturation current can be expressed by equation 15:

[0276]

[0277] If the image force decreases, the barrier height is as shown in Equation 16:

[0278]

[0279] Based on recent findings, the Pt-IGZO interface is not clear. In the transition region, the Pt clusters are surrounded by In, leading to the formation of interface states. This interface state can lead to a size of αqε M The barrier lowering term. Similar trends can also be attributed to the tunneling effect or the electric field penetrating the metal effect. Combining these effects, the effective barrier at the source can be expressed by Equation 17 (same as Equation 1):

[0280]

[0281] Through I lin and I sat In the equation of B，eff Replace Φ B , we get the IV characteristic fitting formula, such as Figure 4C and 4D shown.

[0282] Correction

[0283] While preferred embodiments have been shown and described, various changes and modifications may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims and as described above.

[0284] Summarize

[0285] The present invention provides a Schottky barrier thin film transistor, which includes a Schottky source contact on an oxide semiconductor channel. The Schottky source contact has the function of improving the intrinsic gain of the device, improving the resistance to the short channel effect and / or improving the resistance to negative bias illumination temperature stress. The present invention also provides a method for forming a Schottky source contact on an oxide semiconductor channel, which improves the intrinsic gain of the device, the resistance to the short channel effect and / or the resistance to negative bias illumination temperature stress.

[0286] Although the transistor was invented more than 70 years ago, it is still possible to develop new transistor designs, including adding a source contact electrode similar to a Schottky diode. By finding a way to control the shape and position of the diode barrier and theoretical analysis, the present invention achieves an extremely high voltage amplification gain of up to 29,000, which is several orders of magnitude higher than traditional silicon transistors. Negative bias illumination temperature stress is the main bottleneck encountered by oxide semiconductors in major applications such as display drivers, while the device proposed by the present invention is almost completely unaffected by negative bias illumination temperature stress. In addition, the device with a channel length of 360nm does not produce a significant short channel effect, solving another important problem in high-density integrated circuit and display applications.

[0287] By gaining an understanding of the device physics of Schottky barrier thin film transistors, and in particular a deeper understanding of barrier control, the inventors have achieved the highest intrinsic gain yet achieved in thin film transistors. Furthermore, such devices are not affected by the two most critical problems facing oxide transistors in industry, namely NBITS and short channel effects. Therefore, these devices have great potential for application in large area displays, logic gates and analog circuits.

[0288] Attention is paid to all papers and documents filed concurrently with or prior to this application, which are available to the public with this application, and the contents of all such papers and documents are incorporated herein by reference.

[0289] All features disclosed in this application (including any accompanying claims and drawings), and / or all steps of any method or process so disclosed, may be combined in any combination, except combinations where certain features and / or steps are mutually exclusive.

[0290] Unless expressly stated otherwise, each feature disclosed in this application (including any accompanying claims and drawings) may be replaced by features having the same, equivalent or similar purpose. Therefore, unless expressly stated otherwise, each feature disclosed is only an example of a series of equivalent or similar features.

[0291] The invention is not limited to the details of the above embodiments. The invention extends to any novel or combination of features disclosed in this application (including any accompanying claims and drawings), or steps of any new method or process so disclosed and their combination. Deposited onto an oxide semiconductor channel by sputtering in an atmosphere consisting of oxygen.

Claims

1. A Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel layer, characterized in that: The Schottky barrier transistor has an intrinsic gain of at least 1000; the effective barrier height of the Schottky source contact electrode does not change with the drain voltage VD of the Schottky barrier transistor; The thickness H of the oxide semiconductor channel is small enough so that the highest point of the lowest energy of the conduction band of the oxide semiconductor channel layer is located within 10 nm of the interface between the Schottky source contact electrode and the oxide semiconductor channel at zero bias; During the deposition of the source contact electrode, the sputtering power and oxygen injection are used to control the non-uniformity of the barrier. The sputtering power range for the deposition of the source contact is 0.4 W / cm 2 To 3 W / cm 2 , the oxygen content ranges from 0.1% to 10%.

2. The Schottky barrier transistor according to claim 1, characterized in that: A zinc oxide-based oxide semiconductor is included, and the zinc oxide-based oxide semiconductor is an amorphous zinc oxide-based oxide semiconductor.

3. The Schottky barrier transistor according to claim 1, characterized in that: The oxide semiconductor is amorphous a(In2O3).b(Ga2O3).c(ZnO), where a, b, c are real numbers and a≥0, b≥0, c>0.

4. The Schottky barrier transistor according to claim 1, characterized in that: The oxide semiconductor channel layer thickness H ranges from 5 nm to 50 nm.

5. The Schottky barrier transistor according to claim 1, wherein the Schottky source contact electrode is or comprises a material having a work function of at least 4.5 eV, wherein the material is a metal, an alloy, or a non-metal. 6 . The Schottky barrier transistor according to claim 1 , wherein the oxide semiconductor channel is annealed before depositing the Schottky source contact electrode.

7. A method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 1, the method comprising: A Schottky source contact electrode is deposited on the oxide semiconductor channel layer by sputtering in an atmosphere consisting of oxygen.

8. The method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 7, characterized in that The method comprises depositing a source contact electrode on an oxide semiconductor channel by sputtering, wherein the sputtering power is 0.4 W / cm 2 -3 W / cm 2 .

9. The method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 7, wherein the oxygen gas atmosphere is an inert gas having an oxygen component content between 0.1% and 10%.

10. The method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 9, comprising: -5 mbar to 1×10 -1 mbar. 11 . The method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 7 or 8 , comprising annealing the oxide semiconductor before depositing the source contact electrode. 12 . The method for preparing a Schottky barrier transistor having a Schottky source contact electrode formed on an oxide semiconductor channel according to claim 11 , comprising annealing in an inert atmosphere at a temperature between 200° C. and 400° C.

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