Integrated circuit with functional units and reconfigurable decoupling units

Abstract

A method for designing an integrated circuit to be constructed in a cell, wherein the cell is to comprise functional cells and spare cells, is disclosed. The method comprises a) designing at least one functional cell, and b) placing a plurality of functional cells on associated pattern positions of a pattern matrix, in particular a regular pattern matrix, designed for the functional cells. The method additionally comprises c) placing a gate-based decoupling cell on at least one of the remaining pattern positions of the pattern matrix and in place of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, and, alternatively or additionally, d) placing a gate-based decoupling cell in at least one gap between pattern positions of a pattern matrix and in place of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix.

Description

Technical Field

[0001] The present invention relates to a method for designing an integrated circuit, a method for manufacturing an integrated circuit, and an integrated circuit having spare cells and / or fill cells, wherein the spare cells and / or fill cells are configured as gate-based decoupling cells. Background Technology

[0002] Current integrated circuits can include various types of devices such as transistors, diodes, and capacitors, as well as various types of units such as functional standard units, fill units, spare units, and decoupling units.

[0003] In the context of this application, a "cell" refers to a circuit composed of multiple devices that can be reused (or instantiated) in an integrated circuit and then implemented multiple times on a wafer as needed to benefit from the fact that a large number of predefined cells with specific known properties are available and it is not necessary to create them from scratch for each use case. A very simple example of a cell would be an inverter, which consists of two transistors and has an input signal pin, an output signal pin, and a power supply pin. These cells are often combined into larger cell libraries that can be suited for many different kinds of purposes, such as, for example, inverters, buffers, AND gates, OR gates, NAND gates, XOR gates, flip-flops, multiplexers, etc.

[0004] Depending on the target use case, such libraries may also contain less common cells, such as those designed for high-voltage ICs. A common feature of cells in a library is that they are designed to allow for efficient area utilization, for example, by utilizing consecutive well and substrate structures in the IC's regional design, and to allow the cells to share common power rails, etc.

[0005] In the context of this application, "functional unit" refers to a full-function standard unit, which means a unit that contains means and is provided to meet the functional requirements of an IC, circuit, module or block (such as an inverter, NAND gate or flip-flop).

[0006] When functional units are placed in an integrated circuit design, this typically occurs within a pattern, that is, at patterned locations provided by a generally regular pattern matrix. Placing functional units at patterned locations within the pattern matrix is ​​done for efficiency reasons, such as to enable the sharing of well and substrate rows. However, after the cells are placed, gaps may exist between those placed cells. In such cases, fill cells are used to "fill" these gaps, also for efficiency reasons, such as to continue power rails, wells, and substrate rows.

[0007] In the context of this application, a "fill cell" refers to a cell placed in the gaps between patterned positions in a pattern matrix designed for a functional cell. As mentioned, fill cells are placed between patterned positions in a pattern matrix for efficiency reasons, such as to continue power rails, wells, and substrate rows. Otherwise, these structures would be disrupted and could cause functional problems or require larger cell spacing based on manufacturing rules. Fill cells may include floating structures that are not electrically connected to the power supply voltage provided by the power rails, for ease of manufacturing, such as in active semiconductor layers or polysilicon layers. Fill cells do not contain means that contribute to the construction of a particular cell function, but are added solely to fill gaps, as explained.

[0008] In the context of this application, a "spare cell" refers to a cell configured like a standard functional cell, however, which does not need to meet the functional requirements of the IC. Spare cells are added to the IC design to allow for "cheaper" changes to the IC after it has been manufactured. The reason for adding spare cells to the IC design is that errors may occur during testing or on the customer side that were not detected or accounted for in the simulations performed during the IC design. If the error problem can be solved by including the prepared spare cells, the number of masks to be updated is much smaller (typically only a few metal layers) compared to a full mask set. Furthermore, metal masks are generally much cheaper than deeper layers of the device such as polysilicon, n-wells, and active layers, and manufacturing is faster because wafers are typically stopped and removed from the manufacturing process before the metal layers are applied to prepare for these kinds of error corrections. In "extreme" cases, spare cells can be used to create additional functionality. The potential for gaining advantages using spare cells depends on the number and type of spare cells added. The concept of using spare cells is often a trade-off between providing preparedness for post-manufacturing repair issues and the disadvantages associated with spare cells, such as additional area consumption in IC design and current leakage during IC operation.

[0009] In the context of this application, a "decoupling cell" refers to a cell that is typically part of a cell library and is designed and optimized to provide maximum capacity so as to store the maximum amount of capacitance (or charge). Decoupling cells are provided in IC designs to reduce effects affecting signal integrity, such as dynamic voltage drops, by smoothing current spikes caused by switching between adjacent or neighboring functional cells or by smoothing supply voltage drops during switching between adjacent or neighboring functional cells. Thus, a decoupling cell has a power supply port but no signal port. Decoupling cells can be placed on regular patterned locations for functional cells in the pattern matrix of the IC. Alternatively, decoupling cells can be placed between patterned locations, or in other words, in the gaps between functional cells.

[0010] In today's semiconductor industry, especially in VLSI (Very Large Scale Integration) ICs, spare cells are added to IC designs to allow for post-manufacturing changes to the IC without regenerating the entire mask set, requiring only the mask for the metal layers. This may be necessary to correct errors or enable additional functionality. While these spare cells occupy space, they do not have any direct functional purpose unless they are required by such a metal ECO (Engineering Change Order).

[0011] Current existing integrated circuit technology utilizes two types of spare cell concepts. The first conventional spare cell concept consists of adding a fully functional standard cell to the IC design to allow for the use of these spare cells in the case of a metal ECO. This involves implementing new metal connections to and within the spare cell. The second conventional spare cell concept consists of placing a fill cell with unconnected (or floating) transistors across an IC region. In the case of a metal ECO, the unconnected transistors may need to be internally connected to achieve the required cell function, and new external metal connections are implemented to integrate the spare cell into the reconfigured design according to the metal ECO. In both conventional spare cell concepts, the spare cell has no functional purpose unless it is required by the metal ECO. Summary of the Invention

[0012] The overall objective of this invention is, on the one hand, to provide a more flexible concept for spare cells, and on the other hand, to functionally utilize the IC area occupied by spare cells, particularly even when metal ECO is not required. More specifically, the objective of this invention is to utilize spare cells to gain decoupling capacitance, which is expected to reduce signal integrity effects and limit dynamic voltage drop effects when adjacent functional units are switching, and is expected to increase the stored on-chip capacitance for contactless IC designs.

[0013] This objective is achieved by a subject matter having the features described in the independent patent claims. Specifically, this objective is achieved by a method for designing an integrated circuit according to appended independent claim 1, a method for manufacturing an integrated circuit according to appended independent claim 12, and an integrated circuit according to appended independent claim 14. Further examples of embodiments of the invention are described in the dependent claims.

[0014] According to a first exemplary embodiment of the present invention, a method for designing an integrated circuit is provided, wherein the integrated circuit is constructed in a cell, and wherein the cell includes functional cells and spare cells. The method includes:

[0015] a) Design at least one functional unit;

[0016] b) Placing multiple functional units on associated pattern positions within a particularly regular pattern matrix designed for the functional units; and

[0017] c) Placing a gate-based decoupling unit at at least one remaining pattern position in the remaining pattern positions of the pattern matrix and replacing at least one conceivable spare unit for the at least one remaining pattern position in the remaining pattern positions of the pattern matrix, and / or

[0018] d) Placing gate-based decoupling cells in at least one gap between pattern positions of the pattern matrix, and replacing at least one conceivable filling cell for the at least one gap between pattern positions of the pattern matrix.

[0019] Placing gate-based decoupling cells in the IC design according to steps c) and / or d) provides additional capacity and allows for the storage of more capacitance in the IC than with regular decoupling cells, which can be conceived in the IC design. Furthermore, the gate-based decoupling cells added in the IC design according to the invention can be designed such that they can be reconfigured during a metal ECO (engineering change order) and thus can be used as advantageously as spare cells.

[0020] In an example embodiment of the method, step c) includes placing a plurality of matching gate-based decoupling units at a plurality of remaining pattern positions of the pattern matrix and replacing a plurality of conceivable spare units for the plurality of remaining pattern positions of the pattern matrix.

[0021] In an example embodiment of the method, step d) includes placing a plurality of corresponding gate-based decoupling units in a plurality of gaps between pattern positions of the pattern matrix and replacing a plurality of conceivable filling units for the plurality of gaps between pattern positions of the pattern matrix.

[0022] In an embodiment of the method, the at least one gate-based decoupling unit includes at least one diffusion layer for forming source and / or drain regions of a transistor and a polysilicon layer partially disposed on the at least one diffusion layer. Herein, the polysilicon layer is conductively connected to a power supply line of the gate-based decoupling unit, and the at least one diffusion layer is conductively connected to an opposing power supply line of the gate-based decoupling unit, such that a capacitance is preferably created between the polysilicon layer connected to the power supply line and the diffusion layer connected to the opposing power supply line.

[0023] In the context of this application, "gate-based decoupling cell" refers to a cell that provides capacity, in particular in addition to the capacity provided by conventional decoupling cells, and allows for the storage of capacitance in the IC, in particular in addition to the capacitance stored by conventional decoupling cells. Furthermore, unlike conventional decoupling cells, the gate-based decoupling cell according to the invention is designed to be best suited for reconfiguration in a metal ECO.

[0024] In order to be suitable for reconfiguration in a metal ECO, the gate-based decoupling unit according to the present invention has the following common features and meets the following constraints and requirements for the size of its elements.

[0025] 1. To accommodate reconfiguration in a metal ECO and provide flexibility regarding the type of functional units that can be generated, the gate-based decoupling unit is designed such that as many transistors as possible can be created based on the polysilicon layer and the p-type and n-type diffusion layers. Specifically, the gate-based decoupling unit can be designed such that at least two transistors can be created along the length, as seen in the longitudinal direction of the diffusion layers and / or in a direction parallel to the power supply lines. This imposes a constraint on the number of polysilicon layers, which should be placed parallel to each other and extend over the diffusion layers in a direction transverse to the longitudinal direction of the diffusion layers.

[0026] 2. In addition, in order to be suitable for reconfiguration in a metal ECO and to be able to generate many different types of functional units, the gate-based decoupling unit is preferably designed to have two types of transistors, namely, p-type transistors and n-type transistors.

[0027] 3. In addition, in order to be suitable for reconfiguration in a metal ECO, the p-type diffusion layer and the n-type diffusion layer of the gate-based decoupling unit preferably extend continuously over the entire length of the diffusion layer in the longitudinal direction of the diffusion layer and / or in the direction parallel to the extension direction of the power supply line, i.e., without interruption or gap.

[0028] 4. The length / width of the polysilicon layer in the longitudinal direction corresponding to the gate of the transistor should be close to, i.e., slightly greater than or equal to, the minimum gate width that can be processed according to the manufacturing technology used for the integrated circuit, and should reach a maximum value of approximately twice the minimum processable gate width. - This constraint ensures that many transistors can be placed along the longitudinal direction while the gate width remains small enough to achieve a reasonably short switching time for the transistors.

[0029] 5. According to the manufacturing technology used for the integrated circuit, the length of the polysilicon layer in the longitudinal direction should be greater than the length (or width or diameter) of the metal contact via in the longitudinal direction. To meet this condition, it may be necessary to design the length of the polysilicon layer in the longitudinal direction to be slightly greater than the minimum processable gate width, so as to achieve the extended minimum gate width at least in the segment of the strip polysilicon layer. - This constraint ensures that the metal contact via can be placed in / on the polysilicon layer.

[0030] 6. When multiple polysilicon layers are placed parallel to each other and extend over the p-type diffusion layer in a transverse direction perpendicular to the longitudinal direction, as seen in the longitudinal direction, there should be remaining free lengths (i.e., not covered by the polysilicon layers) in the segments of the p-type diffusion layer, wherein each of the remaining free lengths is greater than the length (or width or diameter) of the metal contact via and / or greater than the length (or width) of the first metal layer (M1).

[0031] Similarly, when multiple polysilicon layers are placed parallel to each other and extend over the n-type diffusion layer in a transverse direction perpendicular to the longitudinal direction, as seen in the longitudinal direction, there should be remaining free lengths (i.e., not covered by the polysilicon layers) in the segments of the n-type diffusion layer, wherein each of the remaining free lengths is greater than the length (or width or diameter) of the metal contact via and / or greater than the length (or width) of the first metal layer (M1).

[0032] These two constraints ensure that metal contact vias and / or the first metal layer (M1) can be placed between the two strip polysilicon layers and / or on each side of each strip polysilicon layer.

[0033] In an example embodiment of the method of the first exemplary embodiment of the present invention, the method further includes:

[0034] Verify that all design and process requirements of the designed integrated circuit are met, including the requirements of the functional unit and the at least one gate-based decoupling unit.

[0035] In an example embodiment of the method, the method further includes:

[0036] e) Reconfigure at least one of the gate-based decoupling units during the metal engineering change command process.

[0037] In a specific embodiment of this example, step e) includes:

[0038] (ei) Determine a suitable new cell function for the at least one gate-based decoupling cell, and

[0039] e.ii) Reconfigure the contact layer and metal layer of the at least one gate-based decoupling unit to implement the determined new cell function of the reconfigured at least one gate-based decoupling unit.

[0040] In a specific embodiment of the two example embodiments mentioned above, the reconfiguration of the at least one gate-based decoupling unit includes:

[0041] - Removing the contact layer and / or the metal layer creates the decoupling function of the at least one gate-based decoupling unit, and

[0042] - Adding new contact layers and / or metal layers creates the desired suitable new cell functionality for at least one gate-based decoupling cell in the reconfiguration.

[0043] In an example embodiment of the method, the reconfiguration of the at least one gate-based decoupling unit is performed manually by an integrated circuit design engineer.

[0044] In an alternative embodiment of the method, reconfiguring the at least one gate-based decoupling unit includes selecting from a library the design of a suitable new unit function for the reconfigured at least one gate-based decoupling unit.

[0045] In specific embodiments of the five example embodiments mentioned above, the method further comprises:

[0046] Verify that all design and process requirements of the integrated circuit that has been reconfigured during the metal engineering change order are met, including the requirements of the functional units and the at least one reconfigured gate-based decoupling unit.

[0047] According to a second exemplary embodiment of the present invention, a method for manufacturing an integrated circuit is provided, wherein the integrated circuit is constructed in a cell, and wherein the cell includes functional cells and spare cells and / or fill cells. The method includes:

[0048] A) Manufacturing the functional units at corresponding associated pattern positions in a particularly regular pattern matrix designed for multiple functional units; and

[0049] B) Fabricate at least one gate-based decoupling unit at at least one of the remaining positions of the pattern matrix and in place of any alternative unit conceivable for the at least one of the remaining positions of the pattern matrix.

[0050] and / or

[0051] C) At least one gate-based decoupling unit is manufactured in at least one gap between the pattern positions of the pattern matrix and in place of conceivable filling units for the at least one gap between the pattern positions of the pattern matrix.

[0052] Fabricating gate-based decoupling cells in the IC according to steps B) and / or C) provides the same advantages as described above as placing gate-based decoupling cells in the IC design according to steps c) and / or d) of the method for designing integrated circuits described above.

[0053] In an example embodiment of the method, step B) includes placing a plurality of matching gate-based decoupling units at a plurality of remaining pattern positions of the pattern matrix and replacing a plurality of conceivable spare units for the plurality of remaining pattern positions of the pattern matrix.

[0054] In an example embodiment of the method, step C) includes placing a plurality of corresponding gate-based decoupling units in a plurality of gaps between pattern positions of the pattern matrix and replacing a plurality of conceivable fill units for the plurality of gaps between pattern positions of the pattern matrix.

[0055] In an embodiment of the method, the at least one gate-based decoupling unit includes at least one diffusion layer for forming source and / or drain regions of a transistor and a polysilicon layer partially disposed on the at least one diffusion layer. Herein, the polysilicon layer is conductively connected to a power supply line of the gate-based decoupling unit, and the at least one diffusion layer is conductively connected to an opposing power supply line of the gate-based decoupling unit, such that a capacitance is preferably created between the polysilicon layer connected to the power supply line and the diffusion layer connected to the opposing power supply line.

[0056] In an example embodiment of the method, the at least one gate-based decoupling unit is configured such that it can be reconfigured during a metal engineering change command to achieve the appropriate new unit function.

[0057] In a specific embodiment of this example, reconfiguration during the metal engineering change command process includes:

[0058] i) Determine a suitable new cell function for the at least one gate-based decoupling cell, and

[0059] ii) Reconfigure the contact layer and metal layer of the at least one gate-based decoupling unit to implement the determined new cell function of the reconfigured at least one gate-based decoupling unit.

[0060] In a specific embodiment of the two example embodiments mentioned above, the reconfiguration of the at least one gate-based decoupling unit includes:

[0061] - Removing the contact layer and / or the metal layer creates the decoupling function of the at least one gate-based decoupling unit, and

[0062] - Adding new contact layers and / or metal layers creates the desired suitable new cell functionality for at least one gate-based decoupling cell in the reconfiguration.

[0063] In an example embodiment of the method, the reconfiguration of the at least one gate-based decoupling unit is performed manually by an integrated circuit design engineer.

[0064] In an alternative embodiment of the method, reconfiguring the at least one gate-based decoupling unit includes selecting from a library the design of a suitable new unit function for the reconfigured at least one gate-based decoupling unit.

[0065] According to a third exemplary embodiment of the present invention, an integrated circuit is provided, wherein the integrated circuit is constructed in a cell, and wherein the cell includes functional cells and spare cells and / or fill cells. The integrated circuit includes:

[0066] A) A plurality of functional units, said functional units being arranged at corresponding associated pattern positions in a particularly regular pattern matrix designed for said functional units; and

[0067] B) At least one gate-based decoupling unit, the at least one gate-based decoupling unit being disposed at at least one remaining position in the remaining positions of the pattern matrix and replacing any conceivable alternative unit for the at least one remaining position in the remaining positions of the pattern matrix.

[0068] and / or

[0069] C) At least one gate-based decoupling unit disposed in at least one gap between pattern positions of the pattern matrix and replacing conceivable filling units for the at least one gap between pattern positions of the pattern matrix.

[0070] Setting up gate-based decoupling units in an IC provides the same advantages as step c) and / or step d) of the method for designing integrated circuits described above, which places gate-based decoupling units in the IC design.

[0071] In an example embodiment of the integrated circuit, the integrated circuit includes a plurality of gate-based decoupling units corresponding to a plurality of remaining pattern locations of the pattern matrix and replacing a plurality of spare units conceivable for the plurality of remaining pattern locations of the pattern matrix.

[0072] In an example embodiment of the integrated circuit, the integrated circuit includes a plurality of gate-based decoupling units that correspond to a plurality of gaps between pattern positions of the pattern matrix and, in place of a plurality of conceivable filling units for the plurality of gaps between pattern positions of the pattern matrix.

[0073] In an example embodiment of the integrated circuit, the at least one gate-based decoupling unit includes at least one diffused layer for forming source and / or drain regions of a transistor and a polysilicon layer partially disposed on the at least one diffused layer. Herein, the polysilicon layer is conductively connected to a power supply line of the gate-based decoupling unit, and the at least one diffused layer is conductively connected to an opposing power supply line of the gate-based decoupling unit, such that a capacitance is preferably created between the polysilicon layer connected to the power supply line and the diffused layer connected to the opposing power supply line.

[0074] In this embodiment example of the integrated circuit, the at least one gate-based decoupling unit, and preferably all gate-based decoupling units, are configured such that they can be reconfigured during metalworking change orders to achieve the appropriate new unit functionality. Attached Figure Description

[0075] In the following description, exemplary embodiments of the present invention are illustrated in detail with reference to the accompanying drawings.

[0076] Figure 1 A top view of a filled cell having four transistors and a floating structure according to a first embodiment of the invention not implementing the present invention is shown.

[0077] Figure 2 A top view of a filled cell having eight transistors and a floating structure according to a second embodiment of the invention not implementing the present invention is shown.

[0078] Figure 3 A cross-sectional view of a transistor according to an embodiment not implementing the present invention is shown, the transistor being capable of... Figure 1 , 2 Implemented in the units shown in 4 to 10.

[0079] Figure 4 This illustrates a NAND gate reconfigured according to an embodiment that does not implement the invention. Figure 1 A top view of the reconfigured filled cells.

[0080] Figure 5 A top view of a gate-based decoupling unit according to a first exemplary embodiment of the present invention is shown, with indications of structural dimensions.

[0081] Figure 6 A top view of a gate-based decoupling unit according to a second exemplary embodiment of the present invention is shown.

[0082] Figure 7 A top view of a gate-based decoupling unit according to a third exemplary embodiment of the present invention is shown.

[0083] Figure 8 A top view of a gate-based decoupling unit according to a fourth exemplary embodiment of the present invention is shown.

[0084] Figure 9 A top view of a gate-based decoupling unit according to a fifth exemplary embodiment of the present invention is shown, with indications of structural dimensions.

[0085] Figure 10 This illustrates how the system can be reconfigured according to an exemplary embodiment of the invention. Figure 6 A top view of an example of a gate-based decoupling cell.

[0086] Figure 11 An exemplary embodiment of the invention is shown in Figure 10 After the reconfiguration implementation shown Figure 6 and 10 A top view of the reconfigured gate-based decoupling cell.

[0087] Figure 12 A flowchart illustrating a method for designing an integrated circuit according to an exemplary embodiment of the present invention is shown.

[0088] Similar or identical parts in different figures are given the same reference numerals. For reasons of simplicity, if a feature that has been described with respect to a particular figure appears in the same or similar form in another figure, that feature may not be described again. Detailed Implementation

[0089] Before describing exemplary embodiments of the invention with reference to the accompanying drawings, some general aspects of the invention as presented by the inventors should still be explained.

[0090] According to the present invention, a novel spare cell method is provided that is more flexible than the conventional known spare cell methods described at the outset. According to the present invention, gate-based decoupling cells are added instead of conventional spare cells at regular patterned locations in the patterned matrix of the IC to be designed, or instead of conventional fill cells in the gaps between regular patterned locations in the patterned matrix of the IC. These gate-based decoupling cells are configured such that they can be reconfigured when metal ECO is required.

[0091] While the insertion of conventional decoupling cells is a common procedure, conventional decoupling cells cannot be used and reconfigured in the same way as the gate-based decoupling cell according to the present invention. This is because the layout of conventional decoupling cells is optimized to provide as much capacity as possible, particularly to store as much capacitance or charge as possible, for example, by using a polycrystalline silicon "plate" instead of, for example Figure 5 , 6 This is achieved using the strip-shaped polysilicon structure 220 shown in Figure 7. Such polysilicon plates are not suitable for forming reasonable transistor gates because such gates would be too large and result in excessively slow transistor switching times.

[0092] The gate-based decoupling unit according to the invention is configured such that, on the one hand, the gate-based decoupling unit provides some capacity, or in other words, some capacitance or capability, to store some charge and thus has a functional purpose, even if the metal ECO is no longer needed. On the other hand, the gate-based decoupling unit according to the invention is configured such that the gate-based decoupling unit can be reconfigured as a functional unit when the metal ECO is needed.

[0093] Compared to known methods using ECO-filled cells, the advantage of providing a gate-based decoupling cell according to the invention is that it provides a decoupling capacitor. Compared to adding unused, fully functional cells as spare cells, the advantage of providing a gate-based decoupling cell is that the cell function of the gate-based decoupling cell is not predefined and can be selected based on metal ECO requirements, as well as, of course, additional capacity and storage capacitance.

[0094] It is envisioned that a metal ECO is the sole reason for reconfiguring the gate-based decoupling cell according to the invention. ICs are prepared for metal ECOs because metal masks are less expensive and faster to manufacture. This is because metal masks are typically a later processing step, and the wafer can remain unchanged before the metal layer.

[0095] In situations where a full-mask ECO would be necessary, such as to correct errors in an IC design, it's not necessary to limit changes to only the metal layers. A full-mask ECO offers considerable freedom for all kinds of updates—in which case spare cells would not be needed. However, from a cost perspective, unplanned full-mask ECOs would be too expensive and therefore not desirable, as masks used for deeper layers such as polysilicon layers or diffusion layers are much more expensive, and the fabricated wafers cannot be reused.

[0096] In contrast, in a metal ECO, all design updates are implemented as changes to only the metal mask. Metal masks are much cheaper than masks used to form transistors, and the common practice is to stop several wafers before processing the metal layers. In this way, the runtime during manufacturing is very short for metal updates.

[0097] If the gate-based decoupling cell is to be reconfigured during the metal ECO process, the technical steps involved in reconfiguration include generally calculating a suitable new cell function for the metal ECO and then updating the contact and metal layers of the gate-based decoupling cell to implement the necessary new function. Although this is possible, it is preferred not to do this manually, but rather to replace the gate-based decoupling cell with a cell taken from a prepared library.

[0098] During testing or on the customer side, errors may pop up that were not detected or anticipated during simulations performed during IC design. Once the problem is identified, for example, during IC testing, it is investigated and a solution is found. In a very simple example, an inverter would be needed to use an inverted version of the signal instead of the original. Therefore, a reconfigurable gate-based decoupling cell in an appropriate location would be selected to be converted into an inverter. This conversion can be implemented manually by removing the contacts that create the decoupling function and adding the contacts and metal required for the inverter. A better approach is to have a library of cells available that can replace the decoupling cells in the design. These cells need to be designed so that the only difference from the gate-based decoupling cell is the layer above the polysilicon layer.

[0099] Figure 1 A top view of cell 110 is shown. Cell 110 is embedded in integrated circuit 100 and is a simplified example of conventional fill cell 140, which has four unconnected transistors, i.e., a floating structure.

[0100] Figure 1 The illustrative conventional filling unit 140 shown includes a p-type diffusion region 230 and an n-type diffusion region 214, wherein the p-type diffusion region 230 can be embedded in, for example... Figure 1The n-type diffusion region 214 can be embedded in the n-well trench (not shown) in the upper portion of the unit 110 shown. Figure 1 The lower part of the unit 110 shown is as follows and as Figure 2 The cross-sectional view shows the p-well trench 204. The p-type diffusion region 230 and the n-type diffusion region 214 can be surrounded by an oxide layer 218, as shown. Figure 1 As shown and as for Figure 2 The cross-sectional view shows the n-type diffusion region 214. Figure 1 The filling unit 140 further includes two polysilicon layers 220, each of which is in Figure 1 In the top view, it is strip-shaped and spans the p-type diffusion region 230 and the n-type diffusion region 214, extending above the p-type diffusion region 230 and the n-type diffusion region 214, similarly as for... Figure 2 The n-type diffusion region 214 is shown in the cross-sectional view.

[0101] Figure 1 The conventional filler unit 140 further includes a power supply line 224, which may represent the power supply line (PWR) of unit 110, and a corresponding power supply line 226, which may represent the voltage ground line (GND) of unit 110. Both power supply lines 224 and 226 may be represented only as the first or lowest layer metal (or M1 layer) 228, where "lowest" and "M1" refer to... Figure 2 The cross-sectional view of transistor 200 shows the lowest metal layer present in the layer-by-layer construction of the transistor. In other embodiments, power supply lines 224, 226 may be embodied on top of each other in the lowest (M1) and next lowest (M2) metal layers, or even on top of each other in additional metal layers (M3, M4, ...), as may be necessary to reduce the ohmic resistance of power supply lines 224, 226 to a desired level.

[0102] Included Figure 1 The four transistors in the simplified conventional filling cell 140 shown are formed by overlapping a strip polysilicon layer 220 with diffusion layers 214 and 230. Two p-type transistors are formed by overlapping the strip polysilicon layer 220 with the p-type diffusion layer 230, and two n-type transistors are formed by overlapping the strip polysilicon layer 220 with the n-type diffusion layer 214.

[0103] As from Figure 1As can be seen, the p-type diffusion layer 230, the n-type diffusion layer 214, and the polysilicon layer 220 are not connected to the power supply lines 224 and 226. Therefore, the conventional fill cell 140 includes four unconnected transistors and is prepared as needed for reconfiguration of the fill cell 140 during the metal ECO process, such as... Figure 4 As shown. It should be noted that a wider range of cells, capable of providing more or fewer floating transistors, can be used before and after the potentially necessary reconfiguration in the metal ECO, as well as when projected onto... Figure 1 Different relative geometric dimensions on a plane (e.g.) Figure 1 The lengths and widths of the structures 214, 230, 218, 220, 224, and 226 shown in the diagram enable the creation of more complex cells.

[0104] For example, for cells with more transistors and greater complexity, Figure 2 A top view of a filled cell 140 with eight unconnected (floating) transistors is shown. Figure 2 In this process, four p-type transistors are formed by overlapping a strip polysilicon layer 220 with a p-type diffusion layer 230, and four n-type transistors are formed by overlapping a strip polysilicon layer 220 with an n-type diffusion layer 214.

[0105] It should be noted that, Figure 1 and 2 In and similarly in Figures 4 to 11 In this context, the first metal layer (M1) 228, polysilicon layer 220, p-type diffusion layer 230, n-type diffusion layer 214, and metal contact via 222 do not represent elements of the integrated circuit unit 110, but can be alternatively considered as representing layout layers and / or mask layers generated by the design of the execution unit 110 and used to manufacture the integrated circuit 100. Additionally, it should be noted that in Figure 1 , 2 and Figures 4 to 11 Not all layout layers and all mask-related layers are shown; only those mask layers deemed necessary for describing and understanding the invention are shown.

[0106] Figure 3 A cross-sectional view of transistor 200 is shown, which can be... Figure 1 and 2 In the filling unit 140 shown and in Figure 4 (showing from) Figure 1 The reconfigured gate-based coupling cell 170' obtained by filling cell 140 in the middle). Figures 5 to 8 (Gate-based coupling units 160, 160' are shown) and Figure 10 and 11 (showing the Figure 10 The gate-based coupling units 160, 160' in the middle are reconfigured as Figure 11 It is implemented in cell 110, which is a reconfigured gate-based coupling cell (170, 170').

[0107] Figure 3 The transistor 200 is an example of a conventional n-type transistor, which is fabricated on a wafer and includes a wafer 202; a p-well 204 formed in the wafer 202, the p-well 204 being doped to include positively charged mobile charge carriers, i.e., holes, as the majority charge carriers; and a shallow trench isolation (STI) 206 formed to surround and horizontally isolate the p-well 204. In the p-well 204, a source region 208, a drain region 210, and a bridging region 212 located between the drain region 210 and the source region 208 are envisioned, wherein it should be noted that the specific source and drain regions are formed only during operation of the transistor 200 according to the applied potential and, i.e., its polarity. Furthermore, in the p-well 204, two n-type diffusion regions (or n-type diffusion regions) have been formed by patterned ionization. + Region 214. Transistor 200 further includes a polysilicon layer 220 that forms the gate of transistor 200 and is arranged to partially cover each of the n-type diffusion regions 214 and bridge from one n-type diffusion region 214 to another. Oxide layer 218 covers shallow trench isolation 206, n-type diffusion regions 214 and polysilicon layer 220 and surrounds and isolates metal contact via 222.

[0108] For contact to be established, transistor 200 further includes two metal contact vias 222, one of which is a contact via (e.g., Figure 3 The contact via shown on the left) and an n-type diffusion region (e.g., one of the n-type diffusion regions 214) in the n-type diffusion region 214. Figure 3 The n-type diffusion region shown on the left is associated with and contacts another contact via in contact via 222 (e.g., Figure 3 The contact via shown on the right) and another n-type diffusion region in n-type diffusion region 214 (e.g., Figure 3 The right-hand n-type diffusion region shown is associated with and in contact with the transistor. Furthermore, the transistor 200 includes two first metal layers (M1) 228, each of which is disposed above the oxide layer 218 for contacting an associated metal contact via in the metal contact via 222.

[0109] In the operation of the n-type transistor 200, if a potential or voltage positive relative to the potential applied to the intended source region 208 is applied to the polysilicon layer 220 or the gate, the associated electric field draws electrons from the p-well 204 layer into the region between the n-type diffusion regions 214, thereby forming the channel region 216 of the transistor 200. Through the channel region 216, a current formed by electrons can flow from one n-type diffusion region 214 (source region 208) to another n-type diffusion region (drain region 210), and thus from one first metal layer (M1) 228 to another first metal layer (M1). This current can be switched and adjusted by switching and adjusting the potential applied to the polysilicon layer 220 forming the gate of the n-type transistor.

[0110] It should also be noted that conventional p-type transistors are necessarily present in the gate-based decoupling units 160, 160' according to the present invention, such as, for example Figures 5 to 9 As indicated, as will be described later. Although p-type transistors are not shown in the accompanying drawings, they can be based on... Figure 3 The n-type transistor shown is described below. In the p-type transistor, the wafer 202, shallow trench isolation 206, oxide layer 218, polysilicon layer 220 (or gate), metal contact via 222, and first metal layer (M1) 228 are substantially similar to the corresponding elements 202, 206, 218, 220, 222, and 228, which are present in the n-type transistor 200 and... Figure 3 As shown in the diagram. The differences between p-type transistors and n-type transistors are as follows:

[0111] 1) Replacing the p-well 204, which is doped with positively charged mobile charge carriers, i.e., holes, as the majority charge carriers, as present in the n-type transistor 200, the p-type transistor ( Figure 3 (Not shown in the image) includes n-wells doped to include negatively charged mobile charge carriers, i.e., electrons, as the majority charge carriers. Figure 3 (Not shown in the image).

[0112] 2) Replacing the two n-type diffusion regions (or n-type diffusion regions) formed in the p-well 204 by patterned ionization, as present in n-type transistor 200. + (District) 214, p-type transistor ( Figure 3 (Not shown) includes two p-type diffusion regions (or p-type diffusion regions) formed in p-well 204 by patterned ionization. + District) 230 ( Figure 3 (Not shown in the image).

[0113] 3) In the operation of a p-type transistor, if a potential or voltage negative relative to the potential applied to the intended source region is applied to the polysilicon layer or the gate, the associated electric field draws holes from the n-well layer into the region between the p-type diffusion regions, thereby forming the channel region of the p-type transistor 200. Through this channel region, current formed by holes can flow from one p-type diffusion region 230 (which thus becomes the source region) to another p-type diffusion region 230 (which thus becomes the drain region), and thus from one first metal layer (M1) to another first metal layer (M1). This current can be switched and adjusted by switching and adjusting the potential applied to the polysilicon layer forming the gate of the p-type transistor.

[0114] To provide a more complete description of transistors, different transistor types, the structural configurations of transistors of different types, and their operation, for example, reference is made to the standard textbook "Semiconductor Circuit Technology (Halbleiter-Schaltungstechnik)" (English translation: "Semiconductor Technology") written in German by Ulrich Tietze and Christoph Schenk, Springer, 13th revised edition, 2010 (October 15, 2009), ISBN-13: 978-3642016219, which is incorporated herein by reference in its entirety.

[0115] Now for reference Figure 4 If for a regular fill cell, such as Figure 1 The illustrative conventional fill cell 140 shown, if a design update or correction of a design error needs to be implemented via a metal ECO, can have its floating transistors connected using a contact layer. Specifically, metal contact vias 222, cell pins, and internal cell connections can be established using a first metal layer (M1) 228 (sometimes also called metal wires). The location of the contacts 222 and cell pins, as well as the internal cell connections via the metal layer (M1) 228, then defines, for example, the type of functional unit generated from fill cell 140.

[0116] For example, Figure 4 It shows Figure 1 A top view of filler unit 140, which has been reconfigured as a NAND gate with two inputs, as an example of reconfigured filler unit 150.

[0117] Contacts (or metal contact vias) 222 are applied to connect to the gate and source connections of the transistors formed in the two diffusion regions 214, 230 and to the gate connection of the transistors (polysilicon layer 220), while a first metal layer (M1) 228 is used to create cell pins and internal cell connections. By updating the metal connections to other external cells of the IC, the reconfigured fill cells can be integrated into the IC design as newly created cells as needed. It should be noted that while the first metal layer 228 is preferably used to create connections, higher metal layers (M2, M3, ...) can also be used to establish the necessary internal cell connections, and adjacent fill cells can be combined to create more complex cells that require a higher number of transistors.

[0118] and Figure 1 , 2 Compared to the illustrative conventional reconfigurable fill cell 140 with floating transistors shown in Figure 4, the following Figures 5 to 11 An illustrative embodiment of the gate-based decoupling units 160, 160' according to the present invention is shown.

[0119] Figure 5 A top view of gate-based decoupling units 160, 160' according to a first exemplary embodiment of the present invention is shown, with indications of structural dimensions.

[0120] Figure 5 The gate-based decoupling units 160, 160' include a first polysilicon layer 220 (e.g., Figure 5 The leftmost polysilicon layer) and the second polysilicon layer 220 (e.g., Figure 5 The polysilicon layer 220 on the right side of the middle section), the first polysilicon layer 220 through the first metal contact via 222 (e.g., Figure 5 The upper-middle metal contact via is connected to the first M1 layer metal 228, and the first M1 layer metal 228 is connected to a power supply line 224 (e.g., Figure 5 The power supply line in the upper middle part), the second polysilicon layer 220 through the second metal contact via 222 (e.g., Figure 5 The lower middle metal contact via is connected to the second M1 layer metal 228, and the second M1 layer metal 228 is connected to the opposite power supply line 226 (e.g., Figure 5 (The power supply line in the lower middle section). Thus... Figure 5 The gate-based decoupling units 160 and 160' include one p-type transistor and one n-type transistor of each type.

[0121] Figure 5 The capacitance / capacitance of the gate-based decoupling units 160 and 160', and similarly Figures 6 to 8The capacitance / capacitance of cells 160, 160' is respectively established between the transistor gate formed by a polysilicon layer 220 connected to a power supply line 224 and diffusion layers 214, 230 connected to opposing power supply lines 226. The power supply line 224 can be connected to, for example, a power source or ground, and the power supply line 226 can be connected to, for example, ground or a power source. The connection to the diffusion layers 214, 230 can be implemented inside or outside the gate-based decoupling cells 160, 160' and is therefore not... Figure 5 It is shown in (and similarly not in) Figures 6 to 11 (as shown in the image), thus recalling what has already been said above, in Figure 1 , 2 Not all layout layers and all mask-related layers are shown in 4 to 11.

[0122] It should be noted that Figure 5 The layout of the gate-based decoupling units 160, 160' shown may include more than Figure 5 The number of transistors can be increased or decreased. Furthermore, the transistor size can be varied, which may include changing the dimensions of the p-type diffusion layer 230, the n-type diffusion layer 214, the polysilicon layer 220, the metal contact via 222, and the first metal layer (M1) 228. Decoupling capacity can also be created using only p-type transistors or only n-type transistors when one or more complementary types of transistors are present.

[0123] The layout / design of the gate-based decoupling units 160, 160' and the selection of the decoupling unit concept will depend on a combination of design constraints and requirements that can determine the distance between the layer structures relative to each other, layer length (or width), density, gradient, overlap, etc., as well as the DRC (Design Rule Check) rules to be applied, and includes verifying that all manufacturing rules provided by the manufacturer (or manufacturing system) are met. The common characteristics of the gate-based decoupling units 160, 160' according to the invention, as well as the constraints and requirements for the dimensions of the elements (i.e., p-type diffusion layer 230, n-type diffusion layer 214, polysilicon layer 220, metal contact via 222, and first metal layer (M1) 228) of the gate-based decoupling units 160, 160' according to the invention, and how these differ from conventional decoupling units, will be discussed below. Figure 9 See the description below. Figure 5 and Figure 9 Further discussion.

[0124] if Figure 5 The gate-based decoupling units 160, 160' shown satisfy the common characteristics of the gate-based decoupling units 160, 160' according to the present invention, as well as the constraints and requirements for the size of their components. Therefore, the gate-based decoupling units 160, 160' can be reconfigured for metal ECO when needed.

[0125] Figure 6 A top view of gate-based decoupling units 160, 160' according to a second exemplary embodiment of the present invention is shown.

[0126] Regarding the width and shape of the polysilicon layer 220, and therefore the extent of its overlap with the diffusion layers 214 and 230, Figure 6 The gate-based decoupling units 160, 160' shown are... Figure 5 The gate-based decoupling units 160 and 160' shown are fundamentally different.

[0127] As in Figure 5 As shown in the gate-based decoupling units 160 and 160', similarly in... Figure 6 In the gate-based decoupling units 160, 160' shown, the capacitance is established between the transistor gate formed by a polysilicon layer 220 connected to a power supply line 224 and a diffusion layer 214, 230 connected to an opposing power supply 226. The power supply line 224 can be connected to, for example, a power source or ground, and the power supply 226 can be connected to, for example, ground or a power source.

[0128] For example Figure 7 As shown, Figure 6 Further layout variations of the gate-based decoupling units 160, 160' shown are possible.

[0129] Figure 7 A top view of gate-based decoupling units 160, 160' according to a third exemplary embodiment of the present invention is shown.

[0130] Figure 7 The gate-based decoupling units 160, 160' shown are... Figure 6 The gate-based decoupling units 160 and 160' shown differ in that only p-type transistors are used (and therefore only p-type diffusion layers 230 are used), and also differ in the connection of one polysilicon layer 220 and the other polysilicon layer 220 to the power supply line; that is, the difference lies in the fact that... Figure 7 In this configuration, both polysilicon layers 220 are connected to the same power supply line 226. This is to ensure that the polysilicon layers are connected to a single power supply line (e.g., ...). Figure 7 The polysilicon layer 220 of the lower power supply line 226 and the power supply line connected to the opposite power supply line (i.e., Figure 7 A capacitance / capacitance is established between the transistor gate formed by the diffusion layer 230 of the upper power supply line 224, and the diffusion layer 230 is connected to the power supply line 224. Figure 7 (Not shown in the image).

[0131] Figure 8A top view of gate-based decoupling units 160, 160' according to a fourth exemplary embodiment of the present invention is shown.

[0132] Figure 8 The gate-based decoupling units 160 and 160' shown have been used as Figure 6 The gate-based decoupling units 160, 160' shown are obtained and differ from them in that an additional first metal layer (M1) 228 is implemented to establish additional capacitance. On one hand, the first metal layer (M1) 228 is applied over the polysilicon layer 220 to almost completely cover the polysilicon layer 220, and on the other hand, an additional first metal layer (M1) 228 is applied in parallel to the first metal layer (M1) 228 applied over the polysilicon layer 220.

[0133] Apart from Figures 5 to 8 In addition to those shown, different constellation embodiments of the gate-based decoupling units 160, 160' can be derived from the exemplary embodiments described above and will be obvious to those skilled in the art and will not be explained in more detail herein. These constellation embodiments may involve different numbers and types of transistors, transistor sizes / widths (e.g., as defined by the size, shape, and width of the polysilicon layer 220 covering the diffusion layers 21, 230), and the use of additional metal layers (M1) 228 or other layers.

[0134] Figure 9 A top view of gate-based decoupling units 160, 160' according to a fifth exemplary embodiment of the present invention is shown, with indications of structural dimensions.

[0135] Figure 9 The gate-based decoupling units 160 and 160' shown are similar to Figure 6 The gate-based decoupling units 160 and 160' shown differ in that the minimum width of the two strip polysilicon layers 220 is selected to be the minimum width L220min allowed by the constraints and requirements of the specific semiconductor manufacturing technology used to manufacture the integrated circuit 100. Therefore, the minimum width L220min of the strip polysilicon layer 220 is smaller than the size (width / diameter) L222 of the metal contact via 222.

[0136] Figure 9 The document also indicates a reconfiguration of the proposed metal ECO, for which the pin contacts to be removed and / or the first layer of metal are indicated (enclosed) by ellipse 236, and the pin contacts to be added and / or the first layer of metal are indicated (enclosed) by ellipse 238. Figure 9The instructions state that if a metal contact via 222 should be added in the reconfiguration to be located on the strip polysilicon layer 220, then a minimum width L220min suitable for the manufacturing technology is required. Figure 9 The right-hand strip of polysilicon layer 220 is too narrow to accommodate a metal contact via 222 with a width L222, which can be determined by manufacturing constraints and requirements. In contrast, Figure 9 The strip-shaped polysilicon layer 220 on the left-hand side is designed such that, as seen in the longitudinal direction of the strip, the central portion of the strip has an extended width L222ext compared to the minimum width L222min existing outside the central portion, wherein the extended width L222ext is greater than the width L222 of the metal contact via 222, so that the metal contact via 222 can actually accommodate... Figure 9 In the central portion of the strip-shaped polycrystalline silicon layer 220 shown on the left-hand side. Figure 9 The specific design of the strip polycrystalline silicon layer 220 shown on the left-hand side is just one example of the constraints arising from the limitations and requirements of manufacturing technology.

[0137] In the following text, see references Figure 5 and Figure 9 This document will describe at least some common characteristics of the gate-based decoupling units 160, 160' according to the invention, as well as at least some constraints and requirements for the dimensions of the elements (i.e., p-type diffusion layer 230, n-type diffusion layer 214, polysilicon layer 220, metal contact via 222, and first metal layer (M1) 228) of the gate-based decoupling units 160, 160' according to the invention, which may arise from manufacturing technology and / or from associated DRC rules, and will show how the gate-based decoupling units 160, 160' according to the invention differ from conventional decoupling units.

[0138] Conventional decoupling cells are typically designed to be optimized for their capacitance or the capacitance they can provide. Similarly, in conventional decoupling cells, such as gate-based decoupling cells 160, 160', capacitance / capacitance is established between the transistor gate formed by a polysilicon layer connected to one power supply line and a diffused layer connected to the opposite power supply line.

[0139] To optimize this capacity, the overlap of the polysilicon layer above the diffusion layer can be optimized. Such optimization would result in the polysilicon layer being designed to cover the diffusion layer as much as possible (according to the rules and constraints of the manufacturing technology). For example, instead of appearing... Figures 5 to 9In the gate-based decoupling units 160, 160' shown, the width of the strip-shaped polysilicon layer above the diffusion layer is increased, allowing for the discussion of a plate-shaped polysilicon layer and its length in a direction parallel to the longitudinal direction of the diffusion layer, which in turn is parallel to the extension direction of the power supply lines 224, 226. This length can almost uniformly and completely cover the diffusion layer along its length direction. Now, if such a plate-shaped polysilicon layer should be contacted during reconfiguration to become a switchable gate electrode of a transistor, the large extension of the polysilicon layer above the diffusion layer would result in very slow (or very long) switching of such transistors, which would therefore be unsuitable. Instead, the gate-based decoupling units 160, 160' are designed to create suitable transistors with appropriate switching times after reconfiguration in a metal ECO. This is just one example of why conventional decoupling layers are generally unsuitable for reconfiguration in a metal ECO, and the same applies to the gate-based decoupling units 160, 160'.

[0140] Furthermore, in conventional decoupling cells, the potentially large extension of the polysilicon layer above the diffusion layer will result in a very small number of transistors that can be generated from the polysilicon layer, possibly only one. Conversely, for gate-based decoupling cells 160, 160', the number of transistors that can be generated from the polysilicon layer during the metal ECO process is expected to be very large, providing significant flexibility in designing different types of functional units during the metal ECO process. This is another example of why conventional decoupling layers are generally unsuitable for reconfiguration in metal ECOs, and the same applies to gate-based decoupling cells 160, 160'.

[0141] In contrast to conventional decoupling units, the gate-based decoupling units 160, 160' according to the present invention are designed to be best suited for reconfiguration in a metal ECO. To be suitable for reconfiguration in a metal ECO, the gate-based decoupling units 160, 160' according to the present invention share the following common features and satisfy the following constraints and requirements regarding the dimensions of their components.

[0142] 1. To accommodate reconfiguration in a metal ECO and provide flexibility regarding the types of functional units that can be generated, the gate-based decoupling units 160, 160' should be designed such that as many transistors as possible can be generated based on the polysilicon layer 220 and the p-type diffusion layer 230 and n-type diffusion layer 214. Specifically, the gate-based decoupling units 160, 160' should be designed such that at least two transistors can be generated along the lengths L214, L230, as seen in the longitudinal direction of the diffusion layers 214, 230 and / or in a direction parallel to the power supply lines 224, 226. This imposes a constraint on the number of polysilicon layers 220, which should be placed parallel to each other and extend over the diffusion layers 214, 230 in a direction transverse to the longitudinal direction of the diffusion layers 214, 230.

[0143] 2. In addition, in order to be suitable for reconfiguration in the metal ECO and to enable the generation of many different types of functional units, the gate-based decoupling units 160, 160' should be designed to have two types of transistors, namely, p-type transistors and n-type transistors.

[0144] 3. In addition, in order to be suitable for reconfiguration in a metal ECO, the p-type diffusion layer 230 and n-type diffusion layer 214 of the gate-based decoupling units 160, 160' should extend continuously over the entire length L214, L230 of the diffusion layers in the longitudinal direction of the diffusion layers 230, 214 and / or in the direction parallel to the extension direction of the power supply lines 224, 226, i.e., without interruption or gap.

[0145] refer to Figure 5 and 9 In order to formulate additional constraints and requirements for the gate-based decoupling units 160, 160' according to the invention to be suitably reconfigurable as functional units in a metal ECO, the following dimensions (length or width) as seen in the top view of the gate-based decoupling units 160, 160' must be taken into account.

[0146] - The length L110 of the unit in the longitudinal direction of the diffusion layers 230, 214 and / or in the direction parallel to the extension direction of the power supply lines 224, 226 (hereinafter referred to as the "longitudinal direction")

[0147] The length of the -n-type diffusion region in the longitudinal direction is L214.

[0148] The length of the -p type diffusion region in the longitudinal direction is L230.

[0149] - The minimum length L220min (or width) of the polysilicon (or gate) layer 220 in the longitudinal direction.

[0150] - The length L220ext (or width) of the polysilicon (or gate) layer 220 after its extension in the longitudinal direction.

[0151] - The maximum length L220max (or width) of the polysilicon (or gate) layer 220 in the longitudinal direction.

[0152] - The length L222 (or diameter) of the metal contact through hole 222.

[0153] - The length (or width) of the first layer of metal (M1) 228 in the longitudinal direction L228.

[0154] The remaining "free" lengths R214-1, R214-2, and R214-3 of the -n-type diffusion region 214, where "free" means "not covered by the polysilicon layer 220," and

[0155] The remaining "free" lengths R230-1, R230-2, and R230-3 of the segment of the -p-type diffusion region 230, where "free" means "not covered by the polysilicon layer 220".

[0156] Using the above dimensions, the following additional constraints and requirements can be formulated, which are based on the characteristics of the gate-based decoupling units 160, 160' according to the present invention.

[0157] 4. The length L220 of the polysilicon layer 220 in the longitudinal direction, corresponding to the gate width of the transistor, should be close to, i.e., slightly greater than or equal to, the minimum gate width that can be processed according to the manufacturing technology used for the integrated circuit 100, and should reach a maximum value (i.e., L220max) that is approximately twice the minimum processable gate width L220min. - This constraint ensures that many transistors can be placed along the longitudinal direction while the gate width remains small enough to achieve a reasonably short switching time for the transistors.

[0158] 5. According to the manufacturing technology used for integrated circuit 100, the length L220 of the polysilicon layer 220 in the longitudinal direction should be greater than the length L222 (or width or diameter) of the metal contact via 222 in the longitudinal direction. To meet this condition, it may be necessary to design the length L220 of the polysilicon layer 220 in the longitudinal direction to be slightly greater than the minimum processable gate width L220min, so as to achieve the extended minimum gate width L220ext at least in the segment of the strip polysilicon layer 220. - As Figure 9 As shown, this constraint ensures that the metal contact via 222 can be placed in / on the polysilicon layer 220.

[0159] 6. When multiple polysilicon layers 220 are placed parallel to each other and extend over the p-type diffusion layer 230 in a transverse direction perpendicular to the longitudinal direction, as seen in the longitudinal direction, the segments of the p-type diffusion layer 230 should have remaining free lengths R230-1, R230-2, R230-3 (i.e., not covered by the polysilicon layer 220), wherein each of the remaining free lengths R230-1, R230-2, R230-3 is greater than the length L222 (or width or diameter) of the metal contact via 222 and / or greater than the length L228 (or width) of the first metal layer (M1) 228.

[0160] Similarly, when multiple polysilicon layers 220 are placed parallel to each other and extend over the n-type diffusion layer 214 in a transverse direction perpendicular to the longitudinal direction, as seen in the longitudinal direction, there should be remaining free lengths R214-1, R214-2, R2140-3 (i.e., not covered by the polysilicon layer 220) in the segments of the n-type diffusion layer 214, wherein each of the remaining free lengths R214-1, R214-2, R214-3 is greater than the length L222 (or width or diameter) of the metal contact via 222 and / or greater than the length L228 (or width) of the first metal layer (M1) 228.

[0161] These two constraints ensure that the metal contact via 222 and / or the first metal layer (M1) 228 can be placed between the two strip polysilicon layers 220 and / or on each side of each strip polysilicon layer 220.

[0162] To illustrate the design constraints and requirements 2 through 6 above, please refer to the following: Figure 10 and 11 .

[0163] Figure 10 This illustrates how the system can be reconfigured according to an exemplary embodiment of the invention. Figure 6 A top view of an example of gate-based decoupling units 160, 160'. Figure 11 An exemplary embodiment of the invention is shown in Figure 10 After the reconfiguration implementation shown Figure 6 and 10 A top view of the reconfigured gate-based decoupling cell.

[0164] Figure 10 It shows Figure 6Gate-based decoupling units 160, 160' are described. It is assumed that these gate-based decoupling units 160, 160' will be reconfigured during the metal ECO process. A suitable new unit function for the gate-based decoupling units 160, 160' has been determined; that is, the units should be reconfigured as NAND gates with two inputs, such as... Figure 4 The NAND gate is shown. Due to the reconfiguration during the metal ECO process, some pin contacts in pin contacts (or metal contact vias) 222 and some portions of the first metal layer 228 must be removed, while new pin contacts (or metal contact vias) 222 and new portions of the first metal layer 228 must be added. The contact elements to be removed are in... Figure 10 and 11 The contact element is indicated by being surrounded by a continuous boundary line 236. In contrast, the contact element to be added is shown in... Figure 10 and 11 The contact element is indicated by being surrounded by a dashed boundary line 238.

[0165] like Figure 11 As shown in the upper left and upper right regions, new portions of the first layer of metal 228 connected to the power supply line 224 and new metal contact vias 222 for contacting the p-type diffusion region 230 have been added. Additionally, similarly in... Figure 11 In the lower right region, a new portion of the first metal layer 228 connected to the opposing power supply line 226 and a new metal contact via 222 contacting the n-type diffusion region 214 are added. The upper two portions of the added first metal layer 228 and metal contact via 222 are placed above the p-type diffusion region 230, and the lower portion of the added first metal layer 228 and metal contact via 222 is placed above the n-type diffusion region 214, in each case next to the strip polysilicon layer 220.

[0166] The addition of the upper two sections of the first layer of metal 228 and the two new metal contact vias 222 is a description of the first constraint mentioned in item 6 above: namely, the remaining free lengths R230-1 and R230-3 (see Figure 5 The length L222 of the new metal contact via 222 is greater than that of the metal contact via 222 and / or the length L228 of the first metal layer 228, so that the new first metal layer 228 and the new metal contact via 222 can be accommodated next to the strip polysilicon layer 220 above the p-type diffusion region 230.

[0167] The addition of the lower portion of the first layer of metal 228 and the new metal contact via 222 is a description of the second constraint mentioned in item 6 above: namely, the remaining free length R214-3 (see Figure 5The length L222 of the new metal contact via 222 is greater than that of the metal contact via 222 and / or the length L228 of the first metal layer 228, so that the new first metal layer 228 and the new metal contact via 222 can be accommodated next to the strip polysilicon layer 220 above the n-type diffusion region 214.

[0168] In addition, such as Figure 11 As shown in the central region, a new metal contact via 222 is added to the p-type diffusion region 230, and a new portion of the first layer of metal 228 is connected to the p-type diffusion region 230 through the new metal contact via 222 and extends over the n-type diffusion region 214.

[0169] The addition of the central portion of the first layer of metal 228 and the new metal contact via 222 is a description of the first and second constraints mentioned above under item 6: namely, the remaining free lengths R230-2 and R214-3 (see Figure 5 The length L222 of the new metal contact via 222 is greater than that of the metal contact via 222 and / or the length L228 of the first metal layer 228, so that the new metal contact via 222 and the new first metal layer 228 can be accommodated between the two strip polysilicon layers 220 above the p-type diffusion region 230 and the n-type diffusion region 214.

[0170] Figure 11 The NAND gate with two inputs shown is an example of reconfigured units 170, 170', which have been changed from... Figure 10 The gate-based decoupling unit shown requires both p-type and n-type transistors and correspondingly requires two types of diffusion regions: p-type diffusion region 230 and n-type diffusion region 214. Figure 11 The ability to be reconfigured into a NAND gate with two inputs, as shown, is an example of the constraint mentioned above under item 2.

[0171] exist Figure 10 and 11 It can also be seen that the p-type diffusion layer 230 and n-type diffusion layer 214 based on the gate decoupling units 160, 160' (and the reconfigured units 170, 170') extend along the entire length L214, L230 of the diffusion layers 230, 214 in the longitudinal direction and / or in the direction parallel to the extension direction of the power supply lines 224, 226 (see [link to documentation]). Figure 5 It extends continuously above, that is, without interruption or gap, which is an example of the constraint mentioned in item 3 above.

[0172] Furthermore, such as Figure 11As shown on the left and right sides of the central region, new metal contact vias 222 are added above the strip polysilicon layer 220, respectively connecting to one polysilicon layer 220 and another polysilicon layer 220, as well as new portions of the first metal layer 228. Adding new metal contact vias 222 above the strip polysilicon layer 220 is an explanation of the constraint mentioned above under item 5: that is, the length L220 of the polysilicon layer 220 in the longitudinal direction (see...) Figure 5 It must be greater than the length L222 (or diameter) of the metal contact through hole 222 in the longitudinal direction.

[0173] Finally, now for reference Figure 5 It should be noted that in this embodiment of the gate-based decoupling units 160, 160', each of the two polysilicon layers 220 has a varying length L220 in the longitudinal direction. For example, the left polysilicon layer of the two polysilicon layers 220 has a minimum length L220min over the p-type diffusion region 230 and a larger length over the n-type diffusion region 214, the minimum length L220min being customizable according to the manufacturing techniques used for the integrated circuit 100, and the larger length being almost twice the length over the p-type diffusion region 230.

[0174] Figure 5 The two polysilicon layers 220 shown are designed to comply with the constraints mentioned above under item 4: that is, the polysilicon layers 220 ( Figure 5 The length L220 of the polysilicon layer on the left in the middle direction extending above the p-type diffusion layer in the vertical direction is close to the minimum gate width that can be processed according to the manufacturing technology used for integrated circuit 100, and reaches a maximum value of about twice the minimum processable gate width L220min (i.e., above the n-type diffusion layer 214, as L220max).

[0175] because Figure 10 The gate-based decoupling units 160, 160' shown satisfy the size constraints of the elements of the gate-based decoupling units 160, 160' according to the present invention mentioned in items 2 to 6 above, therefore Figure 10 The gate-based decoupling units 160, 160' shown can be reconfigured for metal ECO when needed, for example, to become Figure 11 The reconfigured gate-based decoupling units 170, 170' are shown.

[0176] Figure 12 A flowchart of a method 300 for designing an integrated circuit 100 according to an exemplary embodiment of the present invention is shown.

[0177] Method 300 is used to design an integrated circuit 100, wherein the integrated circuit will be constructed in a cell 110, wherein the cell 110 will include functional cells 120 and spare cells 130. Method 300 begins with step 310 of placing and routing the functional cells on patterned locations, which essentially includes step 312 of designing at least one functional cell and step 314 of placing a plurality of functional cells 120 on associated patterned locations of a patterned matrix designed for the functional cells of the integrated circuit.

[0178] The method then proceeds to step 320, in which a gate-based decoupling unit is placed at at least one remaining pattern position in the remaining pattern positions of the pattern matrix, replacing at least one conceivable spare unit 130 for the at least one remaining pattern position in the remaining pattern positions of the pattern matrix. Step 320 may further include placing a plurality of corresponding gate-based decoupling units 160 at a plurality of remaining pattern positions in the pattern matrix, replacing a plurality of conceivable spare units 130 for the plurality of remaining pattern positions in the pattern matrix.

[0179] Alternatively, for step 320, the method proceeds to step 320', where gate-based decoupling units are placed in at least one gap between pattern positions of the pattern matrix, replacing at least one conceivable filler unit 140 for the at least one gap between pattern positions of the pattern matrix. Step 320' may also include placing a plurality of corresponding gate-based decoupling units 160' in a plurality of gaps between pattern positions of the pattern matrix, replacing a plurality of conceivable filler units 140 for the plurality of gaps between pattern positions of the pattern matrix.

[0180] The at least one gate-based decoupling unit 160, 160' placed in step 320 or step 320' includes at least one diffusion layer 214 for forming the source region 208 and / or drain region 210 of the transistor 200 and a polysilicon layer 220 partially disposed on the at least one diffusion layer 214. The polysilicon layer 220 is conductively connected to the power supply line 224 of the gate-based decoupling unit 160, 160', and the at least one diffusion layer 214 is conductively connected to the opposite power supply line 226 of the gate-based decoupling unit 160, 160'. Therefore, a capacitance is created between the polysilicon layer 220 connected to the power supply line 224 and the diffusion layer 214 connected to the opposite power supply line 226.

[0181] The method then proceeds to step 330, in which the requirements for all design and process aspects of the designed integrated circuit are verified to be met, including the requirements for functional unit 120 and the at least one gate-based decoupling unit 160, 160'.

[0182] The method can then proceed to step 340, which includes reconfiguring at least one of the gate-based decoupling units 160, 160' during a metal ECO (Engineering Change Order). Step 340 may include step 342, which determines a suitable new unit function for the at least one gate-based decoupling unit 160, 160', and step 344, which reconfigures the contact layer 234 and metal layers 228, 232 of the at least one gate-based decoupling unit 160, 160'. Steps 342 and 344 can be performed to implement the determined new unit function of the reconfigured at least one gate-based decoupling unit 170, 170'.

[0183] Step 340 of reconfiguring the at least one gate-based decoupling unit 160, 160' may include removing the contact layer 234 and / or the metal layer 232, which creates the decoupling function of the at least one gate-based decoupling unit 160, 160'; and adding a new contact layer 234' and / or the metal layer 232', which creates the desired suitable new unit function of the reconfigured at least one gate-based decoupling unit 170, 170'.

[0184] The reconfiguration of the at least one gate-based decoupling unit 160, 160' according to step 340 can be performed manually by an integrated circuit design engineer. Alternatively, the reconfiguration of the at least one gate-based decoupling unit 160, 160' according to step 160 may include the design of a suitable new cell function for the reconfiguration of at least one gate-based decoupling unit 170, 170' from a library.

[0185] Finally, the method may proceed to step 350, which includes verifying that all design and process requirements of the integrated circuit that has been reconfigured during the metal engineering change order are met, including the requirements of functional unit 120 and the at least one reconfigured gate-based decoupling unit 170, 170'.

[0186] In this specification, exemplary embodiments have been presented with respect to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of these details, can be practiced. The following claims are intended to cover all possible exemplary embodiments.

[0187] Furthermore, it should be noted that "having" or "comprising" does not exclude other elements or steps, and "a / a (a)" does not exclude multiple. Additionally, it should be noted that features or steps described above with reference to one of the above-described embodiment examples may also be used in combination with other features or steps of other embodiment examples described above. Reference numerals in the claims should not be construed as limiting.

[0188] List of reference numerals

[0189] 100 integrated circuits

[0190] Unit 110

[0191] 120 functional units

[0192] 130 spare unit

[0193] 140 filler cells

[0194] 150 reconfigured fill units

[0195] 160, 160' Gate-based decoupling cells

[0196] 170, 170' reconfigured gate-based decoupling unit

[0197] 200 transistors

[0198] 202 wafers

[0199] 204p well

[0200] 206 Shallow Trench Isolation (STI)

[0201] 208 Source Region

[0202] 210 drain region

[0203] 212 Bridging Area

[0204] 214n type diffusion region

[0205] 216 Ditch Area

[0206] 218 oxide layer

[0207] 220 polysilicon (or gate)

[0208] 222 Metal Contact Through Hole

[0209] 224 power supply line

[0210] 226 relative power supply lines

[0211] 228 First layer of metal (M1)

[0212] 230p type diffusion region

[0213] 232-cell inner layer metal (M1)

[0214] 234 Unit Internal Pin Contacts

[0215] 236 Pin contacts and / or first layer of metal to be removed

[0216] 238 Pin contacts to be added and / or first layer of metal

[0217] L110 unit length

[0218] Length of the L214n type diffusion region

[0219] Length of the L230p type diffusion region

[0220] L220min Minimum length (or width) of polysilicon (or gate)

[0221] The minimum length (or width) of the extended L220ext polysilicon (or gate)

[0222] The maximum length (or width) of L220max polysilicon (or gate)

[0223] Length (or diameter) of L222 metal contact via

[0224] Length of the first metal layer (M1) of L228

[0225] Remaining free length of the n-type diffusion region in R214-1, R214-2, and R214-3

[0226] Remaining free length of the p-type diffusion region of R230-1, R230-2, and R230-3

[0227] 300 Methods for Designing Integrated Circuits

[0228] 310 places and wires the functional units on the pattern position.

[0229] 312 Design at least one functional unit

[0230] 314 places multiple functional units on the relevant pattern positions of the pattern matrix designed for the functional units.

[0231] 320 places gate-based decoupling cells on the remaining pattern positions of the pattern matrix.

[0232] 320' places the gate-based decoupling cells in the gaps between the pattern positions of the pattern matrix.

[0233] 330 Verify that all design and process requirements for the functional unit and the at least one gate-based decoupling unit are met.

[0234] 340 Reconfigure at least one gate-based decoupling unit in the gate-based decoupling units

[0235] 342 Determine a suitable new cell function for the at least one gate-based decoupling cell.

[0236] 344 Reconfigure the contact layer and metal layer of the at least one gate-based decoupling unit.

[0237] 350 Verify that all design and process requirements for the functional unit and the at least one gate-based decoupling unit are met.

Claims

1. A method (300) for designing an integrated circuit (100), characterized in that, The integrated circuit will be constructed in a unit (110), wherein the unit (110) will include a functional unit (120) and a spare unit (130), and the method (300) has: a) Design (312) at least one functional unit (120); b) Place (314) multiple functional units (120) on associated pattern positions of a pattern matrix of a particular regular pattern matrix designed for the functional units (120); as well as c) Design at least one spare unit (130) for at least one remaining pattern position in the pattern matrix, and replace the at least one spare unit with a gate-based decoupling unit (160) placed (320) at at least one remaining pattern position in the pattern matrix, wherein the gate-based decoupling unit (160) is designed to be reconfigurable during metalworking change orders to achieve suitable new unit functionality, and d) Design at least one filling cell (140) in at least one gap between pattern positions in the pattern matrix, and replace the at least one filling cell with a gate-based decoupling cell (160') to place (320') in at least one gap between pattern positions in the pattern matrix, wherein the gate-based decoupling cell (160') is designed to be reconfigurable during metalworking change orders to achieve suitable new cell functionality.

2. The method (300) according to claim 1, characterized in that, Step c) includes designing a plurality of spare units (130) at a plurality of remaining pattern positions in the pattern matrix and replacing the plurality of spare units with a plurality of corresponding gate-based decoupling units (160) placed at the plurality of remaining pattern positions in the pattern matrix, wherein each gate-based decoupling unit is designed to be reconfigured during metal engineering change commands to achieve the appropriate new unit function.

3. The method according to claim 1 or 2, characterized in that, Step d) includes designing a plurality of filler cells (140) in a plurality of gaps between pattern positions in the pattern matrix, and replacing the plurality of filler cells with a plurality of corresponding gate-based decoupling cells (160') placed in the plurality of gaps between pattern positions in the pattern matrix, wherein each gate-based decoupling cell is designed to be reconfigurable during metal engineering change commands to achieve a suitable new cell function.

4. The method (300) according to claim 1. Its features are, The at least one gate-based decoupling unit (160, 160') includes at least one diffusion layer (214) for forming a source region (208) and / or a drain region (210) of a transistor (200) and a polysilicon layer (220) partially disposed on the at least one diffusion layer (214). The polysilicon layer (220) is electrically connected to the power supply line 224 of the gate-based decoupling unit (160, 160'), and the at least one diffusion layer (214) is electrically connected to the opposite power supply line (226) of the gate-based decoupling unit (160, 160'). This creates a capacitor between the polysilicon layer (220) connected to the power supply line (224) and the diffusion layer (214) connected to the opposite power supply line (226).

5. The method (300) according to claim 1, characterized in that, Additionally, it has: Verification (330) ensures that the specific design and process requirements of the designed integrated circuit are met, including the requirements of the functional unit (120) and the at least one gate-based decoupling unit (160, 160').

6. The method (300) according to claim 1, characterized in that, In addition, including: e) Reconfigure at least one of the gate-based decoupling units (160, 160') during the metal engineering change command process.

7. The method (300) according to claim 6, characterized in that, Step e) includes (ei) determine (342) a suitable new cell function for the at least one gate-based decoupling cell (160, 160'), and e.ii) Reconfigure (344) the contact layer (234) and metal layer (228, 232) of the at least one gate-based decoupling unit (160, 160') to implement the determined new unit function of the reconfigured at least one gate-based decoupling unit (170, 170').

8. The method (300) according to claim 6 or 7, characterized in that, The reconfiguration (340) of the at least one gate-based decoupling unit (160, 160') includes Removing the contact layer (234) and / or the metal layer (232) creates the decoupling function of the at least one gate-based decoupling unit (160, 160'), and Adding a new contact layer (234') and / or a metal layer (232') creates the desired suitable new cell function for the reconfigured at least one gate-based decoupling cell (170, 170').

9. A method for manufacturing an integrated circuit (100), characterized in that, The integrated circuit is constructed in a unit (110), wherein the unit (110) will include a functional unit (120), a spare unit (130), and a filler unit (140), and the method has the following characteristics: A) The functional units are manufactured at corresponding associated pattern positions of a pattern matrix, particularly a regular pattern matrix, designed for multiple functional units (120); as well as B) Design at least one spare unit (130) for at least one of the remaining pattern positions in the pattern matrix, and fabricate a gate-based decoupling unit (160) on the at least one of the remaining pattern positions in the pattern matrix to replace the spare unit (130), wherein the gate-based decoupling unit (160) is designed to be reconfigurable during metalworking change orders to achieve the appropriate new unit function. and C) Design at least one filling cell (140) in at least one gap between pattern positions in the pattern matrix, and fabricate a gate-based decoupling cell (160') in at least one gap between pattern positions in the pattern matrix to replace the filling cell (140)', wherein the gate-based decoupling cell (160') is designed to be reconfigurable during metalworking change orders to achieve suitable new cell functionality.

10. An integrated circuit (100), characterized in that, The integrated circuit is constructed in a unit (110), wherein the unit (110) includes a functional unit (120), a spare unit (130), and a filler unit (140), and the integrated circuit (100) has: A) A plurality of functional units (120) arranged at corresponding associated pattern positions of a pattern matrix of a particular regular pattern matrix designed for the functional units; as well as B) At least one gate-based decoupling unit (160), the at least one gate-based decoupling unit being disposed at at least one remaining position in the remaining positions of the pattern matrix and replacing a spare unit (130) that can be designed for the at least one remaining position in the remaining positions of the pattern matrix, wherein the gate-based decoupling unit (160) is designed to be reconfigurable during metalworking change orders to achieve suitable new unit functionality; and / or C) At least one gate-based decoupling unit (160'), the at least one gate-based decoupling unit being disposed in at least one gap between pattern positions of the pattern matrix and replacing a filler unit (140) that can be designed for the at least one gap between pattern positions of the pattern matrix, wherein the gate-based decoupling unit (160') is designed to be reconfigurable during metalworking change orders to achieve suitable new unit functionality.

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