Storage device using degradation information to calculate optimal read voltage

Abstract

A storage device includes a first memory device including a plurality of memory blocks and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage to acquire the first degradation information and perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device, the second degradation information estimated using the first degradation information. Each of the first degradation information and the second degradation information includes a number of erroneous bits of each of the plurality of pages.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0095757, filed on August 6, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] An exemplary embodiment of the present invention relates to a storage device that uses degradation information to calculate the optimal read voltage. Background Technology

[0004] Memory devices can experience performance degradation due to various factors, such as increased retention time, read interference errors, and reduced durability due to increased program / erase (P / E) cycles. Read tolerance decreases as the integration density of memory devices increases, and the degree of decrease in read tolerance increases with the severity of memory device performance degradation, which adversely affects data reliability. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a storage device includes: a first memory device including a plurality of memory blocks and a plurality of pages included in each of the plurality of memory blocks; a second memory device configured to store first degradation information of the first memory device; and a controller configured to perform a first read operation on the first memory device using a first read voltage to obtain the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using the second degradation information of the first memory device, the second degradation information being estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits for each of the plurality of pages.

[0006] According to an exemplary embodiment of the present invention, a storage device includes: a first memory device configured to store data requested by a host; a second memory device configured to store first degradation information of the first memory device in page units; and a controller configured to perform a first read operation on the first memory device using a first read voltage and to acquire the first degradation information. The second memory device estimates second degradation information of the first memory device based on the first degradation information and calculates a second read voltage based on the second degradation information, wherein the second read voltage is used to perform the second read operation on the first memory device according to a request from the host.

[0007] According to an exemplary embodiment of the inventive concept, a storage device includes a first memory device configured to store data requested by a host, a second memory device configured to store first degradation information of the first memory device, and a controller configured to detect a number of error bits generated through a first read operation on the first memory device as the first degradation information. The first memory device estimates second degradation information of the first memory device based on the first degradation information in response to a request for a second read operation from the host, and performs the second read operation using a read voltage calculated based on the second degradation information. A programming unit of the second memory device is different from a programming unit of the first memory device. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects and features of the inventive concept will become clearer from the following detailed description of exemplary embodiments thereof, taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a view illustrating a storage system according to an exemplary embodiment of the inventive concept.

[0010] Figures 2 to 5B is a view illustrating a memory device included in a storage device according to an exemplary embodiment of the inventive concept.

[0011] Figure 6 is a view illustrating a change in a threshold voltage distribution according to a degree of degradation of a memory cell included in a first memory device of Figure 1 according to an exemplary embodiment of the inventive concept.

[0012] Figure 7 is a view illustrating a storage device according to an exemplary embodiment of the inventive concept.

[0013] Figure 8 is a view illustrating a degradation information storage unit of Figure 7 according to an exemplary embodiment of the inventive concept.

[0014] Figures 9A to 12 is a view illustrating a method of estimating error information by a read level calculation unit of Figure 7 according to an exemplary embodiment of the inventive concept.

[0015] Figures 13A to 13C is a view illustrating a lookup table according to an exemplary embodiment of the inventive concept.

[0016] Figure 14A and Figure 14B is a graph illustrating a linear polynomial operation of estimating a number of error bits according to an exemplary embodiment of the inventive concept.

[0017] Figure 15A and Figure 15B is a view illustrating an operation method of a storage device according to an exemplary embodiment of the inventive concept. Figure 7

[0018] Figure 16 is a view illustrating a storage device according to an exemplary embodiment of the inventive concept.

[0019] Figure 17 is a view illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept. Figure 16

[0020] Figure 18 is a view illustrating a storage device according to an exemplary embodiment of the inventive concept.

[0021] Figure 19 is a view illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept. Figure 18

[0022] Figure 20 is a view schematically illustrating an electronic device including a storage device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Exemplary embodiments of the inventive concept provide a storage device capable of efficiently controlling a read voltage using degradation information stored in a heterogeneous memory device.

[0024] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the application.

[0025] Figure 1 is a view illustrating a storage system according to an exemplary embodiment of the inventive concept.

[0026] Figures 2 to 5B is a view illustrating a memory device included in a storage device according to an exemplary embodiment of the inventive concept.

[0027] Referring to Figure 1 , a storage system 1 can include a storage device 10 and a host 20.

[0028] The storage device 10 can operate in response to a request of the host 20, and can store data accessed by the host 20.

[0029] The storage device 10 can include a memory device 100 storing various types of data, and a controller 200 controlling overall operations of the memory device 100. ​​​

[0030] The memory device 100 can include a first memory device 110 and a second memory device 120.

[0031] The first memory device 110 can store data accessed by the host 20. In some examples, the first memory device 110 can include a Non-Volatile Memory (NVM). For example, the first memory device 110 can include a NAND flash memory, a NOR flash memory, a flash memory having a hybrid structure in which two or more types of memories are mixed, etc.

[0032] Referring to Figure 2 , the first memory device 110 can include a voltage generator 111, an address decoder 113, control logic 115, a memory cell array 117, and a data input / output circuit 119.

[0033] The control logic 115 can receive various commands and address signals from the controller 200, and can control the address decoder 113 and the data input / output circuit 119 to perform a read operation, a program operation, etc. Further, the control logic 115 can receive a voltage control signal from the controller 200, and control the voltage generator 111 to generate a read voltage, a program voltage, etc.

[0034] The voltage generator 111 can generate a plurality of voltages for driving the first memory device 110. For example, the voltage generator 111 can generate a plurality of read voltages, a plurality of program voltages, a plurality of pass voltages, etc.

[0035] The address decoder 113 can be connected to the memory cell array 117 through a string select line SSL, a plurality of word lines WL1 to WL N , and a ground select line GSL. The address decoder 113 can decode an address signal received from the controller 200, and can apply a read voltage to at least one word line selected according to the decoded address signal among the word lines WL1 to WL N .

[0036] The data input / output circuit 119 can receive data from a plurality of memory cells connected to the word lines WL1 to WL M to which the read voltage is applied, through a plurality of bit lines BL1 to BL N . The data input / output circuit 119 can include a page buffer PB for temporarily storing data read from the memory cell array 117 and data to be programmed in the memory cell array 117. In some examples, the page buffer PB can be implemented with a plurality of data latches.

[0037] The memory cell array 117 can include a plurality of memory blocks BLK1 to BLK n . In addition, each of the memory blocks BLK1 to BLK n may include a plurality of pages PAGE1 to PAGE m . Each of the pages PAGE1 to PAGE m may include a plurality of memory cells, and the plurality of memory cells can be connected to a plurality of word lines WL1 to WL N . The memory cells can include a single layer cell (SLC) storing one bit of data, and a multi-layer cell (MLC) storing two or more bits of data, according to the number of bits of data that can be stored.

[0038] Figure 3 is a view illustrating a plurality of memory blocks BLK1 to BLK n included in the first memory device 110. Referring to Figure 3 , each of the plurality of memory blocks BLK1 to BLK n may include a plurality of cell strings SS connected to a plurality of bit lines BL1 to BL M . Each of the cell strings SS can include selection transistors SST and GST connected to a string selection line SSL and a ground selection line GSL, respectively, and a plurality of memory cell transistors MC1 to MC N connected to different word lines WL1 to WL N . The plurality of memory cell transistors connected to the same word line among the word lines WL1 to WL N may constitute one page.

[0039] The plurality of memory blocks BLK1 to BLK n may have a two-dimensional array structure in which the memory cell transistors MC1 to MC N are arranged in a direction parallel to a substrate. In addition, the plurality of memory blocks BLK1 to BLK n may have a three-dimensional array structure in which the plurality of memory cell transistors MC1 to MC N are stacked in a direction perpendicular to a substrate to extend in first to third directions DIR1 to DIR3, as shown in Figure 4 .

[0040] The second memory device 120 can store degradation information of the first memory device 110. In an exemplary embodiment of the inventive concept, the second memory device 120 can store information about the number of error bits detected by the first memory device 110. In addition, the second memory device 120 can also store information about the temperature of the first memory device 110, information about the P / E cycle of the first memory device 110, information about the interval between the erase state and the program state of the first memory device 110, etc.

[0041] The degradation information stored in the second memory device 120 can be used to adjust the read voltage of the first memory device 110. For example, the first memory device 110 can estimate the number of error bits that can be generated when a read operation is performed using at least one of the number of error bits stored in the second memory device 120. The first memory device 110 can calculate a read voltage having an optimal read level from the estimated number of error bits, and can then perform a read operation using the calculated read voltage.

[0042] In an exemplary embodiment of the inventive concept, the second memory device 120 can include a volatile memory device such as a Dynamic RAM (DRAM), a Static RAM (SRAM), etc., and a next-generation non-volatile memory device such as a Z-NAND flash memory, etc.

[0043] In an exemplary embodiment of the inventive concept, the second memory device 120 can be a memory device having fewer program and read operation units than the program and read operation units of the first memory device 110, and can include a resistive memory device such as a Phase change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), etc. The resistive memory device can have a data processing unit smaller than the data processing unit of the first memory device 110. In a different manner from the NAND flash memory that performs program and read operations in units of pages, the resistive memory device can perform program and read operations in units of bytes, and thus can be suitable for storing relatively small-sized degradation information that can be periodically detected. In addition, since the resistive memory device has a relatively high access speed, it can be possible to prevent a read operation from being delayed. An example of the second memory device 120 can be as shown in FIGS. 1B and 2. Figure 5A and Figure 5B

[0044] Referring to Figure 5A ​A second memory device 500, which can correspond to the second memory device 120, can include word lines 510 extending in a first direction DIR1, bit lines 530 extending in a second direction DIR2 perpendicular to the first direction DIR1, and memory cells 520 disposed between the word lines 510 and the bit lines 530.

[0045] The memory cells 520 can include first electrodes 521 connected to the word lines 510, second electrodes 522 connected to the bit lines 530, and third electrodes 523 disposed between the first electrodes 521 and the second electrodes 522. In addition, the memory cells 520 can include a storage element layer 524 disposed between the first electrodes 521 and the third electrodes 523, and a selection element layer 525 disposed between the third electrodes 523 and the second electrodes 522.

[0046] The storage element layer 524 can include a germanium-antimony-tellurium (GST) material in which germanium (Ge), antimony (Sb), and tellurium (Te) are adhered. The storage element layer 524 can store data depending on a difference in threshold voltage or resistance. For example, the storage element layer 524 can have a relatively low resistance and a relatively low threshold voltage in a crystalline state, can have a relatively high resistance and a relatively high threshold voltage in an amorphous state, and can use such characteristics to store data.

[0047] The selection element layer 525 can be an element for selecting a memory cell, and can include a chalcogenide-based material in which germanium (Ge), selenium (Se), and tellurium (Te) are adhered. The selection element layer 525 can include an Ovonic Threshold Switch (OTS) material.

[0048] Reference Figure 5B A second memory device 600, which can correspond to the second memory device 120, can include first and second word lines 610 and 630 extending in a first direction DIR1 and spaced apart from each other in a third direction DIR3 perpendicular to the first direction DIR1, and bit lines 650 disposed between the first and second word lines 610 and 630 and extending in a second direction DIR2 perpendicular to the first and third directions DIR1 and DIR3. In addition, the second memory device 600 can include first memory cells 620 disposed between the first word lines 610 and the bit lines 650, and second memory cells 640 disposed between the bit lines 650 and the second word lines 630.

[0049] The first and second memory cells 620 and 640 can have the same structure as the memory cells 520 described above with reference to FIG. 5. Figure 5AThe described memory cell 520 has substantially the same structure. For example, the first memory cell 620 can include first to third electrodes 621 to 623, a storage element layer 624 disposed between the first and third electrodes 621 and 623, and a selection element layer 625 disposed between the third electrode 623 and the second electrode 622.

[0050] Referring again to FIG. 1, Figure 1 The controller 200 can be connected to the host 20 through a host interface (I / F) 210 to receive read requests, program requests, and the like, and exchange data. For example, the controller 200 can receive a read request from the host 20 through the host interface 210, and can control a read operation of the memory device 100 accordingly. The host interface 210 can be configured to communicate with the host 20 using at least one of various interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect-Express (PCI-E), Small Computer System Interface (SCSI), Serial-Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and the like.

[0051] The controller 200 can be connected to the memory device 100 through a memory interface (I / F) 220 to process various requests of the host 20 and exchange data. For example, the controller 200 can control the memory device 100 to read or program data in response to a request of the host 20.

[0052] The controller 200 can further include a processor 230, a power management unit 240, an Error Correction Code (ECC) unit 250, and a memory 260.

[0053] The processor 230 can control the overall operation of the memory device 100, and can include a microprocessor, a central processing unit (CPU), or the like. The processor 230 can drive firmware such as a flash translation layer (FTL) to control the memory device 100.

[0054] The processor 230 can control a read operation on a plurality of memory blocks included in the memory device 100 to prevent performance degradation, occurrence of a read failure, or the like due to a retention characteristic of the memory device 100 or the like. Hereinafter, the read operation will be referred to as a patrol read operation to distinguish it from a read operation according to a read request of the host 20.

[0055] The processor 230 can perform the patrol read operation by itself issuing a read command and an address without receiving a read request from the host 20. The patrol read operation can be performed in the background differently from a read operation performed in the foreground according to a read request of the host 20. Also, the patrol read operation can be periodically performed under the control of the processor 230. A period of the patrol read operation can be preset based on an increase rate of error bits, a storage capacity of the memory device 130, a program / erase (P / E) cycle, or the like. In some examples, the period of the patrol read operation can be about 12 hours.

[0056] The number of error bits included in data read from the first memory device 110 as a result of the patrol read operation can represent degradation information of the first memory device 110, and can be stored in the second memory device 120.

[0057] The power management unit 240 can supply and manage power to components of the controller 200, respectively.

[0058] The ECC unit 250 can detect and correct errors included in data read from the memory device 100. For example, the ECC unit 250 can perform an ECC encoding operation on data received from the host 20. The ECC unit 250 can perform an ECC decoding operation on data read from the memory device 100, and can correct corresponding error bits when the number of error bits detected as a result of performing the ECC decoding operation is less than a predetermined threshold. The ECC unit 250 can perform an error correction operation using a low-density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, or the like.

[0059] The memory 260 can be an operation memory, and can store data such as firmware code, etc. for driving the controller 200. Also, the memory 260 can be a buffer memory, and can store data read from the memory device 100 or data to be programmed in the memory device 100. In some examples, the memory 260 can include a volatile memory such as a DRAM, an SRAM, etc.

[0060] Figure 6 is a view showing a change in a threshold voltage distribution of a degree of degradation of memory cells included in a first memory device according to an example embodiment of the present inventive concept. Figure 1 In Figure 6 , the horizontal axis represents a threshold voltage Vth, and the vertical axis represents the number of memory cells.

[0061] Figure 6 Part (a) in Figure 6 shows a threshold voltage distribution (initial state) within a predetermined time after completion of a programming operation on the memory cells, and Parts (b) to (d) in show threshold voltage distributions after the predetermined time after completion of the programming operation on the memory cells.

[0062] Figure 6 Part (b) in Figure 6 shows a threshold voltage distribution of memory cells classified as a group having a relatively low degree of degradation, Part (c) in Figure 6 shows a threshold voltage distribution of memory cells classified as a group having a relatively moderate degree of degradation, and Part (d) in shows a threshold voltage distribution of memory cells classified as a group having a relatively high degree of degradation.

[0063] First, referring to part (b) in Figure 6 , when the number of error bits of the memory cells is 40 or more and less than 80, the corresponding memory cells can be classified as a first group having a relatively low degree of degradation. In the first group of memory cells, the threshold voltage distribution can change by a first value (ΔVth1) compared to the initial state (part (a) in Figure 6 ).

[0064] Referring to part (c) in Figure 6 , when the number of error bits of the memory cells is 80 or more and less than 120, the corresponding memory cells can be classified as a second group having a relatively moderate degree of degradation. In the second group of memory cells, the threshold voltage distribution can change by a second value (ΔVth2) greater than the first value (ΔVth1) compared to the initial state (part (a) in Figure 6 ).

[0065] Reference Figure 6 In part (d) of FIG. 1, when the number of error bits of the memory cell is 120 or more, the corresponding memory cell can be classified into a third group having a relatively high degree of degradation. In the third group of memory cells, the threshold voltage distribution can vary by a third value (ΔVth3) that is greater than the second value (ΔVth2) compared to the initial state (part (a) of FIG. 1). Figure 6

[0066] The memory cell can be degraded due to various factors such as an increase in retention time, occurrence of read disturb errors, a decrease in endurance due to an increased program / erase (P / E) cycle, etc. The degree of degradation of the memory cell can vary for each page, which can be a unit of program and read operation. When adjusting the read voltage in units of a memory block including a plurality of pages without considering the degradation of each page, a page having a relatively low degree of degradation and a page having a relatively high degree of degradation can enter a defense code. In this case, since data recovered after entering the defense code can be copied to another memory block through a read reclaim operation, a problem of an increase in a write amplification factor (WAF) can occur.

[0067] Accordingly, the storage device according to an exemplary embodiment of the inventive concept can perform a patrol read operation to detect the number of error bits of each page, and can classify the degree of degradation of each page using the detected number of error bits. For example, when the number of error bits detected in a first page of the memory device is 50, the storage device can classify the first page into a first group. When the number of error bits detected in a second page of the memory device is 100, the storage device can classify the second page into a second group. Further, when the number of error bits detected in a third page of the memory device is 120, the storage device can classify the third page into a third group.

[0068] The storage device can map different read voltage values for each of a plurality of groups of the degree of degradation set for each page. For example, a first read voltage value can be mapped for a first group having a relatively low degree of degradation, and a third read voltage value greater than the first read voltage value can be mapped for a third group having a relatively high degree of degradation. When a read operation is performed on a particular page, the storage device can change the read voltage using the read voltage value mapped for the group to which the page belongs, and then can perform a read operation on the corresponding page using the changed read voltage.

[0069] ​As described above, the storage device according to exemplary embodiments of the inventive concept can differently control a read voltage value in consideration of a degree of degradation of each page to solve a problem of running at least one defense code for a page having a relatively low degree of degradation through a read retry (or read recovery) operation in units of a memory block.

[0070] Figure 7 is a view illustrating a storage device according to exemplary embodiments of the inventive concept.

[0071] Figure 8 is a view illustrating a storage device according to exemplary embodiments of the inventive concept. Figure 7 of a degradation information storage unit, and Figures 9A to 12 is a view illustrating a method of estimating error information by a read level calculation unit according to exemplary embodiments of the inventive concept. Figure 7

[0072] First, referring to Figure 7 The storage device 10A according to exemplary embodiments of the inventive concept can include a memory device 100A and a controller 200A.

[0073] The memory device 100A can include a first memory device 110A storing data requested by a host, and a second memory device 120A storing degradation information of the first memory device 110A. The first memory device 110A can include a single layer cell (SLC) storing one bit of data, and a multi layer cell (MLC) storing two or more bits of data. In exemplary embodiments of the inventive concept, the first memory device 110A can include a quad layer cell (QLC) capable of storing four or more bits of data in a single memory cell.

[0074] In exemplary embodiments of the inventive concept, the second memory device 120A can be a memory device having a program unit different from that of the first memory device 110A, and can include a resistive memory device such as PRAM, MRAM, RRAM, etc. In this case, since the second memory device 120A can be accessed in byte units and has a relatively fast access speed, the second memory device 120A can be suitable for storing and managing the degradation information of the first memory device 110A in page units.

[0075] ​Furthermore, in an exemplary embodiment of the present invention, the second memory device 120A may be a memory device having a faster access speed than the first memory device 110A, and may include next-generation memory devices, such as Z-NAND flash memory. In this case, since the second memory device 120A has a relatively fast access speed, the latency due to read voltage control can be minimized.

[0076] The second memory device 120A may include a degradation information storage unit HS for storing degradation information of the first memory device 110A. In an exemplary embodiment of the present invention, the degradation information stored in the second memory device 120A may include the number of bit errors of the first memory device 110A, information about the temperature of the first memory device 110A, information about the P / E cycle of the first memory device 110A, information about the interval between the erase state and the programming state of the first memory device 110A, etc.

[0077] Figure 8 A specific example of a degraded information storage unit (HS) is shown in the image. (Reference) Figure 8 The degradation information storage unit HS can store information about groups of degradation levels (e.g., groups one through three) and historical information about the number of error bits for each page. The number of error bits can be obtained by performing a patrol read operation using a predetermined first read voltage until a read failure occurs. In an exemplary embodiment of the inventive concept, the first read voltage can be greater than a second read voltage used to perform a read operation according to a request from the host. When a read failure occurs according to the patrol read operation, a voltage lower than the first read voltage can be used to continuously perform patrol read operations.

[0078] Return to reference Figure 7 The controller 200A may also include a read voltage controller RC, wherein the read voltage controller RC is used to calculate a read voltage suitable for the current read operation using degradation information of the first memory device 110A.

[0079] The voltage reading controller RC may include a reading level calculation unit 201 and a lookup table 203.

[0080] The read level calculation unit 201 can receive existing degradation information of a target page for performing a read operation from the degradation information storage unit HS, and can estimate the degradation information of the target page using the received existing degradation information. For example, the read level calculation unit 201 can receive information about a group of degradation levels to which the target page belongs and information about the number of existing error bits generated in the target page from the degradation information storage unit HS. When a read operation is performed on the target page, the read level calculation unit 201 can estimate the number of error bits that can occur in the target page using the existing degradation information. In such an estimation operation, the read level calculation unit 201 can use a linear polynomial operation.

[0081] In an exemplary embodiment of the inventive concept, the read level calculation unit 201 can change the reference number of existing error bits according to the degradation rate of the target page. For example, the read level calculation unit 201 can refer to the number of error bits (N Figure 9A When the change rate of the number of error bits (S1) is less than a predetermined threshold change rate (S th ), the degradation rate of the target page can be considered relatively slow. In this case, the read level calculation unit 201 can refer to the most recent number of error bits (N m ) to estimate the number of error bits (N m+1 ) after performing a read operation, to improve the calculation speed. The reference Figure 9B When the change rate of the number of error bits (S2) is greater than or equal to a predetermined threshold change rate (S th ), the degradation rate of the target page can be considered relatively high. In this case, the read level calculation unit 201 can refer to two or more recent numbers of error bits (N m and N m-1 ) to estimate the number of error bits (N m+1 ) after performing a read operation, to improve the estimation accuracy.

[0082] The degradation rate of the target page can be divided into a plurality of steps, and for each step, the reference number of existing error bits can vary. For example, the read level calculation unit 201 can refer to the number of error bits (N Figure 10 When the change rate of the number of error bits (S) is greater than or equal to a first threshold change rate (S th1 ), the degradation rate of the target page can be classified as a first step. In this case, the read level calculation unit 201 can refer to three recent numbers of error bits (N m , N m-1 , and N m-2 ) to estimate the number of error bits (N m+1 ) after performing a read operation. When the change rate of the number of error bits (S) is greater than or equal to a second threshold change rate (S th2 ) and less than the first threshold change rate (S th) can be classified as the second level. In this case, the read level calculation unit 201 can refer to two most recent error bit counts (N m and N m-1 ) to estimate an error bit count (N m+1 ) after performing a read operation. When a change rate (S) of the error bit count is less than a second threshold change rate (S th2 ), a degradation rate of the target page can be classified as the third level. In this case, the read level calculation unit 201 can refer to a most recent error bit count (N m ) to estimate an error bit count (N m+1 ) after performing a read operation.

[0083] In an exemplary embodiment of the inventive concept, the read level calculation unit 201 can vary the reference number of the existing error bit count according to a likelihood of an occurrence of an Uncorrectable ECC (UECC) of the target page.

[0084] For example, with reference to FIG. 4, when the most recent error bit count (N m ) is greater than or equal to a predetermined threshold (N th ), the likelihood of the occurrence of the UECC of the target page is relatively high. In this case, in order to more accurately adjust the read voltage, the read level calculation unit 201 can use two or more recent error bit counts (N m and N m-1 ) to estimate an error bit count (N m+1 ) after performing a read operation.

[0085] For example, with reference to FIG. 4, when the most recent error bit count (N m ) is less than a predetermined threshold (N th ), the likelihood of the occurrence of the UECC of the target page is relatively low. In this case, in order to more quickly adjust the read voltage, the read level calculation unit 201 can use the most recent error bit count (N m ) to estimate an error bit count (N m+1 ) after performing a read operation.

[0086] The likelihood of the occurrence of the UECC of the target page can be divided into a plurality of levels, and for each level, the reference number of the existing error bit count can vary. For example, with reference to FIG. 4, when the most recent error bit count (N m ) is greater than or equal to a first threshold (N th1 ), the likelihood of the occurrence of the UECC of the target page is relatively high. In this case, in order to more accurately adjust the read voltage, the read level calculation unit 201 can use two or more recent error bit counts (N m and N m-1 ) to estimate an error bit count (N m ) after performing a read operation.When the probability of a UECC occurring on the target page is considered to be Level 1, the read level calculation unit 201 can refer to the three most recent bit error counts (N). m N m-1 and N m -2) to estimate the number of bit errors (N) after performing the read operation. m+1 When the most recent number of erroneous bits (N) m ) is greater than or equal to the second threshold (N) th2 And less than the first threshold (N) th1 When the probability of a UECC occurring on the target page is considered, it can be classified as Level 2. In this case, the read level calculation unit 201 can refer to the two most recent bit error counts (N). m and N m-1 To estimate the number of bit errors (N) after performing a read operation. m+1 Furthermore, when the most recent number of erroneous bits (N) m ) less than the second threshold (N) th2 When the target page has a UECC error, the probability of UECC occurrence can be classified as Level 3. In this case, the read level calculation unit 201 can refer to the most recent bit error count (N). m To estimate the number of bit errors (N) after performing a read operation. m+1 ).

[0087] The read level calculation unit 201 can use lookup table 203 to calculate the read voltage of the target page from the number of error bits. For example, the read level calculation unit 201 can use the mapping information between error bit information and read voltage correction values ​​stored in lookup table 203 to calculate the read voltage of the target page. An example of lookup table 203 can be found in... Figures 13A to 13C The same as shown.

[0088] Figures 13A to 13C This is a view illustrating an exemplary lookup table according to a concept conceived in this invention. Figure 14A and Figure 14B This is a graph illustrating the linear polynomial operation for estimating the number of bit errors according to an exemplary embodiment of the present invention.

[0089] refer to Figure 13A According to an exemplary embodiment of the present invention, the lookup table 203A can store the number of bit errors (N) that occur when performing a read operation on the target page for each group of degradation levels. m+1 ) and read the voltage correction value (ΔV) READ Mapping information between () and (). In this case, the read level calculation unit 201 can refer to lookup table 203A to obtain the estimated number of bit errors (N) in the target page. m+1 Obtain the read voltage correction value (ΔV)READ ).

[0090] For example, when the target page belongs to the first group of degradation levels and the estimated number of bit errors (N) in the target page. m+1 When the value is 10, the read level calculation unit 201 can refer to the lookup table 203A to calculate the read voltage (V) of the target page. READ Adjust -0.125V. Additionally, when the target page belongs to the second group of degradation levels and the estimated number of bit errors (N) in the target page... m+1 When the value is 40, the read level calculation unit 201 can refer to the lookup table 203A to calculate the read voltage (V) of the target page. READ Adjust to -0.25V.

[0091] Groups whose degradation level can be preset based on the number of bit errors, as shown in the reference above. Figure 6 As described above, pages with 40 or more bit errors and less than 80 bit errors can be classified into a first group with relatively low degradation. Pages with 80 or more bit errors and less than 120 bit errors can be classified into a second group with relatively moderate degradation. Furthermore, pages with 120 or more bit errors can be classified into a third group with relatively high degradation. Since the above is merely illustrative, the classification criteria for degradation groups can be set differently based on the storage capacity of the memory device, system policies, etc.

[0092] In an exemplary embodiment of the present invention, when the mapping information of the target page cannot be obtained from the lookup table 203A, the read level calculation unit 201 can use at least one piece of degradation information that can be obtained from the lookup table 203A and the read voltage correction value (ΔV) mapped thereto. READ To calculate the reading voltage (V) READ For example, when the read level calculation unit 201 does not find the estimated number of error bits (N) in the target page in the lookup table 203A. m+1 When looking up the mapping information in table 203A, the closest value to the estimated number of bit errors (N) in the target page is used. m+1 The two mapping information can be used to calculate the read voltage (V) READ ).

[0093] exist Figure 13A In the example, when the target page belongs to the first group of degradation levels and the estimated number of bit errors (N) in the target page m+1 When the value is 170, the read level calculation unit 201 can be used in 80 error bits (N) m+1 Reading voltage correction value (ΔV) under the condition of ) READ ) and in 120 error bits (N m+1read voltage correction value (ΔV READ ) in the case of 170 error bits (N m+1 ) to calculate a read voltage correction value (ΔV READ ) in the case of 100 error bits (N Figure 14A ).

[0094] In the example of Figure 13A , when the target page belongs to the first group of degradation levels and the estimated number of error bits (N m+1 ) in the target page is 100, the read level calculation unit 201 can perform a linear polynomial operation using a read voltage correction value (ΔV m+1 ) in the case of 80 error bits (N READ ) and a read voltage correction value (ΔV m+1 ) in the case of 120 error bits (N READ ) to calculate a read voltage correction value (ΔV m+1 ) in the case of 100 error bits (N READ ). This example is shown in Figure 14B .

[0095] Next, referring to Figure 13B , the lookup table 203B according to exemplary embodiments of the inventive concept can store mapping information between an increase in the number of error bits (ΔN = N m+1 - N m ) occurring when a read operation is performed on a target page and a read voltage correction value (ΔV READ ) for each group of degradation levels. In this case, the read level calculation unit 201 can obtain a read voltage correction value (ΔV READ ) from an increase in the number of error bits (ΔN) in the target page with reference to the lookup table 203B. For example, when the target page belongs to the first group of degradation levels and the estimated increase in the number of error bits (ΔN) in the target page is 30, the read level calculation unit 201 can adjust the read voltage (V READ ) of the target page by -0.05 V with reference to the lookup table 203B. Also, when the target page belongs to the second group of degradation levels and the estimated increase in the number of error bits (ΔN) in the target page is 20, the read level calculation unit 201 can adjust the read voltage (V READ ) of the target page by -0.03 V with reference to the lookup table 203B.

[0096] When mapping information of the target page cannot be obtained from the lookup table 203B, as described above with reference to Figure 13A , Figure 14A and Figure 14BThe read level calculation unit 201 can calculate the read voltage (V READ ) using at least one piece of degradation information and a read voltage correction value (ΔV READ ) mapped thereto, which can be obtained from the lookup table 203B. For example, the read level calculation unit 201 can perform a linear polynomial operation using two pieces of mapping information closest to an increase (ΔN) in the estimated number of error bits in the mapping information of the lookup table 203B to calculate the read voltage (V READ ).

[0097] Referring to Figure 13C , the lookup table 203C according to an exemplary embodiment of the inventive concept can store mapping information between group information on the number of error bits (N m+1 ) occurring when a read operation is performed on a target page and a read voltage correction value (ΔV READ ) for each group of the degree of degradation. In a different manner from the lookup table 203A of Figure 13A , the lookup table 203C of Figure 13C may group the number of error bits (N m+1 ) into predetermined ranges, and can store mapping information in which the read voltage correction value (ΔV READ ) is mapped to the plurality of groups accordingly.

[0098] In this case, the read level calculation unit 201 can obtain the read voltage correction value (ΔV READ ) from the estimated number of error bits (N m+1 ) in the target page with reference to the lookup table 203C. For example, when the target page belongs to the first group of the degree of degradation and the estimated number of error bits (N m+1 ) in the target page is 40, the number of error bits (N m+1 ) in the target page can belong to the A1 group. In this case, the read level calculation unit 201 can adjust the read voltage (V READ ) of the target page by -0.4 V. Further, when the target page belongs to the second group of the degree of degradation and the estimated number of error bits (N m+1 ) in the target page is 60, the number of error bits (N m+1 ) in the target page can belong to the B2 group. In this case, the read level calculation unit 201 can adjust the read voltage (V READ ) of the target page by -0.5 V

[0099] The storage device 10A according to an exemplary embodiment of the present inventive concept can store the degradation information of the memory cells included in the first memory device 110A in the second memory device 120A which can be accessed in bytes and has a relatively fast access speed, and calculate a read voltage of the first memory device 110A using the degradation information to prevent an increase in a write amplification factor (WAF) due to frequent read recovery operations. Also, the storage device 10A can calculate an optimal read voltage using the degradation information of each page stored in the second memory device 120A to prevent read failures. Hereinafter, a method of operating the storage device 10A according to an exemplary embodiment of the present inventive concept will be described with reference to Figure 15A and Figure 15B a method of operating the storage device according to an exemplary embodiment of the present inventive concept.

[0100] Figure 15A and Figure 15B are views showing a method of operating the storage device according to an exemplary embodiment of the present inventive concept. Figure 7

[0101] First, with reference to Figure 15A , the controller 200A can transfer a first read command and an address signal of a first read operation to the first memory device 110A (S111). In an exemplary embodiment of the present inventive concept, the first read operation can be a patrol read operation which is run in the background to acquire information about the number of error bits of the first memory device 110A.

[0102] The first memory device 110A can perform the first read operation in response to the first read command of the first read operation, and then can transfer read data to the controller 200A corresponding to the first read command (S112).

[0103] The controller 200A can perform an ECC decoding operation on the read data, and can detect the number of error bits included in the read data (S113). Thereafter, the controller 200A can transfer the number of error bits detected in the read data as a result of the ECC decoding operation to the second memory device 120A (S114). The second memory device 120A can set a group of the degree of degradation of the page based on the number of error bits in the read data, and can store the number of error bits together with information about the group of the degree of degradation as the degradation information of the first memory device 110A (S115). In an exemplary embodiment of the present inventive concept, the degradation information stored in the second memory device 120A can include information about the temperature of the first memory device 110A, information about the P / E cycle of the first memory device 110A, information about the interval between the erase state and the program state of the first memory device 110A, etc. in addition to the number of error bits of the first memory device 110A. ​

[0104] Next, referring to Figure 15B , the controller 200A can receive a request for a second read operation from the host (S121). The second read operation can be a read operation for data stored in the first memory device 110A.

[0105] The controller 200A can transmit a command for the second read operation of the degradation information to the second memory device 120A to set a read voltage for the second read operation (S122). In response thereto, the second memory device 120A can transmit the existing number of error bits used to perform the second read operation in the target page and the information about the group of degradation degrees to the controller 200A (S123).

[0106] The controller 200A can calculate a second read voltage suitable for performing the second read operation on the target page using the degradation information (S124). For example, the controller 200A can estimate the number of error bits likely to occur when the second read operation is performed on the target page using the degradation information. The controller 200A can calculate the second read voltage using the estimated number of error bits.

[0107] The controller 200A can transmit a command and an address signal for the second read operation to the first memory device 110A using the calculated second read voltage (S125). In response thereto, the first memory device 110A can perform the second read operation to transmit read data to the controller 200A (S126).

[0108] When the number of error bits estimated by the controller 200A exceeds a predetermined threshold value, the controller 200A can perform a read recovery operation to run a defense code. In an example embodiment of the inventive concept, when the first memory device 110A is a multi-level cell (MLC), the predetermined threshold value can be preset to a value greater than 100 and less than 160.

[0109] Figure 16 is a view illustrating a storage device according to an example embodiment of the inventive concept.

[0110] Referring to Figure 16 , a storage device 10B according to an example embodiment of the inventive concept can include a memory device 100B and a controller 200B.

[0111] The memory device 100B can include a first memory device 110B storing data requested by a host, and a second memory device 120B storing degradation information of the first memory device 110B. The first memory device 110B can include a single layer cell (SLC) storing one bit of data, and a multi layer cell (MLC) storing two or more bits of data. In an exemplary embodiment of the inventive concept, the first memory device 110B can include a quad layer cell (QLC) capable of storing four or more bits of data in a single memory cell.

[0112] In an exemplary embodiment of the inventive concept, the second memory device 120B can be a memory device having a different programming and reading operation unit from the first memory device 110B, and can include a resistive memory device such as PRAM, RRAM, MRAM, etc. Further, in an exemplary embodiment of the inventive concept, the second memory device 120B can be a memory device having a faster access speed than the first memory device 110B, and can include a next generation memory device such as Z-NAND flash memory.

[0113] The second memory device 120B can include a degradation information storage unit 123 for storing degradation information of the first memory device 110B. In an exemplary embodiment of the inventive concept, the degradation information stored in the second memory device 120B can include a number of error bits of the first memory device 110B, information about a temperature of the first memory device 110B, information about a P / E cycle of the first memory device 110B, information about an interval between an erase state and a program state of the first memory device 110B, etc. Specific examples of the degradation information storage unit 123 can be as described above with reference to Figure 8 .

[0114] The second memory device 120B can further include a read voltage controller RC for adjusting a read voltage of a target page using the degradation information of the first memory device 110B.

[0115] The read voltage controller RC can include a read level calculation unit 121 and a lookup table 122.

[0116] The read level calculation unit 121 can receive existing degradation information from the degradation information storage unit 123, and can estimate new degradation information that can occur in a target page when a read operation is performed using the existing degradation information. In an exemplary embodiment of the inventive concept, the read level calculation unit 121 can change a reference number of an existing number of error bits for estimating a number of error bits according to a degradation rate of a target page on which a read operation is to be performed. For example, as described above with reference to Figure 9AAs described above with reference to FIG. 2, when the degradation rate of the current page is relatively slow, the most recent number of error bits can be used to estimate the number of error bits. For example, the read level calculation unit 121 can estimate the number of error bits using the most recent number of error bits and the number of error bits of the previous page. Figure 9B As described above with reference to FIG. 2, when the degradation rate of the current page is relatively slow, the most recent number of error bits can be used to estimate the number of error bits. For example, the read level calculation unit 121 can estimate the number of error bits using the most recent number of error bits and the number of error bits of the previous page.

[0117] The read level calculation unit 121 can use the estimated number of error bits to refer to the lookup table 122 to calculate a read voltage suitable for the read operation. Particular examples of the lookup table 122 can be substantially the same as described above with reference to FIG. 2. Figures 13A to 13C

[0118] Figure 17 is a view illustrating a method of operating a storage device according to an example embodiment of the inventive concept. Figure 16

[0119] Referring to Figure 17 , the controller 200B can receive a request for a second read operation from the host (S221). The second read operation can be a read operation on data stored in the first memory device 110B.

[0120] The controller 200B can request the second memory device 120B to calculate a second read voltage to perform the second read operation requested by the host (S222). In response thereto, the second memory device 120B can calculate the second read voltage using the existing number of error bits and information about the group of the degree of degradation in the target page on which the second read operation is to be performed (S223). For example, the second memory device 120B can estimate the number of error bits likely to occur when the second read operation is performed on the target page using the received degradation information. The second memory device 120B can use the estimated number of error bits to refer to a lookup table to calculate the second read voltage.

[0121] The second memory device 120B can transfer the calculated second read voltage to the controller 200B (S224). Thereafter, when the controller 200B transfers a command and an address signal of the second read operation to the first memory device 110B according to the received second read voltage (S225), in response thereto, the first memory device 110B can transfer read data corresponding to the second read operation to the controller 200B (S226). The received second read voltage can be transferred together with the command and the address signal of the second read operation (e.g., a second read command).

[0122] ​​When the number of erroneous bits estimated by the second memory device 120B exceeds a predetermined threshold, the controller 200B can enter a defense code through a read retry operation. In an exemplary embodiment of the inventive concept, when the first memory device 110B is a multi-level cell (MLC), the predetermined threshold can be preset to a value greater than 100 and less than 160.

[0123] Figure 18 is a view illustrating a storage device according to an exemplary embodiment of the inventive concept.

[0124] Referring to Figure 18 A storage device 10C according to an exemplary embodiment of the inventive concept can include a memory device 100C and a controller 200C.

[0125] The memory device 100C can include a first memory device 110C storing data requested by a host, and a second memory device 120C storing degradation information of the first memory device 110C. The first memory device 110C can include a single-level cell (SLC) storing one bit of data, and a multi-level cell (MLC) storing two or more bits of data. In an exemplary embodiment of the inventive concept, the first memory device 110C can include a quad-level cell (QLC) capable of storing four or more bits of data in a single memory cell.

[0126] In an exemplary embodiment of the inventive concept, the second memory device 120C can be a memory device having a different programming and reading operation unit from the first memory device 110C, and can include a resistive memory device such as PRAM, RRAM, MRAM, etc. Further, in an exemplary embodiment of the inventive concept, the second memory device 120C can be a memory device having a faster access speed than the first memory device 110C, and can include a next-generation memory device such as Z-NAND flash memory.

[0127] The second memory device 120C can include a degradation information storage unit 123 for storing degradation information of the first memory device 110C. In an exemplary embodiment of the inventive concept, the degradation information stored in the second memory device 120B can include a number of erroneous bits of the first memory device 110C obtained according to a patrol read operation, information about a temperature of the first memory device 110C, information about a P / E cycle of the first memory device 110C, information about an interval between an erase state and a program state of the first memory device 110C, etc.

[0128] The first memory device 110C can include a read voltage controller RC for adjusting a read voltage of a target page using the degradation information.

[0129] The read voltage controller RC can include a read level calculation unit 114 and a lookup table 112.

[0130] The read level calculation unit 114 can receive existing degradation information from the degradation information storage unit 123, and can estimate new degradation information that can occur in a target page at the time of performing a read operation using the existing degradation information. In an exemplary embodiment of the inventive concept, the read level calculation unit 114 can change a reference number of an existing number of error bits used to estimate the number of error bits according to a degradation rate of a target page on which a read operation is to be performed.

[0131] The read level calculation unit 114 can use the estimated number of error bits to refer to the lookup table 112 to calculate a read voltage suitable for a read operation.

[0132] Figure 19 is a view illustrating a method of a storage device according to an exemplary embodiment of the inventive concept. Figure 18

[0133] Referring to Figure 19 , the controller 200C can receive a request for a second read operation from the host (S321). The second read operation can be a read operation for data stored in the first memory device 110C.

[0134] The controller 200C can transmit a command for a second read operation of degradation information to the second memory device 120C to perform the second read operation requested by the host (S322). In response thereto, the second memory device 120C can transmit information on an existing number of error bits in a target page for performing the second read operation and a group regarding a degree of degradation to the controller 200C (S323).

[0135] The controller 200C can transmit the degradation information received from the second memory device 120C to the first memory device 110C together with a command and an address signal for a second read operation of the target page (S324). In response thereto, the first memory device 110C can calculate a second read voltage of the target page using the received degradation information (S325). The first memory device 110C can perform a second read operation on the target page using the calculated second read voltage, and as a result, can transmit read data to the controller 200C (S326).

[0136] ​When the number of estimated bit errors by the first memory device 110C exceeds a predetermined threshold, the controller 200C can enter a defense code through a read retry operation. In an exemplary embodiment of the inventive concept, when the first memory device 110C is a multi-level cell (MLC), the predetermined threshold can be preset to a value greater than 100 and less than 160.

[0137] Figure 20 is a block diagram schematically illustrating an electronic device including a storage device according to an exemplary embodiment of the inventive concept.

[0138] The electronic device 700 according to an exemplary embodiment of the inventive concept can include a display 710, a communication unit 720, a storage device 730, a processor 740, an input / output unit 750, and / or the like. The components such as the display 710, the communication unit 720, the storage device 730, the processor 740, the input / output unit 750, and / or the like can communicate with each other through a bus 760. The electronic device 700 can further include a power supply unit, a port, and / or the like, in addition to the above-described components.

[0139] The processor 740 can perform a specific operation, a command, a task, and / or the like. The processor 740 can be a central processing unit (CPU), a microprocessor unit (MCU), an application processor (AP), and / or the like, and can communicate with other components such as the display 710, the storage device 730, the input / output unit 750, and / or the like through the bus 760.

[0140] The storage device 730 included in the electronic device 700 can include a storage device according to an exemplary embodiment of the inventive concept. For example, the storage device 730 can operate according to the exemplary embodiments described with reference to Figures 1 to 19 For example, the storage device 730 can have a hybrid structure including different types of first and second memory devices. The storage device 730 can store and manage various degradation information of the first memory device in the second memory device which can be accessed in byte units and has a relatively fast access speed. When there is a read request for the first memory device, the storage device 730 can calculate an optimal read voltage with reference to the degradation information stored in the second memory device, and then can perform a read operation on the first memory device using the calculated optimal read voltage.

[0141] The storage device according to an exemplary embodiment of the inventive concept can calculate an optimal read voltage using degradation information of a memory device to prevent occurrence of a read failure.

[0142] The storage device according to exemplary embodiments of the present inventive concept can have a hybrid structure in which heterogeneous memory devices are combined to efficiently control a level of a read voltage.

[0143] While the present inventive concept has been illustrated and described with reference to exemplary embodiments, it will be apparent to those of ordinary skill in the art that modifications and variations can be made thereto in form and detail without departing from the spirit and scope of the present inventive concept, as set forth in the appended claims.

Claims

1. A storage device, comprising: a first memory device including a plurality of memory blocks and a plurality of pages included in each of the plurality of memory blocks; a second memory device configured to store first degradation information of the first memory device; and a controller configured to perform a first read operation on the first memory device using a first read voltage to acquire the first degradation information, and perform a second read operation on the first memory device using a second read voltage, wherein the second read voltage is calculated using second degradation information of the first memory device, the second degradation information is estimated using the first degradation information, and each of the first degradation information and the second degradation information includes a number of error bits of each of the plurality of pages, wherein the controller is configured to change an amount of the number of error bits used to calculate the second degradation information based on an increasing rate of the number of error bits included in the first degradation information, such that when a first increasing rate is greater than a second increasing rate, a greater number of error bits is used to calculate the second degradation information for the first increasing rate than for the second increasing rate. the controller is configured to change the amount of the number of error bits used to calculate the second degradation information based on a likelihood of an occurrence of an uncorrectable error correction code (UECC) present in a target page among the plurality of pages in which the second read operation is performed.

2. The storage device of claim 1, wherein, the second memory device includes a resistive memory device, wherein the resistive memory device has a smaller data processing unit than a data processing unit of the first memory device.

3. The storage device of claim 1, wherein, the controller is configured to calculate the second read voltage using a lookup table in which mapping information between the second degradation information and a read voltage correction value is stored.

4. The storage device of claim 1, wherein, each of the first degradation information and the second degradation information further includes degradation level group information indicating a degradation level of each of the plurality of pages.

5. The storage device of claim 1, wherein, the degradation level of each of the plurality of pages is classified into a plurality of levels according to the number of error bits generated in each of the plurality of pages.

6. The storage device of claim 5, wherein, the second memory device includes:

7. The storage device of claim 1, wherein, first and second word lines extending in a first direction and spaced apart from each other in a third direction perpendicular to the first direction; a bit line disposed between the first and second word lines and extending in a second direction perpendicular to the first and third directions; a first memory cell disposed between the first word line and the bit line; and a second memory cell disposed between the bit line and the second word line, wherein each of the first and second memory cells includes: first, second, and third electrodes; a storage element layer disposed between the first and second electrodes and configured to store different data according to a resistance value of the storage element layer; and a selection element layer disposed between the second and third electrodes and including a bidirectional threshold switching (OTS) material. a period for performing the first read operation is set based on at least one of an increasing rate of the number of error bits, a capacity of the first memory device, or a program / erase (P / E) cycle.

8. The storage device of claim 1, wherein, 9.A storage device, comprising: ​ a first memory device configured to store data requested by a host; a second memory device configured to store first degradation information of the first memory device in a page unit; and a controller configured to perform a first read operation on the first memory device using a first read voltage, and acquire the first degradation information, wherein the second memory device estimates second degradation information of the first memory device based on the first degradation information, and calculates a second read voltage based on the second degradation information, wherein the second read voltage is used to perform a second read operation on the first memory device according to a request of the host, wherein the controller is configured to change an amount of error bits used to calculate the second degradation information based on a possibility that an uncorrectable error correction code (UECC) exists in a target page in which the second read operation is performed among a plurality of pages, so that when a first UECC occurrence possibility is greater than a second UECC occurrence possibility, more error bits are used to calculate the second degradation information for the first UECC occurrence possibility than for the second UECC occurrence possibility.

10. The storage device of claim 9, wherein, The second read voltage is less than the first read voltage.

11. The storage device of claim 9, wherein, The second memory device calculates the second read voltage using a lookup table in which mapping information between the second degradation information and a read voltage correction value is stored.

12. The storage device of claim 9, wherein, Each of the first degradation information and the second degradation information includes an error bit number of the first memory device.

13. The storage device of claim 12, wherein, The controller is configured to perform a read recovery operation on the first memory device when the error bit number of the first memory device included in the second degradation information exceeds a predetermined threshold.

14. The storage device of claim 13, wherein, When the first memory device is a multi-level cell (MLC), the predetermined threshold is greater than 100 and less than 160.

15. A memory device, comprising: a first memory device configured to store data requested by a host; a second memory device configured to store first degradation information of the first memory device; and a controller configured to detect an error bit number generated by a first read operation on the first memory device as the first degradation information, wherein the first memory device estimates second degradation information of the first memory device based on the first degradation information in response to a request for a second read operation from the host, and performs the second read operation using a read voltage calculated based on the second degradation information, and a program unit of the second memory device is different from a program unit of the first memory device, wherein the second degradation information includes a result of comparing an error bit number of a target page with a predetermined threshold, wherein the first memory device estimates the error bit number generated by the second read operation using the error bit number stored at least once in the second memory device based on the result.

16. The storage device of claim 15, wherein, The second degradation information includes an amount of change in the error bit number of the target page.

17. The storage device of claim 15, wherein, When the error bit number of the target page is greater than or equal to the predetermined threshold, the first memory device estimates the error bit number generated by the second read operation using error bit numbers stored at two or more most recent times in the second memory device.

18. The storage device of claim 15, wherein, When the error bits of the target page are less than the predetermined threshold, the first memory device estimates the error bits generated by the second read operation using the error bits at the most recent time in the second memory device.

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