Ordered sets for high-speed interconnects

Abstract

A system and apparatus may include a port for transmitting data; and a link coupled to the port. The port may include a physical layer device (PHY) for decoding a physical layer packet, which is received through the link. The physical layer packet may include a first bit sequence corresponding to a first ordered set and a second bit sequence corresponding to a second ordered set, the first bit sequence being adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which may occur after a flow control unit (flit). The first ordered set includes eight bytes and the second ordered set includes eight bytes. In an embodiment, bit errors in an ordered set may be determined by checking the received bits against expected bits of the ordered set interval.

Description

[0001] This application is a divisional application of the patent application with the same name with application number 202010230757.5 filed on March 27, 2020.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application Serial No. 62 / 846,913, filed on May 13, 2019, the entire contents of which are incorporated herein by reference. Background Art

[0004] An ordered set is a physical layer grouping that interconnected link partners can use for various control functions. For example, ordered sets can be used for link training, power management, flow control, and other physical layer functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An embodiment of a block diagram of a computing system including a multi-core processor is shown.

[0006] Figure 2A is a schematic diagram of an interconnected system including two retimers according to an embodiment of the present disclosure.

[0007] Figure 2B is a schematic diagram of a connection system showing an in-band upstream port and retimer configuration according to an embodiment of the present disclosure.

[0008] Figure 3A is a schematic diagram illustrating an example electrical idle ordered-set according to an embodiment of the present disclosure.

[0009] Figure 3B is a schematic diagram illustrating an exemplary electrical idle exit ordered set according to an embodiment of the present disclosure.

[0010] Figure 3C is a schematic diagram illustrating an example skip ordered set according to an embodiment of the present disclosure.

[0011] Figure 4 is a process flow diagram for processing ordered sets according to an embodiment of the present disclosure.

[0012] Figure 5 is a schematic diagram illustrating an example start data stream ordered set according to an embodiment of the present disclosure.

[0013] Fig. 6A is a diagram illustrating an example ordered set for waking up from a low power state according to an embodiment of the present disclosure.

[0014] Figure 6Bis a process flow diagram for processing an ordered set for waking up from a low power state according to an embodiment of the present disclosure.

[0015] Figure 7 An embodiment of a computing system including an interconnect architecture is shown.

[0016] Figure 8 An embodiment of an interconnect architecture including a layered stack is shown.

[0017] Fig. 9 Embodiments of requests or packets to be generated or received within an interconnect fabric are shown.

[0018] Fig.10 An embodiment of a transmitter and receiver pair for an interconnect architecture is shown.

[0019] Fig.11 Another embodiment of a block diagram of a computing system including a processor is shown.

[0020] Fig.12 An embodiment of a block for a computing system including multiple processor sockets is shown.

[0021] Fig.13 An exemplary flow control unit (flit) definition with a per-lane FEC scheme for a x4 PCIe link is shown.

[0022] Fig.14 An exemplary flit definition with a per-lane FEC scheme for x8 and x2 PCIe links is shown.

[0023] Fig.15 A table showing flit characteristics with exemplary flit definitions for each lane FEC scheme for various PCIe link widths is shown.

[0024] Figures 16A-16C Exemplary flit grouping sequences according to various placement rules are shown.

[0025] Fig.17 Table showing PCIe 5.0 TLP efficiency.

[0026] Fig.18A is a schematic diagram of an example protocol stack pair implemented in a transceiver device pair according to an embodiment of the present disclosure.

[0027] Fig.18B is a schematic diagram of an example logic PHY including logic elements for encoding and decoding ordered sets according to an embodiment of the present disclosure.

[0028] The drawings are not drawn to scale. DETAILED DESCRIPTION

[0029] In the following description, many specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details need not be employed to implement the present disclosure. In other instances, in order to avoid unnecessarily obscuring the present disclosure, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / code for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-off and gating techniques / logic, and other specific operational details of computer systems are not described in detail.

[0030] Although the following embodiments may be described with reference to energy conservation and energy efficiency in a particular integrated circuit, such as in a computing platform or microprocessor, other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that can also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or ultrabooks. TM . And can also be used in other devices such as handheld devices, tablet computers, other thin laptops, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations described below. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but can also involve software optimization for energy conservation and efficiency. As will become apparent in the following description, embodiments of the methods, apparatus, and systems described herein (whether with reference to hardware, firmware, software, or a combination thereof) are critical to a "green technology" future balanced with performance considerations.

[0031] As computing systems evolve, the components therein become more complex. As a result, the complexity of the interconnect architectures that couple and communicate between components is also increasing to ensure that bandwidth requirements for optimal component operation are met. In addition, different market segments require different aspects of the interconnect architecture to meet market demands. For example, servers require higher performance, while the mobile ecosystem sometimes sacrifices overall performance to save power. However, the sole purpose of most fabrics is to provide the highest performance and maximum power savings. Below, a number of interconnects are discussed that would potentially benefit from the various aspects of the present disclosure described herein.

[0032] refer to Figure 1 , shows an embodiment of a block diagram of a computing system including a multi-core processor. Processor 100 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SOC), or other device that executes code. In one embodiment, processor 100 includes at least two cores - core 101 and core 102, which may include an asymmetric core or a symmetric core (illustrated embodiment). However, processor 100 may include any number of processing elements that may be symmetric or asymmetric.

[0033] In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include: thread units, thread slots, threads, process units, contexts, context units, logical processors, hardware threads, cores, and / or any other element capable of maintaining the state of a processor (such as an execution state or an architectural state). In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code (such as a software thread, an operating system, an application, or other code). A physical processor (or processor socket) generally refers to an integrated circuit, potentially including any number of other processing elements such as cores or hardware threads.

[0034] A core generally refers to logic located on an integrated circuit capable of maintaining an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. Unlike a core, a hardware thread generally refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states share access to execution resources. It can be seen that the line between the nomenclature of hardware threads and cores overlaps when some resources are shared and others are dedicated to an architectural state. More generally, cores and hardware threads are viewed by an operating system as separate logical processors, where the operating system can schedule operations on each logical processor separately.

[0035] like Figure 1As shown, physical processor 100 includes two cores - cores 101 and 102. Here, cores 101 and 102 are considered to be symmetric cores, i.e., cores with the same configuration, functional units and / or logic. In another embodiment, core 101 includes an out-of-order processor core, and core 102 includes an in-order processor core. However, cores 101 and 102 can be selected separately from any type of core, such as a native core, a software-managed core, a core suitable for executing a native instruction set architecture (ISA), a core suitable for executing a conversion instruction set architecture (ISA), a co-designed core, or other known cores. In a heterogeneous core environment (i.e., an asymmetric core), some form of conversion (e.g., binary conversion) can be utilized to schedule or execute code on one or both cores. However, for further discussion, the functional units shown in core 101 are described in further detail below, because the units in core 102 operate in a similar manner in the depicted embodiment.

[0036] As shown, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Therefore, in one embodiment, a software entity such as an operating system may potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As described above, a first thread is associated with architecture state register 101a, a second thread is associated with architecture state register 101b, a third thread may be associated with architecture state register 102a, and a fourth thread may be associated with architecture state register 102b. Here, each architecture state register (101a, 101b, 102a and 102b) may be referred to as a processing element, thread slot or thread unit, as described above. As shown, architecture state register 101a is replicated in architecture state register 101b, so that each architecture state / context can be stored for logical processor 101a and logical processor 101b. Other smaller resources may also be replicated for threads 101a and 101b in core 101, such as instruction pointers and renaming logic in allocator and renamer block 130. Some resources may be shared through partitioning, such as reorder buffers, ILTB 120, load / store buffers, and queues in reorder / retirement unit 135. Other resources, such as general internal registers, page table base registers, low-level data caches and data TLB 115, execution units 140, and portions of out-of-order unit 135 are potentially fully shared.

[0037] Processor 100 typically includes other resources, which may be fully shared, shared through partitioning, or dedicated to a processing element / pair of processing elements. Figure 1, an embodiment of a purely exemplary processor with illustrative logic units / resources of the processor is shown. Note that the processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not shown. As shown, core 101 includes a simplified, representative out-of-order (OOO) processor core. However, an in-order processor may be used in different embodiments. The OOO core includes a branch target buffer 120 for predicting branches to be executed / taken and an instruction translation buffer (I-TLB) 120 for storing address translation entries for instructions.

[0038] The core 101 also includes a decode module 125, which is coupled to the acquisition unit 120 to decode the acquired elements. In one embodiment, the acquisition logic includes individual sequencers associated with the thread slots 101a, 101b, respectively. Typically, the core 101 is associated with a first ISA, which defines / specifies instructions that can be executed on the processor 100. Machine code instructions that are typically part of the first ISA include a portion of the instruction (called an opcode) that references / specifies the instruction or operation to be performed. The decode logic 125 includes circuits that recognize these instructions from their opcodes and pass the decoded instructions in the pipeline for processing defined by the first ISA. For example, as discussed in more detail below, in one embodiment, the decoder 125 includes logic designed or adapted to recognize specific instructions, such as transaction instructions. As a result of the decoder 125 recognition, the architecture or core 101 takes specific predefined actions to perform tasks associated with the appropriate instructions. It is important to note that any task, block, operation, and method described herein can be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note that in one embodiment, decoders 126 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 126 recognize a second ISA (a subset of the first ISA or a different ISA).

[0039] In one example, the allocator and renamer block 130 includes an allocator for reserving resources, such as a register file for storing instruction processing results. However, threads 101a and 101b are potentially capable of out-of-order execution, where the allocator and renamer block 130 also reserves other resources, such as a reorder buffer that tracks instruction results. Unit 130 may also include a register renamer to rename program / instruction reference registers to other registers internal to processor 100. Reorder / retirement unit 135 includes components, such as the reorder buffers, load buffers, and store buffers mentioned above, to support out-of-order execution and later orderly retirement of instructions executed out-of-order.

[0040] In one embodiment, the scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations on the execution units. For example, floating point instructions are scheduled on the port of the execution unit with an available floating point execution unit. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0041] A lower level data cache and data translation buffer (D-TLB) 150 is coupled to the execution unit 140. The data cache is used to store recently used / operated elements, such as data operands, which are potentially saved in a memory consistency state. The D-TLB is used to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure to divide the physical memory into multiple virtual pages.

[0042] Here, cores 101 and 102 share access to a higher or further level cache, such as a second level cache associated with on-chip interface 110. Note that higher or further levels refer to cache levels increasing or further away from the execution unit. In one embodiment, the higher level cache is a last level data cache - the last cache in the memory hierarchy on processor 100, such as a second or third level data cache. However, the higher level cache is not limited to this, as it may be associated with or include an instruction cache. A trace cache is a type of instruction cache that may be coupled after decoder 125 to store recently decoded traces. Here, instructions potentially relate to macroinstructions (i.e., general instructions recognized by the decoder), which may be decoded into multiple microinstructions (micro-operations).

[0043] In the depicted configuration, the processor 100 also includes an on-chip interface module 110. Historically, a memory controller, described in more detail below, has been included in a computing system external to the processor 100. In this case, the on-chip interface 110 is used to communicate with devices external to the processor 100, such as system memory 175, a chipset (typically including a memory controller hub connected to the memory 175 and an I / O controller hub for connecting peripheral devices), a memory controller hub, a north bridge, or other integrated circuits. And in this case, the bus 105 may include any known interconnect, such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

[0044] Memory 175 may be dedicated to processor 100 or shared with other devices in the system. Common examples of memory 175 types include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 180 may include a graphics accelerator, a processor or card coupled to a memory controller hub, a data storage device coupled to an I / O controller hub, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

[0045] However, recently, as more logic and devices are integrated on a single die such as a SOC, each of these devices can be incorporated on the processor 100. For example, in one embodiment, a memory controller hub is on the same package and / or die as the processor 100. Here, a portion of the core (on-core portion) 110 includes one or more controllers for interfacing with other devices such as memory 175 or a graphics device 180. This configuration including interconnects and controllers for interfacing with these devices is generally referred to as an on-core (or uncore configuration). As an example, the on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. However, in a SOC environment, even more devices, such as network interfaces, coprocessors, memory 175, graphics processors 180, and any other known computer devices / interfaces can be integrated on a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0046] In one embodiment, processor 100 can execute compiler, optimizer and / or converter code 177 to compile, convert and / or optimize application code 176 to support the apparatus and method described herein or interface with it. Compiler generally includes a program or assembly that converts source text / code into target text / code. Generally, using a compiler to compile program / application code is done in multiple stages and multiple passes to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compilers can still be used for simple compilation. Compiler can utilize any known compilation technology and perform any known compiler operation, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion and code optimization.

[0047] Larger compilers typically include multiple phases, but most often these phases are included in two general phases: (1) the front end, which is where syntactic processing, semantic processing, and some transformations / optimizations may typically occur, and (2) the back end, which is where analysis, transformations, optimizations, and code generation may typically occur. Some compilers reference an intermediate portion, which illustrates the blurring depicted between the front end and back end of the compiler. As a result, references to the insertion, association, generation, or other operations of the compiler may occur in any of the above phases or passes, as well as any other known phase or pass of the compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, and the like, at one or more phases of compilation, such as inserting calls / operations at the front end phase of compilation and then transforming the calls / operations to lower level code at the transformation phase. Note that during dynamic compilation, compiler code or dynamically optimized code may insert such operations / calls, as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (compiled code) may be dynamically optimized during runtime. Here, program code may include dynamically optimized code, binary code, or a combination thereof.

[0048] The following detailed description refers to the accompanying drawings. The same reference numerals may be used to identify the same or similar elements in different figures. In the following description, specific details, such as specific structures, architectures, interfaces, technologies, etc., are set forth for the purpose of explanation rather than limitation, so as to provide a thorough understanding of various aspects of various embodiments. However, it will be apparent to those skilled in the art who benefit from this disclosure that various aspects of various embodiments can be practiced in other examples that depart from these specific details. In some cases, descriptions of well-known devices, circuits, and methods are omitted to avoid making the description of various embodiments unclear without unnecessary details.

[0049] Figure 2A 2 is a schematic diagram and timing diagram illustrating an example topology 200 with two retimers 204 and 206 between an upstream component downstream port 202 and a downstream component upstream port 208 according to an embodiment of the present disclosure. The upstream component downstream port 202 may be a port for a PCIe-based device, such as a CPU or other device capable of generating data packets and transmitting the data packets over a data link that complies with the PCIe protocol. The downstream component upstream port 208 may be a port of a peripheral component that can receive data packets from a link that complies with the PCIe protocol. It should be understood that the upstream component downstream port 202 and the downstream component upstream port 208 may send and receive data packets across PCIe links (illustrated as PCIe links 210a-c).

[0050] The topology 200 may include one or more retimers 204 and 206. The retimers 204 and 206 may be used as signal repeaters operating at the physical layer to fine-tune signals from the upstream component 202 and / or the downstream component upstream port 208. The retimers may use continuous time linear equalization (CTLE), decision feedback equalization (DFE), and transmit impulse response equalization (TxFIR EQ or just TxEQ). The retimers are transparent to the data link and transaction layers, but implement a complete physical layer.

[0051] The multi-lane PCIe link is divided into three link segments (LS) 210a, 210b, and 210c in each direction. The upstream component downstream port 202 can be coupled to the retimer 1 204 through the multi-lane PCIe link 210a. The retimer 1 204 can be coupled to the retimer 2 206 through the link segment 210b. And the retimer 2 206 can be coupled to the downstream component upstream port 208 through the link segment 210c.

[0052] Components may also be coupled via sideband links. Upstream component downstream port 202 may be coupled to retimer 1 204 via sideband link 212a. Retimer 1 204 may be coupled to retimer 2 206 via sideband link 212b. And retimer 2 206 may be coupled to downstream component upstream port 208 via sideband link 212c.

[0053] The primary function of a retimer (buffer) device is signal retiming. These functions are performed by retimers 204 and 206. The specific retimer device circuitry will depend on the PHY used for the link. Typically, the retimer circuit is configured to recover the incoming signal and retransmit it using a local clock and new transmit equalization circuitry, and well-known circuits such as phase-locked loops may generally be employed for this purpose. The retimer may further include transmitter and receiver circuitry including one or more amplifier circuits, and various types of well-known signal conditioning circuitry for increasing the drive level of the received signal. Such retimer circuitry is well known to those skilled in the art of high-speed interconnects, and therefore, further details are not shown or discussed herein.

[0054] Each retimer 204 and 206 can have an upstream path and a downstream path. In some embodiments, the retimer can include two pseudo ports, and the pseudo ports can dynamically determine their respective downstream / upstream orientations. In addition, the retimers 204 and 206 can support operating modes including forwarding mode and execution mode. In some cases, the retimers 204 and 206 can decode data received on a sublink and re-encode data forwarded downstream on another sublink thereof. In this way, the retimer can capture the received bit stream before regenerating and resending the bit stream to another device or even another retimer (or redriver or repeater). In some cases, the retimer can modify certain values ​​in the data it receives, such as when processing and forwarding ordered set data. In addition, the retimer can potentially support any width option as its maximum width, such as a set of width options defined by a specification (e.g., PCIe).

[0055] As data rates of serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, the use of retimers to extend channel reach is increasing. Multiple timers can be cascaded to achieve longer channel reach. As can be expected, as signal speeds increase, channel reach generally decreases. Therefore, as interconnect technologies accelerate, the use of retimers can become more prevalent. For example, as PCIe Gen 4 is adopted at 16GT / s to support PCIe Gen 3 (8GT / s), the use of retimers can increase in PCIe interconnects, and the same is true for other interconnects as speeds increase.

[0056] In one implementation, a generic BGA (ball grid array) package may be defined for PCI Express Gen 4 (16GT / s) based retimers. Such a design may address at least some of the example deficiencies found in legacy PCIe Gen 3 (8GT / s) retimer devices, as well as some of the issues that arise with the adoption of PCIe Gen 4. Additionally, the number and volume of retimer vendors is expected to increase with PCIe Gen 4. Due to signal losses at double the data rate (from 8GT / s to 16GT / s), the achievable interconnect lengths in Gen 4 are significantly reduced. In this and other example interconnect technologies, retimers may therefore have greater utility as data rates increase, as they may be used to significantly increase channel lengths that would otherwise be limited by the increased data rates.

[0057] Although the retimer is shown as separate from the upstream and downstream components, the retimer may be part of the upstream or downstream components, on a board with the upstream or downstream components, or on a package with the downstream components.

[0058] The upstream component downstream port 202 may access a storage element 222, such as a flash memory, cache, or other memory device. Retimer 1 204 may optionally include a similar storage element 224. Retimer 2 206 may optionally include a similar storage element 226. The downstream component upstream port 208 may optionally include a similar storage element 228.

[0059] Figure 2B is a schematic diagram of a system 250 showing the connection of an in-band upstream port and a retimer configuration according to an embodiment of the present disclosure. Figure 2A As shown, the upstream component downstream port 202 can be coupled to the downstream component upstream port 208 by the link 210a-c extended by the two retimers 204, 206. In this example, the downstream port 202 can be provided with a retimer configuration register address / data register 252 to save the data to be sent to one of the two retimers in the configuration access command using the field of the enhanced SKP OS. One or more bits of the SKP OS can include a command code, data, or address for the configuration register (e.g., 256, 258, respectively) of the retimer (e.g., 204, 206, respectively) to read or write data from the register 256, 258 to the register 256, 258. The retimer can respond to the configuration access command sent by encoding the data in the instance of the enhanced SKP OS by encoding the response data in the subsequent instance of the enhanced SKP OS itself. The data encoded by the retimer (e.g., 204, 206) can be extracted at the downstream port and recorded in the retimer configuration data return register (e.g., 254). Registers (e.g., 252, 254) maintained at the upstream device downstream port 202 may be read and written by system software and / or other components of the system, allowing (indirect) access to the retimer registers: one register (e.g., 252) conveys the address / data / command to the retimer, and a second register (e.g., 254) stores the response returned from the retimer. In other embodiments, in other examples, such registers (e.g., 260) may be maintained at the downstream component upstream port 208 instead of or in addition to maintaining registers at the upstream component downstream port 202.

[0060] continue Figure 2BIn an example, in conjunction with a mechanism for providing in-band access to retimer registers, the retimer may have constructed registers that are addressable with well-defined bits and characteristics. In this example, an enhanced SKP OS is defined / modified as a periodic pattern generated by the physical layer to pass commands / information from "Retimer Configuration Register Address / Data" (e.g., 252) to the retimer and pass responses from the retimer back to be loaded into "Retimer Configuration Data Return" (e.g., 254), and some bits are allocated for CRC to protect the data. For example, in PCIe, this may include enhancing existing SKP ordered sets (e.g., using CSR access and CSR return (CRC protected bits)). In addition, a process may be defined to ensure that commands / information are guaranteed to be passed to the retimer and corresponding responses are returned. The physical layer mechanism may be enhanced to also include notifications from the retimer (in addition to the response) if a certain service is required, and other example functions may also be included.

[0061] PCIe Gen 6 and later can use pulse amplitude modulation (PAM-4) with forward error correction (FEC) to operate at 64GT / s with an effective bit error rate (BER) within the acceptable range for data streams. FEC and flits of data blocks are typically used for normal operation when the link is in the active (L0) power state.

[0062] However, ordered sets (OS) cannot be protected by the same FEC mechanism because many, if not most, OSes are not scrambled. For example, the Electrical Idle Exit Ordered Set (EIEOS) is used to reset the scrambler, provide a low frequency pattern and obtain block alignment. Therefore, the EIEOS is not scrambled and should not be changed using error correction code (ECC) bits. The length of the Skip Ordered Set (SKP OS) can vary because the retimer can add or remove SKP OSes. Therefore, it is challenging to cover all ordered sets using FEC, and each OS has its own unique set of requirements and lengths. The present disclosure describes an error protection mechanism for ordered sets in high BER interconnect links, such as links based on PCIe Gen 6 or above protocols, while retaining the characteristics and functionality associated with each ordered set.

[0063] In the present disclosure, the physical layer device may divide the 128b OS into two 64-b (8B) parts or chunks. Replication is used with CRC / parity protection to improve reliability and availability.

[0064] Ordered sets fall into two broad categories, each with a different approach to dealing with high raw BER:

[0065] An ordered set such as TS1 / TS2 is considered good if one 8B chunk is good and each sequence is independently protected by CRC.

[0066] Ordered sets sent after the data stream, such as SKP OS (create or remove delay between link partners), EIEOS (retrain), EIOS (low power state), require two 8B blocks to be good to be considered a good OS. Therefore, each 8B block has its own built-in redundancy to improve its effective BER.

[0067] Control SKP ordered set payloads (e.g. parity and margin command / status fields) will be sent in a predetermined flit instead of the data link layer payload to avoid aliasing in the ordered sets due to high raw BER in the link.

[0068] The techniques and devices described herein result in preserving the existing PCIe ordered set mechanism while providing reliability and availability at the high BER expected in Gen6.

[0069] The present disclosure defines each ordered set (OS) as a block of 128 bits (16 bytes). Each 128-bit OS block includes two 64-bit (8B) blocks or parts. This allocation is done to handle fault models where the length of each burst is <= 16. If the burst length is longer, the same principle is applied by making the ordered set longer. For example, if the burst length is less than or equal to 32, each OS can be 256 bits, including two 128-bit blocks. Table 1 illustrates the effective bit error rate (BER) achieved using the OS allocation.

[0070] Table 1. Effective bit error rates (BER) obtained using OS allocation.

[0071]

[0072]

[0073] Each OS falls into two broad categories; each uses a different approach to handling high raw BER using two 8B chunks:

[0074] An ordered set like TS1 / TS2 is considered good if any of the 8B chunks are good and each TSB is protected by CRC.

[0075] Ordered sets sent after the data stream (e.g., SKP OS, EIEOS, EIOS) require two 8B chunks to be considered a good OS. However, each 8B chunk has its own built-in redundancy to improve its effective BER.

[0076] These duplications across two 8B chunks or within each 8B chunk help the OS have the same effective error probability of 1.3E-10 in most cases, as shown in Table 1 below. In some cases (e.g., the original BER of TS1 / TS2 is 1E-4), this number is insufficient. These issues can be addressed by duplication between ordered sets (e.g., sending 24 TS2 ordered sets instead of 16 TS2 ordered sets in PCIe Gen 1-5).

[0077] In the present disclosure, a synchronization header is not used to distinguish between the OS (128b) and the data block. Instead, a SKP ordered set is sent at a fixed interval. After the data stream is started, the SKP ordered set will continue at this fixed interval. However, if the link needs to transition from the active state (L0) to the recovery state, the SKP OS can be replaced by the electrical idle exit ordered set (EIEOS); if the link needs to transition to a low power state (e.g., L0) or from L0 to L1, the SKP OS can be replaced by the electrical idle exit ordered set (EIOS). Therefore, when in the data stream, the receiver can be configured to recognize one of the following 3 OS within a specific interval: SKPOS, EIEOS or EIOS. In this 16B aligned block, assuming that the burst length should be corrected, the receiver can distinguish between one of the three OS.

[0078] Figure 3A is a diagram illustrating an exemplary electrical idle ordered set (EIOS) 300 according to an embodiment of the present disclosure. The EIOS 300 is shown as 16 bytes (or two 8-byte portions 302 and 304). Redundancy is also shown, where each 8B portion is repeated. Figure 3B is a schematic diagram illustrating an exemplary electrical exit ordered set 310 according to an embodiment of the present disclosure. EIEOS 310 is shown as 16 bytes (or two 8-byte portions 312 and 314). Redundancy is also shown, where each 8B portion is repeated.

[0079] Figure 3C is a diagram illustrating an example skip-ordered set 320 according to an embodiment of the present disclosure. Figure 3C SKP OS 322 is shown as an 8B portion, along with other SKP OS portions 324. In an embodiment, a 24-48B SKP OS may be used. SKP_END OS 326 may represent the end of the SKP OS, which may also be divided into 8B portions. A PHY payload 328 may be scheduled after the SKP_END OS 326. The PHY payload may also be replicated in a similar manner to other OSes for redundancy. That is, the PHY payload may be divided into two 8-byte portions, each of which carries the same information.

[0080] Figure 3A –C illustrates example encodings of three ordered sets that may be received immediately following a data block at the planned SKP OS interval. EIEOS 300 is selected to preserve the 1 GHz low frequency content. The EIOS and SKP OS are selected so that there is a reasonable Hamming distance between the 4B aligned encodings between EIOS 300, EIEOS 310, and SKP / SKP_END OS 320, as shown in Table 2 below. Those skilled in the art will recognize that this will prevent any aliasing of burst errors <= 16. The values ​​shown in Table 2 and the corresponding Hamming distances can be used as expected values ​​that can be compared to the received OS. One or both of the received redundant OSs can be checked based on the expected value of the determined OS type and whether the received OS contains errors.

[0081] Table 2. Encoding differences between various OS.

[0082]

[0083]

[0084] Figure 4 is a process flow diagram 400 for processing ordered sets according to an embodiment of the present disclosure. The process flow diagram 400 demonstrates the techniques described herein for identifying appropriate ordered sets and taking appropriate actions even in the presence of errors.

[0085] In this disclosure, as described later, SKP ordered sets arrive at the receiver at regular intervals. During data flow 402, if the received data is outside the SKP OS interval 404, the receiver skips checking for OS 406.

[0086] During the data stream 402, at an interval 404 where an OS (e.g., SKP OS) is expected, the receiver distinguishes between three OSs that may appear at that location. The receiver checks for 5 of the 8 bytes that match the corresponding byte positions (408), (410). This check ensures that any errors that affect up to 3 bytes (bursts of length <= 16 will affect up to 3 bytes) can be corrected and matched. If no match is found, it means more errors and the link enters recovery to retrain the link (412). If 5 of the 8 bytes match (410), the receiver can determine the OS type between SKP OS, EIOS, and EIEOS (414). Receipt of EIOS indicates that the link will enter a low power state (L0, L1) after the next 8 bytes (428). Receipt of EIEOS will cause the link to recover (412).

[0087] If the receiver receives a SKP OS (416) after reading the first 8B, the receiver will continue to check for the next 8 bytes of SKP or SKP_END (418). If 5 of the 8 bytes match the expected SKP_END OS, it indicates data flow after the 8 bytes of PHY payload at the end of SKPOS. The PHY payload can be processed (422) and the receiver returns to check for OS (404) during the scheduled OS interval.

[0088] The length of the received SKP OS can be 24, 32, 40, 48, or 56 bytes. Therefore, if the receiver continues to receive SKP OS, this check (for SKP or SKP_END) can be performed up to 5 times. If at least 5 of the 8 bytes match the SKP OS (424), the receiver can check that the number of received 8B SKP OS does not exceed 5. If the number of 8B SKPOS is greater than or equal to 6 (more than 5), the link can enter the recovery state (412). If at least 5 of the 8 bytes do not match the SKP OS (424), the link enters the recovery state (412). If no SKP or SKP_END OS is found, or if 5 "SKP to SKP_END OS" checks have been performed and the receiver has been receiving a continuous stream of SKP OS, the link will enter the recovery state because it indicates an uncorrectable error.

[0089] If the number of SKP or SKP_END is not more than 5, the receiver can read the next 8B (418) and then continue checking for SKP OS or SKP_END OS from there.

[0090] In the present disclosure, SKP OS are inserted at fixed intervals. This is selected so that it is aligned with the flow control unit (flit) boundary. During data flow, SKP OS can be inserted at the flit boundary or into the ongoing TLP spanning two (or more) flits.

[0091] Each retimer can insert or remove two SKPs (i.e. 8 bytes). The SKP OS sent by the port can be 40 bytes, but when received by the port, the SKP OS can be 24, 32, 40, 48, or 56 bytes. Since 8 bytes are added or removed in each port / pseudo-port, the SKP OS insertion interval can be twice as long as PCIe Gen3-5 (i.e. 740 blocks for SRNS or Common Clock and 74 blocks for SRIS, where 1 block = 16 bytes per channel).

[0092] In Gen4 and Gen5 data rates, the control SKP ordered set is used for payload, such as parity and margin command / status fields. In Gen3 to Gen5 data rates, the SKP OS carries parity information to identify the erroneous lane segment and the LFSR (Linear Feedback Shift Register) value for that lane. The control SKP OS and SKP OS alternate at Gen4 and Gen5 data rates. Given that burst errors are expected in high BER links, the technique described in this article appends this information to the last 8 bytes of the SKP OS interval with replication, as shown in Table 3.

[0093] Table 3. PHY layer payload at the end of SKP OS.

[0094]

[0095] Although one type of SKP OS is used, the payload alternates between a linear feedback shift register (LFSR) sequence and margin command / status, similar to Gen4 and Gen5. The Payload Type field indicates what type of payload is being sent and is replicated 4 times. Similarly, the port parity reflects the even parity of all bits in the flit from the SDS OS or the previous SKP OS (whichever is earlier) to the flit before the current SKP OS, and 2 bits reflecting the parity calculation of each retimer are sent 4 times. The payload type is replicated 4 times, along with the three parity bits. A majority vote is taken on all of these 4-bit vectors to determine which one is correct. The LFSR and its corresponding even parity are sent twice and compared to deploy the correct LFSR. The margin payload is sent twice along with the margin CRC / parity. If one of the two copies passes its parity and CRC check, it will be used as the valid copy.

[0096] Link (re)training is handled via TS1 / TS2 ordered sets, with EIEOS sent once every 32 TS1 / TS2 ordered sets. Link (re)training is performed in the "recovery" and "configuration" states. If the link is in electrical idle before entering recovery, EIEOS is used to wake up the link partner. The present disclosure sends 4 back-to-back EIEOS in a repeating pattern, followed by 32 TS1 ordered sets. 4 back-to-back EIEOS are sent to ensure that the low frequency mode (0.5GHz) is maintained for 8ns to allow the link partner's exit electrical idle (EI) detection circuit to fluctuate. Once the link partner wakes up, it can be demonstrated by recording the exit EI signal (and the optional process of establishing bit lock) that the link can send one EIEOS every 32 TS1 / TS2 ordered sets to minimize the link (re)training time. TS1 / TS2 ordered sets carry a large number of information bits. However, not all information bits are required in all states. Since the link has a higher BER, the proposed invention divides each TS1 / TS2 ordered set (16 symbols, each symbol is one byte) into two identical halves, as shown in Table 4 below. Symbol 0 (and 8) is the TS1 identifier, unscrambled. Information bits that do not need to overlap in each state are sent on the same symbol. For example, "link number" and "channel number" are meaningful in states such as "configuration" but not in "recovery". Equalization information (represented as EQ bytes 0-3) is only useful in the recovery state (and mainly in the Recovery.EQ substate), so they are sent during these states. Therefore, symbols 1 and 2EQ bytes are in the recovery state, but carry the link number / channel number in other states, as shown in Table 4 below. This helps to send related information more frequently within the same number of bytes to effectively correct errors. Every 7 bytes are protected by an 8-bit CRC sent in symbol 8 / 15. It should be noted that since the same symbol is 8 bytes apart, burst errors <= 64 bits will not affect the copy. TS1 / TS2, EIEOS and SKP OS are the only OS that can coexist during (re)training.

[0097] Table 4. TS1 / TS2 ordered sets.

[0098]

[0099] Figure 5 500 is a schematic diagram illustrating an example start data stream ordered set 500 according to an embodiment of the present disclosure. The start data stream (SDS) OS provides a marker before the start of the data stream. The SDS OS indicates the end of TS2. Therefore, the start of the SDS OS also indicates the end of the TS2 OS. The built-in redundancy of the SDS OS is represented by 8B portion 502 and 8B portion 504.

[0100] Fig. 6Ais a diagram illustrating an example ordered set for waking up from a low power state according to an embodiment of the present disclosure. Figure 6B is a flowchart of a process for processing an ordered set to wake up from a low power state according to an embodiment of the present disclosure. The receiver may be in a low power state (e.g., L0 state) (652). When exiting from a low power state, the techniques described herein follow Fig. 6A –B. First, the initial 4 EIEOS cause the link partner's receiver to wake up from a low power state (654). Subsequently, N fast training sequences (FST) enable the receiver to achieve bit lock (656). In some embodiments, TS1 / TS2 OS can be used instead of N FST. Then, EIEOS (1-4 OS) can be used to achieve block alignment (658). After block alignment, the SKP OS sequence (40 bytes) can be used to establish the SKP interval (660) and perform channel-to-channel offset correction (662). The SKP / SKP_END OS uses 5 good bytes in an 8-byte alignment boundary for verification, and the SDS is accepted as long as at least four good E1_87_87_87 (4B) sets in a 4B alignment boundary are received on a 32-byte SDS (such as Figure 4 The SDS may also be used to establish channel-to-channel deskew.

[0101] This disclosure describes the following rules for built-in error correction with reliability during training:

[0102] As long as symbols 0–7 or symbols 8–15 pass the CRC / parity check, the received TS1 / TS2 is considered valid. If both sets pass the CRC / parity check but do not match each other, the set that matches the previous TS1 / TS2 (if any) is considered valid. If there is no previous TS1 / TS2 and both sets do not match, we can accept one of them as a valid TS1 / TS2.

[0103] Before decrypting a TS1 / TS2 ordered set, an EIEOS may be used to obtain block alignment. If a subsequent EIEOS is on a different boundary, the block boundary is updated.

[0104] SKP OS may be received and a strict initial check may be done to match all bytes of SKP and SKP_END (instead of 5 out of 8 bytes matching). Before sending a TS2 ordered set, a SKPOS interval may be established using at least two SKP OS.

[0105] Before starting the data stream, two back-to-back SDSs may be sent, neither of which should overlap with the start position of SKPOS on the transmitter.

[0106] An SDS is considered "received" on an aligned 128b (16B) boundary if:

[0107] 1) SDS is not the starting point of SKP OS;

[0108] 2) According to the LTSSM rules, the receiver has received the mandatory number of TS2s.

[0109] 3) The receiver has received four good E1_87_87_87 (4B) sets, at least two of which are in odd 4B-aligned positions (i.e. bytes 0-3, 8-11). (This third rule ensures that the receiver checks directly for the fixed TS2 unscrambled bytes; EIEOS does this naturally because it is unscrambled in all bytes, similar to SDS.)

[0110] The receiver can receive two SDSs back-to-back to start receiving the data stream.

[0111] Even though the present disclosure is described in the context of PCIe Gen 6, those skilled in the art will recognize that the concepts are applicable to other interconnects (e.g., future generations of multi-lane links such as coherence / storage links, USB, etc.) if an OS is used.

[0112] One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. The primary goal of PCIe is to enable components and devices from different vendors to interoperate in an open architecture across multiple market segments; clients (desktop and mobile), servers (standard and enterprise editions), and embedded and communications devices. PCI Express is a high-performance, general-purpose I / O interconnect defined for a variety of future computing and communications platforms. Certain PCI attributes, such as its usage model, load-store architecture, and software interface, have been retained through its revisions, while the previous parallel bus implementation has been replaced by a highly scalable, fully serial interface. The latest versions of PCI Express leverage advances in point-to-point interconnects, switch-based technology, and packet protocols to provide higher levels of performance and functionality. Power management, quality of service (QoS), hot-swap / hot-plug support, data integrity, and error handling are some of the advanced features supported by PCI Express.

[0113] refer to Figure 7, shows an embodiment of a structure consisting of point-to-point links interconnecting a set of components. System 700 includes a processor 705 and a system memory 710 coupled to a controller hub 715. Processor 705 includes any processing element, such as a microprocessor, a main processor, an embedded processor, a coprocessor, or other processor. Processor 705 is coupled to controller hub 715 via a front-end bus (FSB) 706. In one embodiment, FSB 706 is a serial point-to-point interconnect as described below. In another embodiment, link 706 includes a serial differential interconnect architecture that conforms to different interconnect standards.

[0114] System memory 710 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 700. System memory 710 is coupled to controller hub 715 through memory interface 716. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0115] In one embodiment, controller hub 715 is a root center, root complex or root controller in a peripheral component interconnect express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub 715 include chipsets, memory controller hubs (MCH), north bridges, interconnect controller hubs (ICH), south bridges, and root port controllers / centers. The term chipset generally refers to two physically separated controller hubs, i.e., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems generally include an MCH integrated with processor 705, and controller 715 will communicate with I / O devices in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported by root complex 715.

[0116] Here, controller hub 715 is coupled to switch / bridge 720 via serial link 719. Input / output modules 717 and 721, which may also be referred to as interfaces / ports 717 and 721, include / implement a layered protocol stack to provide communication between controller hub 715 and switch 720. In one embodiment, multiple devices can be coupled to switch 720.

[0117] Switch / bridge 720 routes packets / messages from device 725 from upstream (i.e., upward toward the hierarchy of the root complex) to controller hub 715, and routes downstream from processor 705 or system memory 710 to device 725 toward the hierarchy away from the root port controller. In one embodiment, switch 720 is referred to as a logical component of multiple virtual PCI-PCI bridge devices. Device 725 includes any internal or external device or component to be coupled to an electronic system, such as I / O device, network interface controller (NIC), add-on card, audio processor, network processor, hardware driver, storage device, CD / DVD ROM, monitor, printer, mouse, keyboard, router, portable storage device, Firewire device, universal serial bus (USB) device, scanner and other input / output devices. In PCIe local devices (e.g., devices), it is usually referred to as endpoints. Although not specifically shown, device 725 can include a bridge from PCIe to PCI / PCI-X to support traditional or other versions of PCI devices. Endpoint devices in PCIe are generally classified as legacy, PCIe, or root complex endpoints.

[0118] The graphics accelerator 730 is also coupled to the controller hub 715 via a serial link 732. In one embodiment, the graphics accelerator 730 is coupled to the MCH, which is coupled to the ICH. The switch 720 and the I / O device 725 are then coupled to the ICH. The I / O modules 731 and 718 are also used to implement a layered protocol stack to communicate between the graphics accelerator 730 and the controller hub 715. Similar to the MCH discussion above, the graphics controller or graphics accelerator 730 itself can be integrated into the processor 705.

[0119] Go to Figure 8 , Figure 8 An embodiment of a layered protocol stack is shown. The layered protocol stack 700 includes any form of layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the following reference Figure 7-10 The discussion is about the PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, the protocol stack 800 is a PCIe protocol stack, including a transaction layer 805, a link layer 810, and a physical layer 820. Interfaces, such as Figure 7 The interfaces 717, 718, 721, 722, 726 and 731 in the embodiment may be represented as a communication protocol stack 800. The representation as a communication protocol stack may also be referred to as a module or interface that implements / includes the protocol stack.

[0120] PCI Express uses packets to pass information between components. Packets are formed in the transaction layer 805 and the data link layer 810 to transfer information from the sending component to the receiving component. As the sent packets flow through the other layers, they are expanded with additional information required to process the packets at those layers. On the receiving side, the reverse process occurs and the packet is transformed from its physical layer 820 representation to the data link layer 810 representation and finally (for transaction layer packets) into a form that can be processed by the transaction layer 805 of the receiving device.

[0121] Transaction Layer

[0122] In one embodiment, the transaction layer 805 is used to provide an interface between the processing core of the device and the interconnect architecture, such as the data link layer 810 and the physical layer 820. In this regard, the primary responsibility of the transaction layer 805 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). The transaction layer 805 typically manages credit-based flow control of the TLPs. PCIe implements split transactions, i.e., transactions with requests and responses separated by time, allowing the link to carry other traffic while the target device collects response data.

[0123] In addition, PCIe utilizes credit-based flow control. In this scheme, the device advertises an initial amount of credit for each receive buffer in the transaction layer 805. The external device at the opposite end of the link, such as Figure 7 The controller hub 715 in the , calculates the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be sent. After receiving the response, a certain number of credits will be restored. One advantage of the credit scheme is that if the credit limit is not encountered, the delay in credit return will not affect performance.

[0124] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read requests and write requests to transfer data to or from a memory mapped location. In one embodiment, memory space transactions can use two different address formats, such as a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions in the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

[0125] Thus, in one embodiment, the transaction layer 805 assembles the packet header / payload 706. The current format of the packet header / payload can be found in the PCIe specification at the PCIe specification website.

[0126] Quick Reference Fig. 9, shows an embodiment of a PCIe transaction descriptor. In one embodiment, transaction descriptor 900 is a mechanism for carrying transaction information. In this regard, transaction descriptor 900 supports identification of transactions in the system. Other potential uses include tracking modifications to default transaction ordering and association of transactions with channels.

[0127] Transaction descriptor 900 includes a global identifier field 902, an attribute field 904, and a channel identifier field 906. In the illustrated example, global identifier field 902 is depicted as including a local transaction identifier field 908 and a source identifier field 910. In one embodiment, global transaction identifier 902 is unique for all outstanding requests.

[0128] According to one implementation, the local transaction identifier field 908 is a field generated by the requesting agent and is unique to all outstanding requests that need to be completed by the requesting agent. In addition, in this example, the source identifier 910 uniquely identifies the requester agent within the PCIe hierarchy. Therefore, together with the source ID 910, the local transaction identifier 908 field provides a global identification of a transaction within the hierarchy domain.

[0129] Attribute field 904 specifies the characteristics and relationships of a transaction. In this regard, attribute field 904 is potentially used to provide additional information that allows modification of the default processing of a transaction. In one embodiment, attribute field 904 includes priority field 912, reserved field 914, sort field 916, and non-snooping field 918. Here, priority subfield 912 can be modified by the initiator to assign a priority to a transaction. Reserved attribute field 914 is reserved for future or vendor-defined use. Reserved attribute fields can be used to implement possible usage models that use priority or security attributes.

[0130] In this example, the sorting attribute field 916 is used to provide optional information that conveys the type of sorting that can modify the default sorting rules. According to an example implementation, a sorting attribute of "0" indicates that the default sorting rules are to be applied, wherein a sorting attribute of "1" indicates that the sorting is relaxed, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. The snooping attribute field 918 is used to determine whether the transaction is snooped. As shown, the channel ID field 906 identifies the channel associated with the transaction.

[0131] Link Layer

[0132] The link layer 810 (also referred to as the data link layer 810) acts as an intermediate level between the transaction layer 805 and the physical layer 820. In one embodiment, the responsibility of the data link layer 810 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between the two components of the link. One side of the data link layer 210 accepts the TLPs assembled by the transaction layer 805, applies a packet sequence identifier 811, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., a CRC 812, and submits the modified TLP to the physical layer 820 for transmission across the physical to an external device.

[0133] Physical Layer

[0134] In one embodiment, the physical layer 820 includes a logical sub-block 821 and an electronic block 822 to physically send packets to an external device. Here, the logical sub-block 821 is responsible for the "digital" functions of the physical layer 821. In this regard, the logical sub-block includes a transmit portion for preparing outgoing information for transmission by the physical sub-block 822, and a receive portion for identifying and preparing received information before passing it to the link layer 810.

[0135] Physical block 822 includes a transmitter and a receiver. The transmitter is provided with symbols by logic sub-block 821, and the transmitter serializes the symbols and sends them to an external device. The receiver provides serial symbols from an external device and converts the received signal into a bit stream. The bit stream is deserialized and provided to logic sub-block 821. In one embodiment, 8b / 10b transmission code is used, in which 10-bit symbols are sent / received. Here, special symbols are used to frame packets using frame 823. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0136] As described above, although the transaction layer 805, link layer 810, and physical layer 820 are discussed with reference to a specific embodiment of the PCIe protocol stack, the layered protocol stack is not limited thereto. In fact, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for sequencing packets, i.e., a link layer; and a third layer for sending packets, i.e., a physical layer. As a specific example, a common standard interface (CSI) layered protocol is used.

[0137] Next reference Fig.10, an embodiment of a PCIe serial point-to-point structure is shown. Although an embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link is not limited thereto because it includes any transmission path for sending serial data. In the illustrated embodiment, the basic PCIe link includes two low-voltage differential drive signal pairs: a transmit pair 1006 / 1011 and a receive pair 1012 / 1007. Therefore, device 1005 includes a transmission logic 1006 that transmits data to device 1010 and a receive logic 1007 that receives data from device 1010. In other words, two transmit paths, namely paths 1016 and 1017, and two receive paths, namely paths 1018 and 1019, are included in the PCIe link.

[0138] A transmission path refers to any path for transmitting data, such as a transmission line, copper wire, optical fiber, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices (e.g., device 1005 and device 1010) is called a link, such as link 1015. A link can support a channel - each channel represents a set of differential signal pairs (one pair for transmission and one pair for reception). To expand bandwidth, a link can aggregate multiple channels represented by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0139] A differential pair refers to two transmission paths, such as lines 1016 and 1017, for transmitting differential signals. As an example, when line 1016 switches from a low voltage level to a high voltage level, i.e., a rising edge, line 1017 drives from a high logic level to a low logic level, i.e., a falling edge. Differential signals potentially exhibit better electrical characteristics, such as better signal integrity, i.e., cross-coupling, voltage overshoot / undershoot, ringing, etc. This allows for better timing windows, which makes faster transmission frequencies possible.

[0140] Note that the above apparatus, methods, and systems can be implemented in any electronic device or system as described above. As a specific illustration, the following figure provides an exemplary system for utilizing the present disclosure as described herein. As the following system is described in more detail, many different interconnections are disclosed, described, and reconsidered from the above discussion. And it is apparent that the above advances can be applied to any of those interconnections, structures, or architectures.

[0141] Steering Fig.11, shows a block diagram of an exemplary computer system formed by a processor including an execution unit for executing instructions, wherein one or more interconnections implement one or more features according to an embodiment of the present disclosure. System 1100 includes components, such as processor 1102, to employ an execution unit according to the present disclosure, such as in the embodiments described herein, the execution unit including logic for executing an algorithm for processing data. System 1100 represents a PENTIUM III processor based on a processor available from Intel Corporation in Santa Clara, California. TM , PENTIUM 4 TM , Xeon TM , Itanium, XScale TM and / or StrongARM TM The exemplary system 1000 may be a processing system based on a microprocessor, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In one embodiment, the exemplary system 1000 executes WINDOWS 106 available from Microsoft Corporation in Redmond, Washington. TM The system may be a version of an operating system, but other operating systems (eg, UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Therefore, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

[0142] Embodiments are not limited to computer systems. Alternative embodiments of the present disclosure may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), systems on chips, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0143] In the embodiment described herein, the processor 1102 includes one or more execution units 1008 to implement an algorithm that will execute at least one instruction. An embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multi-processor system. System 1100 is an example of a "center" system architecture. Computer system 1100 includes a processor 1102 for processing data signals. As an illustrative example, processor 1102 includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements an instruction set combination, or any other processor device such as a digital signal processor. Processor 1102 is coupled to a processor bus 1110 that transmits data signals between processor 1102 and other components in system 1100. The elements of system 1100 (e.g., graphics accelerator 1112, memory controller hub 1116, memory 1120, I / O controller hub 1124, wireless transceiver 1126, flash BIOS 1128, network controller 1134, audio controller 1136, serial expansion port 1138, I / O controller 1140, etc.) perform their conventional functions, which are well known to those skilled in the art.

[0144] In one embodiment, processor 1102 includes a level 1 (L1) internal cache memory 1104. Depending on the architecture, processor 1102 may have a single internal cache or multiple layers of internal cache. Other embodiments include a combination of both internal and external caches depending on the specific implementation and requirements. Register file 1106 is used to store various types of data in various registers, including integer registers, floating point registers, vector registers, bank registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

[0145] An execution unit 1108, including logic to perform integer and floating point operations, is also located in the processor 1102. In one embodiment, the processor 1102 includes a microcode (ucode) ROM for storing microcode, which, when executed, will perform certain macroinstruction algorithms or handle complex scenarios. Here, the microcode is potentially updateable to handle logic errors / fixes of the processor 1102. For one embodiment, the execution unit 1108 includes logic for processing a packed instruction set 1109. By including the packed instruction set 1109 in the instruction set 1102 of the general-purpose processor along with the associated circuitry to execute the instructions, operations used by many multimedia applications can be performed using packed data in the general-purpose processor 1102. Therefore, many multimedia applications can be accelerated and executed more efficiently by using the full width of the processor's data bus for performing operations on packed data. This potentially eliminates the need to transfer smaller data units on the processor's data bus to perform one or more operations (one data element at a time).

[0146] Alternative embodiments of execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1100 includes memory 1120. Memory 1020 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1120 stores instructions and / or data represented by data signals to be executed by processor 1102.

[0147] Note that any of the foregoing features or aspects of the present disclosure may be Fig.11 1102, a processor bus 1110 (e.g., Intel Quick Path Interconnect (QPI) or other known high performance computing interconnects), a high bandwidth memory path 1118 to a memory 1120, a point-to-point link to a graphics accelerator 1112 (e.g., a Peripheral Component Interconnect Express (PCIe) compatible structure), a controller hub interconnect 1122, an I / O or other interconnect (e.g., USB, PCI, PCIe) for coupling other components shown. Some examples of such components include an audio controller 1136, a firmware hub (flash BIOS) 1128, a wireless transceiver 1126, a data storage device 1124, a legacy I / O controller 1110 including a user input and keyboard interface 1142, a serial expansion port 1138 (e.g., a universal serial bus (USB)), and a network controller 1134. The data storage device 1124 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0148] Reference now Fig.12 , which is a block diagram of a second system 1200 according to an embodiment of the present disclosure. Fig.12 As shown, multiprocessor system 1200 is a point-to-point interconnect system and includes a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. Each of processors 1270 and 1280 can be a certain version of a processor. In one embodiment, 1252 and 1254 are part of a serial point-to-point coherent interconnect structure, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the present disclosure can be implemented within the QPI architecture.

[0149] Although shown with only two processors 1270, 1280, it should be understood that the scope of the present disclosure is not limited in this regard. In other embodiments, one or more additional processors may be present in a given processor.

[0150] The processors 1270 and 1280 shown include integrated memory controller units 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its bus controller unit; similarly, the second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270, 1280 can exchange information via point-to-point (PP) interface 1250 using PP interface circuits 1278, 1288. Fig.12 As shown, IMCs 1272 and 1282 couple the processors to respective memories, namely, memory 1232 and memory 1234, which may be portions of main memory locally connected to the respective processors.

[0151] Processors 1270, 1280 each exchange information with chipset 1290 via respective PP interfaces 1252, 1254 using point-to-point interface circuits 1276, 1294, 1286, 1298. Chipset 1290 also exchanges information with high-performance graphics circuit 1138 via interface circuit 1292 along high-performance graphics interconnect 1239.

[0152] A shared cache (not shown) may be included in the processor or external to both processors; it is then connected to the processors via the PP interconnect so that if the processors are placed in a low power mode, either or both of the processors' local cache information may be stored in the shared cache.

[0153] Chipset 1290 may be coupled to first bus 1216 via interface 1296. In one embodiment, first bus 1216 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, but the scope of the present disclosure is not limited in this regard.

[0154] like Fig.12 As shown, various I / O devices 1214 are coupled to first bus 1216, and a bus bridge 1218 couples first bus 1216 to a second bus 1220. In one embodiment, second bus 1220 comprises a low pin count (LPC) bus. In one embodiment, various devices are coupled to second bus 1220 including, for example, a keyboard and / or mouse 1222, communication devices 1227, and a storage unit 1228 such as a disk drive or other mass storage device, which generally includes instructions / code and data 1230. Additionally, an audio I / O 1224 is shown coupled to second bus 1220. Note that other architectures are possible in which the included components and interconnect architectures vary. For example, instead of Fig.12 Instead of a point-to-point architecture, the system may implement a multi-drop bus or other such architecture.

[0155] Using the various inertial and environmental sensors present in the platform, many different use cases can be realized. These use cases can perform advanced computing operations including perceptual computing, and can also enhance power management / battery life, security, and system responsiveness.

[0156] For example, with respect to power management / battery life issues, ambient light conditions in the location of the platform are determined based at least in part on information from an ambient light sensor, and the intensity of the display is controlled accordingly. Thus, power consumption to operate the display is reduced under certain lighting conditions.

[0157] Regarding security operations, based on contextual information obtained from sensors, such as location information, it can be determined whether to allow a user to access certain security documents. For example, a user can be allowed to access such documents at a workplace or home location. However, when the platform is located in a public place, the user will be prevented from accessing such documents. In one embodiment, the determination is based on location information determined, for example, via a GPS sensor or camera recognition of a landmark. Other security operations may include providing pairing of devices within close proximity of each other, such as a portable platform as described herein and a user's desktop computer, mobile phone, etc. In some embodiments, when these devices are paired in this way, certain sharing is achieved through near field communication. However, when the device exceeds a specific range, such sharing may be disabled. In addition, when the platform as described herein is paired with a smartphone, an alarm can be configured to trigger when the devices move more than a predetermined distance from each other in a public place. On the contrary, when these paired devices are in a safe location, such as a workplace or home location, these devices can exceed the predetermined limit without triggering such an alarm.

[0158] Sensor information can also be used to enhance responsiveness. For example, even when the platform is in a low power state, sensors can still be operated at a relatively low frequency. Thus, any changes in the platform's position, for example, as determined by inertial sensors, GPS sensors, etc., are determined. If such changes are not registered, there will be a delay in the communication with the previous wireless hub (such as Wi-Fi TM A faster connection to an access point or similar wireless enabler) is achieved because there is no need to scan for available wireless network resources in this case. Thus, a higher level of responsiveness when waking up from a low power state is achieved.

[0159] It should be understood that many other use cases can be enabled using sensor information obtained via the integrated sensors within the platform described herein, and the above examples are for illustrative purposes only. Using the system described herein, a perceptual computing system can allow for the addition of alternative input modalities, including gesture recognition, and enable the system to sense user actions and intent.

[0160] In some embodiments, there may be one or more infrared or other thermal sensing elements, or any other element for sensing the presence or motion of a user. Such sensing elements may include multiple different elements that work together, sequentially, or both. For example, the sensing elements include an element that provides initial sensing, such as light or sound projection, followed by gesture detection through, for example, an ultrasonic time-of-flight camera or a pattern light camera sensing.

[0161] Also in some embodiments, the system includes a light generator that generates an illuminated line. In some embodiments, the line provides a visual cue about a virtual boundary (i.e., an imaginary or virtual location in space), where the user's actions of passing through or breaking through the virtual boundary or plane are interpreted as an intent to engage with the computing system. In some embodiments, the illuminated line can change color when the computing system transitions to a different state with respect to the user. The illuminated line can be used to provide a visual cue of a virtual boundary in space to the user, and can be used by the system to determine transitions in computer states with respect to the user, including determining when the user wishes to engage with the computing system.

[0162] In some embodiments, the computer senses the position of the user and operates to interpret the movement of the user's hand through the virtual boundary as a gesture indicating the user's intent to engage with the computer. In some embodiments, as the user passes over the virtual line or plane, the light generated by the light generator may change, thereby providing visual feedback to the user that the user has entered an area for providing gestures to provide input to the computer.

[0163] The display screen may provide a visual indication of a state transition of the computing system for the user.In some embodiments, a first screen is provided in a first state in which the system senses the presence of a user, for example, by using one or more sensing elements.

[0164] In some implementations, the system senses the identity of the user, such as through facial recognition. Here, a transition to the second screen may be provided in a second state, in which the computing system has identified the identity of the user, wherein in the second state the screen provides visual feedback to the user that the user has transitioned to a new state. The transition to the third screen may occur in a third state in which the user has confirmed the identification of the user.

[0165] In some embodiments, the computing system may use a transition mechanism to determine the location of a user's virtual boundary, where the location of the virtual boundary may vary with the user and context. The computing system may generate light, such as an illuminated line, to indicate a virtual boundary for engagement with the system. In some embodiments, the computing system may be in a wait state, and the light may be generated in a first color. The computing system may detect whether the user has reached outside the virtual boundary, for example, by sensing the user's presence and motion using a sensing element.

[0166] In some embodiments, if it has been detected that a user has crossed a virtual boundary (e.g., the user's hand is closer to the computing system than the virtual boundary line), the computing system can transition to a state for receiving gesture input from the user, where a mechanism for indicating the transition can include the light indicating the virtual boundary changing to a second color.

[0167] In some embodiments, the computing system may then determine whether a gesture motion is detected. If a gesture motion is detected, the computing system may proceed with a gesture recognition process, which may include using data from a gesture database that may reside in a memory of the computing device or otherwise be accessible by the computing device.

[0168] If the user's gesture is recognized, the computing system can perform a function in response to the input and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system can transition to an error state, where a mechanism indicating the error state can include a light indicating that the virtual boundary changes to a third color, and if the user is within the virtual boundary to interact with the computing system, the system returns to receive other gestures.

[0169] As described above, in other embodiments, the system can be configured as a convertible tablet computer system that can be used in at least two different modes, namely a tablet computer mode and a laptop computer mode. The convertible system can have two panels, namely a display panel and a base panel, so that in the tablet computer mode, the two panels are arranged on top of each other. In the tablet computer mode, the display panel faces outward and can provide a touch screen function that a traditional tablet computer has. In the laptop mode, the two panels can be arranged in an open clamshell structure.

[0170] In various embodiments, the accelerometer can be a 3-axis accelerometer with a data rate of at least 50 Hz. A gyroscope can also be included, which can be a three-axis gyroscope. In addition, an electronic compass / magnetometer can be present. Moreover, one or more proximity sensors can be provided (for example, for opening a lid to sense when a person is approaching (or not approaching) the system and adjusting power / performance to extend battery life). For sensor fusion functions of certain OS, including accelerometers, gyroscopes, and compasses, enhanced functionality can be provided. In addition, via a sensor center with a real-time clock (RTC), wake-up from the sensor mechanism can be implemented to receive sensor input when the rest of the system is in a low-power state.

[0171] In some embodiments, an internal lid / display open switch or sensor indicates when the lid is closed / open and can be used to put the system into or automatically wake up from Connected Standby. Other system sensors may include ACPI sensors for internal processor, memory, and skin temperature monitoring to change the operating state of the processor and system based on the sensed parameters.

[0172] In one embodiment, the OS may be a "connected standby" 8 OS (also referred to herein as Win8 CS). Windows 8 Connected Standby or other OS with similar states can provide very low ultra-idle power through the platform described herein to enable applications to remain connected at very low power consumption, for example, to cloud-based locations. The platform can support 3 power states, namely, screen on (normal); connected standby (the default "off" state); and off (power consumption is zero watts). Therefore, in the "connected standby" state, the platform is still logically on (at the lowest power level) even though the screen is off. On such a platform, power management can be made transparent to applications and constant connectivity can be maintained, in part by employing offloading techniques to enable the lowest power components to perform operations.

[0173] Fig.13 An exemplary flit definition with a per-lane FEC scheme for a x4 PCIe link is shown. The flit includes one or more TLPs and DLLPs protected by a flit-level CRC scheme and a per-lane FEC scheme. In some embodiments, as will be discussed in more detail below, the flit can be protected by a flit-level FEC scheme. Flit 1300 includes a transaction layer packet symbol 1310, a data link layer packet symbol 1320, a flit-level CRC code symbol 1330, and an FEC symbol 1340. Flit 1300 includes a total of 324 symbols. In some embodiments, the length of the symbol can be 1DW, but in other embodiments, the symbol can be of different lengths. The 324 symbols in flit 1300 include 288 symbols carrying transaction layer packet information (TL0-TL287), 4 symbols carrying data link layer packet information (DLL0-3), 8 flit-level CRC symbols (CRC0-7), and 24 FEC symbols (12 check symbols (C) and 12 parity check symbols (P)). Eight CRC symbols are used to ensure adequate coverage of multiple TL / DPP symbol errors. Information from a single TLP can span multiple TL symbols in a flit. For example, if a symbol is 1DW long, then a flit 1350 will require 8 TL symbols to store a TLP of length 8DW.

[0174] Flit 1300 is transmitted across lanes 1350 (L0-L3). That is, a different portion of flit 1300 is sent on each of the four lanes. Fig.13 Successive TL, DLL, and CRC symbols are shown transmitted along adjacent lanes, but in other embodiments the symbols may be distributed between the lanes in a different manner.

[0175] A flit 1300 may have a flit sequence number, which may be specified explicitly, implicitly, or opportunistically. If specified explicitly, the flit sequence number may be encoded in reserved bits in the flit. If specified implicitly, the flit sequence number is not sent on the link, and the receiver may determine the flit packet number in another manner, for example, by counting received flits. If specified opportunistically, the flit sequence number may be sent as a payload in a DLLP packet that is sent in whole or in part as part of the flit. In one example where the flit sequence number is sent implicitly, the CRC may include the flit sequence number as consecutive bits in the CRC code, for example, during a CRC calculation. Thus, any dropped or replayed flits may be detected at the receiving end.

[0176] In flit 1300, four one-byte symbols (DLL0-3) are allocated for one DLLP. In other embodiments, information from multiple DLLPs may be carried in a single flit. In other embodiments, DLLPs may be constructed on consecutive flits. For example, in a flit format that allocates five DLLP bytes, four DLLP bytes may carry one DLLP, while the fifth DLLP byte from four consecutive flits may contribute an additional DLLP.

[0177] The flit-level CRC code protects the flit contents minus the FEC check and parity symbols. For example, the flit-level CRC code in symbols CRC0-7 in flit 1300 protects the TL, DLL, and CRC symbols in flit 1300. The per-channel FEC scheme protects all symbols transmitted across one channel in the flit. For example, the six FEC check and parity symbols sent along one of channels L0-L3 protect the 81 symbols (324 flit symbols / 4 channels) sent along that channel. The FEC scheme also employs interleaving. The FEC scheme employed in flit 1300 uses three-way interleaving, as indicated by the shading of each symbol. For example, the check and parity symbol 1360, which is not shown with shading, protects the symbols (TL3, TL7, TL11…TL287, CRC3, CRC7, check / parity symbol 1360) that are also not shown with shading transmitted along channel L3. Therefore, in Fig.13 In the FEC scheme shown, two FEC symbols (one check symbol and one parity symbol) are used to protect 27 flit symbols (81 symbols transmitted along the lane L3 / 3-way interleaving). In other embodiments, alternative interleaving schemes (2-way, 4-way, etc.) as FEC schemes with fewer check and parity bits per lane may be used to achieve the desired bit error rate.

[0178] Different flit definitions can be used for different link widths. Fig.14 An exemplary frame definition with a per-lane FEC scheme for x8 and x2 PCIe links is shown. Flit 1400 defines a 648-symbol flit format for a PCIe x8 link. Flit 1400 includes 1400 symbols (TL0-TL599) containing transaction layer packet data, 4 symbols (DLL0-3) containing data link layer packet data, 8 flit-level CRC symbols (CRC0-7), and 48 FEC symbols (24 check symbols and 24 parity symbols). The 648 symbols are transmitted across eight lanes (L0-L7). As in flit 1300, the six FEC check and parity symbols transmitted in one lane use 3-way interleaving to protect 81 symbols (648 symbols / 8 lanes), with each pair of FEC check and parity symbols pairing 27 symbols (81 symbols / 3-way interleaving).

[0179] Flit 1450 is a 324-symbol flit definition for a PCIe x2 link. Flit 1450 contains 300 symbols with transaction layer packet information (TL0-TL299), 4 symbols with data link layer packet information (DLL0-3), eight CRC symbols (CRC0-7), and 12 FEC symbols (6 check symbols and 6 parity symbols). The 324 symbols are transmitted across two lanes (L0-L1). The six FEC check and parity symbols transmitted in each lane use three-way interleaving to protect 162 symbols (324 symbols / 2 lanes), while each pair of FEC check and parity symbols protects 54 symbols (162 symbols / three-way interleaving).

[0180] Flits 1300, 1400, and 1450 illustrate exemplary flit definitions for specific PCIe link widths. Other flit definitions are possible for specific PCIe links. The number of TL and / or DLL symbols may vary from one flit definition to another, as may the number of flit-level CRC symbols used to protect the flit, the number of FEC symbols used to protect the channel, and the degree of interleaving used for the FEC scheme. Increasing the number of flit-level CRC symbols and / or FEC symbols used may reduce BER, but at the expense of increased overhead, and therefore efficiency.

[0181] In some embodiments, a flit definition for a specific link may be defined, determined, or provided by an operating system or BIOS during system startup. The flit definition of a link may be stored in software or firmware local to the system, may be hardware-coded, or may be stored remotely and accessed during system startup. The flit definition of a specific link does not have to be static and may change during system operation. For example, the physical layer, protocol stack, or operating system may receive an updated flit definition for a specific link, and the link may begin using the updated flit definition at some point after receiving the updated flit definition. An updated flit definition may be provided in response to various events. For example, the physical layer may monitor link performance and send a signal to the protocol stack or operating system indicating that the BER of the link is too high, and the system may switch to the following flit definition: a flit-level CRC scheme with more CRC bytes, a per-channel FEC scheme with more check and parity bits per channel, a flit-level FEC scheme with more check and parity bits per flit, or a combination thereof. In another example, the system may determine a greater information throughput while keeping the BER at an acceptable level, and may use a flit definition that provides higher transmission efficiency. In updated flit definitions, higher efficiency can be achieved by increasing the number of TLP / DLLP packet symbols in a flit, or by reducing the number of flit-level CRC symbols and / or the number of FEC check / parity symbols.

[0182] Fig.15 A table of flit characteristics with exemplary flit definitions for each lane of FEC schemes for various PCIe link widths is shown. Table 1500 shows link characteristics for links 1300, 1400, and 1450 for x4, x8, and x2 links, respectively, and possible link-defined flit characteristics for x1 and x16 links. The FEC delays shown are approximate delay times at the recommended transmission speeds for PCIe Gen 6. Narrower links (x1, x2) have higher FEC delays, which can achieve higher efficiency by amortizing the fixed overhead (flit-level CRC symbols and data link layer packet information) as shown. Different flit sizes for a given link width can be selected to trade off latency for increased efficiency.

[0183] Flit-based packet packing can provide at least the following advantages: First, flit-based packet packing eliminates the need to append an LCRC to each TLP because the flit is protected by a CRC scheme at the flit level. Fig.13The flit 1300 in includes TLP data from 288 TLPs and only eight flit-level CRC symbols. If sent over the link using the current PCIe protocol, these 288 TLPs would be accompanied by 288 LCRCs. In other words, a flit does not contain a CRC that is sent with each TLP contained in the flit. Using flit-based packet packaging, link layer retries occur at the flit level. In one embodiment, a failed flit can be retried with a receiver that stores successfully transmitted flits received at the receiver after a damaged or lost flit. In some embodiments, the transmitter can be notified that the transmitted flit was not successfully received by receiving a NAK DLLP containing the sequence number of the flit to be retransmitted. In some embodiments, a retried flit can indicate that it is being retransmitted by encoding "retry flit" in the corresponding DLLP along with the sequence number of the retried flit.

[0184] Second, the flit-based packet packing allows for a guaranteed DLLP frequency policy. In one embodiment, after sending a flit, the transmitter will receive a DLLP acknowledgment packet indicating that the flit was received no later than n flits after being sent. In another embodiment, the receiver will send a DLLP packet to the transmitter providing a credit update no later than m flits after accumulating x number of credits. Such a policy can reduce storage overhead at the receiver relative to current receiver storage requirements, taking into account current PCIe DLLP scheduling policies and having to handle situations such as sending an ACK or NAK DLLP after a maximum payload size TLP.

[0185] Third, since the flit definition provides a guaranteed location for the DLLPs in the flit, the 2-5% variable bandwidth loss due to DLLP scheduling is traded for a fixed bandwidth reduction for a given flit definition. For example, in a x4 flit definition for flit1300, the bandwidth reduction due to DLLP overhead is only 1.2% (1 / 81).

[0186] Fourth, the bandwidth loss due to the addition of framing information added by the physical layer to each TLP is eliminated because the transaction layer packet information is located at a fixed position in the flit and the flit boundaries are known. That is, for each TLP sent as part of a flit, no physical layer framing information is added to the TLP.

[0187] Fifth, because the specific flit format has a defined length, the synchronization header that is periodically sent in the current PCIe protocol can be replaced with a periodic ordered set (OS), such as a SKP OS (skip ordered set), an EIOS (electrical idle ordered set), or an EIEOS (electrical idle exit ordered set). In one embodiment, for a flit with a length of 10.25ns, a periodic OS can be sent every 72 flits with a 600ppm clock extension. Replacing the synchronization header with a periodic OS can reclaim at least a portion of the bandwidth consumed by using the synchronization header. In the current PCIe protocol format, the synchronization header consumes approximately 1.5% of the bandwidth.

[0188] Figures 16A-16C An exemplary flit packet sequence according to various placement rules is shown. The flit definition defines which time slots or fields in the flit can be occupied by TLP or DLLP information, but in some embodiments, placement or packing rules are used to determine where the TLP or DLLP information is to be sent in the flit. Figures 16A-16C A sequence of 48 flit packets transmitted over a link is shown. The packets are sent sequentially from left to right in each row, with the first row sent first and the third row sent last. Each column is 1DW wide, and each group of four columns is 4DW wide.

[0189] Fig.16AThe TLPs placed in the flit are shown according to the rule that TLP header information or TLP payload (data) information can reside only in each aligned 4DW set. Starting from the upper leftmost packet, the first two 4DW sets contain header information 1602 (h0-h3) and payload information 1604 (d0-d3) for the first TLP. The next two 4DW sets contain NULLTLPs 1606 and 1608. The first 4DW set in the second row contains header information 1610 (h0-h2) for the second header-only TLP. Because the header of this second TLP is only 3DW wide, the fourth DW set is filled with IDL packets. Idle packets can be used to fill 4DW sets where the length of the header or payload information of the packet is less than four DWs. Continuing along the second row, the second and third 4DW sets contain header information 1612 (h0-h2) and payload information 1614 (d0) for the third TLP. Because this third TLP has less than 4DWs for header and payload information, the second and third 4DW sets will be filled with IDL packets. The fourth 4DW set in the second row is filled with header information 1616 (h0-h2) and idle packets for the fourth TLP. The payload 1618 (d0-d1) for the fourth TLP is placed in the first two DWs of the third row, followed by two idle packets. The remaining three 4DW sets in the third row include header information 1620 (h0-h2) for the fifth TLP, and header information 1622 (h0-h3) and payload information 1624 (d0-d3) for the sixth TLP. In total, six TLPs are packed into Fig.16A Of the 48 DWs shown.

[0190] Fig. 16B The TLPs and DLLPs placed in a flit are illustrated according to the rule that each aligned 4DW set can contain header and data information from one TLP, where the DLLPs are placed opportunistically. Fig. 16BStarting with the top left packet of , the first two 4DW sets contain header information 1642 (h0-h3) and payload information 1644 (d0-d3) for the first TLP. The third 4DW set contains a NULL TLP 1646, and the fourth 4DW set contains a first DLLP 1648, followed by three IDL packets. Moving to the second row, the first 4DW set contains header information 1650 (h0-h2) for the second TLP, followed by an IDL packet. The second DW contains header information 1652 (h0-h2) and payload information 1653 (d0) for the third TLP. The first three DWs in the third 4DW set in the second row are filled with header information 1654 (h0-h2) for the fourth TLP and an opportunistically placed second DLLP 1655. The fourth DW set in the second row contains payload information 1656 (d0-d1) for the fourth TLP, and the last two DWs contain idle packets. Continuing with the last row, the first 4DW set contains header information 1660 (h0-h2) and an idle packet for the fifth TLP. The second and third 4DW sets contain header information 1662 (h0-h3) and payload information 1664 (d0-d3) for the sixth TLP. The final 4DW set includes header information 1666 (h0-h2) and payload information 1667 (d0) for the seventh TLP. Placed Fig. 16B The first six TLPs in Fig.16A The same TLP placed in Fig. 16B The associated looser packing rules allow the seventh TLP and two DLLPs to be additionally placed in the same 48 DWs.

[0191] Fig. 16C Figure 1 shows TLPs and DLLPs placed in a flit according to the rule that TLP header and payload information can be placed at any DW boundary, with opportunistic DLLP placement. Fig. 16B The same 7 TLPs and 2 DLLPs are placed in the Fig. 16C In the first line of Fig. 16B. Moving to the second row, the first 4DW set contains information from the second and third TLPs: the header 1690 (h0-h2) from the second TLP and the first DW (h0) of the header information 1691 (h0-h2) of the third TLP. The remaining header information (h1-h2) of the third TLP is placed in the first two DWs of the second 4DW set. The header information 1693 (h0-h2) of the fourth DLP is contained in the last DW of the second 4DW set and the first two DWs of the third 4DW set. The payload information 1694 (d0-d1) of the fourth TLP is placed in the second half of the third 4DW set. The last 4DW set of the second row contains the header information 1695 (h0-h2) of the fifth TLP. The header information 1696 (h0-h3) of the sixth DLP fills the last DW of the second row and continues into the first three DWs of the first 4DW set of the third row. The payload information 1697 (d0-d3) of the sixth TLP fills the last DW of the first 4DW set and the first three DWs of the second 4DW set in the third row. The rest of the last row is filled with the header information 1698 (h0-h2) and payload information 1699 (d0) of the seventh TLP, the second DLLP 1681 and header information 1683 (h0-h2) of the eighth TLP. It is allowed to place the TLP header and payload data in any DW. Fig. 16B The seven TLPs and two DLLPs placed in the can be placed more compactly - they accommodate five fewer DWs and allow for the placement of an eighth TLP.

[0192] Fig.17 Table 1700 shows PCIe 5.0 TLP efficiency. Table 1700 shows how TLP efficiency under the latest version of the PCIe protocol varies with transaction size, with efficiencies exceeding 90% for large payloads and falling to 62.7% for header-only transactions. These efficiencies are the same regardless of link width. Table 1500 in Figure 1500 shows that flit-based packet packing achieves TLP efficiencies from 88.9% to 94.4% across link width, a relatively uniform efficiency compared to the range of TLP efficiencies in PCIe 5.0 across transaction sizes.

[0193] Fig.18AAn exemplary protocol stack pair implemented in a transceiver pair is shown. Protocol stacks 1800 and 1804 can be any kind of protocol or network stack, such as a PCIe stack. Although the PCIe stack is cited herein, the same concept can be applied to other protocols or network stacks. In one embodiment, protocol stack 1800 is a PCIe protocol stack, which includes a transaction layer 1810, a data link layer 1820, and a physical layer 1830. A communication port can be referred to as a module, circuit, interface, or port that implements or includes protocol stack 1800 or any other protocol stack. Therefore, in one embodiment, a protocol stack can include a transaction layer module, a data link layer module, and a physical layer module. Such a protocol stack can also be considered to include a transaction layer circuit, a data link layer circuit, and a physical layer circuit. When referring to the protocol stack as a whole, the protocol stack can be referred to as a protocol stack circuit or a protocol stack module.

[0194] PCI Express uses packets to pass information between root complexes, switches, and endpoints. For example, information to be sent from a sending device 1840 to a receiving device 1850 is sent from a processor 1860 (or any other processing device of the sending device 1840) to the protocol stack 1800. The transaction layer 1810 packet carries the information to be passed from the processor 1860 of the sending device 1840 to the processor 1894 of the receiving device 1850. As the packets formed at the transaction layer 1810 move down the protocol stack to the data link layer 1820 and then to the physical layer 1830, they are extended with information to process the packets at those layers. The physical layer 1830 of the sending device 1840 sends the packet to the physical layer 1870 of the receiving device 1850 over the link 1854. There, the reverse process occurs, and the information added to the packet as it moves down the protocol stack 1800 is stripped off as the packet moves up the protocol stack 1804. The transaction layer 1890 of the protocol stack 1874 passes the payload of the packet sent from the sending device 1840 to the processor 1894 of the receiving device 1850 , resulting in a message being sent from the sending device 1840 to the receiving device 1850 .

[0195] In one embodiment, transaction layer 1810 provides an interface to PCIe protocol stack 1800 for processor 1860. Transaction layer 1810 is responsible for the assembly and disassembly of transaction layer packets (TLPs) that transfer information between devices. Upon receiving information from processor 1860, transaction layer 1810 assembles one or more TLP packets that will transfer the information to receiving device 1850. TLP packet 1842 is an embodiment of a TLP packet. TLP packet 1842 includes a TLP header 1844 and a payload 1846. Other information may be included in the TLP packet, such as an end-to-end cyclic redundancy code (ECRC), an error detection code that the PCIe transaction layer may calculate for the TLP packet.

[0196] The data link layer 1820 acts as an intermediate stage between the transaction layer 1810 and the physical layer 1830. In one embodiment, one of the responsibilities of the data link layer 1820 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between devices across a link. In one embodiment, the reliability mechanism is implemented in part by determining a packet sequence number for a TLP packet and calculating a link CRC (LCRC) value based on the content of the TLP packet and the sequence number of the packet. The data link layer 1820 appends information 1852 to the header of the TLP packet 1842 including the packet sequence number, and appends an LCRC value 1856 to the tail of the TLP packet 1842. The data link layer 1820 submits the TLP 1842 with the additional information to the physical layer 1830 for transmission to the receiving device 1850 across the link 1854.

[0197] In one embodiment, moving down the protocol stack 1800 of the transmitting device 1840, the physical layer 1830 includes a logical sublayer 1832 and an electronic layer 1834 to physically transmit packets to an external device. Here, the logical sublayer 1832 is responsible for the "digital" functions of the physical layer 1830. In this regard, the logical sublayer includes a transmit portion that prepares outgoing information for transmission by the physical sublayer 1834 and a receive portion that is used to identify and prepare received information before passing the received information to the data link layer 1820. The logical sublayer 1832 frames the attached TLP packets together with the start transaction packet (STP) field 1866 to generate a T sent LP 1868 transmitted on the link 1854. The STP field 1866 includes the sequence number 1852, the frame CRC bits, the length of the TLP, and other information.

[0198] As used herein, the term "transaction layer packet" refers to a TLP generated by the transaction layer 1810 and includes a TLP header and payload information. The terms "transaction layer packet information" and "transaction layer packet data" may refer to a TLP header, a TLP payload, or both. As used herein, unless explicitly stated, the term "transaction layer packet" does not include information added to the TLP, such as a sequence number, an LCRC, or framing data added by the data link and physical layers. Similarly, unless explicitly stated, the term "data link layer packet" refers to a data link layer packet that does not include framing data added by the physical layer.

[0199] Electronic layer 1834 includes a transmitter 1836 and a receiver 1838. Transmitter 1836 is provided symbols by logic sublayer 1832, which transmitter 1836 serializes and transmits to receiving device 1850 via link 1854. Received serialized symbols transmitted on link 1854 are provided to receiver 1838 by receiving device 1850 and the received signal is converted into a bit stream. The bit stream is deserialized and provided to logic sublayer 1832. In one embodiment, packets are transmitted over link 1854 using an 8b / 10b data encoding scheme, where eight bits of data are transmitted as ten bits of symbols.

[0200] Although the transaction layer 1810, the data link layer 1820, and the physical layer 1830 are discussed with reference to the embodiment of the PCIe protocol stack, the protocol stack is not limited thereto. In other embodiments, the protocol stack 1800 may have different layers and / or fewer or more layers than those shown. In addition, in other embodiments, Fig.18A The individual layers shown in can be combined into a single layer and as Fig.18A The single layers shown can be combined into multiple layers. Fig.18A Any of the layers in the protocol stack shown in may be implemented as part of an operating system of a computing device, independent of an operating system, or running on another software layer. Fig.18A The layers shown in the may be implemented in software, hardware, firmware, or a combination thereof, and may alternatively be referred to as modules or circuit systems (e.g., "data link layer module", "physical layer circuit system"), or a combination thereof. Reference to a computer device being programmed to perform a method may be programmed to perform the method via software, hardware, firmware, or a combination thereof.

[0201] The physical layer can initiate a physical layer packet (PLP) from a transmitter device and terminate at the physical layer of a receiver device. PLP can include EIOS, EIEOS, SKP OS, and other ordered sets.

[0202] Fig.18B1 is a schematic diagram of an example PHY 1830 and 1970 according to an embodiment of the present disclosure, which includes logical elements for encoding and decoding ordered sets. The physical layer 1830 may include a logic sublayer 1832, which includes an ordered set encoder logic 1902. The ordered set encoder logic 1902 may include circuits, state machines, and / or other logic to encode packets with ordered sets, as described above. The ordered set encoder logic 1902 may include general logic, circuits, state machines, etc. for encoding various types of ordered sets. In some embodiments, each type of OS can be encoded using corresponding encoding logic. For example, SKP OS encoding logic 1904 can be used to encode SKP OS, EIOS OS encoding logic 1906 can be used to encode EIOS, EIEOS can be used to encode EIEOS, TSOS 1910 can be used to encode training symbol OS, and so on.

[0203] The data block can be encoded with SKP ordered sets, EIOS, EIEOS, training (TS1 / TS2) ordered sets, SKP end ordered sets, or other types of ordered sets. OS encoding logic 1912 can encode any type of OS into a data block, in which case a common state machine can be used to perform the encoding of the data block. In some embodiments, each type of OS can be encoded by a corresponding encoding logic, for example, using a unique state machine. A combination of a general encoder and a specific OS encoder can also be used.

[0204] The OS encoding logic 1902 may also include a shift register, such as a linear function shift register (LFSR) 1912. The LFSR 1912 may be implemented using logic circuits, such as circuits including an exclusive OR (XOR) gate or other circuits. The LFSR 1912 may be used to check bits after encoding the packet and before sending the encoded bits to the PHY.

[0205] The receiving device 1850 may include a physical layer 1870, which also includes a logical sublayer 1872. The logical sublayer 1872 includes an OS decoder logic 1922. The OS decoder logic 1922 can decode the OS bit from the received packet. The OS decoder 1922 may include a common state machine (and / or other logic) for decoding the OS bit from the received packet. In some embodiments, each type of OS can be decoded by a corresponding decoder logic. For example, the SKP OS can be decoded using the SKP OS decoding logic 1924, the EIOS can be decoded using the EIOS OS decoding logic 1926, the EIEOS can be decoded using the EIEOS decoding logic 1928, the training symbol OS can be decoded using the TSOS 1930, and so on.

[0206] The OS decoding logic 1922 may also include a shift register, such as a linear function shift register (LFSR) 1932. The LFSR 1932 may be embodied using logic circuits, such as circuits including an exclusive OR (XOR) gate or other circuits. The LFSR 1932 may be used to check the received OS bits in the packet against the expected bits to find transmission errors. For example, when 5 of the 8 SKP OS bits are checked to be accurate relative to the expected bits within a certain interval, the LFSR 1932 may be used to determine whether a bit error has occurred in the received packet.

[0207] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present disclosure.

[0208] The design may go through various stages from creation to simulation to manufacturing. The data representing the design may represent the design in a variety of ways. First, as useful in simulation, a hardware description language or another functional description language may be used to represent the hardware. In addition, a circuit-level model with logic and / or transistor gates may be generated at some stage of the design process. In addition, most designs reach a data level representing the physical locations of various devices in the hardware model at some stage. In the case of using traditional semiconductor manufacturing technology, the data representing the hardware model may be data specifying the presence or absence of various features on different mask layers of a mask used to manufacture an integrated circuit. In any representation of the design, the data may be stored in any form of machine-readable medium. A memory or a magnetic or optical storage device such as a disk may be a machine-readable medium for storing information transmitted via light waves or electrical waves modulated or otherwise generated to transmit such information. When an electrical carrier indicating or carrying a code or design is transmitted, a new copy is made to the extent that the electrical signal is copied, buffered, or retransmitted. Therefore, a communication provider or network provider may store an article of information such as information encoded into a carrier wave embodying the technology of an embodiment of the present disclosure at least temporarily on a tangible machine-readable medium.

[0209] As used herein, module refers to any combination of hardware, software and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-temporary medium storing a code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware that is particularly configured to identify and / or execute a code to be maintained on a non-temporary medium. In addition, in another embodiment, the use of a module refers to a non-temporary medium including a code that is particularly suitable for execution by a microcontroller to implement a predetermined operation. And, as can be inferred, in yet another embodiment, the term module (in this example) can refer to a combination of a microcontroller and a non-temporary medium. Typically, the boundaries of modules illustrated as separate modules typically vary and potentially overlap. For example, a first module and a second module can share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0210] In one embodiment, the use of the words "for", "configured to" refers to a device, hardware, logic or element that is arranged, put together, manufactured, provided to be sold, imported and / or designed to perform a specified or determined task. In this example, a device or element thereof that is not operating is still 'configured to' perform a specified task, provided that it is designed, coupled and / or interconnected to perform the specified task. Purely as an illustrative example, a logic gate can provide 0 or 1 during operation. But a logic gate that is 'configured to' provide an enable signal to a clock does not include every possible logic gate that can provide 1 or 0. Instead, the logic gate is a logic gate coupled in a way that a 1 or 0 output is used to enable the clock during operation. Note again that the use of the term 'configured to' does not require operation, but focuses on the potential state of the device, hardware and / or element, where in the potential state, the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operating.

[0211] Furthermore, in one embodiment, the use of the words "capable / able" and / or "operable" refers to a certain device, logic, hardware, and / or element that is designed in such a way as to enable the use of the device, logic, hardware, and / or element in a specified manner. As mentioned above, in one embodiment, the use for, capable of, or operable refers to a potential state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or element is not operating, but is designed to enable the use of the device in a specified manner.

[0212] As used herein, a value includes any known representation of a number, state, logic state, or binary logic state. Typically, logic levels, logic levels, logic values, or logical values ​​are also referred to as 1 and 0, which simply represent binary logic states. For example, 1 represents a high logic level and 0 represents a low logic level. In one embodiment, a storage unit such as a transistor or a flash memory cell may be able to hold a single logic value or multiple logic values. However, other value representations in computer systems have been used. For example, the decimal tens may also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, a value includes any information representation that can be stored in a computer system.

[0213] In addition, a state may be represented by a value or a portion of a value. As an example, a first value such as a logical 1 may represent a default or initial state, while a second value such as a logical 0 may represent a non-default value. Additionally, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value potentially includes a high logic value, i.e., reset, while an updated value potentially includes a low logic value, i.e., set. Note that any combination of values ​​may be used to represent any number of states.

[0214] Embodiments of the methods, hardware, software, firmware, or code described above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form that can be read by a machine, such as a computer or electronic system. For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from temporary (propagating) signals (e.g., carrier waves, infrared signals, digital signals); etc., to distinguish them from non-transitory media from which information can be received.

[0215] Instructions for programming logic to perform embodiments of the present disclosure may be stored in a memory in the system, such as DRAM, cache, flash memory or other storage devices. In addition, instructions may be distributed via a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or sending information in a machine (e.g., computer) readable form, but is not limited to a floppy disk, an optical disk, a compressed disk, a read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, a flash memory or a tangible machine-readable storage device for transmitting information via an electrical, optical, acoustic or other form of propagation signal (e.g., carrier wave, infrared signal, digital signal, etc.) through the Internet. Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or sending electronic instructions or information in a machine (e.g., computer) readable form.

[0216] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0217] In the foregoing description, reference has been made to specific exemplary embodiments for detailed description. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. The description and drawings are therefore to be considered in an illustrative rather than a restrictive sense. Furthermore, the foregoing use of embodiments and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and unique embodiments as well as potentially the same embodiment.

[0218] The foregoing description of one or more embodiments provides illustration and description, but is not intended to be exhaustive or to limit the scope of the embodiments to the precise forms disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the various embodiments.

[0219] Example 1 is an apparatus including a port for sending data; and a link coupled to the port. The port includes a physical layer device (PHY) for decoding a physical layer packet, the physical layer packet is received through the link, the physical layer packet includes a first bit sequence corresponding to a first ordered set and a second bit sequence corresponding to a second ordered set, the first bit sequence being adjacent to the second bit sequence.

[0220] Example 2 may include the subject matter of Example 1, wherein the first ordered-set is received at a predetermined ordered-set interval.

[0221] Example 3 may include the subject matter of Example 2, wherein the predetermined ordered set interval occurs after a flow control unit (flit).

[0222] Example 4 may include the subject matter of Example 3, wherein the predetermined ordered set interval occurs between two flits.

[0223] Example 5 may include the subject matter of any of Examples 1-4, wherein the first ordered set includes eight bytes and the second ordered set includes eight bytes.

[0224] Example 6 may include the subject matter of Example 5, the port being for reading eight bytes of a first ordered set; and verifying whether five of the eight bytes match an expected ordered set type.

[0225] Example 7 may include the subject matter of any of Examples 1-6, wherein the port is to determine that five of the eight bytes do not match an expected ordered set type; and enter a link recovery state.

[0226] Example 8 may include the subject matter of any of Examples 1-6, the port to determine that five of the eight bytes match an electrical idle ordered set (EIOS); and enter a low power state after a second ordered set.

[0227] Example 9 may include the subject matter of any of Examples 1-6, the port to determine that five of the eight bytes match an electrical idle exit ordered set (EIEOS); and enter a link recovery state after a second ordered set.

[0228] Example 10 may include the subject matter of any of Examples 1-6, the port being for determining that five of the eight bytes match a skip ordered set (SKP OS); reading a second ordered set; and determining a type of the ordered set from the second ordered set.

[0229] Example 11 may include the subject matter of Example 10, the port being used to: determine that the second ordered set matches a skip end ordered set (SKP_END OS); identify the next eight bytes following the SKP_END OS as a PHY payload; identify the next eight bytes following the PHY payload as a copied PHY payload; and determine that a data flow follows the PHY payload following the SKP_END OS.

[0230] Example 12 may include the subject matter of Example 10, the port to: determine that the second ordered set matches the SKP OS; continue to check bytes following the second ordered set for the SKP OS; determine that more than 56 bytes include the SKP OS; and cause the link to enter a recovery state.

[0231] Example 13 may include the subject matter of Example 10, the port being for: determining that the second ordered set matches the SKP OS; determining that five of the eight bytes following the second ordered set match a skip end ordered set (SKP_END OS); identifying the next eight bytes following the SKP_END OS as a PHY payload; and determining that the data flow follows the PHY payload following the SKP_ENDOS.

[0232] Example 14 may include the subject matter of Example 13, the port to identify next eight bytes following the PHY payload as a copied PHY payload.

[0233] Example 15 may include the subject matter of Example 1, wherein the first ordered set includes eight bytes and the second ordered set includes eight bytes, the first and second ordered sets include an electrical idle exit ordered set (EIEOS); the port is used to: receive two additional EIEOS; receive 32 training sequence ordered sets for link training.

[0234] Example 16 may include the subject matter of Example 15, wherein each training sequence ordered set comprises a first part and a second part, the first part comprises eight symbols and the second part comprises eight symbols, each symbol comprises one byte, and the first part contains the same information as the second part in each symbol.

[0235] Example 17 is a method comprising: receiving a first bit sequence corresponding to a first ordered set comprising eight bytes at a port; receiving a second bit sequence corresponding to a second ordered set comprising eight bytes at the port, the first bit sequence being adjacent to the second bit sequence, the first ordered set being the same as the second ordered set; comparing a portion of the first ordered set with an expected ordered set; and determining the type of the ordered set based on the comparison.

[0236] Example 18 may include the subject matter of Example 17, wherein receiving the first sequence comprises receiving the first sequence at predetermined ordered set intervals.

[0237] Example 19 may include the subject matter of Example 18, wherein the predetermined ordered set interval occurs after a flow control unit (flit).

[0238] Example 20 may include the subject matter of Examples 17-19, further comprising: reading eight bytes of the first ordered set through the port; and verifying whether five of the eight bytes match an expected ordered set type.

[0239] Example 21 may include the subject matter of Example 20, further comprising: determining that five of the eight bytes do not match the expected ordered set type; and entering a link recovery state.

[0240] Example 22 may include the subject matter of Example 20, the port being for: determining that five of the eight bytes match an electrical idle ordered set (EIOS); and entering a low power state after a second ordered set.

[0241] Example 23 may include the subject matter of Example 20, the port to: determine that five of the eight bytes match an electrical idle exit ordered set (EIEOS); and enter a link recovery state after a second ordered set.

[0242] Example 24 may include the subject matter of Example 20, the port to: determine that five of the eight bytes match a skip ordered set (SKP OS); read a second ordered set; and determine the ordered set type from the second ordered set.

[0243] Example 25 may include the subject matter of Example 24, the port being used to: determine that the second ordered set matches a skip end ordered set (SKP_END OS); identify the next eight bytes following the SKP_END OS as a PHY payload; identify the next eight bytes following the PHY payload as a copied PHY payload; and determine that a data flow follows the PHY payload following the SKP_END OS.

[0244] Example 26 may include the subject matter of Example 24, the port to: determine that the second ordered set matches the SKP OS; continue to check bytes following the second ordered set for the SKP OS; determine that more than 56 bytes include the SKP OS; and cause the link to enter a recovery state.

[0245] Example 27 may include the subject matter of Example 24, the port being for: determining that the second ordered set matches the SKP OS; determining that five of the eight bytes following the second ordered set match a skip end ordered set (SKP_END OS); identifying the next eight bytes following the SKP_END OS as a PHY payload; and determining that a data flow follows the PHY payload following the SKP_END OS.

[0246] Example 28 may include the subject matter of Example 17, wherein the first ordered set includes eight bytes, the second ordered set includes eight bytes, and the first and second ordered sets include an electrical idle exit ordered set (EIEOS); the method further includes: receiving two additional EIEOS; receiving thirty-two training sequence ordered sets for link training; wherein each training sequence ordered set includes a first part and a second part, the first part includes eight symbols, the second part includes eight symbols, each symbol includes one byte, and the first part contains the same information as the second part in each symbol.

[0247] Example 29 is a system comprising: a host device having a downstream port; a link partner including an upstream port; a link connecting the downstream port and the upstream port. The downstream port sends a first set of eight bytes including a first ordered set and a second set of eight bytes including a second ordered set within a predetermined interval, the first ordered set being the same as the second ordered set. The upstream port receives the first set of eight bytes; determines that the first set of eight bytes is received within an expected ordered set interval; and determines an ordered set type based on the first set of eight bytes.

[0248] Example 30 may include the subject matter of Example 29, wherein the first ordered-set is received at a predetermined ordered-set interval.

[0249] Example 31 may include the subject matter of Example 30, wherein the predetermined ordered set interval occurs after a flow control unit (flit).

[0250] Example 32 may include the subject matter of Example 31, wherein the predetermined ordered set interval occurs between two flits.

[0251] Example 33 may include the subject matter of any of Examples 29-32, wherein the upstream port determines that five of the eight bytes do not match an expected ordered set type; and enters a link recovery state.

[0252] Example 34 may include the subject matter of any of Examples 29-32, the upstream port determining that five of the eight bytes match an electrical idle ordered set (EIOS); and entering a low power state after a second ordered set.

[0253] Example 35 may include the subject matter of any of Examples 29-32, the upstream port determining that five of the eight bytes match an electrical idle exit ordered set (EIEOS); and entering a link recovery state after a second ordered set.

[0254] Example 36 may include the subject matter of any of Examples 29-32, the upstream port determining that five of the eight bytes match a skip ordered set (SKP OS); reading a second ordered set; and determining an ordered set type from the second ordered set.

[0255] Example 37 may include the subject matter of Example 36, wherein the upstream port is operable to determine that the second ordered set matches a skip end ordered set (SKP_END OS); identify the next eight bytes following the SKP_END OS as a PHY payload; identify the next eight bytes following the PHY payload as a copied PHY payload; and determine that a data flow follows the PHY payload following the SKP_END OS.

[0256] Example 38 may include the subject matter of Example 36, wherein the upstream port is used to determine that the second ordered set matches the SKP OS; continue to check bytes after the second ordered set of the SKP OS; determine that more than 56 bytes include the SKP OS; and cause the link to enter a recovery state.

[0257] Example 39 may include the subject matter of Example 29, wherein the first ordered set includes eight bytes, the second ordered set includes eight bytes, the first and second ordered sets include an electrical idle exit ordered set (EIEOS); the upstream port receives two additional EIEOS; and 32 training sequence ordered sets are received for link training.

[0258] Example 40 may include the subject matter of Example 39, wherein each training sequence ordered set comprises a first part and a second part, the first part comprises eight symbols, the second part comprises eight symbols, each symbol comprises one byte, and the first part contains the same information as the second part in each symbol.

Claims

1. A device for communication, comprising: A receiver comprising a port, the port comprising a physical layer circuit PHY, the PHY being configured to: During the SKIP ordered set SKPOS interval, receiving an ordered set OS from the link, wherein the received OS includes first eight bytes and second eight bytes; determining, based on the first eight bytes of the received OS, whether the received OS is SKPOS, an electrical idle OS EIOS, or an electrical idle exit OS EIEOS; Read the second eight bytes of the received OS; determining that the second eight bytes of the received OS match the SKP_END OS when at least five bytes of the second eight bytes of the received OS match the SKP_END OS; and Process the PHY payload following the SKP_END.

2. The apparatus of claim 1, said PHY to determine the type of OS when at least five of the first eight bytes match a type of OS.

3. The apparatus of any one of claims 1 or 2, the PHY to determine that the received OS includes SKPOS when at least five bytes of the first eight bytes of the received OS correspond to expected bytes of SKPOS.

4. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: determining that the received OS includes the EIOS when at least five bytes of the first eight bytes correspond to bytes of the EIOS; and The link is prepared to enter a low power state.

5. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: determining that the received OS includes EIEOS when at least five bytes of the first eight bytes correspond to bytes of EIEOS; and The link is put into recovery.

6. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: Read the second eight bytes of the received OS; determining that at least five of the second eight bytes do not match any type of OS; and The link is put into recovery.

7. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: After receiving the OS, receiving a PHY payload; and The payload type is determined from the PHY Payload Type field, the payload type comprising one of a remainder payload or a linear feedback shift register.

8. The apparatus of any one of claims 1 or 2, the PHY to determine that the received OS is valid when at least five of the first eight bytes correspond to expected values ​​for a type of OS.

9. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: receiving a training sequence ordered set, the training sequence ordered set comprising first eight bytes and second eight bytes; performing a parity check on one of the first eight bytes or the second eight bytes of the training sequence ordered set; and When the first eight bytes or the second eight bytes pass the parity check, it is determined that the training sequence ordered set is valid.

10. The apparatus according to any one of claims 1 or 2, wherein the PHY is configured to: Receive the start data stream ordered set; Checking the E1_87_87_87 set in the starting data stream ordered set; and If four E1_87_87_87 sets are valid, it is determined that the starting data stream ordered set is valid.

11. The device according to any one of claims 1 or 2, wherein: The received OS includes at least 16 bytes.

12. The device according to any one of claims 1 or 2, wherein: SKPOS intervals occur at flit boundaries.

13. The device according to any one of claims 1 or 2, wherein: In SRIS mode, the SKPOS interval occurs after every 74 flits.

14. The device according to any one of claims 1 or 2, wherein: In common clock or SRNS mode, the SKPOS interval occurs after 740 flits.

15. A method for communication, comprising: During the SKIP ordered set SKPOS interval, the ordered set OS is received from the link; Read the first eight bytes of the received OS; determining, based on the first eight bytes of the received OS, whether the received OS is SKPOS, an electrical idle OS EIOS, or an electrical idle exit OS EIEOS; Read the second eight bytes of the received OS; determining that the second eight bytes of the received OS match the SKP_END OS when at least five bytes of the second eight bytes of the received OS match the SKP_END OS; and Process the PHY payload following the SKP_END.

16. The method of claim 15, further comprising determining the type of OS when at least five of the first eight bytes match a type of OS.

17. The method of any one of claims 15 or 16, further comprising determining that the received OS comprises SKPOS when at least five bytes of the first eight bytes of the received OS correspond to expected bytes of SKPOS.

18. The method according to any one of claims 15 or 16, further comprising: determining that the received OS includes the EIOS when at least five bytes of the first eight bytes correspond to bytes of the EIOS; as well as The link is prepared to enter a low power state.

19. The method according to any one of claims 15 or 16, further comprising: determining that the received OS includes EIEOS when at least five bytes of the first eight bytes correspond to bytes of EIEOS; as well as The link is put into recovery.

20. The method according to any one of claims 15 or 16, further comprising: Read the second eight bytes of the received OS; determining that at least five of the second eight bytes do not match any type of OS; as well as The link is put into recovery.

21. The method according to any one of claims 15 or 16, further comprising: After receiving the OS, receiving a PHY payload; as well as The payload type is determined from the PHY Payload Type field, the payload type comprising one of a remainder payload or a linear feedback shift register.

22. The method of any one of claims 15 or 16, further comprising determining that the received OS is valid when at least five of the first eight bytes correspond to expected values ​​for a type of OS.

23. The method according to any one of claims 15 or 16, further comprising: receiving a training sequence ordered set, the training sequence ordered set comprising first eight bytes and second eight bytes; performing a parity check on one of the first eight bytes or the second eight bytes of the training sequence ordered set; and When the first eight bytes or the second eight bytes pass the parity check, it is determined that the training sequence ordered set is valid.

24. The method according to any one of claims 15 or 16, further comprising: Receive the start data stream ordered set; Checking the E1_87_87_87 set in the starting data stream ordered set; and If four E1_87_87_87 sets are valid, it is determined that the starting data stream ordered set is valid.

25. The method according to any one of claims 15 or 16, wherein: The received OS includes at least 16 bytes.

26. The method according to any one of claims 15 or 16, wherein: SKPOS intervals occur at flit boundaries.

27. The method according to any one of claims 15 or 16, wherein: In SRIS mode, the SKPOS interval occurs after every 74 flits.

28. The method according to any one of claims 15 or 16, wherein: In common clock or SRNS mode, the SKPOS interval occurs after 740 flits.

29. A system for communication, comprising: First device; Second device; The second device is coupled to the first device via a link, wherein the link includes a plurality of physical channels; The first device comprises a protocol stack circuit for sending an ordered set to the second device, the ordered set comprising first eight bytes and second eight bytes; The second device includes a protocol stack circuit for: During the SKIP ordered set SKPOS interval, the ordered set OS is received from the link; Read the first eight bytes of the received OS; determining, based on the first eight bytes of the received OS, whether the received OS is SKPOS, an electrical idle OS EIOS, or an electrical idle exit OS EIEOS; Read the second eight bytes of the received OS; determining that the second eight bytes of the received OS match the SKP_END OS when at least five bytes of the second eight bytes of the received OS match the SKP_END OS; and Process the PHY payload following the SKP_END.

30. The system of claim 29, the second device to determine the type of OS when at least five of the first eight bytes match a type of OS.

31. The system of any one of claims 29 or 30, the second device to determine that the received OS includes SKPOS when at least five bytes of the first eight bytes of the received OS correspond to expected bytes of SKPOS.

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