Scan Driver

Abstract

A scan driver including a scan stage is provided herein. The first scan stage includes: a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to a first scan line; a first capacitor connected between the first node and the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to the first power line; a third transistor including a gate electrode coupled to a second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor connected between the second node and the third node.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0150380, filed on November 21, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] Various embodiments of the present disclosure are directed to a scan driver and a display device including the same. Background Art

[0003] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices has increased.

[0004] Each pixel of the display device can emit light at a brightness corresponding to a data voltage supplied through a data line. The display device can display an image frame through a combination of light emission of pixels.

[0005] A plurality of pixels may be coupled to each data line. Therefore, a scan driver is required that provides a scan signal for selecting a pixel to which a data voltage is to be supplied among a plurality of pixels. The scan driver is constructed in the form of a plurality of scan stages coupled to a shift register, and the scan driver may sequentially provide a conduction level scan signal based on a scan line.

[0006] Each scanning stage is required to have a sufficiently large voltage difference between the gate electrode and the source electrode of the buffer transistor to supply the scanning signal to all pixels of the pixel row (eg, pixels coupled to the same scanning line).

[0007] Furthermore, each scanning stage may include a plurality of capacitors, and power consumption needs to be reduced by minimizing charging and discharging of the capacitors. Summary of the invention

[0008] Various embodiments of the present disclosure relate to a scan driver and a display device including the same, which can sufficiently increase a voltage difference between a gate electrode and a source electrode of a buffer transistor without providing an additional external terminal or internal element and can minimize charging and discharging of an internal capacitor.

[0009] An embodiment of the present disclosure may provide a scan driver including a plurality of scan stages, wherein a first scan stage among the plurality of scan stages may include: a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to a first scan line; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to the first power line; a third transistor including a gate electrode coupled to a second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor including a first electrode coupled to a second node and a second electrode coupled to a third node.

[0010] In an embodiment, the first scan stage may further include a fourth transistor including a gate electrode coupled to the second control clock line, a first electrode coupled to the second node, and a second electrode coupled to the first power line.

[0011] In an embodiment, the first scan stage may further include a fifth transistor including a gate electrode coupled to the second control clock line, a first electrode coupled to the scan start line, and a second electrode coupled to the fourth node.

[0012] In an embodiment, the first scan stage may further include a sixth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the second node, and a second electrode coupled to the second control clock line.

[0013] In an embodiment, the first scan stage may further include a seventh transistor including a gate electrode coupled to the second node, a first electrode coupled to the second power line, and a second electrode coupled to the first carry line.

[0014] In an embodiment, the first scan stage may further include an eighth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the first carry line, and a second electrode coupled to the first control clock line.

[0015] In an embodiment, the first scan stage may further include a third capacitor including a first electrode coupled to the fourth node and a second electrode coupled to the first carry line.

[0016] In an embodiment, the first scan stage may further include a ninth transistor including a gate electrode coupled to the first control clock line, a first electrode coupled to the first carry line, and a second electrode coupled to the first node.

[0017] In an embodiment, the first scan stage may further include a tenth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the first node, and a second electrode coupled to the first power line.

[0018] In an embodiment, the first scan stage may further include an eleventh transistor configured to couple the first electrode of the fourth transistor to the second node, and the eleventh transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the first electrode of the fourth transistor, and a second electrode coupled to the second node.

[0019] In an embodiment, the first scan stage may further include a twelfth transistor configured to couple the second electrode of the fifth transistor to the fourth node, and the twelfth transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the fifth transistor, and a second electrode coupled to the fourth node.

[0020] In an embodiment, the first scan stage may further include a thirteenth transistor configured to couple the second electrode of the ninth transistor to the first node, and the thirteenth transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the ninth transistor, and a second electrode coupled to the first node.

[0021] In an embodiment, the plurality of scan stages may include a second scan stage coupled to the second power clock line, the first control clock line, the second control clock line, the first carry line, the second carry line, and the second scan line.

[0022] An embodiment of the present disclosure may provide a display device, the display device comprising: a scan driver including a pixel unit, the pixel unit being driven in a first display mode during a first period and being driven in a second display mode during a second period having a time interval equal to that of the first period; and a plurality of scan stages coupled to the pixel unit through a plurality of scan lines, wherein a first period during which the plurality of scan stages supply a conduction level of a scan signal may be shorter than a second period during which the plurality of scan stages supply a conduction level of the scan signal during the second period, wherein a first scan stage of the plurality of scan stages may include: a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to the first scan line; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to the first power line; a third transistor including a gate electrode coupled to a second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the third node.

[0023] In another embodiment, the first scanning level may also include: a fourth transistor, including a gate electrode coupled to the second control clock line, a first electrode coupled to the second node, and a second electrode coupled to the first power line; and a fifth transistor, including a gate electrode coupled to the second control clock line, a first electrode coupled to the scan start line, and a second electrode coupled to the fourth node.

[0024] In another embodiment, the first scan level may further include: a sixth transistor, including a gate electrode coupled to the fourth node, a first electrode coupled to the second node, and a second electrode coupled to the second control clock line; and a seventh transistor, including a gate electrode coupled to the second node, a first electrode coupled to the second power line, and a second electrode coupled to the first carry line.

[0025] In another embodiment, the first scan stage may further include: an eighth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the first carry line, and a second electrode coupled to the first control clock line; and a third capacitor including a first electrode coupled to the fourth node and a second electrode coupled to the first carry line.

[0026] In another embodiment, the first scan level may further include: a ninth transistor, including a gate electrode coupled to the first control clock line, a first electrode coupled to the first carry line, and a second electrode coupled to the first node; and a tenth transistor, including a gate electrode coupled to the fourth node, a first electrode coupled to the first node, and a second electrode coupled to the first power line.

[0027] In another embodiment, the first scan stage may further include an eleventh transistor configured to couple the first electrode of the fourth transistor to the second node, and the eleventh transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the first electrode of the fourth transistor, and a second electrode coupled to the second node.

[0028] In another embodiment, the first scan level may also include a twelfth transistor configured to couple the second electrode of the fifth transistor to the fourth node and a thirteenth transistor configured to couple the second electrode of the ninth transistor to the first node, and the twelfth transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the fifth transistor, and a second electrode coupled to the fourth node, and the thirteenth transistor may include a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the ninth transistor, and a second electrode coupled to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0031] Figure 3 is a diagram illustrating a high frequency driving method according to an embodiment of the present disclosure.

[0032] Figure 4 is a diagram illustrating a data writing period according to an embodiment of the present disclosure.

[0033] Figure 5 is a diagram illustrating a data writing period according to another embodiment of the present disclosure.

[0034] Figure 6 is a diagram illustrating a low frequency driving method according to an embodiment of the present disclosure.

[0035] Figure 7 is a diagram illustrating a bias refresh period according to an embodiment of the present disclosure.

[0036] Figure 8 is a diagram illustrating a bias refresh period according to another embodiment of the present disclosure.

[0037] Fig. 9 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0038] Fig.10 It is shown that the Fig. 9 Diagram of the scan stage in a scan driver.

[0039] Fig.11 Is shown driving Fig.10 FIG. 10A of the scan-level approach.

[0040] Fig.12 is a diagram illustrating a scan driver according to another embodiment of the present disclosure.

[0041] Fig.13 It is shown that the Fig.12 Diagram of the scan stage in a scan driver.

[0042] Fig.14 Is shown driving Fig.13 FIG. 10A of the scan-level approach.

[0043] Fig.15 Shows Fig.13 Scan-level modifications.

[0044] Fig.16 Is shown driving Fig.15 FIG. 10A of the scan-level approach.

[0045] Fig.17 Shows Fig.13 Another modification of the scanning level.

[0046] Fig.18 Shows Fig.13 Further modifications to the scanning level. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept. The present disclosure may be implemented in various forms and is not limited to the embodiments to be described herein below.

[0048] In the accompanying drawings, parts not related to the present disclosure will be omitted to explain the present disclosure more clearly. Reference should be made to the accompanying drawings, in which similar reference numerals are used to represent similar components in all different drawings. Therefore, the aforementioned reference numerals may be used in other drawings.

[0049] For reference, the size of each component and the thickness of the line showing the component are arbitrarily indicated for the purpose of explanation, and the present disclosure is not limited to those shown in the drawings. In the drawings, the thickness of the components may be exaggerated to clearly indicate several layers and regions.

[0050] Hereinafter, coupling of an electrode or a wire to another electrode or wire means not only that the electrode or wire is “directly” coupled to another electrode or wire but also that the electrode or wire is “indirectly” coupled to another electrode or wire via an intermediate element.

[0051] Figure 1is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0052] Reference Figure 1 , the display device 9 according to the embodiment may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , and a pixel unit 50 .

[0053] The timing controller 10 may receive an external input signal from an external processor, and the external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, an RGB data signal, and the like.

[0054] The vertical synchronization signal may include a plurality of pulses and may indicate the starting point of a frame. The interval between adjacent pulses in the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include a plurality of pulses and may indicate the starting point of a horizontal period. The interval between adjacent pulses in the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may have an enable level for a specific horizontal period and may have a disable level in the remaining horizontal periods. When the data enable signal is an enable level, this may indicate that RGB data signals are supplied in the corresponding horizontal period. The RGB data signals may be simultaneously supplied to pixels in a pixel row during the corresponding horizontal period. The timing controller 10 may generate grayscale values ​​in response to the RGB data signals to correspond to the specifications of the display device 9. The timing controller 10 may generate control signals to be supplied to the data driver 20, the scan driver 30, and the emission driver 40 in response to an external input signal to correspond to the specifications of the display device 9.

[0055] The data driver 20 may generate data voltages to be supplied to the data lines DL1, DL2, ..., DLm using the grayscale values ​​and the control signal received from the timing controller 10, where m is an integer greater than 0. For example, the data driver 20 may sample the grayscale values ​​using the clock signal, and may simultaneously supply data voltages corresponding to the grayscale values ​​of pixels in one pixel row (e.g., pixels coupled to the same scan line) to the data lines DL1, DL2, ..., DLm.

[0056] The scan driver 30 may receive a clock signal, a scan start signal, etc. from the timing controller 10 and generate scan signals to be supplied to the scan lines GIL1, GWNL1, GWPL1, GBL1, . . . , GILn, GWNLn, GWPLn, GBLn. Here, n is an integer greater than 0.

[0057] The scan driver 30 may include a plurality of sub-scan drivers. For example, the first sub-scan driver may provide scan signals for the scan lines GIL1 and GILn, the second sub-scan driver may provide scan signals for the scan lines GWNL1 and GWNLn, the third sub-scan driver may provide scan signals for the scan lines GWPL1 and GWPLn, and the fourth sub-scan driver may provide scan signals for the scan lines GBL1 and GBLn. Each sub-scan driver may include a plurality of scan stages combined in the form of a shift register. For example, the scan signal may be generated in such a manner that a conduction level pulse of a scan start signal supplied to a scan start line is sequentially transmitted to a next scan stage.

[0058] As another example, the first sub-scan driver and the second sub-scan driver may be integrated to provide scan signals for the scan lines GIL1, GWNL1, GILn, and GWNLn, and the third sub-scan driver and the fourth sub-scan driver may be integrated to provide scan signals for the scan lines GWPL1, GBL1, GWPLn, and GBLn. For example, the previous scan line of the n-th scan line GWNLn (i.e., the n-1-th scan line) may be coupled to the same electrical node as the n-th scan line GILn. In addition, for example, the next scan line of the n-th scan line GWPLn (i.e., the n+1-th scan line) may be coupled to the same electrical node as the n-th scan line GBLn.

[0059] In this case, the first sub-scan driver and the second sub-scan driver may supply a scan signal having a pulse of a first polarity to the scan lines GIL1, GWNL1, GILn, and GWNLn. In addition, the third sub-scan driver and the fourth sub-scan driver may supply a scan signal having a pulse of a second polarity to the scan lines GWPL1, GBL1, GWPLn, and GBLn. The first polarity and the second polarity may be opposite to each other.

[0060] Hereinafter, polarity may refer to the logic level of a pulse. For example, if a pulse has a first polarity, the pulse may have a logic high level. When a pulse with a logic high level is supplied to the gate electrode of an N-type transistor, the N-type transistor may be turned on. That is, a pulse with a logic high level may be a turn-on level for an N-type transistor. Here, it is assumed that a voltage of a sufficiently low level is applied to the source electrode of the N-type transistor compared to the gate electrode. For example, the N-type transistor may be an NMOS.

[0061] In addition, if the pulse has a second polarity, the pulse may have a logic low level. When a pulse with a logic low level is supplied to the gate electrode of a P-type transistor, the P-type transistor may be turned on. That is, a pulse with a logic low level may be a turn-on level for a P-type transistor. Here, it is assumed that a voltage of a sufficiently high level is applied to the source electrode of the P-type transistor compared to the gate electrode. For example, the P-type transistor may be a PMOS.

[0062] The emission driver 40 may receive a clock signal, an emission stop signal, etc. from the timing controller 10, and generate an emission signal to be provided to the emission lines EL1, EL2, ..., ELn. For example, the emission driver 40 may sequentially provide an emission signal having an off-level pulse to the emission lines EL1, EL2, ..., ELn. For example, the emission driver 40 may be made in the form of a shift register, and may generate an emission signal under the control of a clock signal in a manner such as sequentially transmitting an off-level pulse of an emission stop signal to a next emission stage.

[0063] The pixel unit 50 includes pixels. For example, the pixels Pxnm may be coupled to corresponding data lines DLm, scan lines GILn, GWNLn, GWPLn, and GBLn, and emission lines ELn.

[0064] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0065] Reference Figure 2 , the pixel PXnm according to an embodiment of the present disclosure includes transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and a light emitting diode LD.

[0066] A first electrode of transistor T1 may be coupled to a first electrode of transistor T2, a second electrode of transistor T1 may be coupled to a first electrode of transistor T3, and a gate electrode thereof may be coupled to a second electrode of transistor T3. Transistor T1 may be referred to as a driving transistor.

[0067] A first electrode of the transistor T2 may be coupled to the first electrode of the transistor T1, a second electrode of the transistor T2 may be coupled to the data line DLm, and a gate electrode thereof may be coupled to the scan line GWPLn. The transistor T2 may be referred to as a scan transistor.

[0068] A first electrode of the transistor T3 may be coupled to the second electrode of the transistor T1, a second electrode of the transistor T3 may be coupled to the gate electrode of the transistor T1, and a gate electrode thereof may be coupled to the scan line GWNLn. The transistor T3 may be referred to as a diode-coupled transistor.

[0069] A first electrode of the transistor T4 may be coupled to the second electrode of the capacitor Cst, a second electrode of the transistor T4 may be coupled to the initialization line VINTL, and a gate electrode thereof may be coupled to the scan line GILn. The transistor T4 may be referred to as a gate initialization transistor.

[0070] A first electrode of the transistor T5 may be coupled to the power line ELVDDL, a second electrode of the transistor T5 may be coupled to the first electrode of the transistor T1, and a gate electrode thereof may be coupled to the emission line ELn. The transistor T5 may be referred to as a first emission transistor.

[0071] A first electrode of the transistor T6 may be coupled to the second electrode of the transistor T1, a second electrode of the transistor T6 may be coupled to the anode of the light emitting diode LD, and a gate electrode thereof may be coupled to the emission line ELn. The transistor T6 may be referred to as a second emission transistor.

[0072] A first electrode of the transistor T7 may be coupled to the anode of the light emitting diode LD, a second electrode of the transistor T7 may be coupled to the initialization line VINTL, and a gate electrode thereof may be coupled to the scan line GBLn. The transistor T7 may be referred to as an anode initialization transistor.

[0073] A first electrode of the storage capacitor Cst may be coupled to the power line ELVDDL, and a second electrode of the storage capacitor Cst may be coupled to the gate electrode of the transistor T1 .

[0074] The anode of the light emitting diode LD may be coupled to the second electrode of the transistor T6, and the cathode of the light emitting diode LD may be coupled to the power line ELVSSL. The voltage applied to the power line ELVSSL may be set to be lower than the voltage applied to the power line ELVDDL. The light emitting diode LD may be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, etc.

[0075] Each of transistors T1, T2, T5, T6, and T7 may be formed by a P-type transistor. The channels of transistors T1, T2, T5, T6, and T7 may be made of polysilicon. The polysilicon transistor may be a low temperature polysilicon (LTPS) transistor. Polysilicon transistors have high electron mobility and therefore have fast driving characteristics.

[0076] Each of transistors T3 and T4 may be formed by an N-type transistor. The channels of transistors T3 and T4 may be made of an oxide semiconductor. Oxide semiconductor transistors may be manufactured by a low temperature process and have a low charge mobility compared to the charge mobility of polysilicon. Therefore, the amount of leakage current generated by the oxide semiconductor transistor in the off state is smaller than the amount of leakage current generated by the polysilicon transistor in the off state.

[0077] Alternatively, the transistor T7 may not be formed of polysilicon but may be formed of an N-type oxide semiconductor transistor. Here, when the transistor T7 is formed of an N-type oxide semiconductor transistor, one of the scan lines GWNLn and GILn instead of the scan line GBLn may be coupled to the gate electrode of the transistor T7.

[0078] Figure 3 is a diagram illustrating a high frequency driving method according to an embodiment of the present disclosure.

[0079] When the pixel unit 50 displays frames at a first driving frequency, the display device 9 can be represented as being in a first display mode. In addition, when the pixel unit 50 displays frames at a second driving frequency less than the first driving frequency, the display device 9 can be represented as being in a second display mode.

[0080] In the first display mode, the display device 9 may display image frames at a frequency of 20 Hz or greater (eg, 60 Hz).

[0081] The second display mode may be a low power display mode. The display device 9 may display image frames at a frequency less than 20 Hz (eg, 1 Hz). For example, a case where only the time and date are displayed in the "always on mode" in the utility mode may correspond to the second display mode.

[0082] The period 1TP may include a plurality of frame periods 1FP. The period 1TP is an arbitrarily defined period for comparing the first display mode and the second display mode. The period 1TP may refer to the same time interval in the first display mode and the second display mode. For ease of description, it is assumed that the frame period 1FP has the same time interval in the first display mode and the second display mode. Therefore, in the first display mode and the second display mode, the period 1TP may include the same number of frame periods 1FP.

[0083] In the first display mode, each of the frame periods 1FP may include a data writing period WP and an emission period EP. For ease of description, Figure 3 It is shown that the data writing period WP is located at the beginning of the frame period 1FP in the first pixel row and the emission period EP is located after the data writing period WP. However, in rows other than the first pixel row, the data writing period WP may be located in the middle or end of the frame period 1FP.

[0084] Therefore, the pixels PX11 to PXnm may display a plurality of image frames corresponding to the number of frame periods 1FP during the period 1TP based on the data voltage received in the data writing period WP.

[0085] Figure 4 is a diagram illustrating a data writing period according to an embodiment of the present disclosure. Figure 5is a diagram illustrating a data writing period according to another embodiment of the present disclosure.

[0086] First, the emission signal En of the off level (high level) may be supplied to the emission line ELn during the data writing period WP. Therefore, the transistors T5 and T6 may be in the off state during the data writing period WP.

[0087] First, a first pulse of a conduction level (high level) is supplied to the scan line GILn. Therefore, the transistor T4 is turned on, and the initialization line VINTL is connected to the gate electrode of the transistor T1. Therefore, the voltage of the gate electrode of the transistor T1 is initialized to the initialization voltage provided from the initialization line VINTL and maintained by the storage capacitor Cst. For example, the initialization voltage of the initialization line VINTL can be sufficiently lower than the voltage of the power line ELVDDL. For example, the initialization voltage can be a voltage of a level that is the same as or similar to the level of the power line ELVSSL. Therefore, the transistor T1 can be turned on.

[0088] Next, the first pulse of the on-level is supplied to the scan lines GWPLn and GWNLn, respectively, and the corresponding transistors T2 and T3 are turned on. Therefore, the data voltage Dm applied to the data line DLm is written into the storage capacitor Cst through the transistors T2, T1 and T3. At this time, the data voltage Dm corresponds to the grayscale value G(n-4) of the pixel before being written into the storage capacitor Cst in 4 horizontal periods to apply the on-bias voltage to the transistor T1. If the on-bias voltage is applied to the transistor T1 before writing the expected data voltage Dm, the hysteresis phenomenon can be improved.

[0089] Next, a first pulse of a conduction level (low level) is supplied to the scanning line GBLn, and the transistor T7 is turned on, thereby initializing the anode voltage of the light emitting diode LD.

[0090] In this case, a second pulse of the on level (high level) is supplied to the scanning line GILn, and the above-mentioned driving process is performed again. That is, the on bias voltage is applied to the transistor T1 again, and the anode voltage of the light emitting diode LD is initialized.

[0091] If the third pulse of the on level is supplied to the scan lines GWPLn and GWNLn by repeating the above process, the data voltage Dm corresponding to the grayscale value Gn of the pixel PXnm is written into the storage capacitor Cst. At this time, the data voltage Dm written into the storage capacitor Cst is a data voltage in which the threshold voltage of the transistor T1 is compensated.

[0092] Finally, if the emission signal En becomes a conduction level (low level), transistors T5 and T6 are turned on. Therefore, a driving current path coupled to the power line ELVDDL, transistors T5, T1 and T6, light emitting diode LD and power line ELVSSL is formed so that the driving current flows through the path. The amount of driving current corresponds to the data voltage Dm stored in the storage capacitor Cst. Since the data voltage after threshold voltage compensation is stored in the storage capacitor Cst, the driving current corresponding to the data voltage Dm can flow regardless of the threshold voltage value of the transistor T1.

[0093] The light emitting diode LD emits light at a desired brightness according to the amount of driving current.

[0094] According to this embodiment, each scanning signal includes three pulses. However, according to another embodiment, each scanning signal may include two pulses or four or more pulses. In another embodiment, each scanning signal may be formed to include one pulse. In this case, the process of applying the on-bias voltage to the transistor T1 is omitted (see Figure 5 ).

[0095] In addition, the interval between adjacent pulses in the horizontal synchronization signal Hsync may correspond to one horizontal period. Figure 4 2 shows that the pulse of the horizontal synchronization signal Hsync is at a low level, but according to another embodiment, the pulse may be at a high level.

[0096] Figure 6 is a diagram illustrating a low frequency driving method according to an embodiment of the present disclosure.

[0097] In the second display mode, a first frame period 1FP of the period 1TP includes a data writing period WP and an emission period EP, and the remaining frame periods 1FP of the period 1TP include a bias refresh period BP and an emission period EP.

[0098] Since the transistors T3 and T4 of the pixel PXnm remain in the off state in the remaining frame period 1FP of the period 1TP, the storage capacitor Cst maintains the same data voltage during multiple image frames. Specifically, since the transistors T3 and T4 can be composed of oxide semiconductor transistors, leakage current can be minimized.

[0099] Therefore, the pixel PXnm may display the same single image frame during the period 1TP based on the data voltage supplied during the data writing period WP.

[0100] Figure 7 is a diagram illustrating a bias refresh period according to an embodiment of the present disclosure. Figure 8 is a diagram illustrating a bias refresh period according to another embodiment of the present disclosure.

[0101] Reference Figure 7 , in the bias refresh period BP, the scan signals GIn and GWNn of the cut-off level (low level) are supplied. Therefore, as described above, in the bias refresh period BP, the data voltage written in the storage capacitor Cst does not change. In this case, the reference data voltage Vref may be applied to the data line DLm.

[0102] In the bias refresh period BP, the emission signal En and the scanning signals GWPn and GBn having the same waveform as that of the data write period WP can be supplied. Therefore, by making the output light waveform of the light emitting diode LD similar in multiple frame periods 1FP of the period 1TP, flickering during low-frequency driving will not be recognized by the user.

[0103] Reference Figures 1 to 7 The pixel PXnm described is an embodiment suitable for high-frequency driving and low-frequency driving. The embodiment to be described later can be applied to pixels having other circuits capable of driving high frequencies and low frequencies. For example, all transistors T1 to T7 in the pixel PXnm can be composed of only P-type transistors. In this case, since the scan driver 30 only has to include a sub-scan driver for P-type transistors, the configuration of the scan driver 30 can be simplified. For example, the transistors of the pixel PXnm may not include light-emitting transistors T5 and T6. In this case, the emission driver 40 may be unnecessary.

[0104] According to this embodiment, each scanning signal GWPn or GBn includes three pulses. However, according to another embodiment, each scanning signal GWPn or GBn may include two pulses or four or more pulses. In another embodiment, each scanning signal GWPn or GBn may be formed to include only one pulse. In this case, the process of applying the on-bias voltage to the transistor T1 is omitted (see Figure 8 ).

[0105] The period 1TP when the pixel unit 50 is driven in the first display mode may be referred to as a first period (see Figure 3 The period 1TP when the pixel unit 50 is driven in the second display mode may be referred to as a second period (see Figure 6 In this regard, the time interval of the first period and the time interval of the second period may be equal to each other. That is, the first period and the second period may include the same number of frame periods 1FP.

[0106] The plurality of scanning stages may supply a scanning signal of a conduction level in a first cycle for a first period. Figure 3 and Figure 5, the scanning signal of the on level may be supplied in proportion to the number of data writing periods WP in the first period. The plurality of scanning stages may supply the scanning signal of the on level with a second cycle for the second period. For example, referring to Figure 6 and Figure 8 , the scanning signal of the conduction level can be supplied in proportion to the number of data writing periods WP in the second period. The number of data writing periods WP included in the second period is less than the number of data writing periods WP included in the first period. Therefore, it can be expressed that the first period is shorter than the second period.

[0107] Fig. 9 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0108] Reference Fig. 9 , shows an exemplary structure of a scan driver 30N including a plurality of scan stages NST1, NST2, NST3, NST4, and NSTn.

[0109] The scan driver 30N may correspond to the reference Figure 1 The second sub-scan driver of the scan driver 30 described above. According to an embodiment, when the transistor receiving the scan signal among the transistors of the pixel is composed of only N-type transistors, the pixel can be operated only by the scan driver 30N. Therefore, the scan driver 30N may not be a sub-scan driver, but may be an independent scan driver.

[0110] The scan driver 30N may include a scan start input terminal INF, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, and a first output terminal OUT1. The scan driver 30N may also include a power input terminal. Fig. 9 is omitted.

[0111] Each of the scanning stages NST1 to NSTn may include first, second, and third input terminals IN1, IN2, IN3, and a first output terminal OUT1. The first scanning stage NST1 may further include a scanning start input terminal INF. The first scanning stage NST1 may be coupled to the scanning start line FLML through the scanning start input terminal INF.

[0112] Each of the scanning stages NST1 to NSTn may be coupled to the first power clock line NCKL1 or the second power clock line NCKL2 through its first input terminal IN1. Adjacent scanning stages among the scanning stages NST1 to NSTn may be coupled to different power clock lines NCKL1 and NCKL2. For example, the second scanning stage NST2 may be coupled to the second power clock line NCKL2, and the first scanning stage NST1 and the third scanning stage NST3 adjacent to the second scanning stage NST2 may be coupled to the first power clock line NCKL1. The first power clock line NCKL1 and the second power clock line NCKL2 may be alternately coupled to the scanning stages NST1 to NSTn. For example, the first power clock line NCKL1 may be coupled to the odd-numbered scanning stages NST1, NST3, ..., NSTn, and the second power clock line NCKL2 may be coupled to the even-numbered scanning stages NST2 and NST4, etc. In contrast, the second power clock line NCKL2 may be coupled to the odd-numbered scanning stages NST1, NST3, . . . , NSTn, and the first power clock line NCKL1 may be coupled to the even-numbered scanning stages NST2 and NST4, and so on.

[0113] Each of the scanning stages NST1 to NSTn can be coupled to the first control clock line CCKL1 or the second control clock line CCKL2 through its second input terminal IN2. Adjacent scanning stages among the scanning stages NST1 to NSTn can be coupled to different control clock lines CCKL1 and CCKL2 through the second input terminal IN2. For example, the second scanning stage NST2 can be coupled to the second control clock line CCKL2 through the second input terminal IN2, and the first scanning stage NST1 and the third scanning stage NST3 adjacent to the second scanning stage NST2 can be coupled to the first control clock line CCKL1 through the second input terminal IN2. The first control clock line CCKL1 and the second control clock line CCKL2 can be alternately coupled to the scanning stages NST1 to NSTn through the second input terminal IN2. For example, the odd-numbered scanning stages NST1, NST3, ..., NSTn can be coupled to the first control clock line CCKL1 through the second input terminal IN2, and the even-numbered scanning stages NST2 and NST4, etc. can be coupled to the second control clock line CCKL2 through the second input terminal IN2. On the contrary, odd-numbered scanning stages NST1, NST3, . . . , NSTn may be coupled to the second control clock line CCKL2 via the second input terminal IN2, and even-numbered scanning stages NST2 and NST4, etc. may be coupled to the first control clock line CCKL1 via the second input terminal IN2.

[0114] Each of the scanning stages NST1 to NSTn may be coupled to the second control clock line CCKL2 or the first control clock line CCKL1 through its third input terminal IN3. The control clock line connected through the third input terminal IN3 in each of the scanning stages NST1 to NSTn may be different from the control clock line connected through the second input terminal IN2.

[0115] The scanning stages NST1 to NSTn may be coupled to the scanning lines GWNL1, GWNL2, GWNL3, GWNL4, and GWNLn, respectively, through the first output terminals OUT1. Each of the scanning stages NST2, NST3, NST4, and NSTn except the first scanning stage NST1 may be coupled to a scanning line of a previous scanning stage.

[0116] In order to reduce the clock frequency or implement other driving methods, the number of the power clock lines NCKL1 and NCKL2 and the control clock lines CCKL1 and CCKL2 may be changed.

[0117] Fig.10 It is shown that the Fig. 9 Diagram of the scan stage in a scan driver.

[0118] Reference Fig.10 , which is shown by way of example Fig. 9 The first scanning stage NST1 of the scanning driver 30N. Since the scanning line of the previous scanning stage is coupled to the second electrode of the transistor P1, Fig. 9 The other scanning stages NST2, NST3, NST4 and NSTn of the first scanning stage NST1 have substantially the same configuration as that of the first scanning stage NST1, so repeated description will be omitted here. The clock line reference numerals coupled to the first to third input terminals IN1, IN2 and IN3 are Fig. 9 Description.

[0119] The first scanning stage NST1 may include transistors P1 to P13 and capacitors CP1 to CP3. The transistors P1 to P13 may be P-type transistors.

[0120] A first electrode of the transistor P1 may be coupled to a second electrode of the transistor P2 , a second electrode of the transistor P1 may be coupled to the scan start line FLM1 , and a gate electrode of the transistor P1 may be coupled to the first power clock line NCKL1 .

[0121] A first electrode of the transistor P2 may be coupled to the second electrode of the transistor P13 , a second electrode of the transistor P2 may be coupled to the first electrode of the transistor P1 , and a gate electrode of the transistor P2 may be coupled to the first control clock line CCKL1 .

[0122] A first electrode of the transistor P3 may be coupled to a gate electrode of the transistor P6 , a second electrode of the transistor P3 may be coupled to the first control clock line CCKL1 , and a gate electrode of the transistor P3 may be coupled to a first electrode of the transistor P2 .

[0123] A first electrode of the transistor P4 may be coupled to the gate electrode of the transistor P6 , a second electrode of the transistor P4 may be coupled to the first power line VGLL having a turn-on level, and a gate electrode of the transistor P4 may be coupled to the first control clock line CCKL1 .

[0124] A first electrode of the transistor P5 may be coupled to a second electrode of the transistor P6 , a second electrode of the transistor P5 may be coupled to the second control clock line CCKL2 , and a gate electrode of the transistor P5 may be coupled to the node NP4 .

[0125] A first electrode of transistor P6 may be coupled to the second power line VGHL, a second electrode of transistor P6 may be coupled to a first electrode of transistor P5 , and a gate electrode of transistor P6 may be coupled to a first electrode of transistor P4 and to a first electrode of transistor P3 .

[0126] A first electrode of the transistor P7 may be coupled to the node NP2 , a second electrode of the transistor P7 may be coupled to the second control clock line CCKL2 , and a gate electrode of the transistor P7 may be coupled to the node NP1 .

[0127] A first electrode of the transistor P8 may be coupled to the node NP3 , a second electrode of the transistor P8 may be coupled to the node NP2 , and a gate electrode of the transistor P8 may be coupled to the second control clock line CCKL2 .

[0128] A first electrode of the transistor P9 may be coupled to the first power clock line NCKL1 , a second electrode of the transistor P9 may be coupled to the node NP3 , and a gate electrode of the transistor P9 may be coupled to the node NP4 .

[0129] A first electrode of the transistor P10 may be coupled to the first power clock line NCKL1 , a second electrode of the transistor P10 may be coupled to the first scan line GWNL1 , and a gate electrode of the transistor P10 may be coupled to the node NP3 .

[0130] A first electrode of the transistor P11 may be coupled to the first scan line GWNL1 , a second electrode of the transistor P11 may be coupled to the first power line VGLL, and a gate electrode of the transistor P11 may be coupled to the node NP4 .

[0131] A first electrode of the transistor P12 may be coupled to the node NP1 , a second electrode of the transistor P12 may be coupled to the gate electrode of the transistor P6 , and a gate electrode of the transistor P12 may be coupled to the first power line VGLL.

[0132] A first electrode of the transistor P13 may be coupled to the node NP4 , a second electrode of the transistor P13 may be coupled to the first electrode of the transistor P2 , and a gate electrode of the transistor P13 may be coupled to the first power line VGLL.

[0133] A first electrode of the capacitor CP1 may be coupled to the first power clock line NCKL1 , and a second electrode of the capacitor CP1 may be coupled to the node NP3 .

[0134] A first electrode of the capacitor CP2 may be coupled to the first electrode of the transistor P5 , and a second electrode of the capacitor CP2 may be coupled to the node NP4 .

[0135] A first electrode of the capacitor CP3 may be coupled to the node NP2 , and a second electrode of the capacitor CP2 may be coupled to the node NP1 .

[0136] Fig.11 Is shown driving Fig.10 FIG. 10A of the scan-level approach.

[0137] Fig.11 A timing diagram of a scan start signal FLM applied to a scan start line FLML, a first control clock signal CCK1 applied to a first control clock line CCKL1, a second control clock signal CCK2 applied to a second control clock line CCKL2, a first power clock signal NCK1 applied to a first power clock line NCKL1, a second power clock signal NCK2 applied to a second power clock line NCKL2, a node voltage VNP1 of a node NP1, a node voltage VNP2 of a node NP2, a node voltage VNP3 of a node NP3, a node voltage VNP4 of a node NP4, and a first scan signal GWN1 applied to a first scan line GWNL1 is shown. The interval between adjacent pulses in a horizontal synchronization signal can be referred to as a horizontal period 1H. The voltage VCP3 is the voltage difference between the first electrode and the second electrode of the capacitor CP3.

[0138] A high level voltage may be applied to the second power line VGHL, and a low level voltage may be applied to the first power line VGLL. Since the transistors P12 and P13 having gate electrodes coupled to the first power line VGLL are turned on during most of the time periods when describing the driving method, the description of the transistors P12 and P13 will be omitted except for specific cases.

[0139] First, at time point t1p, the scanning start signal FLM of the off level (high level) is supplied. At this time, since the transistor P1 is turned on by the low level first power supply clock signal NCK1, the scanning start signal FLM of the high level is supplied to the second electrode of the transistor P2.

[0140] At the time point t2p, the first control clock signal CCK1 of a low level is supplied. Therefore, the transistors P2 and P4 are turned on.

[0141] If the transistor P2 is turned on, the high level scanning start signal FLM is transmitted to the node NP4 through the transistor P13 which is also turned on, and the node voltage VNP4 becomes high level. The transistors P3, P5, P9 and P11 are turned off by the high level node voltage VNP4.

[0142] If transistor P4 is turned on, the gate electrode of transistor P6 is coupled to the first power line VGLL having a turn-on level. Since transistor P12 is turned on most of the time, node voltage VNP1 drops to the voltage supplied by the first power line VGLL. Therefore, transistors P6 and P7 are turned on.

[0143] If the transistor P6 is turned on, the first electrode of the capacitor CP2 is coupled to the second power line VGHL having a high level voltage. Therefore, the node voltage VNP4 of the node NP4 may be kept stable by coupling of the capacitor CP2.

[0144] If the transistor P7 is turned on, the node NP2 is coupled to the second control clock line CCKL2. At this time, since the high level second control clock signal CCK2 is applied to the gate electrode of the transistor P8, the transistor P8 is turned off and the node voltage VNP3 does not change.

[0145] At the time point t3p, the second control clock signal CCK2 of a low level is supplied.

[0146] The second control clock signal CCK2 of the low level is supplied to the node NP2 through the transistor P7. In this case, the node voltage VNP1 drops below the low level through the coupling of the capacitor CP3. Therefore, the transistor P7 can stably maintain the on state and have improved driving characteristics at the same time.

[0147] This drop in node voltage VNP1 does not significantly affect the voltage of the first electrode of transistor P3. Since the low-level voltage is applied to the gate electrode of transistor P12, the voltage of the second electrode (source electrode) of transistor P12 is prevented from being smaller than the sum of the absolute value of the low level and the threshold of transistor P12. Therefore, the source-drain voltage difference of transistor P3 that is cut off can be prevented from increasing excessively, thereby extending the life of transistor P3.

[0148] In addition, transistor P8 is turned on by the low-level second control clock signal CCK2. Therefore, node NP3 is coupled to node NP2. Transistor P10 is turned on by the low-level node voltage VNP3. For reference, at this time, transistor P9 is kept off by the high-level node voltage VNP4.

[0149] At the time point t4p, the high-level first power clock signal NCK1 is supplied. Therefore, the high-level first power clock signal NCK1 is conductively supplied to the first scan line GWNL1 as the high-level first scan signal GWN1 through the turned-on transistor P10.

[0150] At time point t5p, the first control clock signal CCK1 of low level is supplied. At this time, since the first power clock signal NCK1 of low level is supplied, transistors P1 and P2 are turned on. In addition, since the scan start signal FLM of low level is supplied, the node voltage VNP4 drops to a low level. Therefore, transistor P9 is turned on, and transistor P10 is diode-bonded.

[0151] At time point t6p, the second control clock signal CCK2 of low level is supplied. Therefore, transistor P8 is turned on, so that node voltage VNP2 drops along node voltage VNP3. In addition, node voltage VNP4 drops to a voltage lower than the low level due to the combination of transistor P5 and capacitor CP2. Therefore, the low level voltage of the first power line VGLL can be transmitted to the first scan line GWNL1 without being limited by the threshold voltage of transistor P11.

[0152] At time point t7p, a high-level first power clock signal NCK1 is supplied. At this time, since transistor P9 is turned on by node voltage VNP4, node voltage VNP3 rises to a high level. In this case, node voltage VNP2 also rises to a high level through turned-on transistor P8. Since transistor P10 is diode-coupled, the high-level first power clock signal NCK1 is not transmitted to the first scan line GWNL1.

[0153] Fig.12 is a diagram illustrating a scan driver according to another embodiment of the present disclosure.

[0154] Reference Fig.12 , shows an exemplary structure of a scan driver 30Na including a plurality of scan stages NST1a, NST2a, NST3a, NST4a, and NSTna.

[0155] The scanning driver 30Na may correspond to the reference Figure 1The second sub-scan driver of the scan driver 30 described above. According to an embodiment, when the transistor receiving the scan signal among the transistors of the pixel is composed of only N-type transistors, the pixel can be operated only by the scan driver 30Na. Therefore, the scan driver 30Na may not be a sub-scan driver, but may be an independent scan driver.

[0156] The scan driver 30Na may include a scan start input terminal INF, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, and a first output terminal OUT1. The scan driver 30Na may also include a power input terminal. Fig.12 is omitted.

[0157] Each of the scanning stages NST1a to NSTna may include a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, and a first output terminal OUT1. The first scanning stage NST1a may further include a scan start input terminal INF. The first scanning stage NST1a may be coupled to the scan start line FLML through the scan start input terminal INF. The second scanning stage NST2a may be coupled to the second power clock line NCKL2, the first control clock line CCKL1, the second control clock line CCKL2, the first carry line CRL1, the second carry line CRL2, and the second scanning line GWNL2.

[0158] Each of the scanning stages NST1a to NSTna may be coupled to the first power clock line NCKL1 or the second power clock line NCKL2 through its first input terminal IN1. Adjacent scanning stages among the scanning stages NST1a to NSTna may be coupled to different power clock lines NCKL1 and NCKL2. For example, the second scanning stage NST2a may be coupled to the second power clock line NCKL2, and the first scanning stage NST1a and the third scanning stage NST3a adjacent to the second scanning stage NST2a may be coupled to the first power clock line NCKL1. The first power clock line NCKL1 and the second power clock line NCKL2 may be alternately coupled to the scanning stages NST1a to NSTna. For example, the first power clock line NCKL1 may be coupled to the odd-numbered scanning stages NST1a, NST3a, ..., NSTna, and the second power clock line NCKL2 may be coupled to the even-numbered scanning stages NST2a and NST4a, etc. In contrast, the second power clock line NCKL2 may be coupled to odd-numbered scanning stages NST1a, NST3a, . . . , NSTna, and the first power clock line NCKL1 may be coupled to even-numbered scanning stages NST2a and NST4a, and so on.

[0159] Each of the scanning stages NST1a to NSTna may be coupled to the first control clock line CCKL1 or the second control clock line CCKL2 through its second input terminal IN2. Adjacent scanning stages among the scanning stages NST1a to NSTna may be coupled to different control clock lines CCKL1 and CCKL2 through the second input terminal IN2. For example, the second scanning stage NST2a may be coupled to the second control clock line CCKL2 through the second input terminal IN2, and the first scanning stage NST1a and the third scanning stage NST3a adjacent to the second scanning stage NST2a may be coupled to the first control clock line CCKL1 through the second input terminal IN2. The first control clock line CCKL1 and the second control clock line CCKL2 may be alternately coupled to the scanning stages NST1a to NSTna through the second input terminal IN2. For example, the odd-numbered scanning stages NST1a, NST3a, ..., NSTna can be coupled to the first control clock line CCKL1 through the second input terminal IN2, and the even-numbered scanning stages NST2a and NST4a, etc. can be coupled to the second control clock line CCKL2 through the second input terminal IN2. Conversely, the odd-numbered scanning stages NST1a, NST3a, ..., NSTna can be coupled to the second control clock line CCKL2 through the second input terminal IN2, and the even-numbered scanning stages NST2a and NST4a, etc. can be coupled to the first control clock line CCKL1 through the second input terminal IN2.

[0160] Each of the scanning stages NST1a to NSTna may be coupled to the second control clock line CCKL2 or the first control clock line CCKL1 through its third input terminal IN3. The control clock line connected through the third input terminal IN3 in each of the scanning stages NST1a to NSTna may be different from the control clock line connected through the second input terminal IN2.

[0161] The scanning stages NST1 a to NSTna may be coupled to the scanning lines GWNL1 , GWNL2 , GWNL3 , GWNL4 , and GWNLn through first output terminals OUT1 , respectively.

[0162] In order to reduce the clock frequency or implement other driving methods, the number of the power clock lines NCKL1 and NCKL2 and the control clock lines CCKL1 and CCKL2 may be changed.

[0163] In the following, we will mainly describe Fig.12 The scanning driver 30Na and Fig. 9 The difference between the scan driver 30N.

[0164] Scanning stages NST2a, NST3a, NST4a, ..., NSTna other than the first scanning stage NST1a may be coupled to carry lines CRL1, CRL2, CRL3, ..., CRL(n-1) of the previous scanning stage. For example, the second scanning stage NST2a may be coupled to the first carry line CRL1 of the first scanning stage NST1a.

[0165] The carry lines CRL1, CRL2, CRL3, ..., CRL(n-1) do not require separate external terminals. Fig.12 The scan driver 30Na and Fig. 9 The scan driver 30N may include external terminals IN1, IN2, IN3, INF and OUT1 having the same number and function. Fig. 9 Compared with the scan driver 30N, Fig.12 The scan driver 30Na does not require additional external terminals.

[0166] Fig.13 It is shown that the Fig.12 Diagram of the scan stage in a scan driver.

[0167] Reference Fig.13 , which is shown by way of example Fig.12 The first scanning stage NST1a of the scanning driver 30Na. Since the carry line of the previous scanning stage is coupled to the first electrode of the fifth transistor M5, Fig.13 The other scanning stages NST2a, NST3a, NST4a, ..., NSTna of the first scanning stage NST1a have substantially the same configuration as that of the first scanning stage NST1a, so repeated description will be omitted here. The clock line reference numerals coupled to the first to third input terminals IN1, IN2, and IN3 are Fig.12 Description.

[0168] The first scanning stage NST1a may include transistors M1 to M13 and capacitors CM1 to CM3. The transistors M1 to M13 may be P-type transistors.

[0169] A gate electrode of the first transistor M1 may be coupled to the first node NM1 , a first electrode of the first transistor M1 may be coupled to the first power clock line NCKL1 , and a second electrode of the first transistor M1 may be coupled to the first scan line GWNL1 .

[0170] A first electrode of the first capacitor CM1 may be coupled to the first node NM1 , and a second electrode of the first capacitor CM1 may be coupled to the first scan line GWNL1 .

[0171] A gate electrode of the second transistor M2 may be coupled to the second node NM2 , a first electrode of the second transistor M2 may be coupled to the first scan line GWNL1 , and a second electrode of the second transistor M2 may be coupled to the first power line VGLL.

[0172] A gate electrode of the third transistor M3 may be coupled to the second node NM2 , a first electrode of the third transistor M3 may be coupled to the third node NM3 , and a second electrode of the third transistor M3 may be coupled to the second control clock line CCKL2 .

[0173] A first electrode of the second capacitor CM2 may be coupled to the second node NM2 , and a second electrode of the second capacitor CM2 may be coupled to the third node NM3 .

[0174] The gate electrode of the fourth transistor M4 may be coupled to the first control clock line CCKL1, the first electrode of the fourth transistor M4 may be coupled to the second node NM2 through the eleventh transistor M11, and the second electrode of the fourth transistor M4 may be coupled to the first power line VGLL. When the eleventh transistor M11 is turned on, the eleventh transistor M11 may couple the first electrode of the fourth transistor M4 to the second node NM2.

[0175] A gate electrode of the fifth transistor M5 may be coupled to the first control clock line CCKL1, a first electrode of the fifth transistor M5 may be coupled to the scan start line FLML, and a second electrode of the fifth transistor M5 may be coupled to the fourth node NM4 through the twelfth transistor M12. When the twelfth transistor M12 is turned on, the twelfth transistor M12 may couple the second electrode of the fifth transistor M5 to the fourth node NM4.

[0176] The gate electrode of the sixth transistor M6 may be coupled to the fourth node NM4 through the twelfth transistor M12, the first electrode of the sixth transistor M6 may be coupled to the second node NM2 through the eleventh transistor M11, and the second electrode of the sixth transistor M6 may be coupled to the first control clock line CCKL1. When the eleventh transistor M11 is turned on, the eleventh transistor M11 may couple the first electrode of the sixth transistor M6 to the second node NM2.

[0177] The gate electrode of the seventh transistor M7 may be coupled to the second node NM2 through the eleventh transistor M11, the first electrode of the seventh transistor M7 may be coupled to the second power line VGHL, and the second electrode of the seventh transistor M7 may be coupled to the first carry line CRL1. When the eleventh transistor M11 is turned on, the eleventh transistor M11 may couple the gate electrode of the seventh transistor M7 to the second node NM2.

[0178] A gate electrode of the eighth transistor M8 may be coupled to the fourth node NM4 , a first electrode of the eighth transistor M8 may be coupled to the first carry line CRL1 , and a second electrode of the eighth transistor M8 may be coupled to the second control clock line CCKL2 .

[0179] A first electrode of the third capacitor CM3 may be coupled to the fourth node NM4 , and a second electrode of the third capacitor CM3 may be coupled to the first carry line CRL1 .

[0180] The gate electrode of the ninth transistor M9 may be coupled to the second control clock line CCKL2, the first electrode of the ninth transistor M9 may be coupled to the first carry line CRL1, and the second electrode of the ninth transistor M9 may be coupled to the first node NM1 through the thirteenth transistor M13. When the thirteenth transistor M13 is turned on, the thirteenth transistor M13 may couple the second electrode of the ninth transistor M9 to the first node NM1.

[0181] A gate electrode of the tenth transistor M10 may be coupled to the fourth node NM4 , a first electrode of the tenth transistor M10 may be coupled to the first node NM1 , and a second electrode of the tenth transistor M10 may be coupled to the first power line VGLL.

[0182] A gate electrode of the eleventh transistor M11 may be coupled to the first power line VGLL, a first electrode of the eleventh transistor M11 may be coupled to the first electrode of the fourth transistor M4 , and a second electrode of the eleventh transistor M11 may be coupled to the second node NM2 .

[0183] A gate electrode of the twelfth transistor M12 may be coupled to the first power line VGLL, a first electrode of the twelfth transistor M12 may be coupled to the second electrode of the fifth transistor M5 , and a second electrode of the twelfth transistor M12 may be coupled to the fourth node NM4 .

[0184] A gate electrode of the thirteenth transistor M13 may be coupled to the first power line VGLL, a first electrode of the thirteenth transistor M13 may be coupled to the second electrode of the ninth transistor M9 , and a second electrode of the thirteenth transistor M13 may be coupled to the first node NM1 .

[0185] Fig.13 The first scanning stage NST1a comprises Fig.10 The number of the first scanning stage NST1 is the same as the number of internal components M1 to M13 and CM1 to CM3. Fig.10 Compared with the first scanning stage NST1, Fig.13 The first scanning stage NST1a does not require an additional dead zone.

[0186] Fig.14 Is shown driving Fig.13FIG. 10A of the scan-level approach.

[0187] Fig.14 A timing diagram of a scan start signal FLM applied to a scan start line FLML, a first control clock signal CCK1 applied to a first control clock line CCKL1, a second control clock signal CCK2 applied to a second control clock line CCKL2, a first power clock signal NCK1 applied to a first power clock line NCKL1, a second power clock signal NCK2 applied to a second power clock line NCKL2, a first node voltage VNM1 of a first node NM1, a second node voltage VNM2 of a second node NM2, a third node voltage VNM3 of a third node NM3, a fourth node voltage VNP4 of a fourth node NM4, and a first scan signal GWN1 applied to a first scan line GWNL1 is shown. The interval between adjacent pulses in a horizontal synchronization signal can be referred to as a horizontal period 1H. The first voltage VCM1 is a voltage difference between a first electrode and a second electrode of a first capacitor CM1, the second voltage VCM2 is a voltage difference between a first electrode and a second electrode of a second capacitor CM2, and the third voltage VCM3 is a voltage difference between a first electrode and a second electrode of a third capacitor CM3.

[0188] A high level voltage may be applied to the second power line VGHL, and a low level voltage may be applied to the first power line VGLL. Since the transistors M11, M12, and M13 having gate electrodes coupled to the first power line VGLL are turned on in most periods when describing the driving method, the description of the transistors M11, M12, and M13 will be omitted except for specific cases.

[0189] First, at the time point t1m, the scanning start signal FLM of a low level (on level) is supplied. At this time, since the fifth transistor M5 is turned off by the first control clock signal CCK1 of a high level, the fourth node voltage VNM4 does not change.

[0190] At time point t2m, the low-level first control clock signal CCK1 is supplied. Therefore, the fifth transistor M5 and the fourth transistor M4 are turned on. As the fifth transistor M5 is turned on, the low-level scan start signal FLM is transmitted to the fourth node NM4, and the fourth node voltage VNM4 drops to a low level.

[0191] As the fourth node voltage VNM4 drops, the tenth transistor M10 is turned on, and the charge accumulated in the first node NM1 can flow to the first power line VGLL through the tenth transistor M10. Therefore, the voltage of the first node NM1 can drop. However, the first node voltage VNM1 can be greater than the voltage of the first power line VGLL by the threshold voltage of the tenth transistor M10.

[0192] At time point t3m, a high-level first control clock signal CCK1 is supplied. Therefore, the high-level first control clock signal CCK1 is supplied to the second node NM2 through the sixth transistor M6 turned on according to the low-level fourth node voltage VNM4 and the turned-on eleventh transistor M11. Therefore, the second node voltage VNM2 rises.

[0193] At the time point t4m, the second control clock signal CCK2 of a low level is supplied.

[0194] Therefore, the second control clock signal CCK2 of a low level is supplied to the first carry line CRL1 through the eighth transistor M8 turned on according to the fourth node voltage VNM4 of a low level.

[0195] In addition, the fourth node voltage VNM4 may drop to a level lower than the low level due to the coupling of the third capacitor CM3. Therefore, a voltage having a level lower than the low level may be applied to the gate electrode of the tenth transistor M10. Therefore, the low level voltage of the first power line VGLL may be transmitted to the first node NM1 without being limited by the threshold voltage of the tenth transistor M10. That is, the charge accumulated in the first node NM1 may fully flow to the first power line VGLL.

[0196] Such a drop in the fourth node voltage VNM4 does not significantly affect the voltage of the second electrode of the fifth transistor M5. Since the low-level voltage is applied to the gate electrode of the twelfth transistor M12, the voltage of the first electrode (source electrode) of the twelfth transistor M12 is prevented from being smaller than the sum of the absolute value of the low level and the threshold of the transistor M12. Therefore, the source-drain voltage difference of the cut-off fifth transistor M5 can be prevented from excessively increasing, thereby extending the life of the fifth transistor M5.

[0197] At time point t5m, the high level first power clock signal NCK1 may be supplied. Since the first transistor M1 is turned on by the first node voltage VNM1, the high level first power clock signal NCK1 may be supplied to the first scan line GWNL1 as the first scan signal GWN1.

[0198] At the time point t6m, the first power clock signal NCK1 of a low level may be supplied. The first node voltage VNM1 may drop to a level lower than the low level due to coupling of the first capacitor CM1.

[0199] Such a drop in the first node voltage VNM1 does not significantly affect the voltage of the second electrode of the ninth transistor M9. Since the low-level voltage is applied to the gate electrode of the thirteenth transistor M13, the voltage of the first electrode (source electrode) of the thirteenth transistor M13 is prevented from being smaller than the sum of the absolute value of the low level and the threshold value of the thirteenth transistor M13. Therefore, the source-drain voltage difference of the ninth transistor M9 that is cut off can be prevented from increasing excessively, thereby extending the life of the ninth transistor M9.

[0200] At time point t7m, the low-level first control clock signal CCK1 may be supplied. Therefore, the fifth transistor M5 is turned on, and the high-level scan start signal FLM is applied to the fourth node NM4. In addition, the fourth transistor M4 may be turned on, and the low-level voltage of the first power line VGLL may be applied to the second node NM2 through the turned-on eleventh transistor M11.

[0201] At time point t8m, a low-level second control clock signal CCK2 may be supplied. The low-level second control clock signal CCK2 may be supplied to the third node NM3 through the third transistor M3 (the third transistor M3 is turned on by the low-level second node voltage VNM2). Therefore, the second node voltage VNM2 drops to a level lower than the low level due to the coupling of the second capacitor CM2. Therefore, the low-level voltage of the first power supply line VGLL may be transmitted to the first scan line GWNL1 without being limited by the threshold voltage of the second transistor M2.

[0202] Such a drop in the second node voltage VNM2 does not significantly affect the voltage of the first electrode of the sixth transistor M6. Since the low-level voltage is applied to the gate electrode of the eleventh transistor M11, the voltage of the first electrode (source electrode) of the eleventh transistor M11 is prevented from being smaller than the sum of the absolute value of the low level and the threshold value of the eleventh transistor M11. Therefore, it is possible to prevent the source-drain voltage difference of the cut-off sixth transistor M6 from excessively increasing, thereby extending the life of the sixth transistor M6.

[0203] In addition, since the ninth transistor M9 is turned on, the high level voltage of the second power line VGHL is applied to the first node NM1 through the seventh transistor M7, the ninth transistor M9, and the thirteenth transistor M13.

[0204] At the time point t9m, the first power clock signal NCK1 of a high level may be supplied. However, since the first transistor M1 is kept turned off by the first node voltage VNM1 of a high level, the voltage of the first scan line GWNL1 is kept at a low level.

[0205] The time other than the time t1m to t9m for supplying the high-level first scanning signal GWN1 occupies most of the frame period (about 99% of the frame period). Fig.14 It can be seen that the voltages VCM1, VCM2 and VCM3 at both ends of the capacitors CM1, CM2 and CM3 do not change before the time point t1m and after the time point t9m. That is, since the charging and discharging of the capacitors CM1, CM2 and CM3 are prevented in most frame periods, power consumption can be reduced.

[0206] Reference Fig.10 and Fig.11 In the comparative example of FIG. 1 , the voltage VCP3 at both ends of the capacitor CP3 changes continuously even before the time point t1p and after the time point t7p. That is, since the charging and discharging of the capacitor CP3 occur continuously, the power consumption is slightly greater than Fig.13 and Fig.14 The power consumption in the embodiment of FIG.

[0207] In addition, refer to Fig.10 and Fig.11 In the comparative example of FIG. 4 , there is the following problem: the node voltage VNP3 does not drop sufficiently at the time point t3p, thereby not providing a sufficient source-drain voltage difference to the transistor P10. That is, when the low-level second control clock signal CCK2 is supplied to the node NP3 through the transistor P8, the low-level second control clock signal CCK2 is limited by the threshold voltage of the transistor P8. In addition, at the time point t4p, the first power supply clock signal NCK1 may increase, and the increase of the node voltage VNP3 may be induced by the coupling of the capacitor CP1.

[0208] On the contrary, according to Fig.13 and Fig.14 In the embodiment of the present invention, as described above, at the time point t4m, the low level voltage of the first power line VGLL can be transmitted to the first node NM1 without being limited by the threshold voltage of the tenth transistor M10. Therefore, at the time point t4m, the voltage of the first node NM1 can be sufficiently reduced and a sufficient source-drain voltage difference can be provided to the first transistor M1. In addition, even if the first power clock signal NCK1 increases at the time point t5m, there is no capacitor for coupling the first power clock line NCKL1 to the first node NM1, thereby not causing the rise of the first node voltage VNM1.

[0209] Fig.15 Shows Fig.13 Scan-level modifications, Fig.16 Is shown driving Fig.15 FIG. 10A of the scan-level approach.

[0210] Apart from Fig.15 The first scanning stage NST1b does not include the tenth transistor M10. Fig.15 The first scanning stage NST1b and Fig.13 Since other configurations remain the same, repeated descriptions thereof will be omitted here.

[0211] Reference Fig.16 , the first node voltage VNM1 of the first scanning stage NST1b does not drop at the time point t2m'. The first node voltage VNM1 of the first scanning stage NST1b starts to drop from the time point t4m'. Fig.16 The time point t2m' can correspond to Fig.14 At time point t2m, Fig.16 The time point t4m' can correspond to Fig.14 The time point t4m (see the dotted waveform).

[0212] Fig.16 The first scanning stage NST1b may reduce the dead zone by removing the tenth transistor M10.

[0213] Fig.17 Shows Fig.13 Another modification of the scanning level.

[0214] Apart from Fig.17 The first scanning stage NST1c does not include the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13. Fig.17 The first scanning stage NST1c and Fig.13 Since other configurations remain the same, repeated descriptions thereof will be omitted here.

[0215] The first scanning stage NST1c may reduce the dead zone by removing the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13.

[0216] Fig.18 Shows Fig.13 Further modifications to the scanning level.

[0217] Apart from Fig.18 The first scanning stage NST1d does not include the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13. Fig.18 The first scanning stage NST1d and Fig.13 Since other configurations remain the same, repeated descriptions thereof will be omitted here.

[0218] and Fig.13 The first scanning stage NST1a, Fig.15 The first scanning stage NST1b and Fig.17 Compared with the first scanning stage NST1c, the first scanning stage NST1d can reduce a larger dead zone.

[0219] The scan driver and the display device including the same according to the present disclosure can sufficiently increase the voltage difference between the gate electrode and the source electrode of the buffer transistor without providing an additional external terminal or internal element, and can minimize the charging and discharging of the internal capacitor.

[0220] The detailed description of the disclosure described with reference to the accompanying drawings is illustrative only, which is only used for the purpose of describing the disclosure, and is not used to limit the meaning or scope of the disclosure as defined in the attached claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalents of the disclosure are possible. Therefore, the limits and scope of the inventive concept should be determined by the technical spirit of the following claims.

Claims

1. A scanning driver, the scanning driver comprising a plurality of scanning stages, in, A first scanning stage of the plurality of scanning stages comprises: a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to a first scan line; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to a first power line; a third transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor including a first electrode coupled to the second node and a second electrode coupled to the third node, and Wherein, the first power line and the first control clock line are separated from each other.

2. The scan driver according to claim 1, wherein: The first scan stage further includes a fourth transistor including a gate electrode coupled to a second control clock line, a first electrode coupled to the second node, and a second electrode coupled to the first power line.

3. The scan driver according to claim 2, wherein: The first scan stage further includes a fifth transistor including a gate electrode coupled to the second control clock line, a first electrode coupled to a scan start line, and a second electrode coupled to a fourth node.

4. The scan driver according to claim 3, wherein: The first scan stage further includes a sixth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the second node, and a second electrode coupled to the second control clock line.

5. The scan driver according to claim 4, wherein: The first scan stage further includes a seventh transistor including a gate electrode coupled to the second node, a first electrode coupled to a second power line, and a second electrode coupled to a first carry line.

6. The scan driver according to claim 5, wherein: The first scan stage also includes an eighth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the first carry line, and a second electrode coupled to the first control clock line.

7. The scan driver according to claim 6, wherein: The first scan stage also includes a third capacitor including a first electrode coupled to the fourth node and a second electrode coupled to the first carry line.

8. The scan driver according to claim 7, wherein: The first scan stage further includes a ninth transistor including a gate electrode coupled to the first control clock line, a first electrode coupled to the first carry line, and a second electrode coupled to the first node.

9. The scan driver according to claim 8, wherein: The first scan stage also includes a tenth transistor including a gate electrode coupled to the fourth node, a first electrode coupled to the first node, and a second electrode coupled to the first power line.

10. The scan driver according to claim 9, wherein: The first scanning stage also includes: an eleventh transistor configured to couple the first electrode of the fourth transistor to the second node, wherein the eleventh transistor includes a gate electrode coupled to the first power line, a first electrode coupled to the first electrode of the fourth transistor, and a second electrode coupled to the second node; a twelfth transistor configured to couple the second electrode of the fifth transistor to the fourth node, wherein the twelfth transistor includes a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the fifth transistor, and a second electrode coupled to the fourth node; and a thirteenth transistor configured to couple the second electrode of the ninth transistor to the first node, wherein the thirteenth transistor includes a gate electrode coupled to the first power line, a first electrode coupled to the second electrode of the ninth transistor, and a second electrode coupled to the first node, and The plurality of scan stages include a second scan stage coupled to a second power clock line, the first control clock line, the second control clock line, the first carry line, the second carry line and a second scan line.

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