A method and apparatus for constructing a parity check matrix of an LDPC code

Abstract

The application discloses a method for constructing an LDPC code check matrix, comprising: setting at least one of row weight λ and column weight γ of the LDPC code check matrix as a fixed value (constant); setting z of a dimension z×z of a cyclic permutation matrix CPM as a predetermined value; calculating a base matrix of the corresponding LDPC code check matrix based on LDPC code length, code rate, row weight λ and column weight γ, and the cyclic permutation matrix CPM of the dimension z×z; and obtaining the LDPC code check matrix through expansion of the base matrix. According to the technical scheme provided by the application, the code length of the LDPC code is shortened, so that the transmission of small data can be performed in less OFDM symbol (as low as 1 symbol), thereby effectively reducing the time delay and cost. The regular / quasi-regular LDPC code has a very low error code platform, and the reliability of transmission is improved.

Description

Technical Field

[0001] This invention belongs to the field of mobile communication technology, and particularly relates to a method and apparatus for constructing an LDPC code parity check matrix for mobile communication. Background Technology

[0002] The ITU has identified three major application scenarios for 5G: eMBB (enhanced Mobile Broadband), mMTC (massive Machine Type Communication), and URLLC (Ultra-Reliable and Low Latency Communications). Currently, operators' initial 5G deployments are primarily focused on eMBB services.

[0003] With the rise of the Industrial Internet of Things (IIoT) and the emergence of Industry 4.0, uRLLC applications in the IIoT field have gained increasing attention. Various scenarios within the IIoT domain have raised requirements for latency and reliability. Specifically, in the early stages of 5G, uRLLC is primarily applied in Virtual Reality (VR) / Augmented Reality (AR) and other fields, requiring a user plane latency of 1ms and a packet error rate of less than 10^65%. -5 The reliability requirements are increasing. With the further development of IIoT, URLLC services will be increasingly applied in areas such as factory automation (motion control, control-to-control communication), transmission (remote driving), and power distribution (smart grid). These scenarios place higher demands on latency and reliability. Specifically, remote driving requires achieving 10... -5 For reliability, the power distribution system requires achieving 10 GHz with a user plane latency of 2ms. -6 The reliability requirement is high, while factory automation scenarios require achieving 10 GHz with a user plane latency of 1ms. -6 Reliability.

[0004] Regarding the progress in reliability and low latency research for URLLC application scenarios, the latency reduction schemes proposed in 3GPP Rel-15 include:

[0005] (1) Supports more flexible frame structure: 4G LTE only supports a subcarrier spacing of 15kHz, and each subframe (fixed length 1ms) contains two time slots, each time slot contains 7 OFDM symbols. In contrast, 5G / NR supports multiple subcarrier spacings, and sub-6GHz bands can support subcarrier spacing configurations such as 15kHz / 30kHz / 60kHz. Each subframe (fixed length 1ms) contains 2μ time slots, thereby reducing the air interface transmission time of each slot.

[0006] (2) Support for more flexible scheduling units: The smallest scheduling unit of 4G scheduling is the time slot, while 5G supports micro-slot scheduling, i.e., "mini" time slot (minimum 2 symbols).

[0007] (3) Support for high-priority URLLC transmission: In order to ensure the needs of high-priority URLLC services, 5G / NR proposes that URLLC services can preempt eMBB service resources to reduce latency.

[0008] (4) Introduce Mobile Edge Computing (MEC) technology. By deploying general-purpose servers on the radio access side, the Radio Access Network (RAN) is equipped with IT and cloud computing capabilities, thereby enabling service localization and reducing the transmission latency of data from the base station to the core network.

[0009] To further meet the requirements of high reliability and ultra-low latency in URLLC, more technical solutions and methods need to be proposed. Summary of the Invention

[0010] In view of this, the technical problem to be solved by the present invention is to provide a method and apparatus for constructing LDPC codes in mobile communications, so as to adapt to new application scenarios and requirements.

[0011] This invention provides a method for constructing an LDPC code parity-check matrix, comprising:

[0012] Set at least one of the row weight λ and column weight γ of the LDPC parity-check matrix to a fixed value (constant);

[0013] Set the z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value;

[0014] Based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM, the base matrix of the corresponding LDPC code parity check matrix is ​​calculated.

[0015] The LDPC parity-check matrix is ​​obtained by expanding the base matrix.

[0016] Preferably, the LDPC code length is 448; and / or

[0017] When the code rate is 1 / 2, the corresponding code is (448,224) LDPC code.

[0018] When the code rate is 4 / 7, the corresponding code is (448,256) LDPC code.

[0019] Preferably, z = 28, corresponding to a CPM dimension of 28×28, characterized by a row weight λ of 6 and a column weight γ of 3, and is a regular LDPC code; or

[0020] Preferably, z = 32, corresponding to a CPM dimension of 32×32, characterized by a row weight λ of 8 and a column weight γ of 3 or 4, which is a quasi-regular LDPC code.

[0021] In a specific embodiment, more appropriately, when the LDPC code length is 448 and the code rate is 1 / 2, the basis matrix of the parity-check matrix of the corresponding (448, 224) LDPC code is:

[0022] -1 -1 6 -1 27 -1 -1 20 -1 -1 22 -1 -1 7 13 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 13 19 -1 -1 -1 -1 9 27 -1 -1 20 -1 -1 22 -1 -1 7 -1 19 -1 -1 10 -1 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 25 -1 3 -1 -1 6 -1 27 -1 -1 20 -1 -1 -1 21 10 -1 25 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 3 -1 -1 10 -1 25 19 -1 -1 -1 6 -1 -1 0 -1 20 -1 -1 2 -1 10 -1 -1 19 -1 -1 -1 6 9 -1 0 -1 -1 -1

[0023] In a specific embodiment, more preferably, when the LDPC code length is 448 and the code rate is 4 / 7, the base matrix of the parity-check matrix of the corresponding (448,256) LDPC code is:

[0024] 4 14 13 -1 5 21 -1 15 -1 11 -1 -1 7 -1 -1 1 15 2 -1 6 -1 4 0 -1 11 -1 -1 8 9 -1 2 14 3 -1 7 -1 5 13 -1 12 -1 -1 -1 10 -1 10 15 4 -1 -1 -1 14 6 -1 13 5 6 -1 11 -1 10 -1 5 12 -1 -1 13 7 -1 14 15 7 -1 3 -1 -1 20 -1 13 -1 -1 14 8 4

[0025] The LDPC parity-check matrix is ​​obtained by expanding the basis matrix, specifically as follows:

[0026] Each element of the basis matrix is ​​replaced by a cyclic permutation matrix CPM, with dimensions z×z. When the element values ​​of the basis matrix are greater than or equal to 0, CPM is a cyclic shift of the rows of the z×z identity matrix, and the element value represents the number of right shifts of 1s in the first row of CPM. When the element values ​​of the basis matrix are less than 0, CPM is a z×z matrix of all zeros. The rule for the cyclic shift is as follows: assuming the element value of the basis matrix is ​​s, each row of the z×z identity matrix is ​​cyclically shifted s times.

[0027] This invention also provides an apparatus for constructing an LDPC code parity-check matrix, comprising:

[0028] The setting unit is used to set at least one of the row weight λ and column weight γ of the LDPC parity matrix to a fixed value (constant);

[0029] Preset unit, used to set z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value;

[0030] The processing unit calculates the base matrix of the LDPC code parity check matrix based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM.

[0031] The generating unit is used to expand the LDPC parity-check matrix through the basis matrix.

[0032] Preferably, the LDPC code length is 448; and / or

[0033] When the code rate is 1 / 2, the corresponding code is (448,224) LDPC code;

[0034] When the code rate is 4 / 7, the corresponding code is (448,256) LDPC code.

[0035] More appropriately, z = 28, corresponding to a CPM dimension of 28×28, characterized by a row weight λ of 6 and a column weight γ of 3, which is a regular LDPC code; or

[0036] More appropriately, z = 32, corresponding to a CPM dimension of 32×32, characterized by a row weight λ of 8 and a column weight γ of 3 or 4, which is a quasi-regular LDPC code.

[0037] Preferably, when the LDPC code length is 448 and the code rate is 1 / 2, the basis matrix of the parity-check matrix of the corresponding (448, 224) LDPC code is:

[0038] -1 -1 6 -1 27 -1 -1 20 -1 -1 22 -1 -1 7 13 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 13 19 -1 -1 -1 -1 9 27 -1 -1 20 -1 -1 22 -1 -1 7 -1 19 -1 -1 10 -1 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 25 -1 3 -1 -1 6 -1 27 -1 -1 20 -1 -1 -1 21 10 -1 25 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 3 -1 -1 10 -1 25 19 -1 -1 -1 6 -1 -1 0 -1 20 -1 -1 2 -1 10 -1 -1 19 -1 -1 -1 6 9 -1 0 -1 -1 -1

[0039] Preferably, when the LDPC code length is 448 and the code rate is 4 / 7, the base matrix of the parity-check matrix of the corresponding (448, 256) LDPC code is:

[0040]

[0041]

[0042] According to the technical solution provided by this invention, the code length of LDPC codes is shortened, enabling the transmission of small amounts of data in fewer OFDM symbols (as low as one symbol), thereby effectively reducing latency and overhead. Regular / quasi-regular LDPC codes have a very low error plateau, improving transmission reliability.

[0043] For the foregoing and related purposes, one or more embodiments include features that will be described in detail below and particularly pointed out in the claims. The following description and accompanying drawings detail certain exemplary aspects and indicate only a few of the various ways in which the principles of the various embodiments can be utilized. Other benefits and novel features will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents. Attached Figure Description

[0044] Figure 1 This is a flowchart of a method for constructing an LDPC code parity check matrix provided by the present invention;

[0045] Figure 2 This is a schematic diagram of an apparatus for constructing an LDPC code parity check matrix provided in an embodiment of the present invention. Detailed Implementation

[0046] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments. The scope of embodiments of the invention includes the entire scope of the claims and all available equivalents thereof. In this document, these embodiments of the invention may be referred to individually or collectively with the term "invention," which is merely for convenience and is not intended to automatically limit the scope of the application to any single invention or inventive concept if more than one invention is disclosed.

[0047] The technical solution and characteristics of the present invention are described below.

[0048] During channel coding, the scrambled output data bit sequence It performs FEC protection and supports both convolutional coding and LDPC coding for forward error correction.

[0049] To meet the ultra-low latency requirements of URLLC, a better solution is proposed to effectively reduce latency.

[0050] In scenarios such as URLLC and mMTC, the transmitted data bytes are very small (within 32 bytes). Using LDPC with a code length of 1344 / 2688 / 5376 would cause a large amount of redundancy overhead. The solution proposed in this invention adopts an LDPC design with an increased code length of 448 to meet the requirements of low latency and low overhead.

[0051] LDPC codes are high-performance block error-correcting codes characterized by sparse parity-check matrices and ease of parallel decoding. If N represents the code length, K represents the information bit length, M represents the parity bit length, γ represents the column weight, λ represents the row weight, and R represents the code rate, then the LDPC code can be represented as an (N, K)LDPC code, with a code rate R = K / N. If γ and λ are constants, the LDPC code is a regular LDPC code; otherwise, it is an irregular LDPC code. If only one of γ and λ is a constant, then the LDPC code is a quasi-regular LDPC code.

[0052] Reference Figure 1 The present invention provides a method for constructing an LDPC code parity-check matrix, comprising:

[0053] S101, set at least one of the row weight λ and column weight γ of the LDPC parity matrix to a fixed value (constant);

[0054] S102, set the z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value;

[0055] S103, based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM, the base matrix of the corresponding LDPC code parity check matrix is ​​calculated.

[0056] S104, the LDPC parity-check matrix is ​​obtained by expanding the base matrix.

[0057] In a specific embodiment, step S104 involves obtaining the LDPC parity-check matrix through basis matrix expansion, specifically as follows:

[0058] Each element of the basis matrix is ​​replaced by a cyclic permutation matrix CPM, which has dimensions z×z. When the element values ​​of the basis matrix are greater than or equal to 0, CPM is a row cyclic shift of the z×z identity matrix, and the element value represents the number of 1s in the first row of CPM shifted to the right. When the element values ​​of the basis matrix are less than 0, CPM is a z×z matrix of all zeros.

[0059] The rule for row cyclic shifting is as follows: assuming the element value of the basis matrix is ​​s, each row of the z×z identity matrix is ​​cyclically shifted, and the number of shifts is s.

[0060] In the technical solution of this invention, the LDPC code length is 448, and the code rate is either 1 / 2 or 4 / 7, corresponding to the (448,224) LDPC code and the (448,256) LDPC code. Both have a QC (quasi-cyclic) structure in their parity-check matrices. The (448,224) LDPC code is a regular code, and the (448,256) LDPC code is a quasi-regular code.

[0061] For example, when z = 5 and s = 2, the identity matrix and the matrix after row circular shift are shown below:

[0062] 5×5 identity matrix: The matrix after row circular shifting twice:

[0063] When the LDPC code length is 448 and the code rate is 1 / 2, the basis matrix of the parity-check matrix of the corresponding (448, 224) LDPC code is shown in Table 1, z = 28, corresponding to a CPM dimension of 28 × 28. Its characteristics are a row weight λ of 6 and a column weight γ of 3, making it a regular LDPC code.

[0064] Table 1. Basis matrix of the parity-check matrix of LDPC code (448,224)

[0065] -1 -1 6 -1 27 -1 -1 20 -1 -1 22 -1 -1 7 13 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 13 19 -1 -1 -1 -1 9 27 -1 -1 20 -1 -1 22 -1 -1 7 -1 19 -1 -1 10 -1 -1 27 0 -1 -1 -1 -1 22 21 -1 -1 25 -1 3 -1 -1 6 -1 27 -1 -1 20 -1 -1 -1 21 10 -1 25 -1 -1 -1 -1 6 -1 27 0 -1 -1 -1 3 -1 -1 10 -1 25 19 -1 -1 -1 6 -1 -1 0 -1 20 -1 -1 2 -1 10 -1 -1 19 -1 -1 -1 6 9 -1 0 -1 -1 -1

[0066] When the LDPC code length is 448 and the code rate is 4 / 7, the basis matrix of the parity-check matrix of the corresponding (448,256) LDPC code is shown in Table 2, z = 32, corresponding to a CPM dimension of 32×32. Its characteristics are a row weight λ of 8 and a column weight γ of 3 or 4, making it a quasi-regular LDPC code.

[0067] Table 2 (448,256) Base matrix of the parity-check matrix of LDPC codes

[0068]

[0069]

[0070] This invention also provides an apparatus 20 for constructing an LDPC code parity-check matrix, such as... Figure 2 As shown, it includes:

[0071] Setting unit 210 is used to set at least one of the row weight λ and column weight γ of the LDPC parity matrix to a fixed value (constant);

[0072] Preset unit 220 is used to set the z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value;

[0073] Processing unit 230 calculates the base matrix of the LDPC code parity check matrix based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM.

[0074] Generating unit 240 obtains the LDPC parity-check matrix through base matrix expansion.

[0075] In this embodiment, an LDPC code length of 448 is used; and / or

[0076] When the code rate is 1 / 2, the corresponding code is (448,224) LDPC code;

[0077] When the code rate is 4 / 7, the corresponding code is (448,256) LDPC code.

[0078] In a specific embodiment, the preferred parameters are as follows:

[0079] z = 28, corresponding to a CPM dimension of 28×28, characterized by a row weight λ of 6 and a column weight γ of 3, resulting in a regular LDPC code; or

[0080] z = 32, corresponding to a CPM dimension of 32×32, row weight λ of 8, and column weight γ of 3 or 4, resulting in a quasi-regular LDPC code.

[0081] In summary, the technical solution provided by this invention shortens the code length of the LDPC code, enabling the transmission of small amounts of data to be carried out in fewer OFDM symbols (as low as 1 symbol), thereby effectively reducing latency and overhead.

[0082] Those skilled in the art will understand that the various exemplary method steps and apparatus units described herein in conjunction with the disclosed embodiments can be implemented in electronic hardware, software, or a combination of both. To clearly illustrate the interchangeability between hardware and software, the various exemplary steps and units have been generally described above in their functional form. Whether this functionality is implemented in hardware or software depends on the specific application and the design constraints implemented by the entire system. Those skilled in the art can implement the described functionality in various ways for each specific application, but the result of such implementation should not be construed as departing from the scope of the invention.

[0083] The steps of the methods described in conjunction with the above-disclosed embodiments can be directly embodied in hardware, software modules executed by a processor, or a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the art. A typical storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. In an alternative embodiment, the storage medium is a component of the processor. The processor and storage medium may reside in an ASIC. This ASIC may reside in a user station. In an alternative embodiment, the processor and storage medium may exist as discrete components in a user station.

[0084] Based on the disclosed embodiments, those skilled in the art can implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can also be applied to other embodiments without departing from the scope and spirit of the invention. The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for constructing an LDPC code parity-check matrix, characterized in that, include: Set at least one of the row weight λ and column weight γ of the LDPC parity matrix to a constant value; Set the z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value; Based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM, the base matrix of the corresponding LDPC code parity check matrix is ​​calculated. The LDPC parity-check matrix is ​​obtained by expanding the base matrix. The LDPC code length is 448; when the code rate is 1 / 2, the corresponding code is (448, 224) LDPC code; when the code rate is 4 / 7, the corresponding code is (448, 256) LDPC code. z=28 corresponds to a CPM dimension of 28×28, characterized by a row weight λ of 6 and a column weight γ of 3, which is a regular LDPC code; or z=32 corresponds to a CPM dimension of 32×32, characterized by a row weight λ of 8 and a column weight γ of 3 or 4, which is a quasi-regular LDPC code. The process of obtaining the LDPC parity-check matrix through basis matrix expansion includes: Each element of the basis matrix is ​​replaced by a cyclic permutation matrix CPM, with dimensions z×z. When the element values ​​of the basis matrix are greater than or equal to 0, CPM is a cyclic shift of the rows of the z×z identity matrix, and the element value represents the number of right shifts of 1s in the first row of CPM. When the element values ​​of the basis matrix are less than 0, CPM is a z×z matrix of all zeros. The rule for the cyclic shift is as follows: assuming the element value of the basis matrix is ​​s, each row of the z×z identity matrix is ​​cyclically shifted s times.

2. The method for constructing the LDPC code parity-check matrix as described in claim 1, characterized in that, When the LDPC code length is 448 and the code rate is 1 / 2, the basis matrix of the parity-check matrix of the corresponding (448, 224) LDPC code is: 。 3. The method for constructing the LDPC code parity-check matrix as described in claim 1, characterized in that, When the LDPC code length is 448 and the code rate is 4 / 7, the base matrix of the parity-check matrix for the (448, 256) LDPC code is: 。 4. An apparatus for constructing an LDPC code parity-check matrix, characterized in that, include: The setting unit is used to set at least one of the row weight λ and column weight γ of the LDPC parity matrix to a constant fixed value; Preset unit, used to set z of the z×z dimension of the cyclic permutation matrix CPM to a predetermined value; The processing unit calculates the base matrix of the LDPC code parity check matrix based on the LDPC code length, code rate, row weight λ and column weight γ, and the z×z cyclic permutation matrix CPM. The generation unit is used to expand the LDPC parity-check matrix using the basis matrix. The LDPC code length is 448; when the code rate is 1 / 2, the corresponding code is (448, 224) LDPC code; When the code rate is 4 / 7, the corresponding code is (448,256) LDPC code; z=28 corresponds to a CPM dimension of 28×28, characterized by a row weight λ of 6 and a column weight γ of 3, which is a regular LDPC code; or z=32 corresponds to a CPM dimension of 32×32, characterized by a row weight λ of 8 and a column weight γ of 3 or 4, which is a quasi-regular LDPC code. The generation unit obtains the LDPC parity-check matrix through basis matrix expansion, including: Each element of the basis matrix is ​​replaced by a cyclic permutation matrix CPM, with dimensions z×z. When the element values ​​of the basis matrix are greater than or equal to 0, CPM is a row cyclic shift of the z×z identity matrix, and the element value represents the number of right shifts of 1s in the first row of CPM. When the element values ​​of the basis matrix are less than 0, CPM is a z×z matrix of all zeros. The rule for the row cyclic shift is as follows: assuming the element value of the basis matrix is ​​s, each row of the z×z identity matrix is ​​cyclically shifted to the right by s times.

5. The apparatus for constructing an LDPC code parity-check matrix as described in claim 4, characterized in that, When the LDPC code length is 448 and the code rate is 1 / 2, the basis matrix of the parity-check matrix of the corresponding (448, 224) LDPC code is: ； When the LDPC code length is 448 and the code rate is 4 / 7, the base matrix of the parity-check matrix of the corresponding (448, 256) LDPC code is: 。

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