Display device

Abstract

A display device is provided. The display device includes a gain provider to gradually decrease a gain value from a first time point at which a first period elapses from a time point at which an enable signal is generated, and a plurality of pixels to receive a data voltage determined by the gain value and an input gray value. The gain provider determines a length of the first period according to a first load value based on the input gray value at the time point at which the enable signal is generated.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0021277 filed on February 20, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to a display device, and more particularly to a display device capable of reducing flicker according to an image mode while using a screen saver function. Background Art

[0003] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly used.

[0004] The display device may include a plurality of pixels and display frames by combining the light emitted from the pixels. When the plurality of frames are sequentially displayed, the user may recognize the frames as images (moving images or still images).

[0005] When displaying a still image, a screen saver function that reduces image brightness can prevent afterimages and reduce power consumption. However, when the still image changes to a moving image, the image brightness needs to be increased again, and flickering may occur depending on the image mode. Therefore, there is a need to develop a novel display device that improves display quality and reduces power consumption. Summary of the Invention

[0006] The present embodiment provides a display device capable of reducing flicker according to an image mode while using a screen saver function.

[0007] According to one aspect of the present disclosure, a display device is provided, including: a gain provider configured to gradually reduce a gain value from a first moment after a first period of time has passed since a moment when an enable signal is generated; and a plurality of pixels configured to receive a data voltage determined by the gain value and an input grayscale value, wherein the gain provider determines a length of the first period of time according to a first load value based on the input grayscale value at the moment when the enable signal is generated.

[0008] The gain provider may determine the first period to be shorter as the first load value becomes smaller.

[0009] The gain provider may maintain the gain value from a second time instant after the first time instant.

[0010] Regardless of the first load value, the interval between the time when the enable signal is generated and the second time may be set to be constant.

[0011] As the first load value becomes smaller, the interval between the time when the enable signal is generated and the second time can be set to be longer.

[0012] The gain provider may include: a load comparator configured to generate an enable signal when a difference between a load value of a first frame and a load value of a second frame is less than an enable threshold; a first frame counter configured to provide a first count value of frames from the moment when the enable signal is generated; and a set gain controller configured to determine a first time period based on the first load value and the first count value.

[0013] The set gain controller may include a plurality of set gain lookup tables that are different from each other according to the first load value.

[0014] The set gain controller may provide a first gain ratio value corresponding to the first count value with reference to a set gain lookup table selected according to the first load value.

[0015] The display device may further include: a current sensor configured to provide a sensed value of current flowing in the first power line; and an initial gain provider configured to provide an initial gain value based on the sensed value. The first power line may be commonly coupled to the plurality of pixels. The gain provider may further include a gain converter configured to convert the initial gain value into a gain value according to the first gain ratio.

[0016] The initial gain provider may provide an initial gain value such that the sensed value is less than the current limit value. The first gain ratio may be equal to or less than 1.

[0017] The gain provider may gradually increase the gain value from a third time after the second time.

[0018] The gain provider may determine an increase rate of the gain value according to a second load value based on the input grayscale value at a third time instant.

[0019] The gain provider may determine an increasing rate of the gain value according to a difference between the second load value and the first load value.

[0020] When the difference between the load value of the third frame and the load value of the fourth frame is greater than the disable threshold, the load comparator can generate a disable signal. The gain provider can include: a second frame counter configured to provide a second count value of frames from the moment the disable signal is generated; and a reset gain controller configured to determine an increase rate based on the second load value and the second count value.

[0021] The reset gain controller may include a plurality of reset gain lookup tables that are different from each other according to the second load value.

[0022] The reset gain controller may provide a second gain ratio corresponding to the second count value with reference to a reset gain lookup table selected according to the second load value.

[0023] The gain converter may convert the initial gain value into a gain value according to a second gain ratio value. The second gain ratio value may be equal to or less than 1.

[0024] According to another aspect of the present disclosure, a display device is provided, comprising: a plurality of pixels collectively coupled to a first power line; and a current sensor configured to provide a sensing value of a current flowing in the first power line, wherein, while displaying a still image, the pixels gradually reduce the brightness of the still image from a first moment, wherein the first moment is a moment after a first period of time has passed since a moment when display of the still image begins, wherein the length of the first period of time changes according to the sensing value at the moment when display of the still image begins.

[0025] As the sensed value becomes smaller, the first period may become shorter.

[0026] The plurality of pixels may maintain brightness of the still image from a second time after the first time. As the sensing value at the time when the still image display starts becomes smaller, the interval between the time when the still image display starts and the second time may be set longer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, this element can be the only element between the two elements, or one or more intermediate elements may also be present. Like reference numerals always represent like elements.

[0029] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0031] Figure 3 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0032] Figure 4is a diagram illustrating an arrangement of a pixel unit and a data driver according to an embodiment of the present disclosure.

[0033] Figure 5 、 Figure 6 and Figure 7 is a diagram illustrating an example pattern of a frame.

[0034] Figure 8 is a diagram illustrating a sensed value of a current sensor and an initial gain value of an initial gain provider.

[0035] Figure 9 is a diagram illustrating a problem when the screen saver function is used.

[0036] Figure 10 is a diagram illustrating a gain provider according to an embodiment of the present disclosure.

[0037] Figure 11 It shows Figure 10 Schematic diagram of an embodiment of the operation of a gain provider is shown in FIG.

[0038] Figure 12 It shows Figure 10 FIG. 4 is a diagram of another embodiment of the operation of a gain provider shown in FIG.

[0039] Figure 13 is a diagram illustrating a gain provider according to another embodiment of the present disclosure.

[0040] Figure 14 It shows Figure 13 Schematic diagram of an embodiment of the operation of a gain provider is shown in FIG.

[0041] Figure 15 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0042] Figure 16 is a diagram illustrating a data driver according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Hereinafter, example embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the example embodiments described in this specification.

[0044] Parts not related to the description will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be represented by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

[0045] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clear expression, the thickness of several parts and regions is exaggerated.

[0046] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The display device 10 a according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , a current sensor 15 , an initial gain provider 16 , a gain provider 17 , and a grayscale converter 18 .

[0048] The timing controller 11 may receive an input grayscale value and a control signal for each frame from an external processor.

[0049] Grayscale converter 18 can convert an input grayscale value into an output grayscale value based on gain value SSG. For example, gain value SSG can be a value greater than or equal to 0 and less than or equal to 1, and the output grayscale value can be calculated by multiplying the input grayscale value by gain value SSG. The output grayscale value can be less than or equal to the input grayscale value. Gain value SSG can be a value greater than or equal to 0% and less than or equal to 100%. In addition, various methods of expressing gain value SSG are possible.

[0050] The timing controller 11 may provide output grayscale values ​​to the data driver 12. In addition, the timing controller 11 may provide control signals suitable for the specifications of the data driver 12, the scan driver 13, etc. for the purpose of frame display.

[0051] The data driver 12 can convert the output grayscale value into a data voltage. The data driver 12 can generate data voltages to multiple data lines DL1, DL2, DL3, ... and DLn by using the output grayscale value and a control signal. For example, the data driver 12 can sample the output grayscale value by using a clock signal and apply the data voltage corresponding to the output grayscale value to the data lines DL1 to DLn in units of pixel rows. A pixel row can represent a pixel coupled to the same scan line. Here, n can be an integer greater than 0. The data driver 12 can be a group of multiple driver units. When the driver units are grouped, the display device 10a can include multiple data drivers. The arrangement of the driver units will be described with reference to the subsequent drawings.

[0052] The scan driver 13 may generate scan signals to be supplied to the scan lines SL1, SL2, SL3, ... and SLm by receiving a clock signal, a scan start signal, etc. from the timing controller 11. Here, m may be an integer greater than 0.

[0053] The scan driver 13 can sequentially supply scan signals having on-level pulses to the scan lines SL1 to SLm. The scan driver 13 can include a scan stage configured in the form of a shift register. The scan driver 13 can generate scan signals by sequentially transmitting a scan start signal in the form of an on-level pulse to a subsequent scan stage under the control of a clock signal.

[0054] The pixel unit 14 includes a plurality of pixels. Each pixel PXij can be coupled to a corresponding data line and a corresponding scan line. Here, i and j can be integers greater than 0. The pixel PXij can represent a pixel in which a scan transistor is coupled to the i-th scan line and the j-th data line. The pixels can be commonly coupled to a first power line (not shown) and a second power line (not shown).

[0055] The pixel can receive a data voltage determined according to the gain value SSG and the input grayscale value. For example, the first data voltage is determined based on the first input grayscale value and the first gain value. In addition, the second data voltage is determined based on the second input grayscale value and the second gain value. When the first input grayscale value and the second input grayscale value are the same and the first gain value is greater than the second gain value, the first data voltage can be higher than the second data voltage. This is in the driving transistor of the pixel (for example, Figure 2 When the first transistor T1 shown in FIG. 1 is configured as an N-type transistor, when the driving transistor is configured as a P-type transistor, the first data voltage may be lower than the second data voltage.

[0056] The first power line may be coupled to a first power sub-line DSUBL. The first power sub-line DSUBL may be coupled to a corresponding first power source (not shown). In this embodiment, the data driver 12 may include the first power source. Therefore, the first power sub-line DSUBL may be coupled to the data driver 12. In another embodiment, the data driver 12 and the first power source may be configured separately from each other. For example, the first power source may be directly coupled to a power management integrated circuit (PMIC) rather than the data driver 12. The first power sub-line DSUBL may not be coupled to the data driver 12.

[0057] The second power line can be coupled to a second power sub-line SSUBL. The second power sub-line SSUBL can be coupled to a corresponding second power source (not shown). In this embodiment, the data driver 12 may include a second power source. Therefore, the second power sub-line SSUBL can be coupled to the data driver 12. In an embodiment, the data driver 12 and the second power source can be configured separately from each other. For example, the second power source can be directly coupled to the PMIC instead of the data driver 12. The second power sub-line SSUBL may not be coupled to the data driver 12.

[0058] A current sensor 15 may be coupled to the first power line. The current sensor 15 may provide a sensed value SSC of the current flowing in the first power line. The current sensor 15 does not measure branch currents branching to corresponding pixels, but may measure the global current before the global current branches to the pixels. The global current may correspond to the sum of the branch currents.

[0059] In another embodiment, a current sensor 15 may be coupled to the second power line. The current sensor 15 may provide a sensed value SSC of the current flowing in the second power line. The current sensor 15 does not measure the branch currents of the pixels, but rather measures a global current obtained by summing the branch currents. The global current may correspond to the sum of the branch currents.

[0060] The initial gain provider 16 may provide an initial gain value IG based on the sensed value SSC. The initial gain value IG may be a value greater than or equal to 0 and less than or equal to 1. The initial gain value IG may be a value greater than or equal to 0% and less than or equal to 100%. In addition, various methods of expressing the initial gain value IG may be used.

[0061] The initial gain provider 16 may provide an initial gain value IG so that the sensed value SSC is less than the current limit value. The initial gain provider 16 controls the initial gain value IG so that the global current does not exceed the current limit value, thereby applying a primary limit so that the display device 10a does not consume excessive power.

[0062] The gain provider 17 may provide a gain value SSG based on the initial gain value IG. The gain provider 17 may impose a secondary limit so that power consumption can be reduced when the display device 10a performs a screen saver function. Therefore, the gain value SSG may be less than or equal to the initial gain value IG.

[0063] Figure 2 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0064] Reference Figure 2 , the pixel PXij may include a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light emitting diode LD.

[0065] Hereinafter, a circuit implemented with a P-type transistor is described as an example. However, those skilled in the art can design a circuit implemented with an N-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art can design a circuit implemented with a combination of a P-type transistor and an N-type transistor. A P-type transistor refers to a transistor in which the amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in a negative direction. An N-type transistor refers to a transistor in which the amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in a positive direction. The transistor can be configured in various forms including a thin film transistor (TFT), a field effect transistor (FET), a bipolar junction transistor (BJT), etc.

[0066] A gate electrode of the first transistor T1 may be coupled to a first electrode of the storage capacitor Cst, a first electrode of the first transistor T1 may be coupled to the first power line ELVDDL, and a second electrode of the first transistor T1 may be coupled to a second electrode of the storage capacitor Cst. The first transistor T1 may be referred to as a driving transistor.

[0067] The gate electrode of the second transistor T2 may be coupled to the i-th scan line SLi, the first electrode of the second transistor T2 may be coupled to the j-th data line DLj, and the second electrode of the second transistor T2 may be coupled to the gate electrode of the first transistor T1. The second transistor T2 may be referred to as a scan transistor.

[0068] An anode of the light emitting diode LD may be coupled to the second electrode of the first transistor T1, and a cathode of the light emitting diode LD may be coupled to the second power line ELVSSL. The light emitting diode LD may be configured as an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0069] A first power voltage may be applied to the first power line ELVDDL, and a second power voltage may be applied to the second power line ELVSSL.

[0070] When a scan signal having a turn-on level (here, a high level) is applied through the scan line SLi, the second transistor T2 is in a turn-on state. A data voltage applied to the data line DLj is stored in the first electrode of the storage capacitor Cst.

[0071] A positive driving current (branch current) corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the first transistor T1. Thus, the light emitting diode LD emits light having brightness corresponding to the data voltage.

[0072] Next, when a scan signal having a cut-off level (here, a low level) is applied through the scan line SLi, the second transistor T2 is turned off, and the data line DLj and the first electrode of the storage capacitor Cst are electrically separated from each other. Therefore, although the data voltage of the data line DLj changes, the voltage stored in the first electrode of the storage capacitor Cst does not change.

[0073] The embodiment can be applied not only Figure 2 Pixel PXij is shown in FIG, and another circuit can be applied to the pixel.

[0074] The first power sub-line DSUBL may be commonly coupled to the first power line ELVDDL. That is, the electrical node of the first power line ELVDDL and the first power sub-line DSUBL may be the same.

[0075] The second power sub-line SSUBL may be commonly coupled to the second power line ELVSSL. That is, the electrical node of the second power line ELVSSL and the second power sub-line SSUBL may be the same.

[0076] Figure 3 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0077] Reference Figure 3 , the first data driver 12a according to an embodiment of the present disclosure may include a plurality of driver units 121, 122, and 125. When the display device 10a includes the plurality of driver units 121, 122, and 125, the data lines DL1 to DLn may be grouped into data line groups, and each data line group may be coupled to a corresponding driver unit.

[0078] The driver units 121, 122, and 125 may use one clock training line SFC as a common bus. For example, the timing controller 11 may simultaneously transmit a signal notifying that a clock training mode will be supplied to all driver units 121, 122, and 125 through one clock training line SFC.

[0079] The driver units 121, 122, and 125 may be coupled to the timing controller 11 through dedicated clock data lines DCSL. For example, when the display device 10a includes a plurality of driver units 121, 122, and 125, the driver units 121, 122, and 125 may be coupled to the timing controller 11 through each of the clock data lines DCSL.

[0080] At least one clock-data line DCSL may be coupled to each of the driver units 121, 122, and 125. For example, multiple clock-data lines DCSL may be coupled to each driver unit to prepare for situations where using only one clock-data line DCSL is insufficient to achieve the desired bandwidth of the transmission signal. Furthermore, even when the clock-data lines DCSL are configured as differential signal lines to remove common-mode noise, multiple clock-data lines DCSL may be required for each driver unit.

[0081] Each of the driver units 121, 122, and 125 may include a first power source and a second power source. Each of the first power sources may be coupled to at least one of the first power sub-lines DSUBL. Each of the second power sources may be coupled to at least one of the second power sub-lines SSUBL. Each of the first power sources may supply a first power voltage via the first power sub-line DSUBL. Each of the second power sources may supply a second power voltage via the second power sub-line SSUBL.

[0082] For example, the driver unit 121 may supply a first power voltage to the first power line ELVDDL through the first power sub-line DSUBL1, and supply a second power voltage to the second power line ELVSSL through the second power sub-line SSUBL1. Similarly, the driver unit 122 may supply a first power voltage to the first power line ELVDDL through the first power sub-line DSUBL2, and supply a second power voltage to the second power line ELVSSL through the second power sub-line SSUBL2.

[0083] Figure 4 is a diagram illustrating an arrangement of a pixel unit and a data driver according to an embodiment of the present disclosure.

[0084] Reference Figure 4 , showing a case where the data driver 12 includes a first data driver 12a and a second data driver 12b.

[0085] The pixel unit 14 may have a planar shape extending in a first direction DR1 and a second direction DR2 orthogonal to the first direction DR1. In this embodiment, for ease of description, the pixel unit 14 is shown as an example in which the pixel unit 14 is arranged in a rectangular shape. In another embodiment, the pixel unit 14 may also be arranged in a circular shape, an elliptical shape, a diamond shape, etc. In addition, the pixel unit 14 may have a planar shape, a portion of which changes when the pixel unit 14 is bent, folded, or rolled.

[0086] The first data driver 12a may be located at the bottom of the pixel unit 14 and extend parallel to the pixel unit 14 along the first direction DR1. The first data driver 12a may include a plurality of driver units 121 and 122. The driver units 121 and 122 may include first power sub-lines DSUBL1 and DSUBL2 and second power sub-lines SSUBL1 and SSUBL2 extending in the second direction DR2. The first power sub-lines DSUBL1 and DSUBL2 may be arranged in the first direction DR1. The second power sub-lines SSUBL1 and SSUBL2 may be arranged in the first direction DR1.

[0087] The second data driver 12b may be located above the pixel unit 14 and extend parallel to the pixel unit 14 along the first direction DR1. The second data driver 12b may include a plurality of driver units 123 and 124. The driver units 123 and 124 may include first power sub-lines DSUBL3 and DSUBL4 and second power sub-lines SSUBL3 and SSUBL4 extending in the second direction DR2. The first power sub-lines DSUBL3 and DSUBL4 may be arranged in the first direction DR1. The second power sub-lines SSUBL3 and SSUBL4 may be arranged in the first direction DR1.

[0088] Figure 5 、 Figure 6 and Figure 7 is a diagram illustrating an example pattern of a frame. Figure 8 is a diagram illustrating a sensed value of a current sensor and an initial gain value of an initial gain provider.

[0089] Reference Figure 5 , shows mode "A" in which 99% of the pixels of the pixel unit 14 display black gray (eg, gray 0) and 1% of the pixels of the pixel unit 14 display white gray (eg, gray 255). Figure 6 , shows mode "B", in which 60% of the pixels of the pixel unit 14 display black grayscale, and 40% of the pixels of the pixel unit 14 display white grayscale. Figure 7 , shows mode “C”, in which 100% of the pixels of the pixel unit 14 display a white grayscale.

[0090] The load value of mode "C" may be the largest, and the load value of mode "A" may be the smallest. The load value may correspond to the input grayscale value of one frame. In an example, the load value may be a value obtained by adding the input grayscale values ​​of one frame. In another example, the load value may be an average value of the input grayscale values ​​of one frame.

[0091] Figure 8The upper curve LCC shown in FIG. 1 represents the sensed value SSC for the load value. As described above, the current sensor 15 can provide the sensed value SSC of the current flowing in the first power line ELVDDL. When the load value increases according to the image mode, the branch current required in the pixel increases, and therefore the global current flowing through the first power line ELVDDL also increases.

[0092] As described above, the initial gain provider 16 can provide the initial gain value IG so that the sensed value SSC is less than the current limit value CLM. The initial gain provider 16 controls the initial gain value IG so that the global current does not exceed the current limit value CLM to impose a primary limit so that the display device 10a does not consume excessive power.

[0093] For example, when the sensed value SSC is less than the current limit value CLM, the initial gain driver 16 may maintain the initial gain value IG at a maximum. The initial gain value IG may be 1 (or 100%). When the sensed value SSC reaches the current limit value CLM, the initial gain provider 16 reduces the initial gain value IG to prevent the current flowing through the first power line ELVDDL from increasing. The initial gain value IG may be less than 1 (or 100%). That is, in a frame having a load value greater than the load value LLM, the luminance corresponding to each grayscale decreases as the load value increases.

[0094] For example, according to Figure 8 , in the case of mode “A”, the current flowing corresponding to the load value LA1 is less than the current limit value CLM, and therefore, the initial gain provider 16 can provide the initial gain value IGA of 1. Therefore, the pixel corresponding to the white grayscale in mode “A” can emit light with maximum brightness (for example, 1000 nits).

[0095] However, in the case of mode “B”, the current flowing corresponding to the load value LB1 needs to be limited to be less than the current limit value CLM, and therefore, the initial gain provider 16 may provide an initial gain value IGB less than 1. Therefore, the pixel corresponding to the white grayscale in mode “B” may emit light having a luminance lower than the maximum luminance (e.g., 500 nits).

[0096] Furthermore, in the case of mode “C”, it is necessary to limit the current flowing corresponding to the load value LC1 to be less than the current limit value CLM, and therefore, the initial gain provider 16 may provide an initial gain value IGC less than 1. Therefore, a pixel corresponding to the white grayscale in mode “C” may emit light having a luminance lower than the maximum luminance (e.g., 250 nits).

[0097] Figure 9 is a diagram illustrating a problem when the screen saver function is used.

[0098] Reference Figure 9 , when the display device 10a is driven according to the screen saver function, a curve TGCA of gain values ​​corresponding to mode 'A', a curve TGCB of gain values ​​corresponding to mode 'B', and a curve TGCC of gain values ​​corresponding to mode 'C' are shown.

[0099] As described above, the screen saver function reduces the brightness of a still image while the display device 10a is displaying an image, thereby preventing afterimages and reducing power consumption. For example, after a first period of time has passed since the start time t0 of displaying the still image, the brightness of the still image can be gradually reduced from the first time t1. This reduction in brightness can be achieved by reducing the gain value. Alternatively, the brightness of the still image can be maintained from a second time t2 after the first time t1. This maintenance of brightness can be achieved by maintaining the gain value. The gain value can be a saturated gain value GSAT, which is the minimum value. Alternatively, the gain value can return to the initial gain value at a third time t3 after the second time t2. The third time t3 is the time when the difference between the load values ​​of the previous frame and the next frame is greater than a predetermined threshold, such as when a still image changes to another still image or when a still image changes to a moving image. The third time t3 is when the screen saver function ends.

[0100] As described above, modes "A", "B" and "C" have different initial gain values ​​IGA, IGB and IGC. Specifically, in the case of mode "A" (mode "A" has a large degree of change in gain value), flickering that occurs when using the screen saver function may be observed by the user.

[0101] Figure 10 is a diagram illustrating a gain provider according to an embodiment of the present disclosure. Figure 11 It shows Figure 10 Schematic diagram of an embodiment of the operation of a gain provider is shown in FIG.

[0102] Reference Figure 10 The gain provider 17 a according to an embodiment of the present disclosure may include a load comparator 171 , a set gain controller 172 , a first frame counter 173 , and a gain converter 174 .

[0103] When the difference between the load value LOAD(N-1) of the first frame and the load value LOADN of the second frame is less than the enable threshold THE, the load comparator 171 may generate an enable signal SSE. For example, the second frame may be a frame continuous with the first frame. For example, the second frame may be a frame immediately following the first frame.

[0104] As described above, each of the load values ​​LOAD(N-1) and LOADN may correspond to an input grayscale value of one frame. In an example, the load value may be a value obtained by adding the input grayscale values ​​of one frame. In another example, the load value may be an average value of the input grayscale values ​​of one frame. When the input grayscale values ​​are distinguished from each other (such as red, green, and blue), the same weight may be applied to the colors.

[0105] When the difference between the load value LOAD(N-1) of the first frame and the load value LOADN of the second frame is less than the enable threshold THE, the grayscale value of the first frame and the grayscale value of the second frame can be basically equal to each other, and therefore, the first frame and the second frame can correspond to still images.

[0106] The first frame counter 173 can provide a first count value FN1 for a frame starting from time t0 when the enable signal SSE is generated. That is, the first count value FN1 can increase from time t0. The first count value FN1 can use one frame period as a unit to provide time information. For example, the first frame counter 173 can generate the first count value FN1 by counting pulses of the vertical synchronization signal.

[0107] The vertical synchronization signal may include a plurality of pulses, and the time when each pulse is generated indicates that the previous frame period ends and the current frame period begins. The interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period.

[0108] The setting gain controller 172 may determine a first period based on the first load value LOADE and the first count value FN1. The first period may be a period from time t0 when the enable signal SSE is generated to the first time. The first load value LOADE may be based on the input grayscale value at time t0 when the enable signal SSE is generated. That is, the first load value LOADE may be the load value of the frame corresponding to time t0. For example, when the enable signal SSE is generated based on the difference between the load values ​​LOAD(N-1) and LOADN, the first load value LOADE may be equal to the load value LOADN.

[0109] The set gain controller 172 may include a plurality of set gain lookup tables SLUT1, SLUT2, and SLUT3 that are set differently from one another according to the first load value LOADE. The set gain controller 172 may refer to the set gain lookup table selected according to the first load value LOADE to provide a first gain ratio value corresponding to the first count value FN1. The first gain ratio value may be equal to 1 (or 100%) or less than 1 (100%).

[0110] The gain converter 174 may convert the initial gain value IG into a gain value SSG according to the first gain ratio.

[0111] When the gain controller 172 receives the first load value LOADE belonging to the first interval, the gain controller 172 may select the first gain lookup table SLUT1. The first switch SSW1 may be turned on. The first switch SSW1 may be implemented using an algorithm rather than an actual switch. For the first load value LOADE belonging to the first interval, the first gain lookup table SLUT1 may include a first gain ratio value corresponding to the first count value FN1. For example, for the first count value FN1 corresponding to the first time period t0 to t1a, the first gain lookup table SLUT1 may include a first gain ratio value of 1. For the first count value FN1 corresponding to the time period t1a to t2, the first gain lookup table SLUT1 may include gradually decreasing first gain ratio values. For the first count value FN1 corresponding to the time period after the second time t2, the first gain lookup table SLUT1 may include a first gain ratio value that is constantly maintained.

[0112] For example, when the frame of mode "A" has a load value belonging to the first interval, the first set gain lookup table SLUT1 may be selected. The gain converter 174 may provide a gain value SSG obtained by sequentially converting the initial gain value IGA according to the first gain ratio value of the first set gain lookup table SLUT1 (see FIG. Figure 11 The curve TGCA shown in FIG.

[0113] When the gain controller 172 receives the first load value LOADE belonging to the second interval, it may select the second gain lookup table SLUT2. The load value belonging to the second interval may be greater than the load value belonging to the first interval. The second switch SSW2 may be turned on. The second switch SSW2 may be implemented using an algorithm rather than an actual switch. For the first load value LOADE belonging to the second interval, the second gain lookup table SLUT2 may include a first gain ratio value corresponding to the first count value FN1. For example, for the first count value FN1 corresponding to the first time period t0 to t1b, the second gain lookup table SLUT2 may include a first gain ratio value of 1. For the first count value FN1 corresponding to the time period t1b to t2, the second gain lookup table SLUT2 may include gradually decreasing first gain ratio values. For the first count value FN1 corresponding to the time period after the second time t2, the second gain lookup table SLUT2 may include a first gain ratio value that is constantly maintained.

[0114] For example, when the frame of mode "B" has a load value belonging to the second interval, the second set gain lookup table SLUT2 may be selected. The gain converter 174 may provide a gain value SSG obtained by sequentially converting the initial gain value IGB according to the first gain ratio of the second set gain lookup table SLUT2 (see curve TGCB).

[0115] When the set gain controller 172 receives the first load value LOADE belonging to the third interval, the set gain controller 172 may select the third set gain lookup table SLUT3. The load value belonging to the third interval may be greater than the load value belonging to the second interval. The third switch SSW3 may be turned on. The third switch SSW3 may be implemented using an algorithm rather than an actual switch. For the first load value LOADE belonging to the third interval, the third set gain lookup table SLUT3 may include a first gain ratio value corresponding to the first count value FN1. For example, for the first count value FN1 corresponding to the first time period t0 to t1c, the third set gain lookup table SLUT3 may include a first gain ratio value of 1. For the first count value FN1 corresponding to the time period t1c to t2, the third set gain lookup table SLUT3 may include gradually decreasing first gain ratio values. For the first count value FN1 corresponding to the time period after the second time t2, the third set gain lookup table SLUT3 may include a first gain ratio value that is constantly maintained.

[0116] For example, when the frame of mode "C" has a load value belonging to the third interval, the third set gain lookup table SLUT3 may be selected. The gain converter 174 may provide a gain value SSG obtained by sequentially converting the initial gain value IGC according to the first gain ratio value of the third set gain lookup table SLUT3 (see FIG. Figure 11 The curve TGCC shown in FIG.

[0117] That is, when the first period elapses from time t0 when the enable signal SSE is generated, the gain provider 17a may gradually reduce the gain value SSG from the first time t1a, t1b, or t1c. Furthermore, the gain provider 17a may determine the length of the first period t0 to t1a, t0 to t1b, or t0 to t1c based on the first load value LOADE based on the input grayscale value at time t0 when the enable signal SSE is generated. That is, the length of the first period t0 to t1a, t0 to t1b, or t0 to t1c may be changed based on the sensed value SSC at time t0 when the display of the still image begins.

[0118] That is, the gain provider 17a can set the first period tO to tl a, tO to tl b, or tO to tl c to become shorter as the first load value LOADE becomes smaller. Further, the gain provider 17a can allow the gain value SSG to be maintained from a second time t2 after the first time tl a, tl b, or tl c. The interval between the time tO when the enable signal SSE is generated and the second time t2 can be set to a constant regardless of the first load value LOADE.

[0119] Figure 12 is a graph showing another embodiment of the operation of the gain provider shown in Figure 10

[0120] Figure 12 The embodiment shown in Figure 11 differs from the embodiment shown in in that the interval between the time tO when the enable signal SSE is generated and the second time can be set to be longer as the first load value LOADE becomes smaller.

[0121] Figure 12 Referring to , it can be seen that the interval between the time tO when the enable signal SSE is generated and the second time t2a is relatively long in the curve TGCA in the case where the load value is relatively small, and the interval between the time tO when the enable signal SSE is generated and the second time t2c is relatively short in the curve TGCC in the case where the load value is relatively large. That is, the interval between the time tO when the still image starts to be displayed and the second time t2a, t2b, or t2c can be set to be longer as the sensed value SSC at the time tO when the still image starts to be displayed becomes smaller.

[0122] According to this embodiment, the decay rate of the luminance at the time when the screen saver function is executed can be uniform regardless of the magnitude of the first load value LOADE, that is, regardless of the kind of the image mode.

[0123] It can be seen that, in the embodiment shown in Figure 12 , the decay rates DEC1, DEC2, and DEC3 of the curves TGCA, TGCB, and TGCC are constant, and in the embodiment shown in Figure 11 , the decay rates DEC1, DEC2, and DEC3 of the curves TGCA, TGCB, and TGCC are different from each other.

[0124] Figure 13 is a graph showing a gain provider according to another embodiment of the present disclosure. Figure 14 is a graph showing Figure 13 the operation of the gain provider shown in Figure 14 . The curve TGCB corresponding to the mode "B" is shown in

[0125] Reference Figure 13 According to another embodiment of the present disclosure, the gain provider 17b may include a load comparator 171, a setting gain controller 172, a first frame counter 173, a gain converter 174, a reset gain controller 175, and a second frame counter 176. Figure 10 The parts of the gain provider 17a shown in FIG.

[0126] When the difference between the load value LOAD(N-1) of the third frame and the load value LOADN of the fourth frame is greater than the disable threshold THD, the load comparator 171 may generate a disable signal SSD. For example, the fourth frame may be a frame continuous with the third frame. For example, the fourth frame may be a frame immediately following the third frame. The third and fourth frames may be frames different from the first and second frames.

[0127] When the difference between the load value LOAD(N-1) of the third frame and the load value LOADN of the fourth frame is greater than the disable threshold THD, the grayscale value of the third frame and the grayscale value of the fourth frame can be different from each other, and therefore, the third frame and the fourth frame can correspond to motion images (different images).

[0128] The second frame counter 176 can provide a second count value FN2 for frames starting from time t3 when the disable signal SSD is generated. That is, the second count value FN2 can increase from time t3. The second count value FN2 can use one frame period as a unit to provide time information. For example, the second frame counter 176 can generate the second count value FN2 by counting pulses of the vertical synchronization signal.

[0129] The reset gain controller 175 may determine an increase rate of the gain value SSG based on the second load value LOADD and the second count value FN2. The reset gain controller 175 may include a plurality of reset gain lookup tables RLUT1, RLUT2, and RLUT3 that are different from each other according to the second load value LOADD.

[0130] The second load value LOADD may be based on the input grayscale value at time t3 when the disable signal SSD is generated. That is, the second load value LOADD may be the load value of the frame corresponding to time t3. For example, when the disable signal SSD is generated based on the difference between the load values ​​LOAD(N-1) and LOADN, the second load value LOADD may be equal to the load value LOADN.

[0131] The reset gain controller 175 may include a plurality of reset gain lookup tables RLUT1, RLUT2, and RLUT3 that are set differently according to the second load value LOADD. The reset gain controller 175 may refer to the reset gain lookup table selected according to the second load value LOADD to provide a second gain ratio corresponding to the second count value FN2. The second gain ratio may be equal to 1 (or 100%) or less than 1 (or 100%).

[0132] The gain converter 174 may convert the initial gain value IG into a gain value SSG according to the second gain ratio.

[0133] When the reset gain controller 175 receives the second load value LOADD belonging to the fourth interval, the reset gain controller 175 may select the first reset gain lookup table RLUT1. The first switch RSW1 may be turned on. The first switch RSW1 may be implemented using an algorithm rather than an actual switch. For the second load value LOADD belonging to the fourth interval, the first reset gain lookup table RLUT1 may include a second gain ratio corresponding to the second count value FN2. For example, the first reset gain lookup table RLUT1 may include a second gain ratio corresponding to the second count value FN2 that gradually increases according to the first increase rate INC1.

[0134] The gain converter 174 may provide a gain value SSG obtained by sequentially converting the initial gain value IGB according to the second gain ratio of the first reset gain lookup table RLUT1 .

[0135] When the reset gain controller 175 receives the second load value LOADD belonging to the fifth interval, the reset gain controller 175 may select the second reset gain lookup table RLUT2. The load value belonging to the fifth interval may be smaller than the load value belonging to the fourth interval. The second switch RSW2 may be turned on. The second switch RSW2 may be implemented using an algorithm rather than an actual switch. For the second load value LOADD belonging to the fifth interval, the second reset gain lookup table RLUT2 may include a second gain ratio corresponding to the second count value FN2. For example, the second reset gain lookup table RLUT2 may include a second gain ratio corresponding to the second count value FN2 that gradually increases according to the second increase rate INC2. The second increase rate INC2 may be smaller than the first increase rate INC1.

[0136] The gain converter 174 may provide gain values ​​SSG obtained by sequentially converting the initial gain values ​​IGB according to the second gain ratios of the second reset gain lookup table RLUT2 .

[0137] When the reset gain controller 175 receives the second load value LOADD belonging to the sixth interval, the reset gain controller 175 can select a third reset gain lookup table RLUT3. The load value belonging to the sixth interval can be smaller than the load value belonging to the fifth interval. A third switch RSW3 can be turned on. The third switch RSW3 can be implemented with an algorithm instead of an actual switch. The third reset gain lookup table RLUT3 can include a second gain ratio value corresponding to a second count value FN2 for the second load value LOADD belonging to the sixth interval. For example, the third reset gain lookup table RLUT3 can include a second gain ratio value gradually increasing according to a third increase rate INC3 corresponding to the second count value FN2. The third increase rate INC3 can be smaller than the second increase rate INC2.

[0138] The gain converter 174 can provide a gain value SSG obtained by sequentially converting the initial gain value IGB according to the second gain ratio value of the third reset gain lookup table RLUT3.

[0139] That is, the gain provider 17b can gradually increase the gain value SSG from a third time t3 to a fourth time t4 after the second time t2. The gain provider 17b can determine the increase rate INC1, INC2, or INC3 of the gain value SSG according to the second load value LOADD based on the input grayscale value at the third time t3. In another embodiment, the gain provider 17b can determine the increase rate INC1, INC2, or INC3 of the gain value SSG according to a difference between the second load value LOADD and the first load value LOADE.

[0140] According to this embodiment, when the screen protection function ends, the gain value SSG is gradually increased, and thus it is possible to reduce the flickering problem.

[0141] According to this embodiment, the increase rate of the gain value SSG is determined to be smaller as the second load value LOADD becomes smaller. Thus, when a dark image is displayed at the end of the screen protection function, the increase rate of the gain value SSG is set to be smaller, so that flickering can be reduced even when a bright image is subsequently displayed. On the other hand, when a bright image is displayed at the end of the screen protection function, it will be less likely to occur flickering even when a bright image is subsequently displayed. Thus, there is no problem even when the increase rate of the gain value SSG is set to be relatively large.

[0142] Figure 15 FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the disclosure.

[0143] Referring to Figure 15According to another embodiment of the present disclosure, a display device 10b may include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, a current sensor 15, an initial gain provider 16, and a gain provider 17. Figure 1 1 and 2. The portions of the display device 10a shown in FIG.

[0144] according to Figure 15 In the embodiment shown in FIG, the gain provider 17 may provide the gain value SSG to the data driver 12. In this embodiment, no grayscale converter is required.

[0145] Figure 16 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0146] Reference Figure 16 , shows one driver unit 125 included in the data driver 12. The other driver units may have substantially the same structure.

[0147] The driver unit 125 may include a shift register SHR, a sampling latch SLU, a holding latch HLU, a digital-to-analog converter DAU, and an output buffer BFU.

[0148] The data control signal DCD received from the timing controller 11 may include a source start pulse SSP, a grayscale value GD, and a source output enable signal SOE.

[0149] The shift register SHR can sequentially generate sampling signals while shifting the source start pulse SSP in each cycle of the source shift clock SCLK. The number of sampling signals can correspond to the number of data lines DLj to DLn. For example, the number of sampling signals can be equal to the number of data lines DLj to DLn. In another example, when the display device 10b further includes a demultiplexer between the data driver 12 and the data lines DLj to DLn, the number of sampling signals can be smaller than the number of data lines DLj to DLn. For ease of description, it is assumed below that there is no demultiplexer.

[0150] The sampling latch SLU may include sampling latch units whose number corresponds to the number of data lines DLj to DLn, and sequentially receive grayscale values ​​GD for image frames from the timing controller 11. In response to sampling signals sequentially received from the shift register SHR, the sampling latch SLU may store the grayscale values ​​GD sequentially received from the timing controller 11 in corresponding sampling latch units.

[0151] The holding latch HLU can further include holding latch units, the number of which corresponds to the number of the data lines DLj to DLn. When the input source output enable signal SOE is output, the holding latch HLU can store the gradation value GD stored in the sampling latch unit in the holding latch unit.

[0152] The digital-to-analog converter DAU can include digital-to-analog conversion units, the number of which corresponds to the number of the data lines DLj to DLn. For example, the number of the digital-to-analog conversion units can be equal to the number of the data lines DLj to DLn. Each of the digital-to-analog conversion units can apply a gradation voltage GV corresponding to the gradation value GD stored in the corresponding holding latch unit to the corresponding data line.

[0153] The gradation voltage GV can be provided from a gradation voltage generator (not shown). The gradation voltage generator can include a red gradation voltage generator, a green gradation voltage generator, and a blue gradation voltage generator. The gradation voltage GV can be set such that the luminance corresponding to each gradation follows a gamma curve.

[0154] The output buffer BFU can include buffer units BUFj to BUFn. For example, each of the buffer units BUFj to BUFn can be an operational amplifier. Each of the buffer units BUFj to BUFn can be configured in the form of a voltage follower to apply the output of the corresponding digital-to-analog conversion unit to the corresponding data line. For example, the inverting terminal of each of the buffer units BUFj to BUFn can be coupled to its own output terminal, and the non-inverting terminal of each of the buffer units BUFj to BUFn can be coupled to the output terminal of the corresponding digital-to-analog conversion unit. The output of the buffer units BUFj to BUFn can be a data voltage.

[0155] For example, the output terminal of the jth buffer unit BUFj can be coupled to the jth data line DLj, and receive a buffer power voltage VDD and a ground power voltage GND. The buffer power voltage VDD can determine the upper limit of the output voltage (i.e., the data voltage) of the buffer unit BUFj. In addition, the ground power voltage GND can determine the lower limit of the output voltage of the buffer unit BUFj. According to the configuration of the buffer unit BUFj, other voltages instead of the buffer power voltage VDD and the ground power voltage GND can also be applied to the buffer unit BUFj. The other voltages can be control voltages for determining the slew rate of the buffer unit BUFj. The control voltages are different from the buffer power voltage VDD in that the control voltages are not voltages for determining the upper limit or the lower limit of the output voltage of the buffer unit BUFj. The buffer unit BUFj can generate the output voltage by amplifying the input voltage according to a gain value SSG.

[0156] As described above, the gain value SSG can be changed by the initial gain provider 16 and the gain provider 17 .

[0157] According to the present disclosure, a display device can reduce flicker according to an image mode while using a screen saver function.

[0158] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those skilled in the art as of the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically stated. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: A gain provider configured to gradually reduce the gain value starting from a first moment after a first period of time from a moment when the enable signal is generated; as well as a plurality of pixels configured to receive a data voltage determined by the gain value and an input grayscale value, wherein the gain provider determines the length of the first period according to a first load value based on the input grayscale value at the moment when the enable signal is generated, The gain provider determines the first time period to become shorter as the first load value becomes smaller, wherein the gain provider maintains the gain value from a second moment after the first moment, and Wherein, the gain provider includes: a load comparator configured to generate the enable signal when a difference between a load value of the first frame and a load value of the second frame is less than an enable threshold; a first frame counter configured to provide a first count value of frames from the moment when the enable signal is generated; and A set gain controller is configured to determine the first period based on the first load value and the first count value.

2. The display device according to claim 1, wherein Regardless of the first load value, the interval between the time when the enable signal is generated and the second time is set to be constant.

3. The display device according to claim 1, wherein As the first load value becomes smaller, the interval between the timing when the enable signal is generated and the second timing is set to be longer.

4. The display device according to claim 1, wherein The set gain controller includes a plurality of set gain lookup tables that are different from each other according to the first load value.

5. The display device according to claim 4, wherein The set gain controller provides a first gain ratio value corresponding to the first count value with reference to a set gain lookup table selected according to the first load value.

6. The display device according to claim 5, further comprising: a current sensor configured to provide a sensed value of a current flowing in the first power line; as well as an initial gain provider configured to provide an initial gain value based on the sensed value, wherein the first power line is commonly coupled to the plurality of pixels, and The gain provider further includes a gain converter configured to convert the initial gain value into the gain value according to the first gain ratio.

7. The display device according to claim 6, wherein: The initial gain provider provides the initial gain value so that the sensed value is smaller than the current limit value. Wherein, the first gain ratio is equal to 1 or less than 1, The gain provider gradually increases the gain value from a third moment after the second moment. wherein the gain provider determines an increasing rate of the gain value according to a second load value based on the input grayscale value at the third moment; When the difference between the load value of the third frame and the load value of the fourth frame is greater than the disable threshold, the load comparator generates a disable signal. Wherein, the gain provider includes: a second frame counter configured to provide a second count value of frames from the time when the disable signal is generated; and a reset gain controller configured to determine the increase rate based on the second load value and the second count value, wherein the reset gain controller includes a plurality of reset gain lookup tables that are different from each other according to the second load value, The reset gain controller provides a second gain ratio corresponding to the second count value by referring to a reset gain lookup table selected according to the second load value. wherein the gain converter converts the initial gain value into the gain value according to the second gain ratio, and The second gain ratio is equal to or less than 1.

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