Display device

Abstract

The display device includes: a first region and a second region, each including a plurality of pixels; and a plurality of wirings respectively connected to the plurality of pixels to transmit signals; wherein the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, and the number of wirings per unit area in the second region is less than the number of wirings per unit area in the first region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10 - 2020 - 0024388, filed on February 27, 2020, the content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] A display device is a device for displaying an image and includes a liquid crystal display (“LCD”), an organic light - emitting diode (“OLED”) display, etc. The display device is used in various electronic devices such as mobile phones, navigation devices, digital cameras, e - books, portable game consoles, and various terminals.

[0005] The display device may include a plurality of pixels, and within each pixel, various elements such as transistors and capacitors and various wirings capable of supplying signals to these elements may be positioned. It may not be easy to ensure transmittance through these elements and wirings.

[0006] In a display device, components such as a camera may be arranged in some areas surrounded by the area where the screen is displayed. Generally, no pixels are formed in the areas where these components are arranged, so the screen may not be displayed. Thus, it can be recognized that black holes are arranged in some areas of the screen, which may cause interference when viewing an image. Summary of the invention

[0007] Exemplary embodiments will provide a display device in which a screen can be displayed in some areas of the display device where components such as a camera are arranged.

[0008] In addition, exemplary embodiments will provide a display device that can increase the transmittance of a corresponding area, so as not to affect the function of the component and have high brightness, such that the corresponding area is not distinguishable from other adjacent areas.

[0009] A display device according to an exemplary embodiment includes: a first area and a second area, each including a plurality of pixels; and a plurality of wirings respectively connected to the plurality of pixels to transmit signals, wherein the number of pixels per unit area in the second area is less than the number of pixels per unit area in the first area, and the number of wirings per unit area in the second area is less than the number of wirings per unit area in the first area.

[0010] The plurality of wirings may include: a plurality of first initialization voltage supply lines that supply a first initialization voltage; and a plurality of second initialization voltage supply lines that supply a second initialization voltage, and the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the second region may be less than the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region.

[0011] The number of pixels per unit area in the second region may be more than one-sixth and less than one-half of the number of pixels per unit area in the first region, and the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the second region may be more than one-sixth of the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region, and less than the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region.

[0012] The number of pixels per unit area in the second region may be one-fourth of the number of pixels per unit area in the first region, and the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the second region may be one-half of the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region.

[0013] Each of the plurality of pixels may include: a light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light-emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; a third transistor connected between a second electrode of the driving transistor and a gate electrode of the driving transistor, wherein the second electrode of the driving transistor is connected to the light-emitting diode; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; and a seventh transistor connected between the light-emitting diode and a second initialization voltage line to which a second initialization voltage is applied.

[0014] The number of pixels per unit area in the second region may be one-fourth of the number of pixels per unit area in the first region, the number of the first initialization voltage supply lines per unit area in the second region may be one-fourth of the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region, and the second initialization voltage supply lines may not be arranged in the second region.

[0015] Each of the plurality of pixels in the first region may include: a light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light-emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; a third transistor connected between a second electrode of the driving transistor and a gate electrode of the driving transistor, wherein the second electrode of the driving transistor is connected to the light-emitting diode; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; and a seventh transistor connected between the light-emitting diode and a second initialization voltage line to which a second initialization voltage is applied, and each of the plurality of pixels in the second region may include: a light-emitting diode, a driving transistor, a second transistor, a third transistor, a fourth transistor; and a seventh transistor connected between the light-emitting diode and the first initialization voltage line.

[0016] The display device according to an exemplary embodiment may further include at least one or a combination of a camera, a proximity sensor, an illuminance sensor, an attitude sensor, a motion sensor, a fingerprint sensor, and a biometric sensor disposed in the second region.

[0017] The display device according to an exemplary embodiment includes: a plurality of pixels; a plurality of first scan lines connected to the plurality of pixels to transmit a first scan signal; a plurality of second scan lines connected to the plurality of pixels to transmit a second scan signal; a plurality of initialization control lines connected to the plurality of pixels to transmit an initialization control signal; and a connection wiring connecting at least one of the plurality of initialization control lines and at least one of the plurality of second scan lines.

[0018] The plurality of pixels may be arranged in a matrix form along a row direction and a column direction, and the second scan line connected to the pixels of the first row in the matrix form may be connected to the initialization control line connected to the pixels of the nth row in the matrix form.

[0019] The display device according to an exemplary embodiment may further include: a scan driver that generates a first scan signal to be transmitted through the first scan line; and an initialization driving circuit that generates an initialization control signal to be transmitted through the initialization control line, and the initialization driving circuit may transmit the initialization control signal to the second scan line as a second scan signal, and the second scan signal applied to the second scan line connected to the pixels of the first row may have the same timing as the initialization control signal applied to the initialization control line connected to the pixels of the nth row.

[0020] The second scan signal applied to the second scan line of the pixels connected to the first row may have the same timing as the initialization control signal applied to the initialization control line of the pixels connected to the ninth row in a matrix form.

[0021] The second scan line of the pixels connected to the first row may be connected to the second scan line of the pixels connected to the second row in a matrix form, and the initialization control line of the pixels connected to the first row may be connected to the initialization control line of the pixels connected to the second row.

[0022] The display device may further include: a first region and a second region, each including a plurality of pixels, wherein the number of pixels per unit area in the second region may be less than the number of pixels per unit area in the first region, and the number of second scan lines per unit area in the second region may be less than the number of second scan lines per unit area in the first region.

[0023] The number of second scan lines per unit area in the second region may be half of the number of second scan lines per unit area in the first region.

[0024] The number of initialization control lines per unit area in the second region may be less than the number of initialization control lines per unit area in the first region.

[0025] The plurality of pixels may be arranged in a matrix form along a row direction and a column direction. The pixels of two adjacent rows in the matrix form may be connected to the same initialization control line, and the pixels of two adjacent rows may be vertically symmetric with respect to the initialization control line.

[0026] The display device according to an exemplary embodiment includes: a first region and a second region, each including a plurality of pixels, and the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, wherein each of the plurality of pixels includes: a light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light-emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; and a storage capacitor connected between the driving voltage line and the gate electrode of the driving transistor, and the ratio of the width to the length of the channel of the driving transistor in the second region is different from the ratio of the width to the length of the channel of the driving transistor in the first region.

[0027] The ratio of the width to the length of the channel of the driving transistor in the second region may be greater than the ratio of the width to the length of the channel of the driving transistor in the first region.

[0028] The ratio of the width to the length of the channel of the driving transistor in the second region may be 155% or more and 206% or less than the ratio of the width to the length of the channel of the driving transistor in the first region.

[0029] The display device according to an exemplary embodiment may further include: a substrate disposed in the first region and the second region; and a light-shielding member disposed on the substrate, wherein the light-shielding member may not be disposed in the first region.

[0030] The plurality of pixels may include: a first pixel representing red, a second pixel representing green, and a third pixel representing blue. The capacitance of the storage capacitor of the first pixel in the second region may be 86% or more and 140% or less than the capacitance of the storage capacitor of the first pixel in the first region, and the capacitance of the auxiliary capacitor of the first pixel in the second region may be 27% or more and 37% or less than the capacitance of the storage capacitor of the first pixel in the first region.

[0031] The capacitance of the storage capacitor of the second pixel in the second region may be 63% or more and 90% or less than the capacitance of the storage capacitor of the second pixel in the first region, and the capacitance of the auxiliary capacitor of the second pixel in the second region may be 27% or more and 33% or less than the capacitance of the storage capacitor of the second pixel in the first region.

[0032] The capacitance of the storage capacitor of the third pixel in the second region may be 81% or more and 137% or less than the capacitance of the storage capacitor of the third pixel in the first region, and the capacitance of the auxiliary capacitor of the third pixel in the second region may be 26% or more and 37% or less than the capacitance of the storage capacitor of the third pixel in the first region.

[0033] The display device according to an exemplary embodiment includes: a first region and a second region, each including a plurality of pixels; a substrate disposed in the first region and the second region; and a light-shielding member disposed in the second region, wherein the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, and each of the plurality of pixels includes: a light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light-emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; and a storage capacitor connected between the driving voltage line and a gate electrode of the driving transistor, and the light-shielding member is disposed between the substrate and the gate electrode of the driving transistor in the second region to form an auxiliary capacitor.

[0034] According to an exemplary embodiment, a screen may be displayed in some regions of a display device in which components such as a camera are arranged.

[0035] In addition, the transmittance of the corresponding region may be increased so as not to affect the function of the component, or the brightness of the corresponding region may be increased so as not to distinguish it from other adjacent regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a top view schematically showing a display device according to an exemplary embodiment.

[0037] Figure 2 is a top view showing some pixels arranged in a first region of a display device according to an exemplary embodiment.

[0038] Figure 3 is a circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0039] Figure 4 is a top view showing some pixels arranged in a second region of a display device according to an exemplary embodiment.

[0040] Figure 5 is a top view showing some pixels arranged in a second region of a display device according to an exemplary embodiment.

[0041] Figure 6 is a circuit diagram of a pixel arranged in a second region of a display device according to an exemplary embodiment.

[0042] Figure 7 is a view showing the connection relationship between some pixels and wirings of a display device according to an exemplary embodiment.

[0043] Figure 8 is a signal timing diagram showing a plurality of signals applied to two adjacent pixel rows of a display device according to an exemplary embodiment.

[0044] Figure 9 is a signal timing diagram showing the relationship between signals applied to some pixels of a display device according to an exemplary embodiment.

[0045] Figure 10 is a view showing the connection relationship between some pixels and wirings of a display device according to another exemplary embodiment.

[0046] Figure 11 is a top view of some pixels in a first region of a display device according to an exemplary embodiment.

[0047] Figure 12 is along Figure 11A cross-sectional view taken along line XII-XII'.

[0048] Figure 13 is a cross-sectional view taken along Figure 11 line XIII-XIII'.

[0049] Figures 14 to 19 is a top view showing some pixels in a first region in the manufacturing sequence of a display device according to an exemplary embodiment.

[0050] Figure 20 is a top view showing some pixels in a first region of a display device according to an exemplary embodiment.

[0051] Figure 21 is a top view showing some pixels in a second region of a display device according to an exemplary embodiment.

[0052] Figure 22 is along Figure 21 a cross-sectional view taken along line XXII-XXII'.

[0053] Figure 23 is along Figure 21 a cross-sectional view taken along line XXIII-XXIII'.

[0054] Figures 24 to 29 is a top view showing some pixels in a second region in the manufacturing sequence of a display device according to an exemplary embodiment.

[0055] Figure 30 is a top view showing some pixels in a second region of a display device according to an exemplary embodiment. Detailed Description

[0056] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention in its entirety.

[0057] Parts not relevant to the description will be omitted to clearly describe the present invention, and throughout the specification, the same elements will be denoted by the same reference numerals.

[0058] Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited thereto. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. In the drawings, for better understanding and ease of description, the thicknesses of some layers and regions are exaggerated.

[0059] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Further, in the specification, the terms "on" or "above" refer to being positioned on or below a portion of an object and do not necessarily have to refer to being positioned on the upper side of the object portion based on the direction of gravity.

[0060] In addition, unless explicitly described to the contrary, the term "comprising" and variations such as "comprises" or "containing" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0061] Further, in the specification, the phrase "in a plan view" refers to when the object portion is viewed from above, and the phrase "in a cross-sectional view" refers to when the cross-section obtained by vertically cutting the object portion is viewed from the side.

[0062] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a" and "the" are intended to include the plural forms including "at least one". "At least one" should not be construed as limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the "first element", "component", "region", "layer", or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0064] First, refer to Figure 1 Describe the display device 1000 according to an exemplary embodiment.

[0065] Figure 1 Is a top view schematically showing the display device 1000 according to an exemplary embodiment.

[0066] As Figure 1 As shown, the display device 1000 according to an exemplary embodiment may include a display area DA in which an image is displayed and a peripheral area PA in which a driving circuit for driving the display area DA is installed and in which no image is displayed.

[0067] The display area DA may have a basic rectangular shape including a relatively long side and a relatively short side, and a corner portion of the display area DA may have a shape including a chamfered curved surface. However, the shape of the display area DA is merely an example and may be changed into various shapes. A plurality of pixels PX are arranged in the display area DA to display an image. In some areas at the edge of the display area DA, there may be areas where no pixels PX are arranged and no image is displayed.

[0068] The plurality of pixels PX may be arranged in a matrix form along a row direction and a column direction and may receive an image signal to display an image accordingly. However, the arrangement form of the plurality of pixels PX is not limited thereto, and various changes may be made in another exemplary embodiment. Although not shown, the display device 1000 may further include a plurality of wirings. The wirings may be composed of a plurality of scan lines, a plurality of control lines, a plurality of data lines, a plurality of driving voltage lines, and the like. These wirings may transmit a scan signal, a control signal, a data signal, and a driving voltage. The plurality of wirings may be positioned to cross each other in a row direction or a column direction.

[0069] In addition, each pixel PX may include a capacitor connected to a plurality of wirings, a plurality of transistors, and at least one light emitting diode (LED). That is, the display device 1000 may be an organic light emitting display device. However, the type of the display device 1000 is not limited thereto, and in another exemplary embodiment, it may be made of various types of display devices. For example, the display device 1000 may be a liquid crystal display device, an electrophoretic display device, or an electro-wetting display device. In addition, the display device 1000 according to the exemplary embodiment may also be a next-generation display device such as a micro light emitting diode (LED) (Micro LED) display device, a quantum dot light emitting diode (“QLED”) display device, and a quantum dot organic light emitting diode (“QD-OLED”) display device.

[0070] The display area DA may include a first area DA1 and a second area DA2. The first area DA1 and the second area DA2 may each include a plurality of pixels PX. The density of the pixels PX arranged in the first area DA1 and the density of the pixels PX arranged in the second area DA2 may be different. As used herein, the density of the pixels PX refers to the number of pixels PX per unit area. That is, the number of pixels PX per unit area in the first area DA1 may be different from the number of pixels PX per unit area in the second area DA2. The number of pixels PX per unit area in the second area DA2 may be less than the number of pixels PX per unit area in the first area DA1. In addition, the density of the wirings arranged in the first area DA1 and the density of the wirings arranged in the second area DA2 may be different. As used herein, the density of the wirings refers to the number of wirings per unit area. That is, the number of wirings per unit area in the first area DA1 may be different from the number of wirings per unit area in the second area DA2. The number of wirings per unit area in the second area DA2 may be less than the number of wirings per unit area in the first area DA1.

[0071] The second area DA2 may be surrounded by the first area DA1. The area of the first area DA1 may be relatively larger than the area of the second area DA2. The first area DA1 may mainly function to display an image emitted from the pixels PX in the first area DA1, and the second area DA2 may have other functions and also function to display an image. For example, a camera may be further arranged in the second area DA2. The camera may include a plurality of non-emitting elements, and these non-emitting elements may be arranged under the pixels PX. In the second area DA2, in addition to the camera, at least one or a combination of a proximity sensor, an illuminance sensor, an attitude sensor, a motion sensor, a fingerprint recognition sensor, and a biosensor may be arranged. Additionally, other parts with various functions may be arranged in the second area DA2. In Figure 1 it, the display area DA is shown as including one second area DA2, but in another exemplary embodiment, it may also include a plurality of second areas DA2.

[0072] The peripheral area PA may be arranged adjacent to an edge of the display area DA. For example, the peripheral area PA may be connected to the lower edge of the display area DA. However, in another exemplary embodiment, the position of the peripheral area PA may be variously changed. For example, the peripheral area PA may be arranged at two edges of the display area DA. The driving circuit chip IC may be arranged in the peripheral area PA. The driving circuit chip IC is connected to a plurality of pixels PX arranged in the display area DA through wirings, thereby transmitting various signals to the plurality of pixels PX. For example, the driving circuit chip IC may supply a scan signal, a control signal, a data signal, a driving voltage, etc.

[0073] Although not shown, a flexible circuit board may be further arranged in the peripheral area PA. The circuit for controlling the driving of the display device 1000 may be designed on the flexible circuit board and may be attached to the peripheral area PA.

[0074] Next, refer to Figure 2 to describe a first area DA1 of the display device 1000 according to an exemplary embodiment.

[0075] Figure 2 is a top view showing some pixels PX arranged in the first area DA1 of the display device 1000 according to an exemplary embodiment.

[0076] As Figure 2 shown, in the first area DA1, a plurality of pixels PX and a plurality of wirings 127, 128, 171, 1127, and 1128 connected to the plurality of pixels PX to transmit signals may be arranged.

[0077] Figure 2 Some of the pixels PX in the first area DA1 shown in

[0078] are arranged in a matrix form along four rows and sixteen columns, and the number of pixels PX and the number of rows and columns are only examples, and the present invention is not limited thereto. The plurality of pixels PX may include a first pixel PX1 that displays a first color, a second pixel PX2 that displays a second color, and a third pixel PX3 that displays a third color. For example, the first color may be red, the second color may be green, and the third color may be blue. The colors displayed by the plurality of pixels PX are not limited thereto, and in another exemplary embodiment, at least one of cyan, magenta, yellow, and white-based colors may be displayed. Here, one first pixel PX1, two second pixels PX2, and one third pixel PX3 may form a pixel group PXGr.Multiple wirings may include multiple data lines 171 for supplying a data voltage DATA, multiple first initialization voltage supply lines 1127 for supplying a first initialization voltage VINT, multiple first initialization voltage lines 127, multiple second initialization voltage supply lines 1128 for supplying a second initialization voltage AINT, and multiple second initialization voltage lines 128.

[0079] The data lines 171 are arranged for each pixel column and connected to each pixel PX in the pixel column. That is, the pixels PX arranged in the same column may be connected to the same data line 171 to receive the data voltage DATA.

[0080] The first initialization voltage supply lines 1127 may be arranged every four pixel columns. The first initialization voltage lines 127 may connect the first initialization voltage supply lines 1127 and each pixel PX. That is, the first initialization voltage VINT supplied by the first initialization voltage supply lines 1127 may be transmitted to each pixel PX through the first initialization voltage lines 127. For example, the first initialization voltage supply lines 1127 may be respectively arranged between the second pixel column and the third pixel column, between the sixth pixel column and the seventh pixel column, between the tenth pixel column and the eleventh pixel column, and between the fourteenth pixel column and the fifteenth pixel column. However, this is only an example, and in another exemplary embodiment, the arrangement form of the first initialization voltage supply lines 1127 may be variously changed. Multiple first initialization voltage lines 127 are connected to the first initialization voltage supply lines 1127, and multiple pixels PX are connected to the first initialization voltage lines 127.

[0081] The second initialization voltage supply lines 1128 may be arranged every four pixel columns. The second initialization voltage lines 128 may connect the second initialization voltage supply lines 1128 and each pixel PX. That is, the second initialization voltage AINT supplied by the second initialization voltage supply lines 1128 may be transmitted to each pixel PX through the second initialization voltage lines 128. For example, the second initialization voltage supply lines 1128 may be respectively arranged between the fourth pixel column and the fifth pixel column, between the eighth pixel column and the ninth pixel column, between the twelfth pixel column and the thirteenth pixel column, and between the sixteenth pixel column and the seventeenth pixel column. However, this is only an example, and in another exemplary embodiment, the arrangement form of the second initialization voltage supply lines 1128 may be variously changed. Multiple second initialization voltage lines 128 are connected to the second initialization voltage supply lines 1128, and multiple pixels PX are connected to the second initialization voltage lines 128.

[0082] Hereinafter, Figure 3 describe the connection relationship between one pixel PX and each wiring.

[0083] Figure 3It is a circuit diagram of a pixel PX of a display device 1000 according to an exemplary embodiment.

[0084] As Figure 3 shown, one pixel PX of the display device 1000 according to an exemplary embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741, a storage capacitor Cst, a boosting capacitor Cboost, and a light-emitting diode LED.

[0085] The plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of wirings include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, a light-emitting control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0086] The first scan line 151 is connected to a gate driver (not shown) and transmits a first scan signal GW to the second transistor T2. The second scan line 152 may be applied with a voltage having a polarity opposite to that of the voltage applied to the first scan line 151 which is simultaneously used as a signal of the first scan line 151. For example, when a high voltage is applied to the first scan line 151, a low voltage may be applied to the second scan line 152. The second scan line 152 transmits a second scan signal GC to the third transistor T3.

[0087] The initialization control line 153 transmits an initialization control signal GI to the fourth transistor T4. The bypass control line 154 transmits a bypass signal GB to the seventh transistor T7. The bypass control line 154 may correspond to the first scan line 151 of the next stage. The light-emitting control line 155 transmits a light-emitting control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0088] The data line 171 is a wiring for transmitting a data voltage DATA generated from a data driver (not shown), and the luminance emitted by the light-emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0089] The driving voltage line 172 transmits the driving voltage ELVDD. The first initialization voltage line 127 transmits the first initialization voltage VINT, and the second initialization voltage line 128 transmits the second initialization voltage AINT. The common voltage line 741 applies the common voltage ELVSS to the cathode of the light-emitting diode LED. In the present exemplary embodiment, the voltages applied to the driving voltage line 172, the first initialization voltage line 127, the second initialization voltage line 128, and the common voltage line 741 may be constant voltages, respectively.

[0090] Next, the structures and connection relationships of the plurality of transistors will be described in detail.

[0091] The driving transistor T1 may have p-type transistor characteristics and may include a polycrystalline semiconductor. It is a transistor for adjusting the amplitude of the current output to the anode of the light-emitting diode LED according to the data voltage DATA applied to the gate electrode of the driving transistor T1. Since the brightness of the light-emitting diode LED is adjusted according to the amplitude of the driving current output to the anode of the light-emitting diode LED, the brightness of the light-emitting diode LED can be adjusted according to the data voltage DATA applied to the pixel PX. For this purpose, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 through the fifth transistor T5. In addition, the first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2, thereby also receiving the data voltage DATA. The second electrode of the driving transistor T1 is arranged to output a current to the light-emitting diode LED and is connected to the anode of the light-emitting diode LED through the sixth transistor T6. Additionally, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. The gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst (hereinafter also referred to as the second storage electrode). Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and correspondingly, the driving current output by the driving transistor T1 changes. Additionally, the storage capacitor Cst is also used to keep the voltage of the gate electrode of the driving transistor T1 constant within one frame.

[0092] The second transistor T2 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The second transistor T2 is a transistor in the pixel PX that receives the data voltage DATA. The gate electrode of the second transistor T2 is connected to the first scan line 151 and the first electrode of the boosting capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. If the second transistor T2 is turned on by the low voltage of the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0093] The third transistor T3 may have n-type transistor characteristics and may include an oxide semiconductor. The third transistor T3 electrically connects the second electrode and the gate electrode of the driving transistor T1. Therefore, it is a transistor that transmits the compensation voltage in which the data voltage DATA is changed through the driving transistor T1 to the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boosting capacitor Cboost. The third transistor T3 is turned on by the high voltage of the second scan signal GC transmitted through the second scan line 152 to connect the gate electrode of the driving transistor T1 to the second electrode of the driving transistor T1, so that the voltage applied to the first electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst to be stored in the storage capacitor Cst.

[0094] The fourth transistor T4 may have n-type transistor characteristics and may include an oxide semiconductor. The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boosting capacitor Cboost via the second electrode of the third transistor T3. The fourth transistor T4 is turned on by the high voltage of the initialization control signal GI transmitted through the initialization control line 153, and in this case, the first initialization voltage VINT is transmitted to the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst. Accordingly, the voltage of the gate electrode of the driving transistor T1 and the storage capacitor Cst is initialized.

[0095] The fifth transistor T5 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The fifth transistor T5 is used to transmit a driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the light emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0096] The sixth transistor T6 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The sixth transistor T6 is used to transmit the driving current output from the driving transistor T1 to the light emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the light emission control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0097] The seventh transistor T7 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The seventh transistor T7 is used to initialize the anode of the light emitting diode LED. The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. If the seventh transistor T7 is turned on by the low voltage of the bypass signal GB, the second initialization voltage AINT is applied to the anode of the light emitting diode LED to be initialized.

[0098] As described above, a pixel PX includes seven transistors (T1 to T7), a storage capacitor Cst, and a boosting capacitor Cboost. However, the present invention is not limited thereto, and in another exemplary embodiment, the number of transistors, the number of capacitors, and their connection relationships may be variously changed.

[0099] In the present exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor. In addition, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. However, the present invention is not limited thereto, and in another exemplary embodiment, at least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor.

[0100] In the present exemplary embodiment, since the third transistor T3 and the fourth transistor T4 may include a semiconductor material different from that of the driving transistor T1, driving can be performed more stably and reliability can be improved. However, the present invention is not limited thereto, and in another exemplary embodiment, all the transistors included in one pixel PX may include a polycrystalline semiconductor. Additionally, conversely, in yet another exemplary embodiment, all the transistors included in one pixel PX may include an oxide semiconductor.

[0101] As described above, when a high voltage is applied to the first scan line 151, a low voltage is applied to the second scan line 152, and when a low voltage is applied to the first scan line 151, a high voltage is simultaneously applied to the second scan line 152. That is, since the second scan signal GC applied to the second scan line 152 is a signal inverted from the first scan signal GW applied to the first scan line 151, the gate voltage of the driving transistor T1 is decreased after data is written. Conversely, the first scan signal GW increases the gate voltage of the driving transistor T1. Therefore, when a black voltage is written, the black voltage may be decreased. In the present exemplary embodiment, since the boost capacitor Cboost is disposed between the first scan line 151 to which the first scan signal GW is applied and the gate electrode of the driving transistor T1, the gate voltage of the driving transistor T1 increases so that the black voltage can be stably output. As the capacitance of the boost capacitor Cboost increases, the gate voltage of the driving transistor T1 can increase. By adjusting the capacitance of the boost capacitor Cboost, the gate voltage of the driving transistor T1 can be controlled.

[0102] Next, refer to Figure 4 to describe the second region DA2 of the display device 1000 according to an exemplary embodiment.

[0103] Figure 4 is a top view showing some pixels PX disposed in the second region DA2 of the display device 1000 according to an exemplary embodiment.

[0104] As Figure 4 shown, in the second region DA2, a plurality of pixels PX and a plurality of wirings 127, 128, 171, 1127, and 1128 connected to the plurality of pixels PX to transmit signals may be disposed.

[0105] Figure 4Some pixels PX of the second region DA2 shown in [figure] are arranged along two rows and eight columns, and the number of pixels PX and the number of rows and columns are merely examples, and the present invention is not limited thereto. For comparison with the arrangement form of the pixels PX in the first region DA1, the dashed lines corresponding to the pixels PX indicate regions where pixels PX are not actually arranged in the second region DA2. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Four pixels PX (for example, one first pixel PX1, two second pixels PX2, and one third pixel PX3) may form a pixel group PXGr. Two pixel groups PXGr may be positioned adjacent to each other, and another two pixel groups PXGr may be arranged to be spaced apart from the two pixel groups PXGr. That is, the two pixel groups PXGr may be surrounded by regions where pixels PX are not arranged. However, in another exemplary embodiment, the arrangement form of the pixels PX in the second region DA2 may be variously changed.

[0106] In the same area, the first region DA1 may include sixteen pixel groups PXGr, and the second region DA2 may include four pixel groups PXGr. Accordingly, in the same area, the first region DA1 may include sixty-four pixels PX, and the second region DA2 may include sixteen pixels PX. That is, the number of pixels PX per unit area in the second region DA2 is less than the number of pixels PX per unit area in the first region DA1. In this case, the number of pixels PX per unit area in the second region DA2 may be more than about one-sixth and less than about half of the number of pixels PX per unit area in the first region DA1. For example, the number of pixels PX per unit area in the second region DA2 may be about one-fourth of the number of pixels PX per unit area in the first region DA1. As described above, by reducing the number of pixels PX arranged in the second region DA2, the transmittance of the second region DA2 can be increased compared to the first region DA1. Therefore, the influence exerted by the pixels PX on other portions arranged in the second region DA2 can be reduced.

[0107] The plurality of wirings may include a plurality of data lines 171, a plurality of first initialization voltage lines 127, a plurality of first initialization voltage supply lines 1127, a plurality of second initialization voltage lines 128, and a plurality of second initialization voltage supply lines 1128.

[0108] The data line 171 is arranged for each pixel column and connected to each pixel PX in the pixel column. Even if the pixel PX is not arranged, the data line 171 can be arranged. In the same area, the first region DA1 may include sixteen data lines 171, and the second region DA2 may also include sixteen data lines 171. That is, the number of data lines 171 per unit area in the second region DA2 may be substantially the same as the number of data lines 171 per unit area in the first region DA1.

[0109] The first initialization voltage supply line 1127 may be arranged for every eight pixel columns. The first initialization voltage line 127 may connect the first initialization voltage supply line 1127 and each pixel PX. That is, the first initialization voltage VINT supplied by the first initialization voltage supply line 1127 may be transmitted to each pixel PX through the first initialization voltage line 127. For example, the first initialization voltage supply line 1127 may be arranged between the second pixel column and the third pixel column and between the tenth pixel column and the eleventh pixel column. However, this is only an example, and in another exemplary embodiment, the arrangement form of the first initialization voltage supply line 1127 may be variously changed. A plurality of first initialization voltage lines 127 are connected to the first initialization voltage supply line 1127, and a plurality of pixels PX are connected to the first initialization voltage line 127.

[0110] In the same area, four first initialization voltage supply lines 1127 may be arranged in the first region DA1, and two first initialization voltage supply lines 1127 may be arranged in the second region DA2. That is, the number of first initialization voltage supply lines 1127 per unit area in the second region DA2 is less than the number of first initialization voltage supply lines 1127 per unit area in the first region DA1. In this case, the number of first initialization voltage supply lines 1127 per unit area in the second region DA2 may be more than about one-sixth and less than about 1 times the number of first initialization voltage supply lines 1127 per unit area in the first region DA1. For example, the number of first initialization voltage supply lines 1127 per unit area in the second region DA2 may be about half of the number of first initialization voltage supply lines 1127 per unit area in the first region DA1.

[0111] In addition, within the same area, sixteen first initialization voltage lines 127 can be arranged in the first region DA1, and four first initialization voltage lines 127 can be arranged in the second region DA2. That is to say, the number of first initialization voltage lines 127 per unit area in the second region DA2 is less than the number of first initialization voltage lines 127 per unit area in the first region DA1. For example, the number of first initialization voltage lines 127 per unit area in the second region DA2 can be approximately one-fourth of the number of first initialization voltage lines 127 per unit area in the first region DA1.

[0112] The second initialization voltage supply line 1128 can be arranged every eight pixel columns. The second initialization voltage line 128 can connect the second initialization voltage supply line 1128 and each pixel PX. That is to say, the second initialization voltage AINT supplied by the second initialization voltage supply line 1128 can be transmitted to each pixel PX through the second initialization voltage line 128. For example, the second initialization voltage supply line 1128 can be respectively arranged between the fourth pixel column and the fifth pixel column and between the twelfth pixel column and the thirteenth pixel column. However, this is only an example, and in another exemplary embodiment, the arrangement form of the second initialization voltage supply line 1128 can be variously changed. A plurality of second initialization voltage lines 128 are connected to the second initialization voltage supply line 1128, and a plurality of pixels PX are connected to the second initialization voltage line 128.

[0113] Within the same area, four second initialization voltage supply lines 1128 can be arranged in the first region DA1, and two second initialization voltage supply lines 1128 can be arranged in the second region DA2. That is to say, the number of second initialization voltage supply lines 1128 per unit area in the second region DA2 is less than the number of second initialization voltage supply lines 1128 per unit area in the first region DA1. In this case, the number of second initialization voltage supply lines 1128 per unit area in the second region DA2 can be more than approximately one-sixth and less than approximately 1 times the number of second initialization voltage supply lines 1128 per unit area in the first region DA1. For example, the number of second initialization voltage supply lines 1128 per unit area in the second region DA2 can be approximately half of the number of second initialization voltage supply lines 1128 per unit area in the first region DA1.

[0114] In addition, within the same area, sixteen second initialization voltage lines 128 can be arranged in the first region DA1, and four second initialization voltage lines 128 can be arranged in the second region DA2. That is, the number of second initialization voltage lines 128 per unit area in the second region DA2 is less than the number of second initialization voltage lines 128 per unit area in the first region DA1. For example, the number of second initialization voltage lines 128 per unit area in the second region DA2 can be approximately one-fourth of the number of second initialization voltage lines 128 per unit area in the first region DA1.

[0115] That is, the number of wirings per unit area in the second region DA2 is less than the number of wirings per unit area in the first region DA1. The sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the second region DA2 can be more than approximately one-sixth and less than approximately 1 times the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the first region DA1. For example, the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the second region DA2 can be approximately half of the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the first region DA1. As described above, by reducing the number of wirings arranged in the second region DA2, the transmittance of the second region DA2 can be increased compared to the first region DA1. Therefore, the influence exerted by the pixel PX on other parts arranged in the second region DA2 can be reduced.

[0116] Next, refer to Figure 5 and Figure 6 to describe the display device 1000 according to an exemplary embodiment.

[0117] Since the display device 1000 according to the exemplary embodiments shown in Figure 5 and Figure 6 has many parts the same as the display device 1000 according to the exemplary embodiments shown in Figures 1 to 4 , the description of the same parts is omitted. The difference between this exemplary embodiment and the previous exemplary embodiment regarding Figures 1 to 4 is that the second initialization voltage line 128 and the second initialization voltage supply line 1128 are not arranged in the second region DA2, and this is further described.

[0118] Figure 5is a top view showing some pixels PX arranged in a second region DA2 of a display device 1000, and Figure 6 is a circuit diagram of a pixel PX arranged in a second region DA2 of a display device 1000 according to an exemplary embodiment.

[0119] As Figure 5 shown, in the second region DA2, a plurality of pixels PX and a plurality of wirings 127, 171, and 1127 connected to the plurality of pixels PX to transmit signals may be arranged.

[0120] In the present exemplary embodiment, the arrangement form of the pixels PX in the first region DA1 and the second region DA2 may be substantially the same as the arrangement form of the pixels PX in the first region DA1 and the second region DA2 in the previous exemplary embodiment. Accordingly, the number of pixels PX per unit area in the second region DA2 is less than the number of pixels PX per unit area in the first region DA1. For example, the number of pixels PX per unit area in the second region DA2 may be about one-fourth of the number of pixels PX per unit area in the first region DA1.

[0121] The plurality of wirings may include a plurality of data lines 171, a plurality of first initialization voltage lines 127, and a plurality of first initialization voltage supply lines 1127. In the previous exemplary embodiment, a plurality of second initialization voltage lines 128 and a plurality of second initialization voltage supply lines 1128 were arranged in the first region DA1 and the second region DA2. However, in the present exemplary embodiment, the second initialization voltage lines 128 and the second initialization voltage supply lines 1128 are not arranged in the second region DA2. That is, in the present exemplary embodiment, the second initialization voltage lines 128 and the second initialization voltage supply lines 1128 are positioned in the first region DA1 rather than the second region DA2.

[0122] The number of wirings per unit area in the second region DA2 is less than the number of wirings per unit area in the first region DA1. The number of first initialization voltage supply lines 1127 per unit area in the second region DA2 may be more than about one-sixth and less than 1 times the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the first region DA1.

[0123] For example, the number of the first initialization voltage supply lines 1127 per unit area in the second region DA2 may be approximately one-fourth of the sum of the number of the first initialization voltage supply lines 1127 and the number of the second initialization voltage supply lines 1128 per unit area in the first region DA1. As described above, by further reducing the number of wirings arranged in the second region DA2, the transmittance of the second region DA2 can be further increased compared to the first region DA1. Accordingly, the influence exerted by the pixel PX on other parts arranged in the second region DA2 can be reduced.

[0124] Since the second initialization voltage line 128 and the second initialization voltage supply line 1128 are not arranged in the second region DA2, the circuit of the pixel PX arranged in the second region DA2 may be different from the circuit of the pixel PX positioned in the first region DA1. Next, refer to Figure 6 the connection relationship between one pixel PX arranged in the second region DA2 and each wiring.

[0125] As Figure 6 shown in, one pixel PX of the display device 1000 according to an exemplary embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, a boosting capacitor Cboost, and a light emitting diode LED that are connected to a plurality of wirings 127, 151, 152, 153, 154, 155, 171, 172, and 741.

[0126] A plurality of wirings 127, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of wirings include a first initialization voltage line 127, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, a light emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0127] The pixel PX arranged in the first region DA1 is connected to the second initialization voltage line 128, but the pixel PX arranged in the second region DA2 is not connected to the second initialization voltage line 128. Accordingly, the seventh transistor T7 of the pixel PX arranged in the first region DA1 is connected to the second initialization voltage line 128, but the seventh transistor T7 of the pixel PX arranged in the second region DA2 is not connected to the second initialization voltage line 128. The second electrode of the seventh transistor T7 of the pixel PX arranged in the second region DA2 may be connected to the first initialization voltage line 127. If the seventh transistor T7 is turned on by a low voltage of the bypass signal GB, the first initialization voltage VINT is applied to the anode to be initialized of the light emitting diode LED.

[0128] Next, refer to Figures 7 to 9 to describe the display device 1000 according to an exemplary embodiment.

[0129] According to Figures 7 to 9 the display device 1000 according to the exemplary embodiment shown in Figures 1 to 6 is mostly the same as the display device 1000 according to the exemplary embodiment shown in

[0130] First, refer to Figure 7 to describe the connection of the pixel PX and wirings of the display device 1000 according to an exemplary embodiment.

[0131] Figure 7 is a view showing the connection relationship of some pixels PX and wirings of the display device 1000 according to an exemplary embodiment.

[0132] As Figure 7 shown, the display device 1000 according to an exemplary embodiment includes a plurality of pixels PX and a plurality of wirings 151, 152, 153, and 155 connected to the plurality of pixels PX to transmit signals. Figure 7 Only some of the wirings connected to each pixel PX are shown, and the connection relationship between one pixel PX and each wiring of the display device 1000 according to the present exemplary embodiment may have Figure 3 or Figure 6 the form of the circuit diagram shown in

[0133] The display area DA may include a first area DA1 and a second area DA2. The first area DA1 and the second area DA2 may each include a plurality of pixels PX. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3, and four pixels PX (for example, one first pixel PX1, two second pixels PX2, and one third pixel PX3) may form a pixel group PXGr.

[0134] In the present exemplary embodiment, the arrangement form of the pixels PX in the first area DA1 and the second area DA2 may be substantially the same as the arrangement form of the pixels PX in the first area DA1 and the second area DA2 in the previous exemplary embodiment. Therefore, the number of pixels PX per unit area in the second area DA2 is less than the number of pixels PX per unit area in the first area DA1. Figure 7Some pixel columns arranged in the first region DA1 and some pixel columns arranged in the second region DA2 are shown side by side. The pixel PX may not be arranged in the second region DA2 corresponding to the third and fourth pixel rows of the first region DA1, and the pixel PX may not be arranged in the second region DA2 corresponding to the seventh and eighth pixel rows of the first region DA1.

[0135] The plurality of wirings may include a first scan line 151, a second scan line 152, an initialization control line 153, and a light emission control line 155.

[0136] The first scan line 151 is arranged for each pixel row and connected to each pixel PX in the pixel row. That is, the pixels PX arranged in the same row are connected to the same first scan line 151 to receive the first scan signals GW[1] to GW

[10] . The display device 1000 according to an exemplary embodiment may further include a scan driver GWD that generates the first scan signals GW[1] to GW

[10] to be transmitted through the first scan line 151. The scan driver GWD may include a plurality of stages GW_1 to GW_10. Each of the stages GW_1 to GW_10 of the scan driver GWD may correspond to each pixel row. Each of the stages GW_1 to GW_10 of the scan driver GWD is connected to each pixel PX through the first scan line 151, thereby transmitting the first scan signals GW[1] to GW

[10] to each pixel PX. The first scan signals GW[1] to GW

[10] may be sequentially applied to each pixel row.

[0137] The light emission control line 155 is arranged for each pixel row and connected to each pixel PX. That is, the pixels PX arranged in the same row are connected to the same light emission control line 155 to receive the light emission control signals EM[1] to EM

[10] . The display device 1000 according to an exemplary embodiment may further include a light emission driver EMD that generates the light emission control signals EM[1] to EM

[10] to be transmitted through the light emission control line 155. The light emission driver EMD may include a plurality of stages EM_1 to EM_10. Each of the stages EM_1 to EM_10 of the light emission driver EMD may correspond to each pixel row. Each of the stages EM_1 to EM_10 of the light emission driver EMD may be connected to each pixel PX through the light emission control line 155 to transmit the light emission control signals EM[1] to EM

[10] to each pixel PX.

[0138] The initialization control line 153 is connected to each pixel PX. Pixels PX arranged in the same row may be connected to the same initialization control line 153, and initialization control signals GI[1 / 2] to GI[9 / 10] are transmitted. The same initialization control signals GI[1 / 2] to GI[9 / 10] may be applied to two adjacent pixel rows. Accordingly, the initialization control line 153 of the pixels PX connected to the first row may be connected to the initialization control line 153 of the pixels PX connected to the second row. Similarly, the initialization control lines 153 of the pixels PX connected to the third row and the fourth row may be connected to each other, and the initialization control lines 153 of the pixels PX connected to the fifth row and the sixth row may be connected to each other. In the case of the third row and the fourth row, the pixels PX are arranged in the first region DA1, however, the pixels PX are not arranged in the second region DA2. Accordingly, in the second region DA2, a single initialization control line 153 may pass between the third row and the fourth row.

[0139] The display device 1000 according to an exemplary embodiment may further include an initialization driving circuit GID that generates the initialization control signals GI[1 / 2] to GI[9 / 10] to be transmitted through the initialization control line 153. The initialization driving circuit GID may include a plurality of stages GI_1 / 2 to GI_9 / 10. Each of the stages GI_1 / 2 to GI_9 / 10 of the initialization driving circuit GID may correspond to every two pixel rows. Each of the stages GI_1 / 2 to GI_9 / 10 of the initialization driving circuit GID is connected to each pixel PX through the initialization control line 153, thereby transmitting the initialization control signals GI[1 / 2] to GI[9 / 10] to each pixel PX.

[0140] The second scan line 152 is connected to each pixel PX. Pixels PX arranged in the same row are connected to the same second scan line 152, thereby receiving second scan signals GC[1 / 2] to GC[9 / 10] through the second scan line 152. In this case, the same second scan signals GC[1 / 2] to GC[9 / 10] may be applied to two adjacent pixel rows. Accordingly, the second scan line 152 connected to the pixels PX of the first row may be connected to the second scan line 152 connected to the pixels PX of the second row. Similarly, the second scan lines 152 connected to the pixels PX of the third and fourth rows may be connected to each other. The second scan lines 152 connected to the pixels PX of the fifth and sixth rows may be connected to each other. In the case of the third and fourth rows, the pixels PX are arranged in the first region DA1, but the pixels PX are not arranged in the second region DA2. In this case, the second scan line 152 is not arranged in the portion corresponding to the third and fourth rows in the second region DA2. Accordingly, the number of second scan lines 152 per unit area in the second region DA2 is less than the number of second scan lines 152 per unit area in the first region DA1. For example, the number of second scan lines 152 per unit area in the second region DA2 may be approximately half of the number of second scan lines 152 per unit area in the first region DA1. As described above, by reducing the number of wirings arranged in the second region DA2, the transmittance of the second region DA2 may be increased compared to the first region DA1. Accordingly, the influence of the pixel PX on other portions arranged in the second region DA2 may be reduced.

[0141] The display device 1000 according to the present exemplary embodiment does not include a separate driving unit for generating the second scan signals GC[1 / 2] to GC[9 / 10]. Instead, the display device 1000 according to an exemplary embodiment may include a connection wiring CL that connects at least one of the plurality of initialization control lines 153 and at least one of the plurality of second scan lines 152. For example, the connection wiring CL may connect the second scan line 152 among the plurality of second scan lines 152 that is connected to the pixel PX of the first row and the initialization control line 153 among the plurality of initialization control lines 153 that is connected to the pixel PX of the ninth row. This is merely an example, and in another exemplary embodiment, the second scan line 152 connected to the pixel PX of the first row may be connected to the initialization control line 153 connected to the pixel PX of a row other than the ninth row. That is, the second scan line 152 among the plurality of second scan lines 152 that is connected to the pixel PX of the first row may be connected to the initialization control line 153 among the plurality of initialization control lines 153 that is connected to the pixel PX of the nth row, and the value of n may be set in various ways. The second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixel PX of the first row through the connection wiring CL may have the same timing as the initialization control signal GI[9 / 10] applied to the initialization control line 153 connected to the pixel PX of the ninth row. That is, the second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixel PX of the first row may have the same timing as the initialization control signal applied to the initialization control line 153 connected to the pixel PX of the nth row, and the value of n may be set in various ways. Therefore, the initialization driving circuit GID may transmit the initialization control signals GI[1 / 2] to GI[9 / 10] as the second scan signals GC[1 / 2] to GC[9 / 10] to the second scan line 152.

[0142] Next, referring to Figure 8 and Figure 9 describe the signals applied to each wiring.

[0143] Figure 8 is a signal timing diagram showing a plurality of signals applied to two adjacent pixel rows of the display device 1000 according to an exemplary embodiment, and Figure 9 is a signal timing diagram showing the relationship of signals applied to some pixels PX of the display device 1000 according to an exemplary embodiment.

[0144] As Figure 8 and Figure 9As shown, after the light emission control signals EM[1] and EM[2] of high voltage are applied to the pixels PX of the first row and the second row, the initialization control signal GI[1 / 2] of high voltage can be applied to the pixels PX of the first row and the second row. Next, the initialization control signal GI[1 / 2] can be changed to a low voltage, and the first scan signals GW[1] and GW[2] of low voltage can be sequentially applied to the pixels PX of the first row and the second row. In addition, the second scan signals GC[1 / 2] of high voltage can be applied to the pixels PX of the first row and the second row. At this time, the time that the initialization control signal GI[1 / 2] is held at high voltage is similar to the time that the second scan signal GC[1 / 2] is held at high voltage, but there is a difference in the timing of applying the signals. That is, when the initialization control signal GI[1 / 2] has been shifted by a predetermined time, the second scan signal GC[1 / 2] can be obtained. The initialization control signal GI[1 / 2] applied to the pixels PX of the third row and the fourth row can have a value shifted from the initialization control signal GI[1 / 2] applied to the pixels PX of the first row and the second row. The second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX of the first row and the second row can have substantially the same timing as the initialization control signal GI[9 / 10] applied to the initialization control line 153 connected to the pixels PX of the ninth row and the tenth row. However, this is only an example, and according to the design of each pixel PX, the second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX of the first row and the second row can have substantially the same timing as the initialization control signal applied to the initialization control line 153 connected to the pixels PX of the eleventh row and the twelfth row.

[0145] Next, refer to Figure 10 to describe the display device 1000 according to another exemplary embodiment.

[0146] According to Figure 10 the display device 1000 according to the exemplary embodiment shown in Figures 7 to 9 is mostly the same as the display device 1000 according to the exemplary embodiment shown in

[0147] Figure 10 is a view showing the connection relationship of some pixels PX and wirings of the display device 1000 according to the exemplary embodiment.

[0148] As Figure 10As shown in the figure, a display device 1000 according to an exemplary embodiment includes a plurality of pixels PX and a plurality of wirings 151, 152, 153, and 155 connected to the plurality of pixels PX to transmit signals.

[0149] The display area DA may include a first area DA1 and a second area DA2, and the number of pixels PX per unit area in the second area DA2 is less than the number of pixels PX per unit area in the first area DA1.

[0150] The plurality of wirings may include a first scan line 151, a second scan line 152, an initialization control line 153, and a light emission control line 155.

[0151] The initialization control line 153 is connected to each pixel PX. In the case of the previous exemplary embodiment, in the second area DA2, the pixels PX in the first row and the pixels PX in the second row may be connected to different initialization control lines 153, and the initialization control line 153 connected to the pixels PX in the first row may be connected to the initialization control line 153 connected to the pixels PX in the second row. In the case of the present exemplary embodiment, in the second area DA2, the pixels PX in the first row and the pixels PX in the second row are connected to the same initialization control line 153. In this case, the initialization control line 153 may be arranged between the pixels PX in the first row and the pixels PX in the second row. Similarly, in the second area DA2, the pixels PX in the fifth row and the pixels PX in the sixth row are connected to the same initialization control line 153. In this case, the initialization control line 153 may be arranged between the pixels PX in the fifth row and the pixels PX in the sixth row. That is, the pixels PX in two adjacent rows in the second area DA2 may be connected to the same initialization control line 153. Therefore, the number of initialization control lines 153 per unit area in the second area DA2 is less than the number of initialization control lines 153 per unit area in the first area DA1. For example, the number of initialization control lines 153 per unit area in the second area DA2 may be approximately half of the number of initialization control lines 153 per unit area in the first area DA1. In this case, the pixels PX in two adjacent rows in the second area DA2 may have a flipped structure that is symmetric up and down based on the initialization control line 153.

[0152] Next, refer to Figures 11 to 30 to describe the display device 1000 according to an exemplary embodiment.

[0153] According to Figures 11 to 30 the display device 1000 according to the exemplary embodiment shown in the figure and according to Figures 1 to 10Most of the display device 1000 in the exemplary embodiment shown is the same as that in the previous exemplary embodiment, so the description of the same parts is omitted. The difference between this exemplary embodiment and the previous exemplary embodiment is that in the first region DA1 and the second region DA2, the channel length of the driving transistor T1 and the capacitances of the storage capacitors Cst1 and Cst2 are different, and this is further described below.

[0154] First, refer to Figures 11 to 19 to describe the pixel PX in the first region DA1 of the display device 1000 according to the exemplary embodiment.

[0155] Figure 11 is a top view of some pixels PX in the first region DA1 of the display device 1000 according to the exemplary embodiment, Figure 12 is a cross-sectional view taken along the Figure 11 line XII-XII', Figure 13 is a cross-sectional view taken along the Figure 11 line XIII-XIII', and Figures 14 to 19 is a top view sequentially showing the manufacturing sequence of some pixels PX in the first region DA1 of the display device 1000 according to the exemplary embodiment.

[0156] Figures 11 to 19 shows two adjacent pixels PX among the plurality of pixels PX arranged in the first region DA1 of the display device 1000 according to the exemplary embodiment, and corresponds to the circuit diagram shown in Figure 3 . However, this exemplary embodiment is not limited thereto, and may have a pixel structure modified to correspond to the circuit diagram shown in Figure 6 , or various changes may be made in another exemplary embodiment.

[0157] As shown in Figures 11 to 19 , a polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1 may be disposed on the substrate 110. Figure 14 shows the polycrystalline semiconductor. In addition to the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1, the polycrystalline semiconductor may further include the channels, first electrodes, and second electrodes of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively.

[0158] The channel 1132 of the driving transistor T1 may be formed in a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto, and various changes may be made in another exemplary embodiment. For example, the channel 1132 of the driving transistor T1 may be curved into different shapes, or may be formed in a rod shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 may be disposed on both sides of the channel 1132 of the driving transistor T1. The first electrode 1131 of the driving transistor T1 extends vertically up and down on a plane, such that the downward extending portion may be connected to the second electrode of the second transistor T2, and the upward extending portion may be connected to the second electrode of the fifth transistor T5. The second electrode 1133 of the driving transistor T1 extends upward on a plane, and may be connected to the first electrode of the sixth transistor T6.

[0159] The buffer layer 111 may be disposed between the substrate 110 and the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1. The buffer layer 111 may have a single-layer or multi-layer structure. The buffer layer 111 may include an organic insulating material or an inorganic insulating material.

[0160] The first gate insulating layer 141 may be disposed on the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1. The first gate insulating layer 141 may include silicon nitride, silicon oxide, etc.

[0161] The first gate conductor including the gate electrode 1151 of the driving transistor T1 may be disposed on the first gate insulating layer 141. Figure 15 The polycrystalline semiconductor and the first gate conductor are shown together. In addition to the gate electrode 1151 of the driving transistor T1, the first gate conductor may further include the gate electrodes of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively.

[0162] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1.

[0163] The first gate conductor may further include a first scan line 151 and an emission control line 155. The first scan line 151 and the emission control line 155 may extend substantially in the horizontal direction. The first scan line 151 may be connected to the gate electrode of the second transistor T2 and the first electrode of the boost capacitor Cboost. The first scan line 151 may be connected to the gate electrode of the seventh transistor T7 disposed at the pixel of the next stage. That is, the bypass control line 154 connected to the seventh transistor T7 may be composed of the first scan line 151 of the previous stage. The gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be connected to the emission control line 155.

[0164] The doping process may be performed after forming the first gate conductor including the gate electrode 1151 of the driving transistor T1. The polycrystalline semiconductor covered by the first gate conductor is not doped, and the portion of the polycrystalline semiconductor not covered by the first gate conductor is doped to have the same characteristics as the conductor. In this case, the doping process using a p-type dopant may be performed, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including the polycrystalline semiconductor may have p-type transistor characteristics.

[0165] The second gate insulating layer 142 may be disposed on the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the first gate insulating layer 141. The second gate insulating layer 142 may include silicon nitride, silicon oxide, etc.

[0166] On the second gate insulating layer 142, a second gate conductor including the first storage electrode 1153 of the storage capacitor Cst1, the light-shielding layer 3155 of the third transistor T3, and the light-shielding layer 4155 of the fourth transistor T4 may be disposed. Figure 16 The polycrystalline semiconductor, the first gate conductor, and the second gate conductor are shown together.

[0167] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form the storage capacitor Cst1. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst1. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst1 may overlap with the gate electrode 1151 of the driving transistor T1. The light-shielding layer 3155 of the third transistor T3 may overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light-shielding layer 4155 of the fourth transistor T4 may overlap with the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

[0168] The second gate conductor may further include a lower second scan line 152a, a lower initialization control line 153a, and an initialization voltage line 127. The lower second scan line 152a, the lower initialization control line 153a, and the initialization voltage line 127 may extend approximately in a horizontal direction. The lower second scan line 152a may be connected to the light-shielding layer 3155 of the third transistor T3.

[0169] The lower initialization control line 153a may be connected to the light-shielding layer 4155 of the fourth transistor T4.

[0170] The first interlayer insulating layer 161 may be disposed on the second gate conductor including the first storage electrode 1153 of the storage capacitor Cst1, the light-shielding layer 3155 of the third transistor T3, and the light-shielding layer 4155 of the fourth transistor T4. The first interlayer insulating layer 161 may include silicon nitride, silicon oxide, etc.

[0171] On the first interlayer insulating layer 161, an oxide semiconductor including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4 may be disposed. Figure 17 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, and the oxide semiconductor are shown together.

[0172] The oxide semiconductor may include at least one of the following: main metal oxides such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn); binary metal oxides such as In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, or In-Ga-based oxide; ternary metal oxides such as In-Ga-Zn-based oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, or In-Lu-Zn-based oxide; and quaternary metal oxides such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, or In-Hf-Al-Zn-based oxide. For example, the oxide semiconductor may include indium-gallium-zinc oxide (“IGZO”) in the In-Ga-Zn-based oxide.

[0173] The channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4 may be connected to each other to form a single body. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may be disposed on both sides of the channel 3137 of the third transistor T3. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 may be disposed on both sides of the channel 4137 of the fourth transistor T4. The second electrode 3138 of the third transistor T3 may be connected to the second electrode 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 may overlap with the light-shielding layer 3155. The channel 4137 of the fourth transistor T4 may overlap with the light-shielding layer 4155.

[0174] The oxide semiconductor may further include a second electrode of the boost capacitor Cboost. The second electrode of the boost capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3. The second electrode of the boost capacitor Cboost may be connected to the second electrode 4138 of the fourth transistor T4. The second electrode of the boost capacitor Cboost may overlap with the first electrode of the boost capacitor Cboost. The capacitance of the boost capacitor Cboost may be determined by the overlapping area of the first electrode and the second electrode of the boost capacitor Cboost and the thicknesses of the second gate insulating layer 142 and the first interlayer insulating layer 161 disposed between the first electrode and the second electrode.

[0175] The third gate insulating layer 143 may be disposed on the oxide semiconductor including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. The third gate insulating layer 143 may be disposed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. Accordingly, the third gate insulating layer 143 may cover the upper surface and the side surfaces of the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the upper surface and the side surfaces of the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. However, according to this exemplary embodiment of the present invention, it is not limited thereto, and the third gate insulating layer 143 may not be disposed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. For example, the third gate insulating layer 143 may overlap with the channel 3137 of the third transistor T3, but may not overlap with the first electrode 3136 and the second electrode 3138. In addition, the third gate insulating layer 143 may overlap with the channel 4137 of the fourth transistor T4, but may not overlap with the first electrode 4136 and the second electrode 4138.

[0176] On the third gate insulating layer 143, a third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 may be disposed. Figure 18 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, the oxide semiconductor, and the third gate conductor are shown together.

[0177] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may overlap with the light-shielding layer 3155 of the third transistor T3.

[0178] The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4. The gate electrode 4151 of the fourth transistor T4 may overlap with the light-shielding layer 4155 of the fourth transistor T4.

[0179] The third gate conductor may further include a second initialization voltage line 128, an upper second scan line 152b, and an upper initialization control line 153b. The second initialization voltage line 128, the upper second scan line 152b, and the upper initialization control line 153b may extend substantially in a horizontal direction. The upper second scan line 152b and the lower second scan line 152a together form the second scan line 152. The upper second scan line 152b may be connected to the gate electrode 3151 of the third transistor T3. The upper initialization control line 153b and the lower initialization control line 153a together form the initialization control line 153. The upper initialization control line 153b may be connected to the gate electrode 4151 of the fourth transistor T4.

[0180] After forming the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4, a doping process may be performed. The portion of the oxide semiconductor covered by the third gate conductor is not doped, and the portion of the oxide semiconductor not covered by the third gate conductor is doped to have the same characteristics as the conductor. The channel 3137 of the third transistor T3 may be disposed below the gate electrode 3151 to overlap with the gate electrode 3151. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 4137 of the fourth transistor T4 may be disposed below the gate electrode 4151 to overlap with the gate electrode 4151. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151. The doping process of the oxide semiconductor may be performed using an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor may have n-type transistor characteristics.

[0181] The second interlayer insulating layer 162 may be disposed on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. The second interlayer insulating layer 162 may have a first opening 1165, a second opening 1166, a third opening 3165, a fourth opening 3166, a fifth opening 4165, and a sixth opening 4166.

[0182] The first opening 1165 may overlap at least a portion of the gate electrode 1151 of the driving transistor T1. The first opening 1165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. The first opening 1165 may overlap the opening 1152 of the first storage electrode 1153. The first opening 1165 may be disposed inside the opening 1152 of the first storage electrode 1153. The second opening 1166 may overlap at least a portion of the boost capacitor Cboost. The second opening 1166 may be further formed in the third gate insulating layer 143.

[0183] The third opening 3165 may overlap at least a part of the second electrode 1133 of the driving transistor T1. The third opening 3165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141. The fourth opening 3166 may overlap at least a part of the first electrode 3136 of the third transistor T3. The fourth opening 3166 may be further formed in the third gate insulating layer 143.

[0184] The fifth opening 4165 may overlap at least a part of the first electrode 4136 of the fourth transistor T4. The fifth opening 4165 may be further formed in the third gate insulating layer 143. The sixth opening 4166 may overlap at least a part of the first initialization voltage line 127. The sixth opening 4166 may be further formed in the third gate insulating layer 143 and the first interlayer insulating layer 161.

[0185] On the second interlayer insulating layer 162, a first data conductor including a first connection electrode 1175, a second connection electrode 3175, and a third connection electrode 4175 may be disposed. Figure 19 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, the oxide semiconductor, the third gate conductor, and the first data conductor are shown together.

[0186] The first connection electrode 1175 may overlap the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 1165 and the opening 1152 of the first storage electrode 1153. The first connection electrode 1175 may overlap the boost capacitor Cboost. The first connection electrode 1175 may be connected to the second electrode of the boost capacitor Cboost through the second opening 1166. Accordingly, the gate electrode 1151 of the driving transistor T1 and the second electrode of the boost capacitor Cboost may be connected by the first connection electrode 1175. In this case, the gate electrode 1151 of the driving transistor T1 may also be connected by the first connection electrode 1175 to the second electrode 3138 of the third transistor T3 and the second electrode 4138 of the fourth transistor T4.

[0187] The second connection electrode 3175 may overlap with the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 may be connected to the second electrode 1133 of the driving transistor T1 through the third opening 3165. The second connection electrode 3175 may overlap with the first electrode 3136 of the third transistor T3. The second connection electrode 3175 may be connected to the first electrode 3136 of the third transistor T3 through the fourth opening 3166. Accordingly, the second electrode 1133 of the driving transistor T1 and the first electrode 3136 of the third transistor T3 may be connected by the second connection electrode 3175.

[0188] The third connection electrode 4175 may overlap with the first electrode 4136 of the fourth transistor T4. The third connection electrode 4175 may be connected to the first electrode 4136 of the fourth transistor T4 through the fifth opening 4165. The third connection electrode 4175 may overlap with the first initialization voltage line 127. The third connection electrode 4175 may be connected to the first initialization voltage line 127 through the sixth opening 4166. Accordingly, the first electrode 4136 of the fourth transistor T4 and the first initialization voltage line 127 may be connected by the third connection electrode 4175.

[0189] The first data conductor may further include a second initialization voltage supply line 1128. The second initialization voltage supply line 1128 may extend approximately in the vertical direction and may be disposed between two adjacent pixels PX. The second initialization voltage supply line 1128 may branch left and right at the intersection with the second initialization voltage line 128. The second initialization voltage supply line 1128 may be connected to the second initialization voltage line 128 to transmit the second initialization voltage AINT.

[0190] The third interlayer insulating layer 180 may be disposed on the first data conductor including the first connection electrode 1175, the second connection electrode 3175, and the third connection electrode 4175.

[0191] The data line 171 and the driving voltage line 172 may be disposed on the third interlayer insulating layer 180. The data line 171 and the driving voltage line 172 may extend approximately in the vertical direction. The data line 171 may be connected to the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5.

[0192] Although not shown, a passivation layer may be disposed on the data line 171 and the driving voltage line 172, and an anode may be disposed on the passivation layer. The anode may be connected to the sixth transistor T6 and may receive the output current of the driving transistor T1. A partition wall may be disposed above the anode. An opening is formed in the partition wall, and the opening of the partition wall may overlap with the anode. A light-emitting element layer may be disposed in the opening of the partition wall. A cathode may be disposed on the light-emitting element layer and the partition wall. The anode, the light-emitting element layer, and the cathode constitute a light-emitting diode LED.

[0193] As described above, in the display device 1000 according to an exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. As described above, by forming the third transistor T3 and the fourth transistor T4 to include a semiconductor material different from that of the driving transistor T1, driving can be performed more stably and reliability can be improved.

[0194] Above, reference Figure 11 and Figure 19 described that the first connection electrode 1175 is connected to the second electrode 3138 of the third transistor T3, the second electrode 4138 of the fourth transistor T4, and the second electrode of the boost capacitor Cboost through the second opening 1166. In this exemplary embodiment, the shape of the first connection electrode 1175 and the position of the second opening 1166 may be changed, and reference Figure 20 describes this.

[0195] Figure 20 is a top view showing some pixels PX in the first region DA1 of the display device 1000 according to an exemplary embodiment.

[0196] As Figure 20 shown, similar to Figure 11 the exemplary embodiment, the first connection electrode 1175 is connected to the second electrode 3138 of the third transistor T3, the second electrode 4138 of the fourth transistor T4, and the second electrode of the boost capacitor Cboost through the second opening 1166. The widths of both ends of the first connection electrode 1175 are wider than those of other portions. In Figure 11 one of the two ends of the first connection electrode 1175 may overlap with the first scan line 151. That is, the first scan line 151, the second electrode of the boost capacitor Cboost, and the first connection electrode 1175 overlap. In Figure 20 one end of the first connection electrode 1175 is bent to be disposed between the first scan line 151 and the second scan line 152. The first connection electrode 1175 and the first scan line 151 partially overlap, but the overlapping area between the first connection electrode 1175 and the first scan line 151 andFigure 11 It can be smaller compared to. Therefore, the influence on the connection path of the driving transistor T1 and the third transistor T3 can be minimized by the signal applied to the first scan line 151.

[0197] In the above description, the first connection electrode 1175 and the first scan line 151 partially overlap, but this exemplary embodiment of the present invention is not limited thereto. In some cases, the first connection electrode 1175 may not overlap with the first scan line 151 at all.

[0198] Next, refer to Figures 21 to 29 to describe the pixel PX in the second region DA2 of the display device 1000 according to an exemplary embodiment.

[0199] Figure 21 is a top view showing some pixels PX in the second region DA2 of the display device 1000 according to an exemplary embodiment. Figure 22 is a cross-sectional view taken along the Figure 21 line XXII - XXII’, Figure 23 is a cross-sectional view taken along the Figure 21 line XXIII - XXIII’, and Figures 24 to 29 is a top view sequentially showing some pixels PX in the second region DA2 according to the manufacturing sequence of the display device 1000 according to an exemplary embodiment.

[0200] Figures 21 to 29 shows four adjacent pixels PX among the plurality of pixels PX arranged in the second region DA2 of the display device 1000 according to an exemplary embodiment, and they correspond to the Figure 3 circuit diagram. However, this exemplary embodiment is not limited thereto, and a modified pixel structure may be provided to correspond to the Figure 6 circuit diagram shown, or various changes may be made in another exemplary embodiment.

[0201] In the first region DA1 and the second region DA2 of the display device 1000 according to an exemplary embodiment, each layer may be formed in the same process and may have a substantially similar pixel structure. However, the specifications of some layers may be designed to be different, and specifically, the width and length of the channel 1132 of the driving transistor T1 may be designed differently. This will be further described below.

[0202] As Figure 22As shown, the light-shielding member 500 may be disposed on the substrate 110. The light-shielding member 500 may be integrally disposed in the second region DA2. The light-shielding member 500 may not be disposed in the first region DA1. That is, after the light-shielding member 500 is formed as a whole on the substrate 110, the light-shielding member 500 positioned in the first region DA1 may be patterned to be removed. Although not illustrated, a separate insulating layer, buffer layer, etc. may be disposed between the substrate 110 and the light-shielding member 500.

[0203] A polysemiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1 may be disposed on the light-shielding member 500. Figure 24 The polysemiconductor is shown.

[0204] The channel 1132 of the driving transistor T1 may be formed in a rod shape in a plane. However, the shape of the channel 1132 of the driving transistor T1 according to the present invention is not limited thereto, and various changes may be made in another exemplary embodiment. In the first region DA1 and the second region DA2, the planar shape of the channel 1132 of the driving transistor T1 may be different. For example, the planar shape of the channel 1132 of the driving transistor T1 may be formed in a curved shape in the first region DA1 and may be formed in a rod shape in the second region DA2.

[0205] The buffer layer 111 may be disposed between the light-shielding member 500 and the polysemiconductor. The first gate insulating layer 141 may be disposed on the polysemiconductor.

[0206] A first gate conductor including the gate electrode 1151 of the driving transistor T1 may be disposed on the first gate insulating layer 141. Figure 25 The polysemiconductor and the first gate conductor are shown together.

[0207] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1. The overlapping area between the gate electrode 1151 of the driving transistor T1 and the polysemiconductor in the first region DA1 and the overlapping area between the gate electrode 1151 of the driving transistor T1 and the polysemiconductor in the second region DA2 may be different. In addition, the width W1 (see Figure 11 and Figure 20 ) of the channel 1132 of the driving transistor T1 in the first region DA1 and the width W2 (see Figure 21 ) of the channel 1132 of the driving transistor T1 in the second region DA2 may be different. Further, the length L1 (see Figure 12) and the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 (see Figure 22 ) may be different. Additionally, the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1 and the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 may be different.

[0208] The gate electrode 1151 of the driving transistor T1 overlaps with the light shielding member 500 to form an auxiliary capacitor Cas. The light shielding member 500 may be disposed between the substrate 110 and the gate electrode 1151 of the driving transistor T1. The buffer layer 111 and the first gate insulating layer 141 may be disposed between the light shielding member 500 and the gate electrode 1151. Since the light shielding member 500 is disposed in the entire second region DA2, it overlaps not only with the driving transistor T1 but also with the gate electrodes of the second to seventh transistors T2, T3, T4, T5, T6, and T7 to form the auxiliary capacitor Cas. The capacitance of the auxiliary capacitor Cas may be determined by the overlapping area between the light shielding member 500 and the gate electrode 1151 of the driving transistor T1 and the thicknesses of the buffer layer 111 and the first gate insulating layer 141 disposed between the light shielding member 500 and the gate electrode 1151 of the driving transistor T1.

[0209] The first gate conductor may further include a first scan line 151, a light emission control line 155, and a bypass control line 154. The second gate insulating layer 142 may be disposed on the first gate conductor and the first gate insulating layer 141.

[0210] The second gate conductor including the first storage electrode 1153 of the storage capacitor Cst2, the light shielding layer 3155 of the third transistor T3, and the light shielding layer 4155 of the fourth transistor T4 may be disposed on the second gate insulating layer 142. Figure 26 The polycrystalline semiconductor, the first gate conductor, and the second gate conductor are shown together.

[0211] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a storage capacitor Cst2. The capacitance of the storage capacitor Cst2 can be determined by the overlapping area between the gate electrode 1151 of the driving transistor T1 and the first storage electrode 1153 and the thickness of the second gate insulating layer 142 between the gate electrode 1151 of the driving transistor T1 and the first storage electrode 1153. The overlapping area between the gate electrode 1151 of the driving transistor T1 in the first region DA1 and the first storage electrode 1153 may be different from the overlapping area between the gate electrode 1151 of the driving transistor T1 in the second region DA2 and the first storage electrode 1153. Accordingly, the capacitance of the storage capacitor Cst1 in the first region DA1 and the capacitance of the storage capacitor Cst2 in the second region DA2 may be different.

[0212] In the present exemplary embodiment, the number of pixels PX per unit area in the second region DA2 is less than the number of pixels PX per unit area in the first region DA1. Accordingly, when the pixels PX arranged in the first region DA1 and the pixels PX located in the second region DA2 have the same structure and are driven by the same voltage, the brightness of the second region DA2 may be lower than the brightness of the first region DA1. Accordingly, the boundary between the first region DA1 and the second region DA2 can be recognized. In the present exemplary embodiment, the pixels PX arranged in the second region DA2 have a brightness similar to that of the pixels PX arranged in the first region DA1 by distinguishing the structures of the pixels PX arranged in the first region DA1 and the second region DA2, so that the boundary between the first region DA1 and the second region DA2 is not recognized and the image can be naturally displayed. Next, the differences in the length and width of the channel 1132 of the driving transistor T1 and the capacitances of the storage capacitors Cst1 and Cst2 and the auxiliary capacitor Cas between the first region DA1 and the second region DA2 are described.

[0213] Table 1 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the brightness of the second region DA2 to the brightness of the first region DA1 is 60%, 80%, and 100% respectively in the first pixel PX1 representing red.

[0214] In the first region DA1 and the second region DA2, the widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 micrometers (μm).

[0215] (Table 1)

[0216]

[0217]

[0218] When the first pixel PX1 represents red, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. The ratio of the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 to the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1 can be greater than or equal to about 168% and less than or equal to about 185%. Considering the error range, when considering the numerical range described in the parentheses, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than or equal to about 155% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1, and can be less than or equal to about 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. When the first pixel PX1 displays red, the capacitance of the storage capacitor Cst2 in the second region DA2 can be greater than or equal to about 86% and less than or equal to about 140% of the capacitance of the storage capacitor Cst1 in the first region DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second region DA2 can be greater than or equal to about 27% and less than or equal to 37% of the capacitance of the storage capacitor Cst1 in the first region DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second region DA2 can be greater than or equal to about 113% and less than or equal to about 177% of the capacitance of the storage capacitor Cst1 in the first region DA1.

[0219] Table 2 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the luminance of the second region DA2 to the luminance of the first region DA1 is 60%, 80%, and 100% respectively in the second pixel PX2 representing green. In the first region DA1 and the second region DA2, the widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 μm.

[0220] (Table 2)

[0221]

[0222]

[0223] When the second pixel PX2 represents green, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. The ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than or equal to approximately 155% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1, and can be less than or equal to approximately 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1 when considering the error range. When the second pixel PX2 displays green, the capacitance of the storage capacitor Cst2 in the second region DA2 can be greater than or equal to approximately 63% and less than or equal to approximately 90% of the capacitance of the storage capacitor Cst1 in the first region DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second region DA2 can be greater than or equal to approximately 27% and less than or equal to 33% of the capacitance of the storage capacitor Cst1 in the first region DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second region DA2 can be greater than or equal to approximately 90% and less than or equal to 123% of the capacitance of the storage capacitor Cst1 in the first region DA1.

[0224] Table 3 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the brightness of the second region DA2 to the brightness of the first region DA1 is 60%, 80%, and 100% respectively in the third pixel PX3 representing blue. In the first region DA1 and the second region DA2, the widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 μm.

[0225] (Table 3)

[0226]

[0227] When the third pixel PX3 represents blue, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. The ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be approximately 185% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. Considering the error range, when considering the numerical range described in the parentheses, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second region DA2 can be greater than or equal to approximately 168% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1, and can be less than or equal to approximately 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first region DA1. When the third pixel PX3 displays blue, the capacitance of the storage capacitor Cst2 in the second region DA2 can be more than approximately 81% and less than approximately 137% of the capacitance of the storage capacitor Cst1 in the first region DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second region DA2 can be more than approximately 26% and less than 37% of the capacitance of the storage capacitor Cst1 in the first region DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second region DA2 can be more than approximately 107% and less than 174% of the capacitance of the storage capacitor Cst1 in the first region DA1.

[0228] The second gate conductor may further include a lower second scan line 152a, a lower initialization control line 153a, and an initialization voltage line 127. The first interlayer insulating layer 161 may be disposed on the second gate conductor.

[0229] On the first interlayer insulating layer 161, an oxide semiconductor including a channel 3137, a first electrode 3136, and a second electrode 3138 of a third transistor T3 and a channel 4137, a first electrode 4136, and a second electrode 4138 of a fourth transistor T4 may be disposed. Figure 27 The polysemiconductor, the first gate conductor, the second gate conductor, and the oxide semiconductor are shown together.

[0230] The oxide semiconductor may further include a second electrode of a boost capacitor Cboost, and the second electrode of the boost capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3 and the second electrode 4138 of the fourth transistor T4. The third gate insulating layer 143 may be disposed on the oxide semiconductor.

[0231] On the third gate insulating layer 143, a third gate conductor including a gate electrode 3151 of a third transistor T3 and a gate electrode 4151 of a fourth transistor T4 may be disposed. Figure 28 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, the oxide semiconductor, and the third gate conductor are shown together.

[0232] The third gate conductor may further include a second initialization voltage line 128, an upper second scan line 152b, and an upper initialization control line 153b. A second interlayer insulating layer 162 may be disposed on the third gate conductor.

[0233] On the second interlayer insulating layer 162, a first data conductor including a first connection electrode 1175, a second connection electrode 3175, and a third connection electrode 4175 may be disposed. Figure 29 The polycrystalline semiconductor, the first gate conductor, the second gate conductor, the oxide semiconductor, the third gate conductor, and the first data conductor are shown together.

[0234] The first connection electrode 1175 may be connected to a gate electrode 1151 of a driving transistor T1, a second electrode 3138 of the third transistor T3, a second electrode 4138 of the fourth transistor T4, and a second electrode of a boosting capacitor Cboost. The second connection electrode 3175 may be connected to a second electrode 1133 of the driving transistor T1 and a first electrode 3136 of the third transistor T3. The third connection electrode 4175 may be connected to a first electrode 4136 of the fourth transistor T4 and a first initialization voltage line 127.

[0235] The first data conductor may further include a driving voltage line 172, a first initialization voltage supply line 1127, and a second initialization voltage supply line 1128.

[0236] The driving voltage line 172 may extend substantially in a vertical direction and transmit a driving voltage ELVDD. The driving voltage line 172 may be connected to a first storage electrode 1153 of a fifth transistor T5 and a storage capacitor Cst2. The first storage electrodes 1153 of the storage capacitors Cst2 of four adjacent pixels PX may be connected to each other. Therefore, it is not necessary to dispose a driving voltage line 172 for each pixel column. For example, the driving voltage line 172 may be disposed one for every two pixel columns or one for every four pixel columns.

[0237] The first initialization voltage supply line 1127 may extend substantially in a vertical direction and may transmit a first initialization voltage VINT. The first initialization voltage supply line 1127 may be connected to the first initialization voltage line 127. The first initialization voltage line 127 is connected to each pixel PX to transmit the first initialization voltage VINT. The first initialization voltage supply line 1127 may be disposed one for every four pixel columns.

[0238] The second initialization voltage supply line 1128 may extend approximately in the vertical direction and may transmit the second initialization voltage AINT. The second initialization voltage supply line 1128 may be connected to the second initialization voltage line 128. The second initialization voltage line 128 is connected to each pixel PX to transmit the second initialization voltage AINT. The second initialization voltage supply line 1128 may be arranged one for every four pixel columns.

[0239] The third interlayer insulating layer 180 may be arranged on the first data conductor. The data line 171 may be arranged on the third interlayer insulating layer 180. The data line 171 may extend substantially in the vertical direction and may be connected to the second transistor T2 of each pixel PX.

[0240] Although not shown, a passivation layer, an anode, a partition wall, a light-emitting element layer, a cathode, etc. may be positioned on the data line 171.

[0241] Pixels PX of two adjacent rows in the second region DA2 of the display device 1000 according to an exemplary embodiment may have a vertically symmetric structure. Refer to Figure 30 for a description thereof.

[0242] Figure 30 is a top view showing some pixels PX of the second region DA2 of the display device 1000 according to an exemplary embodiment. Figure 30 is a view showing together Figure 21 the four pixels PX shown in

[0243] Pixels PX of two adjacent rows in the second region DA2 of the display device 1000 according to an exemplary embodiment may have a flipped structure that is symmetric up and down based on the first initialization voltage line 127. Accordingly, eight adjacent pixels PX are connected to the same initialization voltage line 127 to receive the first initialization voltage VINT. As described above, the number of wirings arranged in the second region DA2 is reduced compared to the first region DA1 to increase the transmittance of the second region DA2.

[0244] This is only an example, and instead of the first initialization voltage line 127, pixels PX of two adjacent rows may be symmetric based on other wirings. For example, pixels PX of two adjacent rows may be symmetric based on the second initialization voltage line 128.

[0245] Although the present disclosure has been described in connection with currently considered practical exemplary embodiments, it will be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0246] <Description of Symbols>

[0247] DA1: First region DA2: Second region

[0248] 127: First initialization voltage line 128: Second initialization voltage line

[0249] 151: First scan line 152: Second scan line

[0250] 153: Initialization control line 154: Bypass control line

[0251] 155: Light emission control line 171: Data line

[0252] 172: Driving voltage line 500: Light-shielding member

[0253] 741: Common voltage line

[0254] 1127: First initialization voltage supply line 1128: Second initialization voltage supply line

[0255] PX: Pixel

[0256] Cst: Storage capacitor Cas: Auxiliary capacitor

Claims

1. A display device, comprising: A first region and a second region, each including a plurality of pixels; And A plurality of wirings respectively connected to the plurality of pixels to transmit signals, Wherein the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, The number of wirings per unit area in the second region is less than the number of wirings per unit area in the first region, The plurality of wirings include: a plurality of first initialization voltage supply lines for supplying a first initialization voltage; and a plurality of second initialization voltage supply lines for supplying a second initialization voltage, The second initialization voltage supply lines are arranged in the first region and not in the second region, Pixels in the plurality of pixels in the first region are connected to the first initialization voltage supply lines and the second initialization voltage supply lines, Each of the plurality of pixels in the second region has a circuit different from the circuit of the pixels in the plurality of pixels in the first region, and is connected to the first initialization voltage supply lines and not connected to the second initialization voltage supply lines, and The number of first initialization voltage supply lines per unit area in the second region is less than the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region.

2. The display device according to claim 1, wherein The number of pixels per unit area in the second region is more than one-sixth and less than half of the number of pixels per unit area in the first region, and The number of first initialization voltage supply lines per unit area in the second region is more than one-sixth of the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region, and less than the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region.

3. The display device according to claim 2, wherein The number of pixels per unit area in the second region is one-fourth of the number of pixels per unit area in the first region, and The number of first initialization voltage supply lines per unit area in the second region is one-fourth of the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region.

4. The display device according to claim 2, wherein Each of the plurality of pixels in the first region includes: A light-emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; A driving transistor connected between the driving voltage line and the light-emitting diode; A second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, the first electrode of the driving transistor being connected to the driving voltage line; A third transistor connected between a second electrode of the driving transistor and the gate electrode of the driving transistor, the second electrode of the driving transistor being connected to the light-emitting diode; A fourth transistor, connected between the gate electrode of the driving transistor and a first initialization voltage line to which the first initialization voltage is applied; and a seventh transistor, connected between the light-emitting diode and a second initialization voltage line to which the second initialization voltage is applied, and each of the plurality of pixels in the second region includes: the light-emitting diode, the driving transistor, the second transistor, the third transistor, the fourth transistor, and a seventh transistor, connected between the light-emitting diode and the first initialization voltage line.

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