Method, device and computer-readable storage medium for frequency modulation of a chip

Abstract

The present disclosure discloses a method, device and computer-readable storage medium for frequency modulation of a chip. The frequency modulation device may be included in a combined processing device, and the combined processing device may also include a universal interconnect interface and other processing devices. The device interacts with other processing devices to jointly complete the calculation operation specified by the user. The combined processing device may also include a storage device, which is respectively connected to the device and other processing devices and is used to store data of the device and other processing devices. The scheme disclosed in the present disclosure can dynamically adjust the working frequency of the chip by measuring the power consumption of the system in real time, thereby improving the computing performance of the computing chip and the combined processing device. The scheme has the advantages of convenience and flexibility, and fast frequency adjustment speed.

Description

Technical Field

[0001] The present disclosure generally relates to the field of chip control, and more specifically, to a method, device and computer-readable storage medium for frequency modulation of a chip. Background Art

[0002] In recent years, with the increase in data volume and computing power, a large number of chips are usually integrated into computing devices and test equipment used for data computing. Since the working performance and manufacturing process of various chips vary greatly, they will directly affect the power consumption and computing performance of the entire system, especially the working frequency of the computing chip can determine the power consumption and working performance of the entire combined processing device. Therefore, how to dynamically adjust the actual required frequency of the chip has become an urgent problem to be solved. Summary of the invention

[0003] In order to at least solve one or more of the problems described in the above background technology section, so as to improve the working performance of the entire combined processing device by adjusting the working frequency of the chips in one or more combined processing devices, the present disclosure proposes the following technical solution and its multiple embodiments.

[0004] In one aspect, the present disclosure discloses a method for frequency modulation of a chip, the method comprising obtaining a real-time power consumption sampling value when at least one chip is operating; determining an error value between the real-time power consumption sampling value and a power consumption target value based on the real-time power consumption sampling value and the power consumption target value; and based on the error value, using a PID control module to determine an adjustment amount for adjusting the clock frequency of the at least one chip.

[0005] In another aspect, the present disclosure also discloses a method for frequency modulation of a chip, the method comprising obtaining a real-time power consumption sampling value when at least one chip is operating; determining whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold; when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold, performing a fast frequency reduction operation on the at least one chip; when the real-time power consumption sampling value is less than the fast frequency reduction threshold, determining an error value between the real-time power consumption sampling value and the power consumption target value; and based on the error value, using a PID control module to determine an adjustment amount for adjusting the clock frequency of the at least one chip.

[0006] In another aspect, the present disclosure further discloses a device for frequency modulation of a chip, the device comprising: an acquisition module, configured to acquire a real-time power consumption sampling value of at least one chip during operation; a PID control module, configured to determine an error value between the real-time power consumption sampling value and the power consumption target value based on the real-time power consumption sampling value and the power consumption target value; and based on the error value, determining an adjustment amount for adjusting the clock frequency of the at least one chip.

[0007] In one aspect, the present disclosure discloses a device for frequency modulation of a chip, the device comprising: an acquisition module configured to acquire a real-time power consumption sampling value when at least one chip is operating; a determination module configured to determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold; a fast frequency reduction module configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; and a PID control module configured to perform, when the real-time power consumption sampling value is less than the fast frequency reduction threshold: determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and determining an adjustment amount for adjusting the clock frequency of the at least one chip based on the error value.

[0008] In another aspect, the present disclosure also discloses a device for frequency modulation of a chip, the device comprising: at least one processor; at least one memory for storing program instructions, when the program instructions are executed by the at least one processor, the device executes the aforementioned method for frequency modulation of a chip.

[0009] In yet another aspect, the present disclosure discloses a board for frequency modulation of a chip, wherein the board includes any of the aforementioned devices for frequency modulation of a chip.

[0010] In one aspect, the present disclosure discloses an integrated circuit chip, which includes a core for frequency tuning of the chip. When the integrated circuit chip is in operation, the core can be configured to execute the aforementioned method for frequency tuning of the chip.

[0011] According to the method, device and computer-readable storage medium proposed in the present disclosure, the improved PID control technology can be used to control the frequency modulation of the relevant chips. In some application scenarios, the solution disclosed in the present disclosure for controlling the frequency modulation of the relevant chips through an external MCU ("Microcontroller Unit") can be directly applied to chips with a frequency modification interface, thereby realizing dynamic frequency modulation. At the same time, during the frequency control process, local data can be directly managed and applied locally after being collected, so that the frequency modulation speed is faster. In addition, the technical solution disclosed in the present disclosure can also be flexibly adjusted, such as adjusting the proportional coefficient, adjusting the timed clearing time, and removing the integral term, etc., to meet different application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By combining the accompanying drawings, the above features of the present disclosure can be better understood, and its many purposes, features and advantages are obvious to those skilled in the art. The drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0013] Figure 1 is a block diagram illustrating an operation flow of an example system for frequency tuning a chip according to an embodiment of the present disclosure;

[0014] Figure 2 is an overall flow chart showing a method for frequency tuning a chip according to an embodiment of the present disclosure;

[0015] Figure 3 is a detailed flow chart showing a method for frequency tuning a chip according to an embodiment of the present disclosure;

[0016] Figure 4 is a flow chart showing a frequency modulation method for fast frequency reduction according to an embodiment of the present disclosure;

[0017] Figure 5 is an overall flow chart showing a multi-stage dynamic frequency modulation method according to an embodiment of the present disclosure;

[0018] Figure 6 is a flowchart showing a two-level dynamic frequency modulation method according to an embodiment of the present disclosure;

[0019] Figure 7 is a flowchart showing a three-level dynamic frequency modulation method according to an embodiment of the present disclosure;

[0020] Figure 8 is a flowchart showing a multi-stage dynamic frequency modulation method according to an embodiment of the present disclosure;

[0021] Fig. 9 is a flowchart illustrating a frequency modulation method with multiple stages and fast frequency reduction according to an embodiment of the present disclosure;

[0022] Fig.10 is a schematic block diagram showing frequency modulation of a chip using the device of an embodiment of the present disclosure;

[0023] Fig.11 is another schematic block diagram showing frequency modulation of a chip using the device of an embodiment of the disclosure;

[0024] Fig.12 is a structural block diagram showing a combined processing device according to an embodiment of the present disclosure; and

[0025] Fig.13 is a structural block diagram showing a board for frequency modulation of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The technical solution disclosed in the present invention provides a method, device and computer-readable storage medium for frequency modulation of a chip. By collecting data such as the power consumption of the chip in real time and using a PID control module to incrementally adjust the operating frequency of the chip, the overall working performance of the system is controlled. In some embodiments, the solution disclosed in the present invention uses a single or single-stage PID control module to incrementally adjust the operating frequency of a single or multiple chips. In other embodiments, the solution disclosed in the present invention uses a multi-stage PID control module in series to make a more precise adjustment to the frequency of the chip. Using the technical solution disclosed in the present invention, incremental adjustment of the operating frequency of one or more chips in a combined processing device can be achieved. While the static error effect can be eliminated during the frequency adjustment process, the influence of overshoot can also be weakened. At the same time, the frequency modulation scheme disclosed in the present invention is stable and reliable. When the business can achieve the set target power consumption, the actual average power consumption of the board can be controlled within the range of ±1W of the target power consumption.

[0027] It should be understood that the present disclosure sets forth many specific details regarding the above-mentioned chip frequency modulation scheme in order to provide a thorough understanding of the multiple embodiments described in the present disclosure. However, those of ordinary skill in the art can practice the multiple embodiments described in the present disclosure without these specific details under the guidance of the disclosure disclosed content. In other cases, the disclosure disclosed content does not describe in detail the well-known methods, processes and components to avoid unnecessarily obscuring the embodiments described in the present disclosure. Further, the description should not be considered to limit the scope of the multiple embodiments disclosed.

[0028] The technical solutions in multiple embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0029] Figure 1 1 is a block diagram showing an operation flow 100 of an example system for frequency modulation of a chip according to an embodiment of the present disclosure. It should be noted that the system and its operation flow here are merely exemplary and not restrictive. In addition to the frequency modulation operation, the system can also perform other operations, which will not be described in detail here so as not to unnecessarily confuse the solution of the present disclosure.

[0030] like Figure 1 As shown, the system operation flow of the present disclosure includes performing an initialization operation on the system at step 101. For example, in the initialization operation, corresponding parameter settings can be performed for the system according to actual application conditions, and initial data can also be called in to prepare for the execution of subsequent programs.

[0031] After the above initialization operation, at steps 102 and 103, the frequency modulation system of the present disclosure can respectively perform the main loop operation and the dynamic frequency modulation operation in parallel or in series. Here, the main loop operation can be various operations or tasks required by the system to perform in addition to the dynamic frequency modulation operation, such as operations related to machine learning in the field of artificial intelligence. In the dynamic frequency modulation operation, as mentioned above, a PID control module can be used to adjust the operating frequency of the chip.

[0032] In an application scenario, under the control of the timer as shown in the figure, the MCU including the PID control module disclosed herein can obtain the real-time power consumption sampling value of at least one chip during operation at a fixed time interval (e.g., 1 millisecond), and determine the adjustment amount for adjusting the clock frequency of the chip by combining the power consumption target value. Thereafter, the adjustment amount can be used to perform frequency modulation on the clock frequency of one or more chips in step 104 for relevant situations, thereby further controlling the power consumption of the entire device or system. The relevant situation here may be, for example, that the operating frequency of the chip is too high or too low, or other scenarios that require dynamic frequency modulation.

[0033] Combined with the above Figure 1 The operation process of the system for frequency modulation of a chip disclosed in the present invention is briefly described. Figure 2-Figure 13 The process method, equipment and device for frequency modulation of the chip are further described.

[0034] Figure 2 2 is a general flow chart showing a method 200 for frequency modulation of a chip according to an embodiment of the present disclosure. It is understood that the frequency modulation method discussed herein can be combined with Figure 1 The system's operating procedures are followed.

[0035] like Figure 2 As shown, at step 201, method 200 can obtain the real-time power consumption sampling value of at least one chip during operation. Then, at step 202, method 200 determines the error value between the real-time power consumption sampling value (for example, the chip power consumption sampled within 1 millisecond) and the power consumption target value (for example, the expected power consumption of the chip) according to the real-time power consumption sampling value. In one embodiment, the error value between the real-time power consumption sampling value and the power consumption target value can be obtained by taking the difference between the two. Then, at step 203, method 200 determines the adjustment amount for adjusting the clock frequency of at least one chip based on the error value using the PID control module. In one embodiment, the adjustment amount here can be a relative increment based on the previous adjustment frequency. Thus, the clock frequency of the chip adjusted for this operation can be obtained by adding the adjustment amount to the current clock frequency of the chip.

[0036] In order to better understand the technical solution of the present disclosure, the PID control algorithm used in the present disclosure will be introduced below.

[0037] The PID control algorithm is a control algorithm that combines proportion (P), integration (I) and differentiation (D). The essence of its control is to perform calculations according to the functional relationship of proportion, integration and differentiation based on the input deviation value, and use the calculation results to control the output. The PID control algorithm disclosed in this disclosure improves the existing PID control algorithm. The output value is an adjustment value, and can be an increment relative to the previous adjustment value, which is different from the situation where the output value of the existing PID control algorithm is an absolute value. In one embodiment, the PID control algorithm disclosed in this disclosure can use the following formula (1) to obtain the adjustment value △u(t):

[0038] △u(t)=k p *e(t)+k i *Σe(t)+k d *(e(t)-e(t-1)) (1)

[0039] where k p is the proportionality coefficient, k i is the integration coefficient, k d is the differential coefficient. e(t) is the error value, Σe(t) is the cumulative sum of the error values, and e(t-1) is the previous error value. k p *e(t) is the proportional term, k i *Σe(t) is the integral term, k d *(e(t)-e(t-1)) is the differential term.

[0040] According to different application scenarios, the scheme disclosed in the present invention can obtain the adjustment amount through the proportional term, or by combining the proportional term with any one of the integral term and the differential term. Furthermore, the aforementioned three can be used in combination to obtain the adjustment amount, and then the frequency modulation scheme of the chip is executed. In addition, by making improvements based on continuous actual measurements, the PID control algorithm disclosed in the present invention extends the traditional PID algorithm that is only applicable to quasi-linear systems to nonlinear systems, and the actual measured effect is good.

[0041] Combination of the above Figure 2The scheme of the present disclosure and the PID control module used are described. Based on the above description, those skilled in the art can understand that the PID control module of the present disclosure can have a proportional control unit for determining a proportional term in terms of implementation. Optionally, it can further include at least one of an integral control unit for determining an integral term and a differential control unit for determining a differential term. By combining the proportional term or the proportional term with at least one of the integral term and the differential term to determine the adjustment amount, the present disclosure provides a variety of flexible ways to perform frequency modulation operations on the chip.

[0042] Figure 3 3 is a detailed flow chart showing a method 300 for frequency modulation of a chip according to an embodiment of the present disclosure. Through the following description, those skilled in the art can understand Figure 3 yes Figure 2 A further refinement of the method for frequency tuning a chip as shown, and with respect to Figure 2 The description also applies to Figure 3 The content shown.

[0043] like Figure 3 As shown, at step 301, method 300 obtains a real-time power consumption sampling value. In one embodiment, obtaining the real-time power consumption sampling value includes periodically (e.g., 1 millisecond) obtaining a plurality of the real-time power consumption sampling values. Next, method 300 enters step 302 to calculate the error value between the current real-time power consumption and the target power consumption. In one embodiment, the error value between each of the real-time power consumption sampling values ​​and the power consumption target value can be determined by taking the difference between the real-time power consumption sampling value and the power consumption target value (e.g., the expected power consumption of a chip or board defined by a user), and the difference is regarded as the error value.

[0044] After obtaining the error value, method 300 proceeds to step 303, where a proportional term can be obtained based on the error value. In one embodiment of using the aforementioned PID control module to determine the adjustment amount, the proportional term can be obtained based on the error value using a proportional control unit in the PID control module. In a specific implementation, obtaining the proportional term can include obtaining it based on the error value, a selected proportional coefficient (e.g., a parameter adjusted based on actual measurement results), and a dimension (e.g., Hertz / Watt). In one embodiment, a first adjustment amount for adjusting the clock frequency can be determined based on the proportional term. Then, as Figure 3 As shown in , method 300 can directly proceed to step 310 to perform frequency modulation. Specifically, the frequency modulation operation can be performed on the clock frequency of one or more chips according to the obtained first adjustment amount combined with the previous adjustment of the clock frequency.

[0045] As an alternative to the above, at step 304, method 300 determines whether a predetermined time period (eg, a time period of 1 second) has been reached, which can be achieved, for example, by Figure 1 . When the predetermined time period arrives, method 300 executes step 305, that is, performs a zeroing operation on the cumulative sum, so as to restart the cumulative operation of the error value in the next predetermined time period. According to the scheme disclosed in the present invention, the zeroing operation of the cumulative sum can clear the cumulative effect that may be caused by power consumption regulation. For the convenience of illustrating the cumulative effect, it is assumed that in an implementation scenario, the target power consumption value (the expected power consumption value set by the user) is 75 watts, and the chip is always in no-load during the predetermined time period, so that the real-time power consumption sampling value obtained during the predetermined time period is always 30 watts. In this case, when the cumulative operation is performed, the cumulative sum of the error values ​​in the predetermined time period will be relatively large. If the power consumption sampling value of the chip exceeds the target power consumption value (i.e., 75 watts) at this time, the error value of this power consumption will be neutralized (i.e., the aforementioned cumulative effect) because the cumulative sum is already too large, thereby causing the system power consumption to exceed the standard for a long time, thereby affecting the system performance. In view of this, the solution disclosed herein therefore proposes to accumulate the error values ​​and perform a zeroing operation within a predetermined time period to avoid the accumulation effect.

[0046] As an alternative to steps 304 and 305, method 300 may determine whether the predetermined time period has been reached in another way. Specifically, the time period for obtaining a real-time power consumption sampling value may be referred to as a sampling cycle, and thus the predetermined time period may be set to include a certain number of sampling cycles. When the number of sampling cycles is reached, the error value obtained in the earliest sampling cycle may be cleared from the cumulative sum, and the error value obtained in the most recent sampling cycle may be included in the cumulative sum. For example, taking the case where the predetermined time period includes 100 sampling cycles, starting from the first sampling cycle, the error value between the real-time power consumption sampling value obtained in the sampling cycle and the target power consumption value is determined, and the error value is sequentially accumulated with the error value of the next cycle to obtain the cumulative sum. When the 100th sampling cycle is reached, method 300 may clear the error value of the earliest sampling cycle (i.e., the first sampling cycle) in the predetermined number of sampling cycles in the cumulative sum, so as to perform an accumulation operation on the error value of the most recent sampling cycle (i.e., the 101st sampling cycle) to obtain the cumulative sum. That is, the updated cumulative sum cumulatively calculates the error value from the 2nd sampling period to the 101st sampling period. It can be seen that by setting the predetermined time period differently, the present disclosure provides multiple solutions for determining the cumulative sum, thereby further improving the application flexibility of the present disclosure.

[0047] On the contrary, when the predetermined time period has not yet arrived, the method 300 executes step 306, that is, the error value of this time is added to the cumulative sum. After obtaining the updated cumulative sum, at step 307, the method 300 obtains the integral term according to the cumulative sum. As described above, obtaining the integral term may include obtaining the integral term according to the cumulative sum, the selected integral coefficient and the dimension (e.g., Hertz / Watt). Then, at step 308, the integral term range is limited. In one embodiment, the integral term may be limited to a selected range to eliminate static error effects and avoid overshoot effects. The range may be, for example, an empirical statistical value or an adjustment amount determined after multiple actual measurements. Thereafter, the method 300 enters step 309, where a frequency adjustment parameter, such as the adjustment amount referred to in the present disclosure, may be obtained based on the proportional term and the integral term after the limited range. Thereafter, the method 300 proceeds to step 310, where the method 300 performs a frequency modulation action on the clock frequency of at least one chip according to the obtained adjustment amount.

[0048] Alternatively or optionally, after obtaining the proportional term at step 303 or the proportional term and the integral term after limitation at step 309, the frequency adjustment parameter can be obtained by combining with the differential term according to the actual application scenario. In this case, the method 300 performs a subtraction operation according to the error value determined this time and the error value determined last time to obtain a differential difference. Then, based on the differential difference, the differential control unit in the PID control module is used to obtain the differential term. As described above, obtaining the differential term may include obtaining the differential term according to the differential difference, the selected differential coefficient and the dimension (e.g., Hertz / Watt). Finally, at step 310, the method 300 may perform a frequency modulation action on the clock frequency of the chip according to the adjustment amount obtained by the proportional term and at least one of the integral term and the differential term. When the differential term is used in the process of determining the adjustment amount, it can play a certain leading adjustment role in the frequency modulation, and can also make the frequency modulation reaction speed faster.

[0049] Through the above description in combination with steps 304-310, those skilled in the art can understand that the present disclosure, in one embodiment, periodically (e.g., 1 millisecond) obtains a plurality of the real-time power consumption sampling values, and determines the error value between each of the real-time power consumption sampling values ​​and the power consumption target value for each of the real-time power consumption sampling values ​​within a predetermined time period (e.g., 1 second), and performs an accumulation operation on the error value determined each time to obtain a cumulative sum. Further, based on the cumulative sum, an integral term is obtained using the integral control unit in the PID control module. Next, a second adjustment amount (relative to the aforementioned first adjustment amount) for adjusting the clock frequency of the at least one chip can be determined based on the obtained proportional term and the integral term obtained using the integral control unit.

[0050] As mentioned above, in addition to obtaining the above-mentioned second adjustment amount, in one or more embodiments, the present disclosure can also determine a third adjustment amount for adjusting the clock frequency of the at least one chip based on the obtained proportional term and the differential term obtained using the differential control unit. Similarly, the fourth adjustment amount for adjusting the clock frequency of the at least one chip can also be determined based on the aforementioned obtained proportional term, integral term, and differential term. In an application scenario, each of the second adjustment amount, the third adjustment amount, and the fourth adjustment amount is an increment relative to the previous adjustment of the clock frequency. For these four exemplary adjustment amounts, those skilled in the art can make real-time adjustments based on the actual frequency modulation effect monitored, thereby realizing real-time frequency modulation operations on the chip.

[0051] Combination of the above Figure 2 and Figure 3 The present disclosure describes the frequency modulation operation performed on the chip when the power consumption of the chip is within a reasonable range. Figure 4 The invention describes in detail the operation of rapidly reducing the frequency of the chip when the power consumption fluctuation of the chip becomes larger than the normal range instantly.

[0052] Figure 4 FIG. 4 is a flow chart showing a frequency modulation method 400 for fast frequency reduction according to an embodiment of the present disclosure. Figure 4 As shown, at step 401, method 400 obtains the real-time power consumption sampling value of at least one chip when operating. For example, the real-time power consumption sampling value of at least one chip can be collected periodically (for example, 1 millisecond). Then, at step 402, it is determined whether the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold. In an application scenario, the fast frequency reduction threshold can be determined according to product specification requirements, and its calculation formula can be, for example, the following formula:

[0053] P th =U*I max (2)

[0054] Where U represents the operating voltage, I max Indicates the maximum allowable current, P th Indicates the fast frequency reduction threshold, and * indicates the product relationship.

[0055] In another embodiment, the fast frequency reduction threshold may also be adjusted within a certain range based on the calculation result of the above formula and according to actual measurement results. The adjustment range may be determined, for example, based on empirical values.

[0056] When the real-time power consumption sampling value is greater than or equal to the above-mentioned fast frequency reduction threshold, method 400 proceeds to step 403, at which time method 400 performs a fast frequency reduction operation on at least one chip. Before performing the fast frequency reduction operation, in one or more embodiments, the target frequency value of the chip for this adjustment can be determined. In one embodiment, the target frequency value can be determined by the following formula:

[0057] F aim =F now *(P aim -P idle ) / (P now -P idle ) (3)

[0058] where F aim is the target frequency, F now is the current frequency, P aim is the target power consumption, P idle is the idle power consumption, P now is the current power consumption, and * indicates a multiplication relationship. It should be noted that at the moment of fast frequency reduction, it can be approximately considered that there is a linear relationship between power consumption and frequency. The disclosed solution can obtain a target frequency value by means of such a linear relationship, and the target frequency value can be used as the clock frequency for this adjustment, thereby performing a corresponding frequency modulation action on at least one chip.

[0059] On the contrary, when the real-time power consumption sampling value is less than the fast frequency reduction threshold, the method 400 performs a normal frequency modulation operation at step 404. For example, the method 400 can determine the error value between the real-time power consumption sampling value and the power consumption target value. Then, based on the aforementioned error value, the method 400 can use the PID control module to determine the adjustment amount for adjusting the clock frequency of the at least one chip. Thus, the normal frequency modulation operation can be performed on the clock frequency of one or more chips according to the obtained adjustment amount combined with the previous adjustment of the clock frequency. It can be understood by those skilled in the art that the normal frequency modulation operation here can be the above combined with the adjustment amount. Figure 3 The frequency modulation operation performed, so the previous combination Figure 3 The described operation of frequency modulation of the chip is also applicable to the normal frequency modulation operation here, so the same or similar contents will not be repeated here.

[0060] In the above, the present disclosure combines Figure 1-Figure 4 Describes the implementation of a single-stage PID on a chip (e.g. Figure 6 The frequency modulation operation of the second stage shown in FIG. 1 and described in detail later) will be combined with Figure 5-Figure 9 The multi-level PID frequency modulation operation disclosed in the present invention is further explained.

[0061] Figure 51 is an overall flow chart showing a multi-level dynamic frequency modulation method 500 according to an embodiment of the present disclosure. By using the method 500 to perform multi-level serial PID dynamic frequency modulation on a chip, the frequency adjustment can be made more precise, and to a certain extent, the power consumption can exceed the TDP (“Thermal Design Power”) power consumption in a short time, thereby improving the system performance.

[0062] like Figure 5 As shown, at step 501, method 500 obtains a real-time power consumption sampling value of at least one chip during operation and an average power consumption value within N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2. In one embodiment, N-1 predetermined execution cycles T1, ... T N-1 And the sampling period T of the real-time power consumption sampling value N Satisfying the relationship T1 (e.g. 1 second) > T2 (e.g. 500 milliseconds)...T N-1 (e.g. 50 ms)>T N (For example, 1 millisecond). Then, at step 502, method 500 determines the adjustment amount for adjusting the clock frequency of the at least one chip based on the real-time power consumption sampling value, the average power consumption value and the average power consumption reference value using N PID control modules connected in series step by step. In one implementation scenario, the average power consumption reference value disclosed herein can be flexibly set according to actual conditions. For example, it can be set through the "Power Capping" function of the host computer, which allows the user to limit the average power consumption reference value to a specified range. Furthermore, after modifying the average power consumption reference value, the user does not need to adjust other parameters, and all parameters related to the previous average power consumption reference value will be automatically adjusted accordingly according to the new average power consumption reference value given by the user.

[0063] Combination of the above Figure 5 The overall process of the multi-level dynamic frequency modulation method 500 is briefly described. In order to facilitate a further understanding of the multi-level frequency modulation scheme disclosed in the present invention, the following will be combined with Figure 6 The multi-stage dynamic frequency modulation method is described in detail by connecting two-stage PID control modules in series.

[0064] Figure 6 6 is a flowchart illustrating a method 600 for two-level dynamic frequency modulation according to an embodiment of the present disclosure. As will be appreciated, the method 600 is a method of the aforementioned Figure 5 In the described N-stage dynamic frequency modulation method, when N is equal to 2, the adjustment amount is determined by using the primary PID control module and the final PID control module connected in series, and the adjustment amount is output from the final PID control module.

[0065] like Figure 6As shown, the method 600 can respectively obtain the first average power consumption value 601 and the average power consumption reference value 602 associated with the primary PID control module within a predetermined execution period T1 (for example, 1 second) of the primary PID control module of at least one chip. Then, the method 600 can input the first average power consumption value and the average power consumption reference value into the primary PID control module 603. Further, the method 600 can input the output value of the primary PID control module 603, that is, the adjustment amount of this time and the real-time power consumption target value of the previous adjustment operation into a processing module for calculation, and the output of the processing module is the real-time power consumption target value 604 of this adjustment operation. Thereafter, the method 600 can input it into the final-stage PID control module 606. Then, based on the real-time power consumption sampling value 605 and the real-time power consumption target value 604 of this adjustment operation, the final-stage PID control module 606 is used to output the adjustment amount. The workflow of inputting the real-time power consumption target value and the real-time power consumption sampling value into the final-stage PID control module is combined with the above. Figure 3 The method for performing single-stage frequency modulation on the chip described is the same or similar and will not be repeated here.

[0066] Finally, at step 607, method 600 can obtain the clock frequency of the current chip adjustment operation based on the output value of the final PID control module 606 and the clock frequency of the previous chip adjustment operation, and perform the corresponding frequency modulation action according to the clock frequency. As mentioned above, the adjustment amount can be an increment relative to the previous adjustment clock frequency. In one embodiment, the predetermined execution period T1 (e.g., 1 second) of the primary PID control module is greater than the sampling period T1 of the real-time power consumption sampling value. N (e.g. 1 millisecond).

[0067] Figure 7 is a flowchart showing a three-level dynamic frequency modulation method 700 according to an embodiment of the present disclosure. Figure 5-Figure 6 Based on this, the scheme disclosed herein is further described in detail. Figure 5-Figure 6 The description of multi-level dynamic frequency modulation also applies to Figure 7 Operations. Figure 7 As shown, the situation when N is equal to 3 in the N-stage dynamic frequency modulation method is drawn here, that is, the adjustment amount is determined by using the primary PID control module, the second-stage PID control module and the final-stage PID control module connected in series, and the adjustment amount is output from the final-stage PID control module.

[0068] Specifically, the method 700 obtains the first average power consumption value 701 within the predetermined execution cycle T1 (e.g., 1 second) of the primary PID control module of the at least one chip and the average power consumption reference value 702 associated with the primary PID control module, and inputs them into the primary PID control module 703 to make it output the adjustment value of the second average power consumption target value associated with the second-level PID control module 706. Next, the method 700 obtains the second average power consumption value 705 within the predetermined execution cycle T2 of the second-level PID control module, and inputs it into the second-level PID control module 706. Further, the second average power consumption target value is adjusted by using the adjustment value to obtain the adjusted second average power consumption target value 704, and inputs it into the second-level PID control module 706.

[0069] Furthermore, the real-time power consumption target value 707 of the current adjustment operation is obtained based on the output value of the second-stage PID control module 706 and the real-time power consumption target value of the previous adjustment operation, and is input to the final-stage PID control module 709. Then, based on the real-time power consumption sampling value 708 and the real-time power consumption target value 707 of the current adjustment operation, the final-stage PID control module 709 outputs the adjustment amount. In one embodiment, the sampling period of the real-time power consumption sampling value is T N , and the predetermined execution period T2 of the second-level PID control module satisfies the relationship T1 (e.g., 1 second)>T2 (e.g., 200 milliseconds)>T N (e.g., 1 millisecond). In an exemplary implementation scenario, when the average power consumption reference value used as the input value of the primary PID control module is the TDP power consumption (e.g., 75 watts), if the first average power consumption value within a predetermined execution period (e.g., 1 second) is lower than the average power consumption reference value (i.e., TDP power consumption), the input value of the next-level PID control module (e.g., the second-level PID control module) can be increased so that the average power consumption target value reduces the intensity of suppressing power consumption; conversely, when the first average power consumption value is higher than the average power consumption reference value (i.e., TDP power consumption), the average power consumption target value of the next-level PID control module can be reduced to increase the intensity of suppressing power consumption.

[0070] similar Figure 6 As shown in, after obtaining the clock frequency adjustment amount of at least one of the above-mentioned chips, at step 710, method 700 can obtain the clock frequency of the current adjustment operation of the chip based on the output value of the final-stage PID control module 709 and the clock frequency of the previous adjustment operation of the chip, and perform corresponding frequency modulation actions according to the clock frequency.

[0071] Figure 8 8 is a flowchart showing a multi-stage dynamic frequency modulation method 800 according to an embodiment of the present disclosure. Figure 5-Figure 7 Based on this, the scheme disclosed herein is further described in detail. Figure 5-Figure 7 The description of multi-level dynamic frequency modulation also applies to Figure 8 operation.

[0072] like Figure 8 As shown, it shows the situation when N is greater than or equal to 4 in the N-stage dynamic frequency modulation method, that is, the adjustment amount is determined by using the primary PID control module, the second-stage PID control module, ..., the N-1-th stage PID control module and the final stage PID control module connected in series, and the adjustment amount is output from the final stage PID control module.

[0073] First, the method 800 obtains the primary PID control module 803 to the N-1th PID control module 809 in their respective predetermined execution cycles T1, ...T N-1 The first average power consumption value 801, the second average power consumption value 805 to the N-1th average power consumption value 808 are input into the primary PID control module 803, the second level PID control module 806, ... to the N-1th level PID control module 809. In one embodiment, the respective predetermined execution periods T1, ... T2 of the primary PID control module to the N-1th level PID control module are N-1 And the sampling period T of the real-time power consumption sampling value N Satisfying the relationship T1 (e.g. 1 second) > T2 (e.g. 500 milliseconds)...T N-1 (e.g. 50 ms)>T N (e.g. 1 millisecond). Next, the first average power consumption value 801 and the average power consumption reference value 802 associated with the primary PID control module are input into the primary PID control module 803, and the outputs of the primary PID control module to the N-2nd level PID control module are input into the respective next-level PID control modules, wherein each output of the primary PID control module to the N-2nd level PID control module is an adjustment value of the average power consumption target value associated with the corresponding next-level PID control module. Further, the average power consumption target value of the corresponding next-level is adjusted by each adjustment value to obtain the adjusted second average power consumption target value 804, ... and the N-1st average power consumption target value 807, respectively, and they are respectively input into the corresponding second-level PID control module 806, ... to the N-1st level PID control module 809.

[0074] Furthermore, the real-time power consumption target value 810 of the current adjustment operation is obtained based on the output value of the N-1th level PID control module 809 and the real-time power consumption target value of the previous adjustment operation, and is input to the final level PID control module 812. And, based on the real-time power consumption sampling value 811 and the real-time power consumption target value 810 of the current adjustment operation, the final level PID control module 812 outputs the adjustment amount. The workflow of the real-time power consumption sampling value and the real-time power consumption target value being input to the final level PID control module is combined with the above Figure 3 The method for performing single-stage frequency modulation on the chip described is the same or similar, and will not be repeated here. Finally, at step 813, method 800 can obtain the clock frequency of the current adjustment operation of the chip based on the output value of the final PID control module 812 and the clock frequency of the previous adjustment operation of the chip, and perform corresponding frequency modulation actions according to the clock frequency.

[0075] The foregoing text of this disclosure describes the power consumption collection and frequency modulation scheme in conjunction with at least one chip. However, the scheme of this disclosure is also applicable to the power consumption collection of a board including one or more chips. In other words, the object of power consumption collection in this disclosure can be either a chip or a board including a chip. Fig. 9 The frequency modulation method is further described by taking the power consumption of the entire acquisition board as an example.

[0076] Fig. 9 is a flowchart showing a frequency modulation method 900 with multiple stages and fast frequency reduction according to an embodiment of the present disclosure. It can be understood by those skilled in the art that Fig. 9 The technical solution is Figure 4-Figure 8 The frequency modulation method is a combination of fast frequency reduction and multi-level PID frequency modulation. Figure 4-Figure 8 The technical details described in Fig. 9 The same applies to .

[0077] like Fig. 9 As shown, at step 901, the chip is frequency modulated by the output of the final PID. Since the frequency modulation action takes a certain amount of time from the start to the completion, the scheme disclosed herein also allows other tasks (such as Figure 1), thereby improving the efficiency of dynamic frequency modulation. Until the previous frequency modulation action is completed, method 900 enters step 902, where the power consumption of the entire board can be obtained, and the entire board can be a board including one or more chips to be frequency modulated. In an actual scenario, for example, the power consumption of the entire board can be collected in real time by a sensor on the board to obtain a real-time power consumption sampling value when the entire board is in operation, or the power consumption of the chip can be collected in real time by a sensor on the board to obtain a real-time power consumption sampling value when at least one chip is in operation, and then the real-time power consumption sampling value of the entire board is obtained. Then, at step 903, after each real-time power consumption sampling value of the entire board is obtained, method 900 determines whether the real-time power consumption sampling value of the entire board is greater than or equal to the fast frequency reduction threshold of the entire board. In one embodiment, the fast frequency reduction threshold can be calculated according to the aforementioned formula (2). In another embodiment, the threshold can also be adjusted within a certain range based on the numerical value calculated by the aforementioned formula (2) according to the actual measurement results, and the adjustment range can be determined according to the empirical value.

[0078] When the real-time power consumption sampling value of the whole board is less than the fast frequency reduction threshold of the whole board, the method 900 proceeds to step 904, where the average power consumption value within a predetermined time period (e.g., 1 second) is calculated. Next, at step 905, the method 900 performs a multi-level dynamic frequency modulation operation, i.e., the above combined Figure 6-Figure 8 Finally, at step 906, the method 900 obtains the frequency modulation parameter (ie, clock frequency) of the current chip operation adjustment according to the determined adjustment amount and the clock frequency of the previous chip adjustment operation.

[0079] On the contrary, when the real-time power consumption sampling value of the whole board is greater than or equal to the fast frequency reduction threshold of the whole board, method 900 calculates the target frequency value of the fast frequency reduction of the whole board at step 908. This situation may occur, for example, when it is detected that the instantaneous power consumption of the whole board is large (for example, more than 1.2 times TDP). In order to reduce the chip frequency in a short time to meet the power consumption requirements of the board, a fast frequency reduction operation is performed at this time. Before performing the fast frequency reduction operation, it is necessary to determine the target frequency value of the chip to be adjusted. In one or more embodiments, the target frequency value can be calculated according to the aforementioned formula (3).

[0080] Finally, according to the clock frequency of the chip adjusted in step 906 or 908, at step 907, method 900 performs the corresponding frequency modulation action according to the clock frequency. Figure 1-Figure 9 Those skilled in the art can understand Figure 1-Figure 9The method for chip frequency regulation shown can also be implemented in various forms in one or more devices. These implementation forms may include but are not limited to the following four forms: 1) The chip hardware itself has or supports a certain dynamic frequency modulation capability, and the PID module disclosed herein is constructed through hardware analog circuits and / or digital circuits to implement frequency modulation operations on it; 2) The upper-level driver or operating system kernel processes the locally collected power consumption or chip occupancy data related to power consumption in a manner similar to the PID module disclosed herein, so as to dynamically control the frequency modulation of the chip; 3) The chip is frequency modulated by a device disposed outside the chip; 4) The chip is frequency modulated by a device disposed inside the chip. Regarding the implementation forms of items 3 and 4 here, the following will be combined with Fig.10 and Fig.11 To elaborate.

[0081] Fig.10 A schematic block diagram showing the frequency modulation of a chip using the device of the embodiment of the disclosure is shown. Fig.11 Another schematic block diagram of using the device of the embodiment of the present disclosure to modulate the frequency of a chip is shown. As can be seen from the two figures, the device of the present disclosure can be placed outside or inside a chip to perform frequency modulation operations on at least one chip.

[0082] like Fig.10 As shown, the device 1001 performs frequency modulation operation on the chip outside the chip 1004. The device 1001 includes an acquisition module 1003, which is configured to obtain a real-time power consumption sampling value when at least one chip is operating and an average power consumption value within N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2. In one embodiment, the acquisition module can be a sensor. The device 1001 can also include a PID control module 1002, which can be, for example, a single-stage or N PID control modules connected in series step by step, to perform dynamic frequency modulation operation on the chip 1004. In one embodiment, the PID control module 1002 can be implemented on an MCU ("Microcontroller Unit"). Thus, the device 1001 can be an MCU.

[0083] Despite Fig.10 It is not shown in the figure, but those skilled in the art can Figure 4-Figure 9 According to the description, it can also be imagined that in order to implement the fast frequency reduction scheme, the above-mentioned device may also include: a determination module, which is configured to determine whether the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; and a fast frequency reduction module, which is configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold.

[0084] for Fig.10For the frequency modulation control method shown in the figure, the chip receiving dynamic frequency modulation can be configured with an interface for modifying the frequency and the aforementioned external device can realize dynamic frequency modulation of the chip only by modifying or upgrading its firmware, so that the operation is convenient and flexible. In addition, the local data is directly managed locally (such as at the board) after being collected, so the data processing speed is faster than that processed by the upper driver or the operating system kernel.

[0085] like Fig.11 As shown, the device for frequency modulation disclosed in the present invention can also be placed inside a chip to implement frequency modulation operations on the chip, that is, the chip 1102 includes a device 1101 inside, and the device is used to perform frequency modulation operations on the chip. In some application scenarios, the device 1101 can be embodied as software code (such as instructions for various situations) residing inside the chip. Figure 2-Figure 9 The description of single-stage, multi-stage, and fast frequency reduction of chips also applies to Fig.11 equipment, so it will not be described in detail here.

[0086] Apart from Fig.10 and Fig.11 The exemplary device block diagram shown, the solution disclosed herein can also be implemented in an integrated circuit chip, which includes a device 1101 for frequency modulation of the chip. In some scenarios, the aforementioned device 1101 can be the core of the chip. When the integrated circuit chip is working, the core can be configured to execute the above-mentioned method for frequency modulation of the chip. The integrated circuit chip can be implemented, for example, using hardware such as CPLD ("Complex Programmable Logic Device"), FPGA ("Field Programmable Gate Array"), ASIC (Application Specific Integrated Circuit), MPU (Microprocessor Unit), CPU (Central Processing Unit), etc.

[0087] In addition, those skilled in the art may also think that the solution of the present disclosure may also be implemented in a device or a board. Specifically, the device includes at least one processor; at least one memory for storing program instructions, and when the program instructions are executed by the at least one processor, the device executes the above-mentioned method for frequency modulation of the chip. Further, the board includes the above-mentioned device for frequency modulation of the chip. In another aspect, when the frequency modulation operation of the present disclosure is implemented by program instructions, the present disclosure also discloses a computer-readable storage medium, which stores program instructions for frequency modulation of the chip, and when the program instructions are executed by the processor, the above-mentioned frequency modulation operation is performed.

[0088] Fig.12 1 is a block diagram showing a structure of a combined processing device 1200 according to an embodiment of the present disclosure. Fig.12 As shown, the combined processing device 1200 includes a frequency modulation device 1201 having the aforementioned architecture, which can be configured to perform the frequency modulation method described in conjunction with the accompanying drawings. In addition, the combined processing device also includes a universal interconnection interface 1202 and other processing devices 1203. The frequency modulation device 1201 according to the present disclosure can interact with other processing devices 1203 through the universal interconnection interface 1202 to jointly complete the relevant operations specified by the user.

[0089] According to the scheme disclosed herein, the other processing device may include one or more types of processors in general and / or special processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a neural network processor, etc., and the number of processors may not be limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the frequency modulation device disclosed herein and external data and control, and perform functions including but not limited to data transfer, and complete basic control of the frequency modulation device such as starting and stopping; other processing devices may also cooperate with the frequency modulation device to complete computing tasks.

[0090] According to the solution disclosed herein, the universal interconnection interface can be used to transmit data and control instructions between the frequency modulation device and other processing devices. For example, the frequency modulation device can obtain the required input data from other processing devices via the universal interconnection interface and write it into the storage device (or memory) on the frequency modulation device chip. Further, the frequency modulation device can obtain control instructions from other processing devices via the universal interconnection interface and write them into the control cache on the frequency modulation device chip. Alternatively or optionally, the universal interconnection interface can also read the data in the storage module of the frequency modulation device and transmit it to other processing devices.

[0091] Optionally, the combined processing device may further include a storage device 1204, which may be connected to the frequency modulation device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the frequency modulation device and the other processing device, especially data that cannot be fully stored in the internal or on-chip storage device of the frequency modulation device or other processing devices.

[0092] According to different application scenarios, the combined processing device disclosed herein can be used as a SOC chip system for mobile phones, robots, drones, video surveillance equipment and other devices, effectively reducing the core area of ​​the control part, improving the processing speed, and adjusting the frequency of the chip to reduce the overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Some of these components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a Wifi interface.

[0093] In some embodiments, the present disclosure further discloses a chip, which includes the frequency modulation device or the combined processing device. In other embodiments, the present disclosure further discloses a chip packaging structure, which includes the chip.

[0094] In some embodiments, the present disclosure also discloses a board, which includes the above chip packaging structure. Fig.13 , which provides the aforementioned exemplary board card, which, in addition to the aforementioned chip 1301, may also include other supporting components, including but not limited to: a storage device 1302, an interface device 1303 and a control device 1304.

[0095] The memory device is connected to the chip in the chip package structure via a bus for storing data. The memory device may include multiple groups of storage units 1305 and 1306. Each group of the storage units is connected to the chip via a bus. It is understood that each group of the storage units may be DDR SDRAM ("Double Data Rate SDRAM, double data rate synchronous dynamic random access memory", referred to as DDR).

[0096] The above-mentioned DDR can double the transmission speed of SDRAM without increasing the clock frequency. DDR allows data to be transmitted on the rising and falling edges of the clock pulse. The transmission speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, 64 bits of the above-mentioned 72-bit DDR4 controllers are used to transmit data, and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units, the theoretical bandwidth of a single storage unit to transmit data can reach 25600MB / s.

[0097] In one embodiment, each group of the storage units includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is arranged in the chip to control the data transmission and data storage of each of the storage units.

[0098] The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 1307 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through a standard PCIE interface to realize data transfer. Preferably, when the PCIE3.0 X16 interface is used for transmission, the theoretical bandwidth can reach 16000MB / s. In another embodiment, the interface device can also be other interfaces. This disclosure does not limit the specific forms of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

[0099] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a CPU or a single-chip microcomputer. In one or more embodiments, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing cores and / or multiple processing circuits in the chip.

[0100] In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the above-mentioned board. According to different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a means of transportation, a household appliance, and / or a medical device. The means of transportation include an airplane, a ship and / or a vehicle; the household appliances include a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical equipment includes an MRI, an ultrasound machine and / or an electrocardiograph.

[0101] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0102] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or it can be in electrical, optical, acoustic, magnetic or other forms.

[0103] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement the solution of this embodiment. In addition, the functional units in the various embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software program modules.

[0104] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory ("ROM, Read-Only Memory"), random access memory ("RAM, Random Access Memory"), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0105] In the above embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The foregoing content can be better understood in accordance with the following terms:

[0107] Clause A1. A method for frequency tuning a chip, comprising:

[0108] Obtaining a real-time power consumption sampling value of at least one chip during operation;

[0109] Determining an error value between the real-time power consumption sampling value and the power consumption target value; and

[0110] Based on the error value, a PID control module is used to determine an adjustment amount for adjusting the clock frequency of the at least one chip.

[0111] Clause A2. The method of clause A1, wherein the PID control module includes a proportional control unit, wherein determining the adjustment amount using the PID control module includes:

[0112] Based on the error value, using the proportional control unit to obtain a proportional term; and

[0113] A first adjustment amount for adjusting the clock frequency is determined based on the proportional term.

[0114] Clause A3. The method according to clause A2, wherein obtaining the proportional term comprises obtaining the proportional term based on the error value and a selected proportional coefficient.

[0115] Clause A4. A method according to clause A2 or A3, wherein the first adjustment amount is a first increment relative to a previous adjustment of the clock frequency.

[0116] Clause A5. The method according to clause A1, wherein the PID control module includes a proportional control unit and at least one of an integral control unit and a differential control unit, wherein determining the adjustment amount using the PID control module includes:

[0117] Based on the error value, using the proportional control unit to obtain a proportional term; and

[0118] determining a second adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and the integral term obtained by the integral control unit; or

[0119] determining a third adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and the differential term obtained by the differential control unit; or

[0120] A fourth adjustment amount for adjusting the clock frequency of the at least one chip is determined based on the proportional term, the integral term, and the differential term.

[0121] Clause A6. The method of clause A5, wherein each of the second adjustment amount, the third adjustment amount, and the fourth adjustment amount is an increment relative to a previous adjustment of the clock frequency.

[0122] Clause A7. A method according to clause A5, wherein obtaining the real-time power consumption sampling value comprises periodically obtaining a plurality of the real-time power consumption sampling values, wherein determining the integral term comprises performing for each of the real-time power consumption sampling values ​​within a predetermined time period:

[0123] Determine an error value between each of the real-time power consumption sampling values ​​and the power consumption target value;

[0124] performing an accumulation operation on the error value determined each time to obtain an accumulated sum; and

[0125] Based on the accumulated sum, an integral term is obtained using the integral control unit.

[0126] Clause A8. The method of clause A7, wherein obtaining the integral term comprises obtaining the integral term based on the accumulated sum and a selected integral coefficient.

[0127] Clause A9. The method according to clause A8, further comprising limiting the integral term within a selected range to eliminate static error effects and avoid overshoot operation.

[0128] Clause A10. The method according to clause A7, wherein when the predetermined time period arrives, the method further comprises:

[0129] A clearing operation is performed on the accumulated sum so as to perform the next accumulation operation within the next predetermined time period.

[0130] Clause A11. A method according to clause A7, wherein when a predetermined number of sampling periods within the predetermined time period is reached, the method further comprises:

[0131] The error value of the earliest sampling period in the predetermined number of sampling periods in the accumulated sum is cleared, so as to perform the accumulation operation on the error value of the most recent sampling period.

[0132] Clause A12. The method according to clause A5, wherein determining the adjustment amount using the derivative control unit in the PID control module comprises:

[0133] performing a subtraction operation on the error value determined this time and the error value determined last time to obtain a differential difference value; and

[0134] Based on the differential difference, a differential term is obtained using the differential control unit.

[0135] Clause A13. A method according to clause A12, wherein obtaining the differential term comprises obtaining the differential term based on the differential difference and a selected differential coefficient.

[0136] Clause A14. A method for frequency tuning a chip, comprising:

[0137] Obtaining a real-time power consumption sampling value of at least one chip during operation;

[0138] Determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold;

[0139] When the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold, performing a fast frequency reduction operation on the at least one chip;

[0140] When the real-time power consumption sampling value is less than the fast frequency reduction threshold, executing:

[0141] Determining an error value between the real-time power consumption sampling value and the power consumption target value; and

[0142] Based on the error value, a PID control module is used to determine an adjustment amount for adjusting the clock frequency of the at least one chip.

[0143] Clause A15. A device for frequency tuning a chip, comprising:

[0144] An acquisition module configured to acquire a real-time power consumption sampling value of at least one chip during operation;

[0145] PID control module, which is configured to:

[0146] Determining an error value between the real-time power consumption sampling value and the power consumption target value; and

[0147] Based on the error value, an adjustment amount for adjusting a clock frequency of the at least one chip is determined.

[0148] Clause A16. A device for frequency tuning a chip, comprising:

[0149] An acquisition module configured to acquire a real-time power consumption sampling value of at least one chip during operation;

[0150] A determination module configured to determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold;

[0151] a fast frequency reduction module, configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; and

[0152] The PID control module is configured to execute, when the real-time power consumption sampling value is less than the fast frequency reduction threshold:

[0153] Determining an error value between the real-time power consumption sampling value and the power consumption target value; and

[0154] An adjustment amount for adjusting a clock frequency of the at least one chip is determined based on the error value.

[0155] Clause A17. A device for frequency tuning a chip, comprising:

[0156] at least one processor;

[0157] At least one memory is used to store program instructions, and when the program instructions are executed by the at least one processor, the device executes the method according to any one of claims 1-14.

[0158] Clause A18. A board for frequency tuning a chip, comprising a device according to any one of claims 15-17.

[0159] Item A19. An integrated circuit chip, comprising a core for frequency tuning the chip, wherein when the integrated circuit chip is operating, the core can be configured to execute the method according to any one of claims 1-14.

[0160] It should be understood that the terms "first", "second", "third", and "fourth" in the claims, specifications, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their collections.

[0161] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0162] As used in this specification and claims, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if upon determining [the described condition or event]" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [the described condition or event] is detected" or "in response to detecting [the described condition or event]", depending on the context.

[0163] The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present disclosure, the specific implementation methods and the scope of application of the present disclosure, all belong to the scope of protection of the present disclosure. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A method for frequency modulation of a chip, comprising: Obtaining a real-time power consumption sampling value of at least one chip during operation; Determine an error value between the real-time power consumption sampling value and the power consumption target value; as well as Based on the error value, using a PID control module to determine an adjustment amount for adjusting a clock frequency of the at least one chip; The PID control module includes a primary PID control module and a final PID control module; Determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; And based on the error value, determining the adjustment amount for adjusting the clock frequency of the at least one chip by using a PID control module comprises: Acquire a first average power consumption value within a predetermined execution cycle of the primary PID control module and an average power consumption reference value associated with the primary PID control module; inputting the first average power consumption value and the average power consumption reference value into the primary PID control module; Based on the output value of the primary PID control module and the real-time power consumption target value of the previous adjustment operation, obtaining the real-time power consumption target value of the current adjustment operation; Inputting the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation into the final-stage PID control module; Determine an error value between the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation; Based on the error value, the final-stage PID control module is used to output the adjustment amount.

2. The method according to claim 1, wherein the PID control module comprises a proportional control unit, wherein determining the adjustment amount by using the PID control module comprises: Based on the error value, using the proportional control unit to obtain a proportional term; as well as A first adjustment amount for adjusting the clock frequency is determined based on the proportional term. 3 . The method of claim 2 , wherein obtaining the proportional term comprises obtaining the proportional term based on the error value and a selected proportionality coefficient. The method according to claim 2 or 3, wherein the first adjustment amount is a first increment relative to a previous adjustment of the clock frequency.

5. The method according to claim 1, wherein the PID control module comprises a proportional control unit and at least one of an integral control unit and a differential control unit, wherein determining the adjustment amount by using the PID control module comprises: Based on the error value, using the proportional control unit to obtain a proportional term; as well as determining a second adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and the integral term obtained by using the integral control unit; or determining a third adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and the differential term obtained by the differential control unit; or A fourth adjustment amount for adjusting the clock frequency of the at least one chip is determined based on the proportional term, the integral term, and the differential term. 6 . The method according to claim 5 , wherein each of the second adjustment amount, the third adjustment amount, and the fourth adjustment amount is an increment relative to a previous adjustment of the clock frequency.

7. The method according to claim 5, wherein acquiring the real-time power consumption sampling value comprises periodically acquiring a plurality of the real-time power consumption sampling values, and wherein determining the integral term comprises performing, for each of the real-time power consumption sampling values ​​within a predetermined time period: Determine an error value between each of the real-time power consumption sampling values ​​and the power consumption target value; Performing an accumulation operation on the error value determined each time to obtain an accumulated sum; as well as Based on the accumulated sum, an integral term is obtained using the integral control unit. 8 . The method of claim 7 , wherein obtaining the integral term comprises obtaining the integral term according to the accumulated sum and a selected integral coefficient.

9. The method of claim 8, further comprising limiting the integral term within a selected range to eliminate dead time effects and avoid overshoot operation.

10. The method according to claim 7, wherein when the predetermined time period arrives, the method further comprises: A clearing operation is performed on the accumulated sum so as to perform the next accumulation operation within the next predetermined time period.

11. The method according to claim 7, wherein when a predetermined number of sampling periods within the predetermined time period is reached, the method further comprises: The error value of the earliest sampling period in the predetermined number of sampling periods in the accumulated sum is cleared, so as to perform the accumulation operation on the error value of the most recent sampling period.

12. The method according to claim 5, wherein determining the adjustment amount by using the derivative control unit in the PID control module comprises: Performing a subtraction operation on the error value determined this time and the error value determined last time to obtain a differential difference value; as well as Based on the differential difference, a differential term is obtained using the differential control unit.

13. The method of claim 12, wherein obtaining the differential term comprises obtaining the differential term according to the differential difference and a selected differential coefficient.

14. A method for frequency modulation of a chip, comprising: Obtaining a real-time power consumption sampling value of at least one chip during operation; Determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold; When the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold, performing a fast frequency reduction operation on the at least one chip; When the real-time power consumption sampling value is less than the fast frequency reduction threshold, executing: Determine an error value between the real-time power consumption sampling value and the power consumption target value; as well as Based on the error value, using a PID control module to determine an adjustment amount for adjusting a clock frequency of the at least one chip; The PID control module includes a primary PID control module and a final PID control module; Determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; And based on the error value, determining the adjustment amount for adjusting the clock frequency of the at least one chip by using a PID control module comprises: Acquire a first average power consumption value within a predetermined execution cycle of the primary PID control module and an average power consumption reference value associated with the primary PID control module; inputting the first average power consumption value and the average power consumption reference value into the primary PID control module; Based on the output value of the primary PID control module and the real-time power consumption target value of the previous adjustment operation, obtaining the real-time power consumption target value of the current adjustment operation; Inputting the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation into the final-stage PID control module; Determine an error value between the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation; Based on the error value, the final-stage PID control module is used to output the adjustment amount.

15. A device for frequency modulation of a chip, comprising: An acquisition module configured to acquire a real-time power consumption sampling value of at least one chip during operation; PID control module, which is configured to: Determining an error value between the real-time power consumption sampling value and the power consumption target value; and Based on the error value, determining an adjustment amount for adjusting a clock frequency of the at least one chip; The PID control module includes a primary PID control module and a final PID control module; The device also performs the following operations through the acquisition module, the primary PID control module and the final PID control module: Acquire a first average power consumption value within a predetermined execution cycle of the primary PID control module and an average power consumption reference value associated with the primary PID control module; inputting the first average power consumption value and the average power consumption reference value into the primary PID control module; Based on the output value of the primary PID control module and the real-time power consumption target value of the previous adjustment operation, obtaining the real-time power consumption target value of the current adjustment operation; Inputting the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation into the final-stage PID control module; Determine an error value between the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation; Based on the error value, the final-stage PID control module is used to output the adjustment amount.

16. A device for frequency modulation of a chip, comprising: An acquisition module configured to acquire a real-time power consumption sampling value of at least one chip during operation; A determination module configured to determine whether the real-time power consumption sampling value is greater than or equal to a fast frequency reduction threshold; A fast frequency reduction module, configured to perform a fast frequency reduction operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency reduction threshold; as well as The PID control module is configured to execute, when the real-time power consumption sampling value is less than the fast frequency reduction threshold: Determine an error value between the real-time power consumption sampling value and the power consumption target value; as well as determining an adjustment amount for adjusting a clock frequency of the at least one chip based on the error value; The PID control module includes a primary PID control module and a final PID control module; The device also performs the following operations through the acquisition module, the primary PID control module and the final PID control module: Acquire a first average power consumption value within a predetermined execution cycle of the primary PID control module and an average power consumption reference value associated with the primary PID control module; inputting the first average power consumption value and the average power consumption reference value into the primary PID control module; Based on the output value of the primary PID control module and the real-time power consumption target value of the previous adjustment operation, obtaining the real-time power consumption target value of the current adjustment operation; Inputting the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation into the final-stage PID control module; Determine an error value between the real-time power consumption sampling value and the real-time power consumption target value of the current adjustment operation; Based on the error value, the final-stage PID control module is used to output the adjustment amount.

17. A device for frequency modulation of a chip, comprising: at least one processor; At least one memory is used to store program instructions, and when the program instructions are executed by the at least one processor, the device executes the method according to any one of claims 1-14.

18. A board for frequency modulation of a chip, comprising the device according to any one of claims 15-17.

19. An integrated circuit chip, comprising a core for frequency tuning the chip, wherein when the integrated circuit chip is in operation, the core can be configured to execute the method according to any one of claims 1 to 14.

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