Signal Path Biasing in Memory Systems

Abstract

The present application relates to biasing of signal paths in electronic systems (e.g., memory systems). In one example, a memory device, a host device, or both may be configured to bias a signal path to an intermediate or mid-bias voltage level between an idle state and information transfer or between information transfer and an idle state, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage (e.g., a mid-bias voltage) may be associated with an access command or other command for information to be communicated between devices of the electronic system (e.g., a command for information to be communicated between a memory device and a host device).

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 028465, entitled “SIGNAL PATH BIASING IN AMEMORY SYSTEM,” filed by Spirkl et al. on April 16, 2020, which claims priority to U.S. patent application No. 16 / 849,740, entitled “SIGNAL PATH BIASING IN AMEMORY SYSTEM,” filed by Spirkl et al. on April 15, 2020, and U.S. provisional patent application No. 62 / 835,264, entitled “SIGNAL PATH BIASING IN AMEMORY SYSTEM,” filed by Spirkl et al. on April 17, 2019, each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to signal path biasing in memory systems. Background Art

[0004] The following relates generally to a system including at least one memory device, and more particularly to signal path biasing in a memory system.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most commonly store one of two states, usually indicated by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write a state or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain its stored logic state for a long time even in the absence of external power. Volatile memory devices such as DRAM may lose their stored state when disconnected from the external power supply.

[0007] In some systems, signals transmitted between a memory device and a host device (e.g., a device hosting the memory device) may cause interference. Thus, signals transmitted in the memory system may affect other signals of the memory system, including other signals communicated between the memory device and the host device. Summary of the invention

[0008] A method is described. In some examples, the method may include: receiving an access command associated with information to be transmitted to a host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing, by a memory device, the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command; and transmitting, through the signal path, a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0009] A memory device is described. In some examples, the memory device may include: a receiver configured to receive an access command associated with information to be transmitted to a host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The memory device may also include a driver configured to bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command, and transmit a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level.

[0010] A method is described. In some examples, the method may include: transmitting an access command associated with information to be transmitted through a signal path to a memory device using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing the signal path to a fourth voltage level between the first voltage level and the third voltage level by a host device based on the access command; and transmitting through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0011] A host device is described. In some examples, the host device may include a transmitter configured to transmit an access command associated with information to be transmitted to a memory device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The host device may also include a driver configured to bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command, and transmit a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level.

[0012] A system is described. In some examples, the system may include: a memory device; and a host device coupled to the memory device, the system configured to: communicate a read command associated with information to be communicated from the memory device to the host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; bias the signal path to a fourth voltage level between the first voltage level and the third voltage level; and communicate through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0013] A system is described. In some examples, the system may include: a memory device; and a host device coupled to the memory device, the system configured to: communicate a write command associated with information to be communicated from the host device to the memory device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; bias the signal path to a fourth voltage level between the first voltage level and the third voltage level; and communicate through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An example of a system supporting signal path biasing in a memory system according to examples as disclosed herein is described.

[0015] Figure 2 An example of a memory die supporting signal path biasing in a memory system according to examples as disclosed herein is illustrated.

[0016] Figure 3 An example of a system supporting signal path biasing in a memory system according to examples as disclosed herein is described.

[0017] Figure 4 An example of a timing diagram supporting signal path biasing in a memory system according to examples as disclosed herein is illustrated.

[0018] Figure 5 A block diagram of a memory device supporting signal path biasing in a memory system is shown according to examples as disclosed herein.

[0019] Figure 6 A block diagram of a host device supporting signal path biasing in a memory system is shown according to examples as disclosed herein.

[0020] Figure 7 and 8 A flow chart illustrating one or more methods of supporting signal path biasing in a memory system according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0021] Some electronic systems may include a memory device and a host device (e.g., a device that uses the memory device to store information), and may transmit signals between the memory device and the host device. In some electronic systems, such signaling may cause interference (e.g., radio frequency (RF) interference, electromagnetic (EM) interference, electric field interference) with other signaling, such as other signaling between the memory device and the host device. In some cases, a signal transmitted by a memory device or a host device may affect a component configured to receive such a signal. Therefore, the transmission of a signal between a memory device and a host device may affect the reception of a signal at the memory device or the host device, which may affect various operations performed by an electronic system including a memory system and a host device.

[0022] In some electronic systems, a transition between an idle state and a subsequent information transfer or a transition between an information transfer and a subsequent idle state may be associated with causing or driving relatively high interference. For example, in an idle state, one or both of a memory device or a host device may be configured to bias a signal path to an idle voltage, such as a termination voltage (e.g., a termination voltage for a memory device, a termination voltage for a host device, a voltage level associated with termination logic, a voltage level at a termination impedance), which may be associated with lower power consumption than when the signal path is biased to some voltage other than the idle or termination voltage. At a transition between an idle state and a subsequent information transfer (or vice versa), a change in a signal or signal path bias may be relatively large when transitioning from the idle voltage to a voltage level of a modulation scheme that is relatively farthest from the idle voltage (e.g., in a first modulation symbol of a data transfer). Such a relatively large change in a signal or signal path bias may be associated with relatively high interference in an electronic system.

[0023] According to examples as disclosed herein, an electronic system may be configured to bias a signal path in a manner that reduces interference with other signals during transitions to and from an idle state. For example, in some electronic systems, a memory device, a host device, or both may be configured to bias a signal path to a voltage level (e.g., a mid-bias voltage) between voltage levels of a modulation scheme used to convey information between an idle state and a subsequent information transfer or between an information transfer and a subsequent idle state. In some examples, the bias may include biasing the signal path to a voltage greater than the lowest voltage level of the modulation scheme, less than the highest voltage level of the modulation scheme, or both. In some examples, the bias may be a voltage level that is an intermediate value (e.g., an average voltage level, a mean voltage level) between the voltage levels of the modulation scheme, and the intermediate value may or may not correspond to a voltage level of the modulation scheme used to convey information (e.g., the bias may not correspond to one of the voltage levels of the modulation scheme). In some examples, the bias may correspond to a voltage level of the modulation scheme used to convey information, but may or may not be an arithmetic mean of other voltage levels of the modulation scheme.

[0024] Features of the present disclosure are initially described in reference Figure 1 and 2 The features of the present disclosure are described in the context of the memory systems and memory dies described herein. Figure 3 and 4 These and other features of the present disclosure are described in the context of the diagrams and illustrative modulation schemes described herein. Figures 5 to 8 The described apparatus diagrams and flow diagrams related to channel modulation for a memory device are further illustrated and described with reference to the apparatus diagrams and flow diagrams.

[0025] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples as disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0026] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, etc. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle, etc. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100.

[0027] At least a portion of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, a vehicle, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some examples, external memory controller 105 may be referred to as a host or host device. In some examples, system 100 is a graphics card.

[0028] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide a physical memory address or other space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes used to modulate signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, or other factors.

[0029] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0030] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be in electronic communication with each other using a bus 140.

[0031] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In this case, the processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system on a chip (SoC), among other instances.

[0032] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0033] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripherals.

[0034] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0035] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface, or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0036] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0037] The components of system 100 may be composed of general or special purpose circuit systems designed to perform their functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, gates, decoders, amplifiers, or other active or passive elements configured to perform the functions described herein.

[0038] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Reference Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0039] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or stacked next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce production costs or improve performance of the memory array, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0040] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to perform commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 will store certain data on behalf of a component of the system 100 (e.g., the processor 120), or a read command indicating that the memory device 110 will provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, or other.

[0041] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. In addition, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0042] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 for the external memory controller 105 to satisfy. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0043] In some cases, the external memory controller 105 or another component of the system 100, or its functions described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or another component of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0044] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105, and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel.

[0045] In some cases, the pins or pads of the terminals may be part of a signal path of channel 115. Additional signal paths may be coupled with the terminals of the channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or its components, such as signal paths internal to memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0046] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, channel 115 may be an aggregate channel and, therefore, may include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. The signals conveyed through the channel may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. The signals conveyed through the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded for each clock cycle.

[0047] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command with an address of desired data. In some cases, CA channel 186 may be recorded on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0048] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to communicate one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state, and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or for other full system operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors).

[0049] In some cases, the channels 115 may include one or more data (DQ) channels 190. The data channels 190 may be configured to communicate data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may communicate information to be written to the memory device 110 (e.g., bidirectionally) or information to be read from the memory device 110. The data channels 190 communicate signals that may be modulated using various different modulation schemes (e.g., non-return to zero (NRZ), pulse amplitude modulation (PAM) with a certain number of symbols or voltage levels, such as a PAM3 scheme associated with three symbols or voltage levels, a PAM4 scheme associated with four symbols or voltage levels, etc.).

[0050] In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

[0051] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference (e.g., a timing reference for both read and write operations) that is typically used for access operations of the memory device 110. Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, an oscillator, a crystal, logic gates, transistors, or the like).

[0052] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be configured to communicate error detection signals, such as checksums, to improve system reliability. EDC channels may include any number of signal paths and may communicate signals modulated using a modulation scheme, such as PAM with a certain number of symbols or voltage levels.

[0053] The channel 115 may couple the external memory controller 105 with the memory device 110 using a variety of different architectures. Examples of the various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0054] The signals communicated over the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme with M equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, NRZ, unipolar encoding, bipolar encoding, Manchester encoding, PAM with two symbols (e.g., PAM2), and the like.

[0055] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., where the symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0056] In some examples, signaling transmitted between memory device 110 and a host device (e.g., via channel 115) may cause interference, such as radio frequency (RF) interference, electromagnetic (EM) interference, electric field interference, etc. In some examples, interference caused by the transmitted signaling may involve a level or rate of change of a current associated with the transmitted signaling, a level or rate of change of a voltage associated with the transmitted signaling, or various combinations thereof. For example, a relatively faster rate of change of a current or voltage of a transmitted signal may be associated with a relatively stronger or faster rate of change in an electric or electromagnetic field associated with the transmitted signal, while a relatively slower rate of change of a current or voltage of a transmitted signal may be associated with a relatively weaker or slower change in an electric or electromagnetic field associated with the transmitted signal. The transmitted signaling may be referred to as an aggressor or an aggressor signal, and interference may be based at least in part on the level of the aggressor, the rate of change of the aggressor, and other phenomena.

[0057] In some systems, interference from transmitted signaling may be incident on a signal carrying path (e.g., a channel 115, a conductive path of a memory device 110 or a host device, a conductive path between a host device and a memory device 110) or a component that is part of a signal carrying path for a signal to be received (e.g., a component of a memory device 110 or a host device, a component between a host device and a memory device 110). For example, an electric or electromagnetic field caused by signaling transmitted by a memory device 110, which may be an oscillating or otherwise varying electric or electromagnetic field, may be incident on a channel 115 associated with a signal to be received by a memory device 110 or an external memory controller 105. Similarly, an electric or electromagnetic field caused by signaling transmitted by an external memory controller 105, which may be an oscillating or otherwise varying electric or electromagnetic field, may be incident on a channel 115 associated with a signal to be received by a memory device 110 or an external memory controller 105.

[0058] In some examples, a channel 115 associated with a received signal may have a capacitive or inductive connection or coupling with an aggressor, such as a capacitive or inductive connection or coupling with another channel 115, a component of the memory device 110 (e.g., a transmitter), a component of a host device, or various combinations thereof. In one example, an incident electric or electromagnetic field caused by transmitted signaling may change or interrupt a signal to be received (e.g., change or interrupt a current or voltage on a conductive path), or affect a component configured to receive a signal, which may be referred to as "crosstalk" (e.g., AC crosstalk, capacitive crosstalk). In some examples, such crosstalk may affect (e.g., reduce, prevent) the ability of the memory device 110 or a host device (e.g., an external memory controller 105) to simultaneously transmit and receive signals.

[0059] The system 100 may be configured to transmit signaling or otherwise bias a signal path in a manner that reduces interference with other signals or components. For example, the memory device 110, the host device (e.g., the external memory controller 105), or both may be configured to bias a signal path (e.g., a signal path of a DQ channel) to a voltage level (e.g., a mid-bias voltage) between voltage levels of a modulation scheme used to convey information between an idle state and a subsequent information transfer or between an information transfer and a subsequent idle state. The described biasing of the mid-bias voltage may be associated with an access command (e.g., a read command, a write command) for information to be communicated between the memory device 110 and the host device. In one example, the memory device 110 may receive a read command (e.g., over a CA channel), and based at least in part on receiving the read command (e.g., in response to receiving the read command), the memory device 110 may bias the signal path (e.g., the signal path of the DQ channel) to a mid-bias voltage level before transmitting signaling modulated to include information associated with the read command. In another example, a host device (e.g., external memory controller 105) may transmit a write command (e.g., via a CA channel), and based at least in part on the write command (e.g., accompanying the transmission of the write command), the host device may bias a signal path (e.g., a signal path of a DQ channel) to a medium bias voltage level prior to transmitting signaling modulated to include information associated with the write command. In some examples, such biasing performed prior to transmitting signaling modulated to include information associated with an access command may be referred to as a "preamble" (e.g., a medium bias preamble), and such biasing performed after transmitting signaling modulated to include information associated with an access command may be referred to as a "postamble" (e.g., a medium bias postamble).

[0060] Using the techniques described herein, interference of signaling between an idle state and a subsequent information transfer, or interference of signaling between an information transfer and a subsequent idle state, can be reduced relative to other techniques. For example, by inserting a bias (e.g., as a preamble, as a postamble) between such transitions, the rate of change of signaling or signal path bias can be reduced, which can reduce electromagnetic fields, electric fields, or other forms of interference induced by the transmitted signaling. Thus, the signal path associated with the received signaling can be exposed to reduced interference, which can improve the device's ability to simultaneously transmit and receive signaling. Thus, by reducing the signal swing or rate of change of signaling at such transitions, communication between the memory device 110 and the host device can be improved, which can improve the performance of the system 100.

[0061] Figure 2 An example of a memory die 200 according to examples disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0062] The memory cell 205 may store a charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor including a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed.

[0063] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting access lines such as word lines 210 and / or digit lines 215. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, and digit lines, or the like, may be interchangeable without loss of understanding or operation. Activating or selecting word lines 210 or digit lines 215 may include applying a voltage to the corresponding line.

[0064] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and the digit lines 215. By biasing the word lines 210 and the digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0065] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 may receive a column address from a local memory controller 260 and activate a digit line 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 at its intersection may be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0066] Memory cell 205 may include a logic storage component, such as capacitor 230 and switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switch component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switch component 235 may be an example of a transistor or any other type of switching device that selectively establishes or releases electronic communication between two components.

[0067] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch component 235. Capacitor 230 can be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 can be coupled to digit line 215. In some cases, switch component 235 is a transistor and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, switch component 235 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switch component 235, and switch component 235 can be activated / deactivated based on the voltage applied to word line 210.

[0068] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for accessing the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching element 235 of the memory cell 205 and may be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0069] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0070] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be very small. Therefore, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect small changes in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., to the input / output 255).

[0071] The local memory controller 260 may control the operation of the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 220, the column decoder 225, and the sensing component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive data from the external memory controller 105 (or reference Figure 1 The local memory controller 260 may receive commands and / or data, translate the commands and / or data into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 may generate row address signals and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied, and may be different for the various operations discussed when operating the memory die 200.

[0072] The local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may apply a specific signal (e.g., a voltage) to the digit line 215 during a write operation to store a specific state (e.g., a charge) in the capacitor 230 of the memory cell 205, which may indicate a desired logic state.

[0073] The local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify a target memory cell 205 on which a read operation is to be performed. As part of the read operation, the local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller 155).

[0074] The local memory controller 260 may be configured to transmit data associated with a write command or a read command to a host device. The local memory controller 260 (or the device memory controller, as the case may be) may be configured to bias a signal path as part of transmitting data associated with a read command or a write command in a manner that reduces interference with other signals or components. For example, the local memory controller 260 may be configured to bias the signal path to a voltage level between the voltage levels of the modulation scheme used to convey information (e.g., a mid-bias voltage) between an idle state and a subsequent information transfer or between an information transfer and a subsequent idle state.

[0075] Figure 3 An example of a system 300 supporting signal path biasing in a memory system according to an example as disclosed herein is illustrated. The system 300 includes a host device 310 and a memory device 330, and can be configured to support signaling between the host device 310 and the memory device 330 through a channel (e.g., reference Figure 1 Signal paths, transmission paths, channels 115) are described.

[0076] Host device 310 may include transmitter 320 and receiver 325, which in some examples may be reference Figure 1 Components of the external memory controller 105 described. In some examples, the transmitter 320 and the receiver 325 may be part of a transceiver component of the host device 310 (e.g., to support bidirectional communication). The transmitter 320 may include or otherwise refer to a modulator or driver configured to process received information (e.g., received from another component of the host device 310) and modulate a signal based on the processed information into information that includes information for transmission by the host device 310 (e.g., by biasing a signal path associated with a channel according to a voltage level of a modulation scheme). The receiver 325 may include or otherwise refer to a demodulator configured to demodulate a signal that includes information for reception at the host device 310 (e.g., by detecting or decoding a bias on a signal path associated with a channel according to a voltage level of a modulation scheme).

[0077] Although illustrated as including a single transmitter 320, in some examples, the host device 310 may include a transmitter 320 for each channel in a channel set, for each pin in a pin set (e.g., in a pin set associated with a channel), or various other configurations. Likewise, although illustrated as including a single receiver 325, in some examples, the host device 310 may include a receiver 325 for each channel in a channel set, for each pin in a pin set (e.g., in a pin set associated with a channel), or various other configurations. In some examples, the transmitter 320 and the receiver 325 may be included in a channel-specific transceiver, such as a transceiver configured to communicate signaling over a bidirectional data channel (e.g., a DQ channel) or some other channel having one or more transmission paths (e.g., one or more pins, one or more conductors).

[0078] Memory device 330 may include transmitter 340 and receiver 345, which in some examples may be reference Figure 1 Components of the device memory controller 155 described. In some examples, the transmitter 340 and the receiver 345 may be part of a transceiver of the memory device 330 (e.g., to support bidirectional communication). The transmitter 340 may include or otherwise refer to a regulator or driver configured to process received information (e.g., received from another component of the memory device 330) and modulate a signal based on the processed information to include information for transmission by the memory device 330 (e.g., by biasing a signal path associated with a channel according to a voltage level of a modulation scheme). The receiver 345 may include or otherwise refer to a demodulator configured to demodulate a signal including information for reception at the memory device 330 (e.g., by detecting or decoding a bias on a signal path associated with a channel according to a voltage level of a modulation scheme).

[0079] Although illustrated as including a single transmitter 340, in some examples, the memory device 330 may include a transmitter 340 for each channel in a set of channels, for each pin in a set of pins (e.g., a set of pins associated with a channel), or various other configurations. Likewise, although illustrated as including a single receiver 345, in some examples, the memory device 330 may include a receiver 345 for each channel in a set of channels, for each pin in a set of pins (e.g., a set of pins associated with a channel), or various other configurations. In some examples, the transmitter 340 and the receiver 345 may be included in a channel-specific transceiver, such as a transceiver configured to communicate over a bidirectional channel, such as a data channel (e.g., a DQ channel) having one or more transmission paths (e.g., one or more pins, one or more conductors).

[0080] The system 300 may be configured to communicate first signaling 350 (e.g., signaling from the host device 310 to the memory device 330) and second signaling 360 (e.g., signaling from the memory device 330 to the host device 310). In some examples, the first signaling 350 may include or refer to access command signaling (e.g., write command, read command, rewrite command, refresh command) on a channel (e.g., CA channel) configured for access command signaling, or include or refer to data or other information signaling (e.g., write data, write signal) on a channel (e.g., DQ channel) configured for data, or other information signaling. In some examples, the second signaling 360 may include or refer to data or other information signaling (e.g., read data, read signal) on a channel (e.g., DQ channel) configured for data, error detection signaling (e.g., error detection information, checksum, error detection signal) on a channel (e.g., EDC channel) configured for error detection and correction information, or other information signaling. In various examples, the first signaling 350 and the second signaling 360 can be associated with one or more signal paths. For example, the first signaling 350 or the second signaling 360 can be carried on 1-line channel, 2-line channels, 4-line channels, 8-line channels, or some other number of signal paths.

[0081] The configuration of system 300 may cause one signal of system 300 to cause interference (e.g., be an aggressor signal or otherwise associated with an aggressor signal path), and another signal of system 300 to be affected by such interference (e.g., be a victim signal or otherwise associated with a victim signal path). For example, second signaling 360 (e.g., an aggressor signal) may cause interference to first signaling 350 (e.g., a victim signal), such as radio frequency (RF) interference, electromagnetic (EM) interference, electric field interference, etc. In some examples, the interference caused by second signaling 360 may involve a level or rate of change of a current associated with the transmitted signaling, a level or rate of change of a voltage associated with the transmitted signaling, or various combinations thereof. For example, a relatively faster rate of change of a current or voltage of second signaling 360 may be associated with a relatively stronger or faster change in an electric field or electromagnetic field, while a relatively slower rate of change of a current or voltage of second signaling 360 may be associated with a relatively weaker or slower change in an electric field or electromagnetic field associated with the transmitted signal.

[0082] Interference from the second signaling 360 may be experienced on a signal carrying path (e.g., channel 115, a conductive path of a memory device 110 or a host device, a conductive path between a host device and a memory device 110), such as a signal path associated with the first signaling 350, or a component (e.g., receiver 345, transmitter 320) for the first signaling 350 that is part of the signal carrying path, any of which may be referred to as a victim signal path. For example, an electric or electromagnetic field (which may be an oscillating or otherwise changing electric or electromagnetic field) caused by the second signaling 360 may be incident on a channel configured to carry the first signaling 350. In some examples, the incidence or susceptibility of such interference may be associated with capacitive coupling or inductive coupling, which may be related to the geometry or layout of various components of the system 300. The incident electric or electromagnetic field caused by the second signaling 360 may change or interrupt the first signaling 350 (e.g., change or interrupt the current or voltage on the conductive path), or affect a component (e.g., receiver 345) configured to receive the first signaling 350. Likewise, the incident electric or electromagnetic field caused by the first signaling 350 may change or interrupt the second signaling 360 (e.g., change or interrupt the current or voltage on the conductive path), or affect a component (e.g., receiver 325) configured to receive the second signaling 360. In some examples, crosstalk or other examples of crosstalk phenomena, aggressors or victims, such as the examples described, may affect (e.g., reduce, prevent) the ability of one or both of the host device 310 or the memory device 330 to transmit and receive signals simultaneously.

[0083] In some examples of system 300, signal transitions between an idle state and information transfer can be associated with causing or driving relatively high interference on a victim signal or signal path. In various examples, the idle state can refer to an idle state of system 300, an idle state of host device 310, an idle state of memory device 330, or a combination thereof. For example, in the idle state, one or both of memory device 330 or host device 310 can be configured to bias the signal path to an idle voltage. In some examples, the idle voltage can be equal to or otherwise associated with a termination voltage (e.g., a termination voltage level for memory device 330, a termination voltage level for host device 310, a termination voltage level for a signal path), which can be associated with lower power consumption than when the signal path is biased to some voltage other than the termination voltage. For information transfer between memory device 330 and host device 310, the system may be configured to communicate signaling modulated using a modulation scheme that includes a set of voltage levels (e.g., by biasing a signal path of one or more signal paths, such as a DQ channel, to one of the voltage levels of the modulation scheme to represent, transmit, or otherwise communicate a modulation symbol).

[0084] At a transition between an idle state and a subsequent information transmission, for example, when transitioning from an idle voltage to a voltage level of the modulation scheme that is relatively farthest from the idle voltage (e.g., in the first modulation symbol of a data transmission), a change in the bias of a signal or signal path may be relatively large, and a relatively large change in the bias of a signal or signal path at the beginning of an information transmission may be associated with driving or causing a relatively high interferer (e.g., a relatively strong aggressor). At a transition between an information transmission and a subsequent idle state, for example, when transitioning from a voltage level of the modulation scheme that is relatively farthest from the idle voltage (e.g., in the last modulation symbol of an information transmission) to the idle voltage, a change in the bias of a signal or signal path may be relatively large, and a relatively large change in the bias of a signal or signal path after an information transmission may be correspondingly associated with a relatively high interferer (e.g., a relatively strong aggressor).

[0085] The system 300 may be configured to communicate signaling (e.g., first signaling 350, second signaling 360) or otherwise bias a signal path in a manner that reduces interference with other signals or signal paths (reduces interference with victim signals or signal paths). The memory device 330, the host device 310, or both may be configured to bias the signal path to an intermediate or mid-bias voltage level between an idle state and a subsequent information transfer or between an information transfer and a subsequent idle state. For example, the memory device 330 or the host device or both may bias the signal path to a voltage level (e.g., a mid-bias voltage) between the voltage levels of the modulation scheme used to communicate information, which may reduce the rate of change of the signaling associated with such a transition.

[0086] In various examples, the described biasing of the centering bias or another intermediate voltage may be associated with or otherwise accompany an access command (e.g., a read command, a write command) for information to be communicated between the memory device 330 and the host device 310. In one example, the memory device 330 may receive a read command from the host device 310 (e.g., over a CA channel, via a first signaling 350), and based at least in part on receiving the read command (e.g., in response to receiving the read command), the memory device 330 may bias the signal path to a mid-bias voltage level prior to transmitting (e.g., over a DQ channel, via a second signaling 360) signaling modulated to include information associated with the read command. In another example, the host device 310 may transmit a write command to the memory device 330 (e.g., over the CA channel, via the first signaling 350), and based at least in part on the write command (e.g., accompanying the transmission of the write command), the host device 310 may bias the signal path to a medium bias voltage level before transmitting (e.g., over the DQ channel, via the first signaling 350) signaling modulated to include information associated with the write command.

[0087] In some examples, such biasing performed before transmitting a signal modulated to include information associated with an access command may be referred to as a "preamble" (e.g., a mid-biased preamble, a mid-preamble symbol or sequence), and such biasing performed after transmitting a signal modulated to include information associated with an access command may be referred to as a "postamble" (e.g., a mid-biased postamble, a mid-postamble symbol or sequence). In the event that the preamble and postamble are included in signaling via a bidirectional channel, a transmitter of the preamble or postamble may have voltage control or bias authority over the bidirectional channel for a duration (e.g., for biasing one or more signal paths associated with the channel according to a particular preamble or postamble), and a receiver of the preamble or postamble may recognize the presence of the preamble or postamble on the bidirectional channel for a corresponding duration, which may include the receiver ignoring signaling associated with the preamble or postamble, or otherwise processing the preamble or postamble differently than other data, payload, or information (e.g., avoiding decoding the preamble or postamble, decoding the preamble or postamble but recognizing that the preamble or postamble is not part of information associated with an access command).

[0088] Figure 4 An example of a timing diagram 400 illustrating signal path biasing in a support memory system according to an example as disclosed herein. The timing diagram 400 may illustrate voltages of a signal path in the system 300 (e.g., a signal path between a host device 310 and a memory device 330) over time, as shown in FIG. Figure 3 In some examples, timing diagram 400 can illustrate voltages of one or more signal paths of a channel (e.g., a DQ channel associated with the one or more signal paths) configured to communicate information between host device 310 and memory device 330, which in some examples can be a bidirectional channel.

[0089] The timing diagram 400 illustrates a burst 430 of information conveyed through a signal path of a channel along with an idle period, a preamble (e.g., a preamble duration 410), and a postamble (e.g., a postamble duration 450). The timing diagram 400 is illustrated by having a set of voltages that can be configured in the system 300. Although the configured voltage levels of the timing diagram 400 are illustrated by specific intervals along the vertical axis, the voltage levels of the timing diagram 400 are for illustrative purposes and do not indicate any limitation on the specific relative magnitude of the intervals between one voltage level and another voltage level. In addition, the biasing described with reference to the timing diagram 400 may include selective coupling with a voltage source initiated in the described operation, and the described signal path may or may not instantaneously or otherwise reach the same voltage as the coupled voltage source. For example, as illustrated, the signal path may approach the voltage level of the coupled voltage source according to a time constant behavior, but the signal path may be coupled to the voltage source or otherwise controlled to a specific voltage level for the entire duration between the described operations.

[0090] Timing diagram 400 includes an idle voltage level V idle , which may refer to the voltage of the signal path during an idle or standby state (e.g., when memory device 330 is not actively reading from or writing to). In various examples, the signal path may be biased to V by host device 310, memory device 330, or both based on the configuration of system 300 or the operating state of system 300 (e.g., based on the configuration of one device or another device having voltage control or bias authority over the signal path during an idle state). idle In some examples, the idle voltage may be configured to be equal to a termination voltage of the system 300 (e.g., a termination voltage at the memory device 330, a termination voltage at the host device 310), which may reduce power consumption during an idle state compared to when the signal path is biased to a voltage different from the termination voltage. In some instances, the idle voltage level may be configured to be equal to the input / output supply voltage. Although the timing diagram 400 is illustrated as having a relatively high idle voltage level, in some instances, the idle voltage level may be relatively low, such as a ground voltage, a chassis ground, or a virtual ground, which may be used in a ground termination system.

[0091] Timing diagram 400 also includes a set of voltages {V mod,1 ,V mod,2 ,V mod,3}, which can be used to convey information along a signal path (e.g., voltage levels corresponding to modulation symbols of a modulation scheme). In the example of timing diagram 400, three voltage levels associated with the modulation scheme are illustrated, which can correspond to voltage levels of a PAM3 modulation scheme. However, the described techniques can be used to support signal paths of modulation schemes that include any number of voltage levels (e.g., four voltage levels of a PAM4 modulation scheme, more than four voltage levels, two voltage levels of a binary modulation scheme).

[0092] Although each of the voltage sets associated with the modulation scheme in the example of timing diagram 400 is shown as being different from the idle voltage (e.g., V idle Not included in {V mod,1 ,V mod,2 ,V mod,3}), but in other instances, V idle can be included in the set of voltage levels used in the modulation scheme. For example, V idle can be equal to the highest voltage level of the modulation scheme (e.g., V idle Can be equal to V mod,3 ), or V idle can be equal to the lowest voltage level of the modulation scheme (e.g., V idle Can be equal to Vmod,1 , the V mod,1 may be equal to or otherwise correspond to a ground or chassis ground voltage level), and either of the highest voltage level and the lowest voltage level may be equal to a termination voltage level.

[0093] Timing diagram 400 also illustrates one or more voltage levels that may be used as bias voltages during preamble duration 410. Such voltage levels may be referred to as preamble voltages V pre , which may refer to the voltage level of the preamble, the preamble symbol, the preamble sequence, or other intermediate bias of the signal path after the idle state and before subsequent information transmission. In some examples, the preamble voltage may be higher than the lowest voltage level associated with the modulation scheme (e.g., V pre Can be higher than V mod,1 ), below the highest voltage level associated with the modulation scheme (e.g., V pre Can be lower than V mod,3 ), or both (e.g., V pre Available in V mod,1 With V mod,3 In some examples (not shown), the preamble voltage may be a midpoint voltage level (e.g., V pre Can be equal to V mod,1 With V mod,3 In another example (not shown), when (e.g., according to a PAM4 modulation scheme) a set of four voltage levels {V mod,1a ,V mod,2a ,V mod,3a ,V mod,4a} modulation scheme on the signal path, V pre Can be equal to V mod,1a With V mod,4a an average value of , which may not be included in the set of voltage levels associated with the modulation scheme.

[0094] Although the preamble voltage is illustrated as a voltage level different from the voltage level used in the modulation scheme, in some examples, the preamble voltage may be equal to one of the voltage levels included in the modulation scheme. For example, on a signal path using a modulation scheme that includes three voltage levels for conveying information (which, as illustrated, may correspond to a PAM3 modulation scheme), the preamble voltage level may be equal to a middle voltage level of the modulation scheme (e.g., V pre Can be equal to V mod,2 In another example (not shown), when (e.g., according to a PAM4 modulation scheme) a set of four voltage levels {V mod,1a ,V mod,2a ,Vmod,3a ,V mod,4a}, the preamble voltage level may be equal to any of the intermediate voltage levels of the modulation scheme (e.g., V pre Can be equal to V mod,2a or V mod,3a ), which may be based on a static configuration, a dynamic configuration, or an operating condition of the system 300, or a modulation of a particular information transmission (e.g., based at least in part on a voltage level of a first symbol of the information transmission).

[0095] Although the preamble voltage is illustrated as being within the voltage level range of the modulation scheme, in other examples (not shown), the preamble voltage may be outside the voltage level range of the modulation scheme and still support reduced interference as described herein, such as when the idle voltage prior to information transfer is also outside the voltage level range of the modulation scheme. In other words, to support the described reduction in interference between the idle state and subsequent information transfer, the preamble voltage may be any voltage level between the voltage level of the idle state and the voltage level of the modulation scheme that is farthest from the voltage level of the idle state for subsequent information transfer, wherein such a preamble voltage will correspondingly cause a voltage swing reduction when transitioning from the idle state to the subsequent information transfer (e.g., in a single step or operation).

[0096] Timing diagram 400 also illustrates one or more voltage levels that may be used as bias voltages during post-code duration 450. Such voltage levels may be referred to as post-code voltages V post , which may refer to a voltage level of a post-code, a post-code symbol, a post-code sequence, or other intermediate bias of a signal path after information transfer and before a subsequent idle state. Although timing diagram 400 is illustrated as having equal pre-code and post-code voltages, in various examples, the post-code voltage may or may not be equal to the pre-code voltage (e.g., V post Can be equal to V pre or V post Different from V pre ). Although the example of timing diagram 400 includes both a preamble and a postamble as described herein, in some examples, system 300 or its operation may support or include one of a preamble prior to information transmission or a postamble after information transmission, in which case one of the preamble voltage or the postamble voltage and associated operations may be omitted.

[0097] In some examples, the post-code voltage may be higher than the lowest voltage level associated with the modulation scheme (eg, V post Can be higher than V mod,1 ), below the highest voltage level associated with the modulation scheme (e.g., V post Can be lower than V mod,3 ), or both (e.g., Vpost Available in V mod,1 With V mod,3 In some examples (not shown), the post-code voltage may be a midpoint voltage level (e.g., V post Can be equal to V mod,1 With V mod,3 In another example (not shown), when (e.g., according to a PAM4 modulation scheme) a set of four voltage levels {V mod,1a ,V mod,2a ,V mod,3a ,V mod,4a} modulation scheme on the signal path, V post Can be equal to V mod,1a With V mod,4a an average value of , which may not be included in the set of voltage levels associated with the modulation scheme.

[0098] Although the post-code voltage is illustrated as a voltage level different from the voltage level used in the modulation scheme, in some examples, the post-code voltage may be equal to one of the voltage levels included in the modulation scheme. For example, on a signal path using a modulation scheme that includes three voltage levels to convey information (which, as illustrated, may correspond to a PAM3 modulation scheme), the post-code voltage level may be equal to the middle voltage level of the modulation scheme (e.g., V post Can be equal to V mod,2 In another example (not shown), when (e.g., according to a PAM4 modulation scheme) a set of four voltage levels {V mod,1a ,V mod,2a ,V mod,3a ,V mod,4a}, the post-code voltage level may be equal to any of the intermediate voltage levels of the modulation scheme (e.g., V post Can be equal to V mod,2a or V mod,3a ), which may be based on a static configuration, a dynamic configuration, or an operating condition of the system 300, or a modulation of a particular information transmission (e.g., based at least in part on a voltage level of a last symbol of the information transmission).

[0099] Although the post-code voltage is illustrated as being within the voltage level range of the modulation scheme, in other examples (not shown), the post-code voltage may be outside the voltage level range of the modulation scheme and still support reduced interference as described herein, such as when the idle voltage following the information transfer is also outside the voltage level range of the modulation scheme. In other words, to support the described reduction in interference between the information transfer and the subsequent idle state, the post-code voltage may be any voltage level between the voltage level for the information transfer and the voltage level of the subsequent idle state of the modulation scheme that is furthest from the voltage level of the subsequent idle state, wherein such a post-code voltage will correspondingly cause a voltage swing reduction when transitioning from the information transfer to the subsequent idle state (e.g., in a single step or operation).

[0100] The timing diagram 400 illustrates various transitions from one of the configuration voltage levels to another, which are described relative to a particular order of operations of the system 300. Although described with reference to a particular time, such a time or associated operation may be related to one or both of the host device 310 or the memory device 330, and may correspond to one of the devices having voltage control or bias authority over the signal path at the time. In various examples, the one of the devices having voltage control or bias authority over the signal path may be the same device for each of the operations of the timing diagram 400, or different devices may have voltage control or bias authority at different operations of the timing diagram 400, including the examples described at each of the operations of the timing diagram 400.

[0101] At 401, system 300 may be in an idle state. Thus, depending on whether host device 310 or memory device 330 has voltage control or bias authority for the signal path at 401 (e.g., based on the configuration of bias authority during the idle state), the signal path may be biased to an idle voltage V idle , which can be controlled by the host device 310 or the memory device 330.

[0102] At 402, system 300 may initiate biasing of a signal path to a middle or intermediate bias voltage level (eg, V pre), the intermediate or mid bias voltage level may be associated with a preamble (e.g., a preamble voltage level, a preamble symbol). For example, the operation of 402 may illustrate prepending a preamble (e.g., to burst 430), or changing a voltage of a signal path with a preamble. In some examples, the operation of 402 may be triggered based at least in part on an access operation (e.g., a read operation of the memory device 330, a write operation of the memory device, a rewrite operation of the memory device, a refresh operation of the memory device), and thus may be based on or otherwise accompanied by an access command. In some examples, the bias initiated at 402 may be associated with a preamble duration 410 between the start bias and the start of information transfer (e.g., starting burst 430 at 403).

[0103] In the example of timing diagram 400 illustrating aspects of a read operation, memory device 330 may receive a read command (e.g., through a control channel, via a CA channel), and memory device 330 may initiate or otherwise control biasing of a signal path to V at 402 based at least in part on receiving the read command. pre (e.g., appending a preamble voltage level, symbol, or sequence to a read information transmission). In such an example, the memory device 330 may have bias permissions for the signal path, which may be based on or otherwise accompanied by command signaling from the host device 310 (e.g., determination of bias permissions by the memory device 330 based on a read command from the host device 310). In various examples, the host device 310 may ignore the bias initiated at 402 (e.g., within the preamble duration 410), or the host device 310 may avoid decoding the bias initiated at 402, or the host device 310 may decode the bias initiated at 402 but understand that the bias is not part of the information associated with the read operation (e.g., based on an understanding of the preamble duration 410). In some examples, the host device 310 may switch to or maintain a higher receiver impedance (e.g., a higher impedance termination of the receiver 325) at 402, which may support greater power savings or efficiency than when a lower receiver impedance is configured during the preamble duration. In some examples of timing diagram 400 illustrating aspects of a read operation, such as when host device 310 maintains bias privileges from an idle state through operation at 402 and prior to burst 430, host device 310 may transmit a read command and may also initiate or otherwise control biasing of the signal path to V at 402. pre (eg, according to the predefined preamble duration 410).

[0104] In the example of timing diagram 400 illustrating aspects of a write operation, host device 310 may transmit a write command to memory device 330 (e.g., over a control channel, over a CA channel), and host device 310 may initiate or otherwise control biasing of a signal path to V based at least in part on the write command at 402. pre (e.g., appending a preamble voltage level, symbol, or sequence to a write information transfer). In such an example, the host device 310 may have bias authority for the signal path, which may be based on or otherwise accompanied by command signaling from the host device 310 (e.g., determination of bias authority by the host device 310 based on determining or transmitting a write command of the host device 310). In various examples, the memory device 330 may ignore the bias initiated at 402 (e.g., within the preamble duration 410), or the memory device 330 may avoid decoding the bias initiated at 402, or the memory device 330 may decode the bias initiated at 402 but understand that the bias is not part of the information associated with the write operation (e.g., based on an understanding of the preamble duration 410). In some examples, the memory device 330 may switch to or maintain a higher receiver impedance at 402 (e.g., a higher impedance termination of the receiver 345), which may support greater power savings or efficiency than when a lower receiver impedance is configured during the preamble duration.

[0105] At 403, the system 300 may initiate information transmission. For example, the system may communicate signaling via a signal path, wherein the signaling corresponds to modulation including using a signal having a voltage level set {V mod,1 ,V mod,2 ,V mod,3 Thus, at 403, depending on the information to be conveyed in the first modulation symbol of the information transmission (eg, depending on the value of the first modulation symbol starting at 403), the signal path may start from V pre Transition to V mod,1 、V mod,2 or V mod,3 one of the.

[0106] Since the signal path is biased to V as initiated at 402 pre The voltage swing associated with the operation of 403 may be smaller than the possible voltage swing that the system 300 would experience if the operation of 402 were omitted (e.g., due to the preamble). For example, when the first modulation symbol of the information transmission corresponds to the voltage level farthest from the idle voltage (e.g., V mod,1 ), the voltage swing associated with the operation of 403 can be equal to V when the operation of 402 is omitted. idle -V mod,1 same high, but can be reduced to V when including 402 operation pre-V mod,1 Therefore, by including the operation of 402, interference associated with the operation of 403 may be reduced.

[0107] In some examples, the means for biasing at 403 may be based on the type of access operation associated with the information to be communicated. For example, where timing diagram 400 illustrates aspects of a read operation, memory device 330 may initiate or otherwise control biasing of the signal path at 403 to one of the voltage levels of the modulation scheme based on information associated with the read operation to be carried in the first modulation symbol (e.g., when memory device 330 has voltage control or bias authority for the signal path to communicate information associated with the read command). Thus, host device 310 may detect the biasing to demodulate or otherwise decode the signaling to receive the information at some time after 403 (e.g., before initiating subsequent biasing at 404). In another example, where timing diagram 400 illustrates aspects of a write operation, host device 310 may initiate or otherwise control biasing of the signal path at 403 to one of the voltage levels of the modulation scheme based on information associated with the write operation to be carried in the first modulation symbol (e.g., when host device 310 has voltage control or bias authority for the signal path to communicate information associated with the write command). Thus, memory device 330 may detect the biasing to demodulate or otherwise decode the signaling to receive the information at some time after 403 (e.g., before initiating subsequent biasing at 404).

[0108] In some examples, the biasing at 403 may be associated with starting a first modulation symbol at 403 and starting a subsequent modulation symbol (eg, starting biasing the signal path to a voltage set {V mod,1 ,V mod,2 ,V mod,3}). In some examples, the symbol duration 420 may be associated with a transition of a clock signal (e.g., when communicated over a WCK channel), and the symbol duration 420 may correspond to a duration between rising edges of the clock signal or a duration between falling edges of the clock signal (e.g., according to single data rate timing), or the symbol duration 420 may correspond to a duration between a rising edge and a falling edge of the clock signal or a falling edge and a rising edge of the clock signal (e.g., according to double data rate timing). In some examples, the information of the access command may be associated with a set of modulation symbols, and thus may be associated with a set of symbol durations 420. For example, the timing diagram 400 may illustrate an example of information transmission associated with four modulation symbols (e.g., a first modulation symbol starting at 403, a second modulation symbol starting at 404, a third modulation symbol starting at 405, and a fourth modulation symbol starting at 406). In other examples, information transmission in accordance with the described techniques can be associated with a single modulation symbol or symbol duration 420 or any other number of modulation symbols or symbol durations 420 .

[0109] In some examples, information communicated for an access command may be arranged according to one or more bursts including a plurality of modulation symbols, such as a burst 430 including four modulation symbols and thus corresponding to a burst duration 440 including four symbol durations 420. Although the burst 430 is illustrated as including four modulation symbols (e.g., four symbol durations 420), the burst 430 may include any number of modulation symbols or symbol durations 420 (e.g., two-symbol bursts, eight-symbol bursts, sixteen-symbol bursts, single-symbol bursts). Furthermore, although the timing diagram 400 is illustrated with a single burst 430 after the preamble of 402 (e.g., before the postamble), various access operations according to the described biasing of the intermediate voltage level prior to information transfer may be associated with any number of bursts 430 (e.g., one or more burst durations 440).

[0110] At 407, and after or at the end of the burst 430, the system 300 may initiate biasing the signal path to an intermediate or mid-bias voltage level (eg, V post ), the intermediate or mid bias voltage level may be associated with a post-code. For example, the operation of 407 may illustrate appending a post-code (e.g., to burst 430), or changing a voltage of a signal path with a post-code. In various examples, the operation of 407 may be initiated by the host device 310 or the memory device 330. In some examples, the bias initiated at 407 may be associated with a post-code duration 450 between the starting bias and initiating a transition to an idle state (e.g., at 408).

[0111] In the example where timing diagram 400 illustrates aspects of a read operation, memory device 330 may initiate or otherwise control biasing of a signal path to V at 407 based at least in part on completing burst 430 (e.g., appending a post-code voltage level, symbol, or sequence to the end of burst 430). post In such an example, the memory device 330 can maintain bias permissions for the signal path, which can be based on or otherwise accompanied by command signaling from the host device 310 (e.g., a determination of bias permissions by the memory device 330 based on a read command from the host device 310). In various examples, the host device 310 can ignore the bias starting at 407 (e.g., within the post-code duration 450, based on the host device 310's understanding that the burst 430 has completed, such as an understanding of the amount of information associated with the read command or an understanding of the burst duration 440), or the host device 310 can avoid decoding the bias starting at 407, or the host device 310 can decode the bias starting at 407 but understand that the bias is not part of the information associated with the read operation (e.g., based on the understanding of the post-code duration 450 and the understanding that the burst 430 has completed). In some examples, host device 310 may switch to or maintain a higher receiver impedance (e.g., a higher impedance termination of receiver 325) at 407, which may support greater power savings or efficiency than when a lower receiver impedance is configured during the postamble duration. In some examples where timing diagram 400 illustrates aspects of a read operation, host device 310 may know when burst 430 will end, and thus host device 310 may initiate or otherwise control biasing of the signal path to V at 407 in an example where timing diagram 400 illustrates a read command. post , such as when the host device 310 takes over bias authority after the burst 430 and before or through the idle state.

[0112] In the example where timing diagram 400 illustrates aspects of a write operation, host device 310 may initiate or otherwise control biasing of the signal path to V at 407 based at least in part on completing burst 430 (e.g., appending a post-code voltage level, symbol, or sequence to the end of burst 430). postIn such an example, the host device 310 can maintain bias permissions for the signal path, which can be based on or otherwise accompanied by command signaling from the host device 310 (e.g., a determination of bias permissions by the host device 310 based on determining or transmitting a write command of the host device 310). In various examples, the memory device 330 can ignore the bias starting at 407 (e.g., within the post-code duration 450, based on an understanding of the memory device 330 that a burst 430 has completed, such as an understanding of the amount of information associated with the write command or an understanding of the burst duration 440), or the memory device 330 can avoid decoding the bias starting at 407, or the memory device 330 can decode the bias starting at 407, but with an understanding that the bias is not part of the information associated with the write operation (e.g., based on an understanding of the post-code duration 450 and an understanding that the burst 430 has completed). In some examples, memory device 330 may switch to or maintain a higher receiver impedance (eg, a higher impedance termination of receiver 345) at 407, which may support greater power savings or efficiency than when a lower receiver impedance is configured during the postamble duration.

[0113] At 408, and before biasing the signal path to an intermediate voltage V post Thereafter, system 300 may initiate a transition to an idle state, which may include initiating biasing of the signal path to an idle voltage (eg, V idle ). Since the signal path is biased to V as initiated at 407 post (eg, due to the post-code), the voltage swing associated with the operation of 408 (eg, V idle –V post ) may be less than the possible voltage swing that system 300 would experience if operation 407 were omitted (e.g., where the voltage swing associated with operation 408 may be greater than V depending on the final modulation symbol of burst 430). idle -V mod,1 Therefore, by including the operation of 407, interference associated with the operation of 408 can be reduced.

[0114] At 409, the signal path may have reached an idle voltage V idle , and thus the system 300 can return to an idle state.

[0115] Although the timing diagram 400 illustrates an example of the system 300 returning to an idle state (e.g., at 409), in some examples, the system 300 may not return to the idle state after the burst 430 or after the post-code duration 450. For example, when another access command of the system 300 is determined or communicated, another burst 430 associated with the other access command may be communicated without the system 300 returning to the idle state (e.g., omitting the operations of 408 and 409). In various examples, the other burst 430 may or may not be associated with the same type of access command. For example, a burst 430 associated with a read command may be followed by another burst 430 associated with a read command, or by another burst 430 associated with a write command. In another example, a burst 430 associated with a write command may be followed by another burst 430 associated with a write command, or by another burst 430 associated with a read command.

[0116] In various examples, a burst 430 may be immediately followed by another burst 430, or a burst 430 may be followed by another burst 430 with an intermediate offset between bursts 430, which may include a preamble, a postamble, or both. In some examples, the system 300 may be configured to omit the preamble duration 410, the postamble duration 450, or both when another access command has been issued or is otherwise pending (e.g., before the idle voltage offset is initiated at 408, before the postamble offset is initiated at 407). In other examples, the preamble duration 410, the postamble duration 450, or both may be statically configured to accompany the burst 430, in which case the preamble duration 410, the postamble duration 450, or both may not be omitted.

[0117] Although the operations of 401 to 409 are illustrated at specific intervals along the horizontal axis, the timing of the operations of the timing diagram 400 is for illustrative purposes and is not intended to indicate any limitation on a specific relative duration between one operation and another operation. For example, the preamble duration 410 or the postamble duration 450 may have different relative durations when compared to or associated with the symbol duration 420 or the burst duration 440. In some examples, one or both of the preamble duration 410 or the postamble duration 450 may be equal to the burst duration 440 so that the signal path is biased to an intermediate voltage for a duration equal to the burst duration 440, or otherwise controlled to be biased to an intermediate voltage. In some examples, one or both of the preamble duration 410 or the postamble duration 450 may be less than the burst duration 440 so that the signal path is biased to an intermediate voltage for a duration less than the burst duration 440, or otherwise controlled to be biased to an intermediate voltage. For example, one or both of the preamble duration 410 or the postamble duration 450 may be equal to the symbol duration 420 such that the signal path is biased, or otherwise controlled to be biased, to an intermediate voltage for a duration equal to the symbol duration 420 .

[0118] Furthermore, although the bias initiated at 402 (eg, preamble) is illustrated as transitioning to a single voltage level (eg, a single V pre ), but other examples according to the present disclosure may include more than one intermediate voltage (e.g., more than one V pre ). For example, the bias initiated at 402 may include a first bias to a first preamble voltage level and a second bias to a second preamble voltage level, wherein the first preamble voltage may be between an idle voltage and a second preamble voltage (e.g., according to a stepped preamble having two or more steps). In some examples, the corresponding preamble duration 410 may include a plurality of shorter durations (e.g., a plurality of durations each equal to the symbol duration 420), and each bias of the stepped preamble may be performed according to a respective one of the shorter durations. In some examples, including single-step preambles or multi-step preambles, the configuration may be rate sensitive, which may include a static configuration or a dynamic configuration based at least in part on an operating rate of the system 300 (e.g., clock rate, symbol duration 420).

[0119] Likewise, although the bias starting at 407 (eg, post-code) is illustrated as transitioning to a single voltage level (eg, a single V post ), but other examples according to the present disclosure may include more than one intermediate voltage (e.g., more than one V post). For example, the bias initiated at 407 may include a first bias to a first post-code voltage level and a second bias to a second post-code voltage level, wherein the second post-code voltage may be between the first post-code voltage level and an idle voltage level (e.g., according to a stepped post-code having two or more steps). In some examples, the corresponding post-code duration 450 may include a plurality of shorter durations (e.g., a plurality of durations each equal to the symbol duration 420), and each bias of the stepped post-code may be performed according to a respective one of the shorter durations. In some examples, including a single-step post-code or a multi-step post-code, the configuration may be rate sensitive, which may include a static configuration or a dynamic configuration based at least in part on an operating rate of the system 300 (e.g., a clock rate, a symbol duration 420).

[0120] Furthermore, although the timing diagram 400 is described with reference to a single signal path, the described techniques may be performed for multiple signal paths in accordance with the present disclosure. For example, when information is passed through a channel associated with multiple signal paths (e.g., a multipath DQ channel), each of the signal paths may be associated with the same or different preamble or postamble bias (e.g., the same or different timing for initiating preamble or postamble operation, the same or different voltage level or set of voltage levels for the preamble or postamble).

[0121] In some instances, each of the signal paths of a multipath channel may have a preamble that starts at the same time (e.g., the operation of 402 associated with one signal path may conform to the operation of 402 associated with each of the other signal paths). In other instances, each of the signal paths of a multipath channel may have a preamble that starts at a different time (e.g., the operation of 402 associated with one signal path may not conform to the operation of 402 associated with any of the other signal paths). In other words, in some instances, the preambles of a multipath channel may be stepped or sequenced in time before a burst 430 (e.g., according to a sequence of durations equal to the symbol duration 420, such as when the preamble duration 410 is equal to the burst duration 440 of the set including the symbol duration 420). However, in some instances, a burst 430 may be initiated simultaneously on each of the signal paths of the channel. Additionally or alternatively, a set of signal paths of a multipath channel may each be associated with the same preamble voltage or set of stepped preamble voltages, or a set of signal paths of a multipath channel may not each be associated with the same preamble voltage or set of stepped preamble voltages. Such instances of temporally sequencing preambles for different signal paths or using different preamble voltages for different signal paths may further reduce interference from different signal paths when compared to conditions where the preambles are started at the same time or with the same voltage being used for different signal paths.

[0122] In some instances, each of the signal paths of a multipath channel may have a postamble that starts at the same time (e.g., the operation of 407 associated with one signal path may coincide with the operation of 407 associated with each of the other signal paths). In other instances, each of the signal paths of a multipath channel may have a postamble that starts at a different time (e.g., the operation of 407 associated with one signal path may not coincide with the operation of 407 associated with any of the other signal paths). In other words, in some instances, the postambles of a multipath channel may be stepped or sequenced in time after a burst 430 (e.g., according to a sequence of durations equal to the symbol duration 420, such as when the postamble duration 450 is equal to the burst duration 440 of the set including the symbol duration 420), but the burst 430 may be completed simultaneously on each of the signal paths of the channel. Additionally or alternatively, a set of signal paths of a multipath channel may be associated with the same postamble voltage or set of stepped postamble voltages, or a set of signal paths of a multipath channel may not each be associated with the same postamble voltage or set of stepped postamble voltages. Such instances of temporally sequencing post-codes for different signal paths or using different post-code voltages for different signal paths may further reduce interference from different signal paths when compared to conditions where the post-codes are initiated at the same time or with the same voltage being used for different signal paths.

[0123] Although timing diagram 400 is described with reference to host device 310 and memory device 330, the described techniques may be applicable to other electronic systems configured to bias signal paths in a manner that reduces interference with other signals during transitions to and from an idle state. For example, components or devices of various electronic systems that support information transfer according to modulation symbols may be configured to bias the signal path to a voltage level between an idle state and a subsequent information transfer or between an information transfer and a subsequent idle state, the voltage level being between the voltage levels of the modulation scheme used to convey the information (e.g., a mid-bias voltage). Thus, the described techniques may be generally applied in systems such as graphics cards, vehicle control systems such as advanced driver assistance systems (ADAS), networking equipment, and other electronic systems that support modulated information transfer, and are configured to support transitions between operating modes, such as transitions to and from an idle state.

[0124] Figure 5 A block diagram 500 is shown of a memory device 505 supporting signal path biasing in a memory system according to examples as disclosed herein. The memory device 505 may be a memory device as described in reference Figures 1 to 4An example of aspects of a memory device is described. The memory device 505 may include an access command receiver 510, a signal path driver 515, and a signal transmitter 520. Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

[0125] The access command receiver 510 may be configured to receive an access command associated with information to be transmitted to the host device via the signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. In some cases, the access command includes a read command received via the control channel.

[0126] The signal path driver 515 may be configured to bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command. In some instances, the signal path driver 515 may bias the signal path to a fifth voltage level between the first voltage level and the third voltage level after transmitting the signal. In some cases, the fourth voltage level is equal to the fifth voltage level. In some instances, the signal path driver 515 may bias the signal path to a sixth voltage level between the fifth voltage level and the termination voltage level after biasing the signal path to the fifth voltage level.

[0127] In some examples, the signal path driver 515 may be configured to bias the signal path to a seventh voltage level between the termination voltage level and the fourth voltage level before biasing the signal path to the fourth voltage level. In some examples, biasing the signal path to the fourth voltage level includes a preamble (e.g., pre-adding a preamble, applying a preamble voltage), and biasing the signal path to the fifth voltage level includes a postamble (e.g., appending a postamble, applying a postamble voltage). In some cases, the fourth voltage level is equal to the second voltage level of the modulation scheme. In some cases, the fourth voltage level is different from the voltage level of the modulation scheme used to convey information.

[0128] In some cases, the fourth voltage level is a midpoint voltage level between the first voltage level and the third voltage level. In some cases, the signal path is biased to the fourth voltage level for a duration equal to at least one burst duration. In some cases, the signal path is biased to the fourth voltage level for a duration shorter than at least one burst duration. In some cases, the duration is equal to one symbol duration.

[0129] The signal transmitter 520 may be configured to transmit a signal modulated using a modulation scheme to include information through the signal path after biasing the signal path to the fourth voltage level. In some cases, the transmission signal lasts for at least one burst duration including a symbol duration set. In some cases, the modulation scheme is a PAM3 modulation scheme including a first voltage level, a second voltage level, and a third voltage level. In some cases, the modulation scheme is a PAM4 modulation scheme including a first voltage level, a second voltage level, a third voltage level, and an eighth voltage level between the second voltage level and the third voltage level.

[0130] Figure 6 A block diagram 600 is shown of a host device 605 supporting signal path biasing in a memory system according to examples as disclosed herein. The host device 605 may be a Figures 1 to 4 An example of aspects of a host device is described. The host device 605 may include an access command transmitter 610, a signal path driver 615, and a signal transmitter 620. Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

[0131] The access command transmitter 610 may be configured to transmit an access command associated with information to be transmitted to the memory device via the signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. In some cases, the access command includes a write command transmitted via the control channel.

[0132] The signal path driver 615 may bias the signal path to a fourth voltage level between the first voltage level and the third voltage level by the host device based on the access command. In some examples, the signal path driver 615 may bias the signal path to a fifth voltage level that is higher than the first voltage level of the modulation scheme and lower than the third voltage level of the modulation scheme after transmitting the signal. In some examples, the signal path driver 615 may bias the signal path to a sixth voltage level between the fifth voltage level and the termination voltage level after biasing the signal path to the fifth voltage level.

[0133] In some examples, the signal path driver 615 may bias the signal path to a seventh voltage level between the termination voltage level and the fourth voltage level before biasing the signal path to the fourth voltage level. In some examples, biasing the signal path to the fourth voltage level includes a preamble (e.g., pre-adding a preamble, applying a preamble voltage), and biasing the signal path to the fifth voltage level includes a postamble (e.g., appending a postamble, applying a postamble voltage). In some cases, the fourth voltage level is equal to the fifth voltage level. In some cases, the fourth voltage level is equal to the second voltage level of the modulation scheme.

[0134] In some cases, the fourth voltage level is different from the voltage level of the modulation scheme used to convey information. In some cases, the fourth voltage level is a midpoint voltage level between the first voltage level and the third voltage level. In some cases, the signal path is biased to the fourth voltage level for a duration equal to at least one burst duration. In some cases, the signal path is biased to the fourth voltage level for a duration shorter than at least one burst duration. In some cases, the duration is equal to one symbol duration.

[0135] The signal transmitter 620 may transmit a signal modulated using a modulation scheme to include information through the signal path after biasing the signal path to the fourth voltage level. In some cases, the transmission signal lasts for at least one burst duration including a symbol duration set. In some cases, the modulation scheme is a PAM3 modulation scheme including a first voltage level, a second voltage level, and a third voltage level. In some cases, the modulation scheme is a PAM4 modulation scheme including a first voltage level, a second voltage level, a third voltage level, and an eighth voltage level that is higher than the second voltage level and lower than the third voltage level.

[0136] Figure 7 A flowchart illustrating one or more methods 700 of supporting signal path biasing in a memory system according to examples as disclosed herein is shown. The operations of the method 700 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory device or components thereof as described herein. Figure 5 The memory device described herein performs the functions described herein. In some examples, the memory device may execute instruction sets to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0137] At 705, the memory device may receive an access command associated with information to be transmitted to the host device via a signal path using a modulation scheme including three or more voltage levels, including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The operation of 705 may be performed according to the methods described herein. In some examples, the access command may be received by a memory device as described in reference to Figure 5 Aspects of the operation of the access command receiver 705 are described.

[0138] At 710, the memory device may bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command. The operation of 710 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to Figure 5 Aspects of the operation of the signal path driver 710 are described.

[0139] At 715, the memory device may transmit a signal modulated using the modulation scheme to include information through the signal path after biasing the signal path to the fourth voltage level. The operation of 715 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to Figure 5 Aspects of the operation of the signal transmitter 715 are described.

[0140] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an access command associated with information to be transmitted to a host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing the signal path to a fourth voltage level between the first voltage level and the third voltage level by a memory device based on the access command; and transmitting through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0141] Some examples of the methods 700 and apparatus described herein may further include operations, features, means, or instructions for the following operations: after transmitting the signal, biasing the signal path to a fifth voltage level between the first voltage level and the third voltage level. In some examples of the methods 700 and apparatus described herein, the fourth voltage level and the fifth voltage level may be equal.

[0142] Some examples of the methods 700 and apparatus described herein may further include operations, features, means, or instructions for: after biasing the signal path to the fifth voltage level, biasing the signal path to a sixth voltage level that may be between the fifth voltage level and a termination voltage level (e.g., for a host device, for a memory device, for a signal path). In some examples of the methods 700 and apparatus described herein, biasing the signal path to the fourth voltage level includes a preamble (e.g., prepending a preamble, applying a preamble voltage), and biasing the signal path to the fifth voltage level includes a postamble (e.g., appending a postamble, applying a postamble voltage).

[0143] Some examples of the methods 700 and apparatus described herein may further include operations, features, means, or instructions for: biasing the signal path to a seventh voltage level that may be between a termination voltage level (e.g., for a host device, for a memory device, for a signal path) and the fourth voltage level before biasing the signal path to the fourth voltage level. In some examples of the methods 700 and apparatus described herein, the fourth voltage level may be equal to the second voltage level of the modulation scheme. In some examples of the methods 700 and apparatus described herein, the fourth voltage level may be different from a voltage level of the modulation scheme used to convey the information.

[0144] In some examples of the methods 700 and devices described herein, the fourth voltage level may be a midpoint voltage level between the first voltage level and the third voltage level. In some examples of the methods 700 and devices described herein, the signal may be transmitted for at least one burst duration comprising a set of symbol durations, and the signal path may be biased to the fourth voltage level for a duration that may be equal to the at least one burst duration. In some examples of the methods 700 and devices described herein, the signal may be transmitted for at least one burst duration comprising a set of symbol durations, and the signal path may be biased to the fourth voltage level for a duration that may be shorter than the at least one burst duration. In some examples of the methods 700 and devices described herein, the duration may be equal to one symbol duration.

[0145] In some examples of the methods 700 and devices described herein, the access command includes a read command that can be received via a control channel (e.g., a CA channel). In some examples of the methods 700 and devices described herein, the modulation scheme can be a PAM3 modulation scheme including the first voltage level, the second voltage level, and the third voltage level. In some examples of the methods 700 and devices described herein, the modulation scheme can be a PAM4 modulation scheme including the first voltage level, the second voltage level, the third voltage level, and an eighth voltage level between the second voltage level and the third voltage level.

[0146] Figure 8 A flow chart illustrating one or more methods 800 of supporting signal path biasing in a memory system according to examples as disclosed herein is shown. The operations of the method 800 may be implemented by a host device or components thereof as described herein. For example, the operations of the method 800 may be implemented by a host device or components thereof as described herein. Figure 6The host device described herein performs the functions described herein. In some examples, the host device may execute a set of instructions to control functional elements of the host device to perform the functions described herein. Additionally or alternatively, the host device may use dedicated hardware to perform aspects of the functions described herein.

[0147] At 805, the host device may transmit an access command associated with information to be transmitted to the memory device via a signal path using a modulation scheme including three or more voltage levels, including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The operation of 805 may be performed according to the methods described herein. In some examples, the access command may be transmitted by a host device as described in reference to Figure 6 Aspects of the operation of the access command transmitter 805 are described.

[0148] At 810, the host device may bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based on the access command. The operation of 810 may be performed according to the methods described herein. In some examples, the operation may be performed as described in reference to Figure 6 Aspects of the operation of the signal path driver 810 are described.

[0149] At 815, the host device may transmit a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level. The operation of 815 may be performed according to the method described herein. In some examples, the signal path may be transmitted by the host device as described in reference to Figure 6 Aspects of the operation of the signal transmitter 815 are described.

[0150] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting an access command associated with information to be transmitted to a memory device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing the signal path to a fourth voltage level between the first voltage level and the third voltage level by a host device based on the access command; and transmitting a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level.

[0151] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for biasing the signal path to a fifth voltage level that is higher than the first voltage level of the modulation scheme and lower than the third voltage level of the modulation scheme after transmitting the signal.

[0152] In some examples of the methods 800 and apparatus described herein, the fourth voltage level and the fifth voltage level may be equal. Some examples of the methods 800 and apparatus described herein may further include operations, features, means, or instructions for the following operations: after biasing the signal path to the fifth voltage level, biasing the signal path to a sixth voltage level that may be between the fifth voltage level and a termination voltage level (e.g., for a host device, for a memory device, for a signal path).

[0153] In some examples of the method 800 and apparatus described herein, biasing the signal path to the fourth voltage level includes a preamble (e.g., prepending a preamble, applying a preamble voltage), and biasing the signal path to the fifth voltage level includes a postamble (e.g., appending a postamble, applying a postamble voltage). Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for the following operations: before biasing the signal path to the fourth voltage level, biasing the signal path to a seventh voltage level that may be between a termination voltage level (e.g., for a host device, for a memory device, for a signal path) and the fourth voltage level.

[0154] In some examples of the methods 800 and devices described herein, the fourth voltage level may be equal to the second voltage level of the modulation scheme. In some examples of the methods 800 and devices described herein, the fourth voltage level may be different from the voltage level of the modulation scheme used to convey the information. In some examples of the methods 800 and devices described herein, the fourth voltage level may be a midpoint voltage level between the first voltage level and the third voltage level.

[0155] In some examples of the methods 800 and apparatus described herein, the signal may be transmitted for at least one burst duration comprising a set of symbol durations, and the signal path may be biased to the fourth voltage level for a duration that may be equal to the at least one burst duration. In some examples of the methods 800 and apparatus described herein, the signal may be transmitted for at least one burst duration comprising a set of symbol durations, and the signal path may be biased to the fourth voltage level for a duration that may be shorter than the at least one burst duration. In some examples of the methods 800 and apparatus described herein, the duration may be equal to one symbol duration. In some examples of the methods 800 and apparatus described herein, the access command comprises a write command that may be transmitted via a control channel.

[0156] In some examples of the methods 800 and devices described herein, the modulation scheme may be a PAM3 modulation scheme including the first voltage level, the second voltage level, and the third voltage level. In some examples of the methods 800 and devices described herein, the modulation scheme may be a PAM4 modulation scheme including the first voltage level, the second voltage level, the third voltage level, and an eighth voltage level that is higher than the second voltage level and lower than the third voltage level.

[0157] A memory device is described. In some examples, the memory device may include a receiver configured to transmit an access command associated with information to be transmitted to a host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The apparatus may also include a driver configured to bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based at least in part on the access command, and transmit a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level.

[0158] In some examples, the driver may be configured to bias the signal path to a fifth voltage level between the first voltage level and the third voltage level after transmitting the signal. In some examples, biasing the signal path to the fourth voltage level includes prepending a preamble, and biasing the signal path to the fifth voltage level includes appending a postamble. In some examples, the driver may be configured to bias the signal path to a seventh voltage level between a termination voltage level for the signal path and the fourth voltage level before biasing the signal path to the fourth voltage level.

[0159] A host device is described. In some examples, the host device may include a transmitter configured to transmit an access command associated with information to be transmitted to a memory device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. The host device may include a driver configured to bias the signal path to a fourth voltage level between the first voltage level and the third voltage level based at least in part on the access command, and transmit a signal modulated using the modulation scheme to include the information through the signal path after biasing the signal path to the fourth voltage level.

[0160] In some examples, the driver may be configured to bias the signal path to a fifth voltage level between the first voltage level and the third voltage level after transmitting the signal.

[0161] A system is described. In some examples, the system may include a memory device and a host device coupled to the memory device. The system may be configured to: communicate a read command associated with information to be communicated from the memory device to the host device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; bias the signal path to a fourth voltage level between the first voltage level and the third voltage level; and communicate through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0162] A system is described. In some examples, the system may include a memory device and a host device coupled to the memory device. The system may be configured to: communicate a write command associated with information to be communicated from the host device to the memory device through a signal path using a modulation scheme including three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; bias the signal path to a fourth voltage level between the first voltage level and the third voltage level; and communicate through the signal path a signal modulated using the modulation scheme to include the information after biasing the signal path to the fourth voltage level.

[0163] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods described may be combined.

[0164] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have various bit widths.

[0165] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of the virtual ground can temporarily fluctuate and return to approximately 0V in a stable state. Virtual ground can be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other embodiments are also possible. "Virtual ground" or "virtual ground" means connecting to approximately 0V.

[0166] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between the components that are electronically connected with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0167] The term "coupled" refers to a condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between the components through a conductive path, to a closed circuit relationship between the components, in which signals are able to communicate between the components through the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0168] The term "isolation" refers to a relationship between components where a signal is currently unable to flow between the components. If an open circuit exists between the components, the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, the controller implements the following changes: a signal is prevented from flowing between the components using a conductive path that previously permitted the signal to flow.

[0169] As used herein, the term "substantially" means that the modified property (eg, a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to achieve the advantage of the property.

[0170] As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, lead, conductive line, conductive layer, or the like that provides an electrically conductive path between elements or components of a memory array.

[0171] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components via activation of a single intermediate component between the two components in question. For example, a first component shorted to a second component may exchange signals with the second component when a switch between the two components is closed. Thus, shorting may be a dynamic operation that enables charge flow between components (or lines) in electronic communication.

[0172] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0173] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carrier is a signal), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carrier is a hole), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0174] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The specific implementation includes specific details that provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0175] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0176] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0177] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0178] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including distribution so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of"), "or" indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as a reference to a closed conditional set. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0179] Computer-readable media include both non-transitory computer storage media and communication media, including any media that helps to transfer a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory medium that can be used to carry or store the required program code means in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0180] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving an access command associated with information to be transmitted to a host device via a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing, by a memory device based at least in part on the access command, the signal path from a termination voltage level to a fourth voltage level between the first voltage level and the third voltage level; as well as A signal modulated using the modulation scheme to include the information is transmitted through the signal path after biasing the signal path to the fourth voltage level.

2. The method according to claim 1, further comprising: After transmitting the signal, the signal path is biased to a fifth voltage level between the first voltage level and the third voltage level. The method of claim 2 , wherein the fourth voltage level is equal to the fifth voltage level.

4. The method according to claim 2, further comprising: After biasing the signal path to the fifth voltage level, biasing the signal path to a sixth voltage level between the fifth voltage level and the termination voltage level. 5 . The method of claim 2 , wherein biasing the signal path to the fourth voltage level comprises prepending a preamble, and biasing the signal path to the fifth voltage level comprises appending a postamble.

6. The method according to claim 1, further comprising: Prior to biasing the signal path to the fourth voltage level, the signal path is biased to a seventh voltage level between the termination voltage level and the fourth voltage level. The method of claim 1 , wherein the fourth voltage level is equal to the second voltage level of the modulation scheme.

8. The method of claim 1, wherein the fourth voltage level is different than a voltage level of the modulation scheme used to convey the information. 9 . The method of claim 1 , wherein the fourth voltage level is a midpoint voltage level between the first voltage level and the third voltage level.

10. The method of claim 1, wherein: transmitting the signal for at least one burst duration comprising a plurality of symbol durations; and The signal path is biased to the fourth voltage level for a duration equal to the at least one burst duration.

11. The method according to claim 1, wherein: transmitting the signal for at least one burst duration comprising a plurality of symbol durations; and The signal path is biased to the fourth voltage level for a duration shorter than the at least one burst duration. The method according to claim 11 , wherein the duration is equal to one symbol duration.

13. The method of claim 1, wherein the access command comprises a read command received over a control channel. 14 . The method of claim 1 , wherein the modulation scheme is a PAM3 modulation scheme including the first voltage level, the second voltage level, and the third voltage level. 15 . The method of claim 1 , wherein the modulation scheme is a PAM4 modulation scheme including the first voltage level, the second voltage level, the third voltage level, and an eighth voltage level between the second voltage level and the third voltage level.

16. A memory device comprising: a receiver configured to receive an access command associated with information to be transmitted to a host device via a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; as well as The driver is configured to: biasing the signal path from a termination voltage level to a fourth voltage level between the first voltage level and the third voltage level based at least in part on the access command; as well as A signal modulated using the modulation scheme to include the information is transmitted through the signal path after biasing the signal path to the fourth voltage level.

17. The memory device of claim 16, wherein the driver is further configured to: After transmitting the signal, the signal path is biased to a fifth voltage level between the first voltage level and the third voltage level.

18. The memory device of claim 17, wherein biasing the signal path to the fourth voltage level comprises prepending a preamble, and biasing the signal path to the fifth voltage level comprises appending a postamble.

19. The memory device of claim 16, wherein the driver is further configured to: Prior to biasing the signal path to the fourth voltage level, the signal path is biased to a seventh voltage level between the termination voltage level and the fourth voltage level.

20. A method comprising: transmitting an access command associated with information to be transmitted to a memory device via a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing, by a host device based at least in part on the access command, the signal path from a termination voltage level to a fourth voltage level between the first voltage level and the third voltage level; as well as A signal modulated using the modulation scheme to include the information is transmitted through the signal path after biasing the signal path to the fourth voltage level.

21. The method according to claim 20, further comprising: After transmitting the signal, the signal path is biased to a fifth voltage level that is higher than the first voltage level of the modulation scheme and lower than the third voltage level of the modulation scheme.

22. The method of claim 21, wherein the fourth voltage level is equal to the fifth voltage level.

23. The method of claim 21, further comprising: After biasing the signal path to the fifth voltage level, biasing the signal path to a sixth voltage level between the fifth voltage level and the termination voltage level.

24. The method of claim 21, wherein biasing the signal path to the fourth voltage level comprises prepending a preamble, and biasing the signal path to the fifth voltage level comprises appending a postamble.

25. The method of claim 20, further comprising: Prior to biasing the signal path to the fourth voltage level, the signal path is biased to a seventh voltage level between the termination voltage level and the fourth voltage level.

26. The method of claim 20, wherein the fourth voltage level is equal to the second voltage level of the modulation scheme.

27. The method of claim 20, wherein the fourth voltage level is different than a voltage level of the modulation scheme used to convey the information.

28. The method of claim 20, wherein the fourth voltage level is a midpoint voltage level between the first voltage level and the third voltage level.

29. The method of claim 20, wherein: transmitting the signal for at least one burst duration comprising a plurality of symbol durations; and The signal path is biased to the fourth voltage level for a duration equal to the at least one burst duration.

30. The method of claim 20, wherein: transmitting the signal for at least one burst duration comprising a plurality of symbol durations; and The signal path is biased to the fourth voltage level for a duration shorter than the at least one burst duration.

31. The method of claim 20, wherein the modulation scheme is a PAM4 modulation scheme including the first voltage level, the second voltage level, the third voltage level, and an eighth voltage level that is higher than the second voltage level and lower than the third voltage level.

32. A host device, comprising: a transmitter configured to transmit an access command associated with information to be transmitted to a memory device via a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; as well as The driver is configured to: biasing the signal path from a termination voltage level to a fourth voltage level between the first voltage level and the third voltage level based at least in part on the access command; as well as A signal modulated using the modulation scheme to include the information is transmitted through the signal path after biasing the signal path to the fourth voltage level.

33. The host device of claim 32, wherein the driver is further configured to: After transmitting the signal, the signal path is biased to a fifth voltage level between the first voltage level and the third voltage level.

34. A system comprising: Memory device; as well as a host device coupled to the memory device, The system is configured as follows: communicating a read command associated with information to be communicated from the memory device to the host device over a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing the signal path from a termination voltage level to a fourth voltage level between the first voltage level and the third voltage level; as well as A signal modulated using the modulation scheme to include the information is communicated through the signal path after biasing the signal path to the fourth voltage level.

35. A system comprising: Memory device; as well as a host device coupled to the memory device, The system is configured as follows: communicating a write command associated with information to be communicated from the host device to the memory device over a signal path using a modulation scheme comprising three or more voltage levels, the modulation scheme including a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level; biasing the signal from a termination voltage level path to a fourth voltage level between the first voltage level and the third voltage level; as well as A signal modulated using the modulation scheme to include the information is communicated through the signal path after biasing the signal path to the fourth voltage level.

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