Stacked structure, semiconductor device and electronic device including the same, and method for manufacturing stacked structure

Abstract

A laminated structure, a semiconductor device, a semiconductor apparatus, and an electronic apparatus including the same, and a method of manufacturing the laminated structure are provided. The laminated structure includes a substrate, and a thin film structure on the substrate, the thin film structure including a first antiferromagnetic layer parallel to the substrate, a second antiferromagnetic layer parallel to the substrate, and a ferroelectric layer parallel to the substrate, wherein the ferroelectric layer is between the first antiferromagnetic layer and the second antiferromagnetic layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0057184, filed on May 13, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a stacked structure, semiconductor devices, semiconductor equipment and electronic devices including the stacked structure, and a method for manufacturing a stacked structure. Background Technology

[0004] Ferroelectric materials are materials that possess ferroelectric properties and can maintain spontaneous polarization by aligning their internal electric dipole moments, even when no external electric field is applied. In other words, ferroelectric materials are materials in which the polarization intensity (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is restored to zero volts. Studies have been conducted to improve the performance of electronic devices by applying these ferroelectric properties to semiconductor devices. For example, research has been conducted on applying the characteristic that the polarization intensity value of a ferroelectric material exhibits hysteresis relative to voltage changes to memory devices.

[0005] Furthermore, recent research has revealed the possibility that if ferroelectrics possess negative capacitance in specific regions and are applied to transistors, the subthreshold swing could be reduced to below 60 mV / dec, which is the theoretical limit for conventional silicon-based transistors. For this reason, research is underway to utilize ferroelectrics in low-power logic devices.

[0006] Furthermore, since hafnium-based oxides have been found to possess ferroelectric properties, research has also been conducted on their use in semiconductor devices. Hafnium oxide is expected to be useful for the miniaturization of semiconductor devices because it is semiconductor process-friendly and exhibits ferroelectricity, even in very thin films with a thickness of a few nanometers. Summary of the Invention

[0007] One exemplary embodiment provides a stacked structure comprising ferroelectrics and antiferroelectrics and a method thereof for manufacturing the same.

[0008] Another embodiment provides a semiconductor device with improved hysteresis characteristics including the said stacked structure, as well as semiconductor devices and electronic devices including the same.

[0009] Another embodiment provides a stacked structure comprising layers of crystalline metal oxides having a concentration gradient of hafnium.

[0010] Other aspects will be set forth in part in the following description, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0011] According to one aspect, a stacked structure may include: a substrate; and a thin film structure on the substrate. The thin film structure may include: a first antiferroelectric layer parallel to the substrate, a second antiferroelectric layer parallel to the substrate, and a ferroelectric layer parallel to the substrate, the ferroelectric layer being between the first antiferroelectric layer and the second antiferroelectric layer. At least one of the first antiferroelectric layer and the second antiferroelectric layer may cover 80% or more of the surface of the ferroelectric layer. The first antiferroelectric layer and the second antiferroelectric layer may be in direct contact with the ferroelectric layer.

[0012] At least one of the ferroelectric layer, the first antiferroelectric layer, and the second antiferroelectric layer may independently include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium-zirconium oxide (Hf x Zr 1-x O2, 0 < x < 1).

[0013] The ferroelectric layer may include hafnium-zirconium oxide represented by Hf x Zr 1-x O2 (0.2 ≤ x < 1). Each of the first antiferroelectric layer and the second antiferroelectric layer may independently include zirconium oxide and at least one of hafnium-zirconium oxide represented by Hf x Zr 1-x O2 (0 < x < 0.2). The hafnium element content of the ferroelectric layer may be greater than the hafnium element content of one or more (two) of the first antiferroelectric layer and the second antiferroelectric layer. The molar ratio of the hafnium element of at least one of the first antiferroelectric layer and the second antiferroelectric layer to the hafnium element of the ferroelectric layer is in the range of 0 to 0.8.

[0014] The zirconium element content of the ferroelectric layer may be less than the zirconium element content of any one or more of the first antiferroelectric layer and the second antiferroelectric layer. The molar ratio of the zirconium element of the ferroelectric layer to the zirconium element of at least one of the first antiferroelectric layer and the second antiferroelectric layer is in the range of 0 to 1.

[0015] At least one of the ferroelectric layer, the first antiferroelectric layer, and the second antiferroelectric layer may include one or more dopant materials. The dopant materials may include at least one of C, Si, Ge, Sn, Pb, Al, Y, La, Gd, Mg, Ca, Sr, Ba, Ti, Zr, and Hf. The content of the dopant material in the ferroelectric layer may be less than the content of the dopant material in at least one of the first antiferroelectric layer and the second antiferroelectric layer. The ferroelectric layer may have a content of the dopant material in the range of 0 atomic % to 10 atomic % compared to the metal element of the substrate material; and each of the first antiferroelectric layer and the second antiferroelectric layer may independently have a content of the dopant material in the range of 4 atomic % to 20 atomic % compared to the metal element of the substrate material.

[0016] The ferroelectric layer may include an orthorhombic crystal structure, and the first antiferroelectric layer and the second antiferroelectric layer may include a tetragonal crystal structure.

[0017] The thickness of each of the first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer may independently be in the range of 0.1 nm to 10 nm. The thickness ratio of at least one of the first antiferroelectric layer and the second antiferroelectric layer to the ferroelectric layer may be greater than 0 and less than or equal to 10.

[0018] The thin film structure may further include a paraelectric layer. The paraelectric layer may be between the ferroelectric layer and at least one of the first antiferroelectric layer and the second antiferroelectric layer, and may include at least one of the following: aluminum oxide (Al2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and silicon dioxide (SiO2).

[0019] According to another aspect, a stacked structure may include: a substrate; and a crystalline metal oxide layer on the substrate. The crystalline metal oxide layer includes at least two of hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium-zirconium oxide (Hf x Zr 1-x O2, 0 < x < 1). The crystalline metal oxide layer includes a first surface layer portion, a central portion, and a second surface layer portion sequentially stacked in the thickness direction, where the hafnium element content of the central portion is greater than the hafnium element content of one or more of the first surface layer portion and the second surface layer portion.

[0020] The stacked structure and the semiconductor device may be manufactured by a manufacturing method including: forming a first amorphous layer on a substrate; forming a second amorphous layer on the substrate; forming a third amorphous layer on the substrate; annealing the first amorphous layer to form a first antiferroelectric layer; annealing the second amorphous layer to form a ferroelectric layer; and annealing the third amorphous layer to form a second antiferroelectric layer.

[0021] The first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer may be formed parallel to the substrate. The first amorphous layer, the second amorphous layer, and the third amorphous layer may be formed sequentially on the substrate in the thickness direction.

[0022] The stacked structure can be manufactured by simultaneously performing two or more of the following processes: annealing the first amorphous layer, annealing the second amorphous layer, and annealing the third amorphous layer.

[0023] The capacitor can be manufactured by further providing electrodes on the second antiferroelectric layer, wherein the substrate includes a conductor.

[0024] A field-effect transistor can be fabricated by further providing electrodes on the second antiferroelectric layer, wherein the substrate comprises a semiconductor material. Furthermore, source and drain electrodes can be further formed on the substrate. Attached Figure Description

[0025] The above and other aspects, features, and advantages of some embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 and 2 A schematic diagram illustrating a semiconductor device (field-effect transistor) according to some exemplary embodiments;

[0027] Figure 3A This is a schematic diagram illustrating the relationship between the electric field E applied to an example ferroelectric material and the polarization intensity P. Figure 3B This is a schematic diagram illustrating the relationship between charge Q and energy U in an example ferroelectric material.

[0028] Figure 4A This is a schematic diagram illustrating the relationship between the electric field E applied to the dielectric and the polarization intensity P. Figure 4B This is a schematic diagram showing the relationship between the charge Q and energy U of a dielectric.

[0029] Figure 5 A diagram illustrating, conceptually, the capacitance matching using ferroelectrics and dielectrics;

[0030] Figure 6A This is a schematic diagram illustrating the relationship between the electric field E applied to an antiferroelectric material and the polarization intensity P. Figure 6B This is a schematic diagram showing the relationship between the charge Q and energy U of an antiferroelectric material.

[0031] Figure 7 A diagram illustrating, conceptually, the use of ferroelectrics and antiferroelectrics for capacitance matching;

[0032] Figure 8 A schematic diagram illustrating a semiconductor device (field-effect transistor) according to an example embodiment;

[0033] Figure 9A and 9B A schematic diagram illustrating a semiconductor device (field-effect transistor) according to an example embodiment;

[0034] Figure 10A and 10B A schematic diagram illustrating a semiconductor device (field-effect transistor) according to an example embodiment;

[0035] Figure 11 A schematic diagram illustrating a semiconductor device (capacitor) according to an example embodiment;

[0036] Figure 12A Describe the circuit structure of a memory cell in a memory device that includes semiconductor devices and capacitors;

[0037] Figure 12B A schematic diagram illustrating a semiconductor device according to an example implementation;

[0038] Figure 12C The structure of a trench capacitor type dynamic random access memory (DRAM) according to an example implementation;

[0039] Figure 13 and 14 A conceptual diagram illustrating an electronic device structure applicable to an electronic device according to some exemplary embodiments; and

[0040] Figure 15 and 16 This is a schematic diagram illustrating a stacked structure according to some example implementations. Detailed Implementation

[0041] Some exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items. Expressions such as "at least one of" modify the entire list of elements when appearing before or after the list of elements, without modifying any individual element of the list.

[0042] The terminology used in this specification is for describing particular embodiments only and is not intended to limit the spirit of the art. Contents described as “upper” or “lower” may include those that are directly above / below / left / right in a contact manner, and those that are above / below / left / right in a non-contact manner.

[0043] Singular terms may include plural forms unless otherwise specified. The terms “comprising” or “having” are intended to mean that, unless expressly stated to the contrary, the features, figures, steps, actions, components, parts, components, materials, or combinations thereof described in this specification are present, and therefore it should be understood that one or more additional features or figures, steps, actions, components, parts, components, materials, or combinations thereof are not excluded in advance.

[0044] Terms such as “first,” “second,” and “third” may be used to describe various components, but only to distinguish one component from another, and the order and type of components are not restricted. Additionally, terms such as “unit,” “device,” and “module” refer to a unit of integrated configuration that performs at least one function or operation, and may be implemented in hardware or software, or a combination of hardware and software.

[0045] In expressions such as “at least one of the first antiferroelectric layer and the second antiferroelectric layer covers 80% or more of the surface of the ferroelectric layer” as used herein and other similar expressions, the term “cover” encompasses the following situations: (1) at least one of the first antiferroelectric layer and the second antiferroelectric layer is in direct contact with the surface of the ferroelectric layer, and (2) there is an intermediate layer (e.g., a paraelectric layer) between at least one of the first antiferroelectric layer and the second antiferroelectric layer and the ferroelectric layer, and therefore at least one of the first antiferroelectric layer and the second antiferroelectric layer overlaps with the ferroelectric layer without being in direct contact with the ferroelectric layer.

[0046] In the following description, exemplary embodiments will be illustrated in detail with reference to the accompanying drawings. In the figures below, the same reference numerals refer to the same components, and for clarity and convenience, the dimensions of the components (layer thickness, width, area, etc.) may be enlarged. Furthermore, the embodiments described below are merely exemplary, and various modifications to these embodiments are possible.

[0047] According to some exemplary embodiments, semiconductor devices including ferroelectrics and antiferroelectrics, and electronic devices (appliances) including the same, can be provided. The semiconductor device may be a non-memory device and may include, for example, field-effect transistors, capacitors, or combinations thereof, but is not limited thereto. The semiconductor device can be used in a variety of electronic devices. Such electronic devices may offer advantages in efficiency, speed, and power consumption compared to conventional devices.

[0048] Figure 1 and 2 A schematic diagram of a field-effect transistor according to some exemplary embodiments is shown. (Refer to...) Figure 1 and 2 Field-effect transistors D10 and D20 may include a substrate 100, a gate electrode 300 on the substrate 100, and a thin-film structure 200 between the substrate 100 and the gate electrode 300. The substrate 100 may include sources 120 and 121 and drains 130 and 131, and the thin-film structure may have ferroelectric and antiferroelectric properties. The field-effect transistors may be logic switching devices. For example, the logic switching device may represent the opposite concept to a memory device (e.g., a memory transistor), may have non-memory (non-storage) characteristics, and may be a switching device for non-memory on / off switching.

[0049] The substrate 100 may include semiconductor materials (e.g., Si, Ge, SiGe, and / or III-V semiconductors) and may be implemented in various forms. For example, the substrate 100 may include a germanium-on-insulator (GOI) substrate and / or a silicon-on-insulator (SOI) substrate.

[0050] The substrate 100 may include source electrodes 120 and 121 and drain electrodes 130 and 131, and channels 110 and 111 electrically connected to the source electrodes 120 and 121 and the drain electrodes 130 and 131. Source electrodes 120 and 121 may be electrically connected to one end of channels 110 and 111, and drain electrodes 130 and 131 may be electrically connected to the other end of channels 110 and 111. For example, source electrodes 120 and 121 may contact a first end of channels 110 and 111, while drain electrodes 130 and 131 may contact a second end of channels 110 and 111.

[0051] Reference Figure 1 The channel 110 may be included in the substrate region 101 and may be located in the substrate 100 between the source 120 and the drain 130. The source 120 and drain 130 may be formed by implanting impurities into different regions of the substrate 100. For example, the substrate region 101 may include a semiconductor material, and the source 120 and drain 130 may be regions of the semiconductor material doped with impurities different from those in the substrate region 101. The impurities in the source 120 and drain 130 may have different charges than those in the substrate region 101, and / or the source 120 and drain 130 may have different impurity concentrations than those in the substrate region. For example, the substrate region 101 may be a P-type semiconductor, and the source 120 and drain 130 may include N-type dopants. Alternatively, the substrate region 101 may be an N-type semiconductor, and the source 120 and drain 130 may include P-type dopants. The source 120, channel 110, and drain 130 may include a substrate material as a base material.

[0052] Additionally, refer to Figure 2 The channel 111 may include a material layer (e.g., a thin film) separate from the substrate region 101. The channel 111 may have semiconductor properties. For example, in addition to semiconductor materials such as Si, Ge, SiGe, and III-V semiconductors, the channel 111 may also include oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots, organic semiconductors, and / or combinations thereof. For example, the oxide semiconductor may include InGaZnO, the 2D material may include transition metal dichalcogenides (TMDs) and / or graphene, and the quantum dot may include colloidal quantum dots (colloidal QDs), nanocrystalline structures, etc. The source 121 and drain 131 may include conductive materials. For example, the source 121 and drain 131 may each independently include a metal, a metal compound, and / or a conductive polymer.

[0053] The gate electrode 300 may be on and spaced apart from the substrate 100, and may face the channels 110 and 111. The gate electrode 300 may have a sheet resistance of about 1 megohm / □ (MΩ / sq) or less. The gate electrode 300 may comprise a metal, a metal nitride, a metal carbide, polysilicon, and / or combinations thereof. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and / or tantalum (Ta); the metal nitride may include titanium nitride (TiN) and / or tantalum nitride (TaN); and the metal carbide may include metal carbides doped with aluminum and / or silicon (e.g., TiAlC, TaAlC, TiSiC, and / or TaSiC). The gate electrode 300 may include a structure in which various materials are stacked. For example, the gate electrode 300 may include a stacked structure of metal nitride layers / metal layers such as TiN / Al and / or a stacked structure of metal nitride layers / metal carbide layers / metal layers such as TiN / TiAlC / W. The gate electrode 300 may also include titanium nitride (TiN) and / or molybdenum (Mo), and the above examples can be used in various modified forms.

[0054] The thin film structure 200 may be located between the substrate 100 and the gate electrode 300. For example, the thin film structure 200 may be formed on channels 110 and 111, and / or the gate electrode 300 may be formed on the thin film structure 200. The thin film structure 200 may include a first antiferroelectric layer 210, a second antiferroelectric layer 230 spaced apart from the first antiferroelectric layer 210, and a ferroelectric layer 220 between the first antiferroelectric layer 210 and the second antiferroelectric layer 230. The first antiferroelectric layer 210 and the second antiferroelectric layer 230 may include antiferroelectric materials and may have antiferroelectric properties, and the ferroelectric layer 200 may include ferroelectric materials and may have ferroelectric properties. The first antiferroelectric layer 210, the ferroelectric layer 220, and the second antiferroelectric layer 230 may be arranged sequentially, for example, in the thickness direction of the thin film, and stacked parallel to the substrate 100 and / or the gate electrode 300. The thin film structure 200 may form a gate stack together with the gate electrode 300.

[0055] As mentioned above, ferroelectrics can have negative capacitance in specific operating regions, and when applied to the gate stack of a transistor, they can reduce the subthreshold swing (SS) of the transistor. However, because there is a hysteresis in the polarization intensity value for voltage changes, when ferroelectrics are applied to logic devices such as logic transistors, structures can be added to control this hysteresis.

[0056] For hysteresis control, ferroelectrics and dielectrics can be used for capacitance matching. Figure 3A This is a schematic diagram illustrating the relationship between the electric field E applied to an example ferroelectric material and the polarization intensity P. Figure 3B This is a schematic diagram illustrating the relationship between charge Q and energy U in an example ferroelectric material. Additionally, Figure 4A This is a schematic diagram illustrating the relationship between the electric field E applied to the example dielectric material and the polarization intensity P. Figure 4B This is a schematic diagram illustrating the relationship between charge Q and energy U in an example dielectric material. (Refer to...) Figure 3B The charge Q versus energy U diagram of a ferroelectric material has two wells. The shapes of these two wells correspond to two stable polarization states, and the diagram shape represents hysteresis behavior.

[0057] Figure 5 This is a schematic diagram illustrating the relationship between charge Q and energy U when capacitor matching is performed using a ferroelectric material and a dielectric material that does not possess antiferroelectric properties. As shown, hysteresis is eliminated through capacitor matching, and a relatively wide U-shaped curve can appear. However, in this case, because a dielectric material with a low dielectric constant is used, the efficiency of the gate can be reduced when this dielectric material is applied to the gate stack of the transistor.

[0058] However, according to example implementations, ferroelectrics and antiferroelectrics can be used for capacitance matching. Figure 6AThis is a schematic diagram illustrating the relationship between the electric field E applied to an example antiferroelectric material and the polarization intensity P. Figure 6B This is a schematic diagram showing the relationship between the charge Q and energy U of an antiferroelectric material. Figure 7 This diagram conceptually illustrates the capacitance matching using ferroelectrics and antiferroelectrics. (See diagram for example.) Figure 6B As shown, the charge Q versus energy U graph of the antiferroelectric has a different curve than that of the ferroelectric. Therefore, as Figure 7 As shown, ferroelectrics and antiferroelectrics can be used for capacitance matching, and the relationship between charge Q and energy U is shown as a U-shaped diagram rather than a diagram with two well shapes. Therefore, capacitance-matched ferroelectrics and antiferroelectrics do not exhibit hysteresis behavior.

[0059] Thin-film structures incorporating ferroelectrics and antiferroelectrics can also have lower internal polarization values ​​than thin-film structures incorporating ferroelectric and dielectric materials. Without being bound by any particular theory, combinations of ferroelectric and dielectric materials can include dissimilar materials such as hafnium oxide and silicon oxide. Due to these material dissimilarities, interfacial polarization can occur due to interfacial traps at the interface between the ferroelectric and dielectric materials. Unlike ferroelectric and dielectric materials, because ferroelectrics and antiferroelectrics can include similar materials such as hafnium oxide, zirconium oxide, and / or hafnium-zirconium oxide, there is a lower likelihood of interfacial polarization due to interfacial traps at the interface between the ferroelectric and antiferroelectric materials. Furthermore, antiferroelectrics can have a dielectric constant approximately 10 times higher than that of typical dielectrics, and therefore, when applied to the gate electrode of a transistor, gate efficiency may not be reduced.

[0060] Furthermore, when thin-film structures comprising ferroelectrics and antiferroelectrics are applied to semiconductor devices, the subthreshold swing of the semiconductor device can be reduced. (Refer to...) Figure 6A and 6BThe antiferroelectric is a material that does not possess spontaneous polarization states in the absence of an electric field, but exhibits electrical properties similar to those of a ferroelectric when an electric field at or above a threshold intensity is present. For example, while a ferroelectric exhibits spontaneous polarization via dipoles even in the absence of an external electric field, and the polarization direction can vary within a domain unit by an external electric field, an antiferroelectric may not exhibit spontaneous polarization or may exhibit low (e.g., close to 0) spontaneous polarization because adjacent dipoles have opposite directions in the absence of an electric field, and / or because dipoles are absent. However, when an electric field at or above a threshold intensity is present, the antiferroelectric can exhibit spontaneous polarization like a ferroelectric, and the polarization direction can vary within a domain unit. Therefore, when a voltage is applied to a semiconductor device, the subthreshold swing SS of the device can be further reduced by amplifying the voltage generated during domain switching of both the ferroelectric and antiferroelectric materials.

[0061] Refer again Figure 1 and 2 Ferroelectric layer 220 may be located between two antiferroelectric layers (e.g., first and second antiferroelectric layers 210 and 230). The surfaces of the first and second antiferroelectric layers 210 and 230 may contact ferroelectric layer 220. For example, the first antiferroelectric layer 210 may contact the lower surface of ferroelectric layer 220, and the second antiferroelectric layer 230 may contact the upper surface of ferroelectric layer 220. The first and second antiferroelectric layers 210 and 230 may cover 80% or more of the ferroelectric layer. For example, the first and second antiferroelectric layers 210 and 230 may cover 85% or more, 90% or more, 95% or more, 98% or more, or 100% of the upper and / or lower surfaces of ferroelectric layer 220. As described above, the polarization hysteresis of ferroelectric layer 220 can be reduced by controlling the interface at the surface of ferroelectric layer 220. Ferroelectric layer 220 may have a depolarization field, and the depolarization field may be in the direction opposite to the spontaneous polarization of the ferroelectric material. The depolarization field can vary depending on the interface between the ferroelectric layer 220 and the outside. When the first and second antiferroelectric layers 210 and 230 are on the ferroelectric layer 220, as the proportion of the first and second antiferroelectric layers 210 and 230 covering the ferroelectric layer 220 (i.e., the proportion of the surface area of ​​the ferroelectric layer 220 covered by the first and second antiferroelectric layers 210 and 230) increases, the depolarization field of the ferroelectric layer 220 increases, thereby reducing the total polarization intensity value and decreasing the hysteresis. In a contrast field-effect transistor in which the ferroelectric layer 220 and the gate electrode 300 are in contact, compared with... Figure 1 and 2Unlike field-effect transistors D10 and D20, the ferroelectric layer 220 receives charge compensation from the gate electrode 300, thus maintaining the spontaneous polarization of the ferroelectric material. The charge compensation from the gate electrode 300 can be controlled by the ratio of the first and second antiferroelectric layers 210 and 230 covering the ferroelectric layer 220. For example, as the ratio increases, the total polarization intensity value can decrease and the hysteresis can be reduced.

[0062] Therefore, as Figure 1 and 2 As shown, the thin-film structure 200, comprising a stacked first antiferroelectric layer 210, a ferroelectric layer 220, and a second antiferroelectric layer 230, can be implemented in devices exhibiting domain switching effects, maximized voltage amplification, and reduced hysteresis. For example, semiconductor devices incorporating the thin-film structure 200 can be implemented, where the thin-film structure 200 exhibits substantially no hysteresis in response to changes in current I according to an externally applied voltage Vg. For instance, a field-effect transistor at an operating voltage of 1V can have a hysteresis window of 10mV or less in the voltage-to-current I-Vg curve.

[0063] Figure 8 This is a schematic diagram illustrating a semiconductor device D30 (e.g., a field-effect transistor) according to an example embodiment. (Refer to...) Figure 8 The dielectric layer 400 may be further included between the channel 110 and the thin film structure 200. The dielectric layer 400 may be configured to suppress and / or prevent electrical leakage. The thickness of the dielectric layer 400 may be 0.1 nm or greater, 0.3 nm or greater, or 0.5 nm or greater, and / or may be 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, or 1 nm or less. The dielectric layer 400 may include paraelectric and / or high-k dielectric (dielectric) materials (e.g., silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc.) and / or 2D insulators (e.g., hexagonal boron nitride (h-BN)). For example, the dielectric layer 400 may include silicon oxide (SiO2), silicon nitride (SiN), etc. x The dielectric layer 400 may further include at least one of the following: hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), tantalum oxide (e.g., Ta2O5), titanium oxide (e.g., TiO2), strontium titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), and red scandium tantalum oxide (e.g., PbSc). 0.5 Ta 0.5The dielectric layer 400 may also include metal oxynitrides such as aluminum oxynitride (e.g., AlON), zirconium oxynitride (e.g., ZrON), hafnium oxynitride (e.g., HfON), lanthanum oxynitride (e.g., LaON), yttrium oxynitride (e.g., YON), silicates such as ZrSiON, HfSiON, YSiON, LaSiON, and aluminates such as ZrAlON and HfAlON.

[0064] Reference Figure 8 The conductive layer 500 may be located between the channel 110 and the thin film structure 200. The conductive layer 500 may have a sheet resistance of about 1 MΩ / sq or less. The conductive layer 500 may be a floating electrode and may include metals and / or metal compounds.

[0065] Although field-effect transistors D10, D20, and D30 are shown as 1-gate-on-channel transistors, they can be implemented in various forms and / or configurations. For example, field-effect transistors D10, D20, and D30 may include two-dimensional and / or three-dimensional configurations. For example, the field-effect transistors may have a 1-gate-on-channel configuration (e.g., a planar FET), a 3-gate-on-channel configuration (e.g., a Fin-FET), and / or a 4-gate-on-channel configuration (e.g., a Gate-all-around-FET).

[0066] Figure 9A To illustrate a schematic diagram of a semiconductor device (field-effect transistor) according to an example embodiment, and Figure 9B For along Figure 9A The cross-sectional view taken along line A-A'. (Refer to...) Figure 9A and 9B The semiconductor device may be a Fin-FET D40 and includes a source 120, a drain 130, and a channel 110 or 111 therebetween. The channel 110 may be included as part of a substrate, and / or the channel 111 may include a material layer (e.g., a thin film) on the substrate. The channel 110 and / or 111 may have a fin shape. A gate electrode 300 may span the fin shape on the substrate 100. The channel 110 or 111 may be formed in the region where the fin shape intersects with the gate electrode 300. A thin film structure 200 including a ferroelectric layer 220 and antiferroelectric layers 210 and 230 may be present between the channel 110 or 111 and the gate electrode 300, and the first antiferroelectric layer 210, the ferroelectric layer 220, and the second antiferroelectric layer 230 may be sequentially arranged to surround the fin shape of the channel 110 and / or 111. For example, the gate electrode 300, the first antiferroelectric layer 210, the ferroelectric layer 220, and / or the second antiferroelectric layer 230 may cover the sidewalls and the top surface of the fin structure.

[0067] Figure 10A To illustrate a schematic diagram of a semiconductor device (field-effect transistor) according to an example embodiment, and Figure 10B For along Figure 10A The cross-sectional view taken along line B-B'. (Refer to...) Figure 10A and 10B The semiconductor device may be a gate-all-around FET D50 and includes a source 120, a drain 130, and a channel 111 therebetween. The channel 111 may be in the form of a wire, a sheet, etc. The source 120, drain 130, and channel 111 may be disposed separately from the substrate region 101. The gate electrode 300 may intersect with and surround the source 120, drain 130, and channel 111. The channel 111 may be formed in the region surrounded by the gate electrode 300. A thin film structure 200 including a first antiferroelectric layer 210, a ferroelectric layer 220, and a second antiferroelectric layer 230 may be located between the channel 111 and the gate electrode 300. The first antiferroelectric layer 210, the ferroelectric layer 220, and the second antiferroelectric layer 230 may sequentially surround the channel 111.

[0068] Figure 11 A schematic diagram illustrating a capacitor according to an exemplary embodiment is shown below. (Refer to...) Figure 11 The capacitor D60 may include a first electrode 600, a second electrode 700 facing and separated from the first electrode 600, and a thin film structure 200 between the first electrode 600 and the second electrode 700. The thin film structure 200 may include a ferroelectric layer 220 and antiferroelectric layers 210 and 230. The first electrode 600 and the second electrode 700 may be referred to as the lower electrode and the upper electrode, respectively. The thin film structure 200 may include a first antiferroelectric layer 210, a second antiferroelectric layer 230 facing and separated from the first antiferroelectric layer 210, and a ferroelectric layer 220 between the first antiferroelectric layer 210 and the second antiferroelectric layer 230. The first antiferroelectric layer 210, the ferroelectric layer 220, and the second antiferroelectric layer 230 may be sequentially arranged parallel to the first electrode 600 and / or the second electrode 700 in the thickness direction of the thin film.

[0069] The first electrode 600 and the second electrode 700 may have a sheet resistance of about 1 MΩ / sq or less, and may comprise the same or different materials. For example, the first electrode 600 and the second electrode 700 may each independently comprise at least one of the following: TiN, TaN, Ti, Ta, TiCN, TiSiN, WSiN, TiAlN, TaAlN, TiAlCN, TiW, RuTiN, RuCN, Pt, Au, Mo, and Al. As a specific example, the first electrode 600 and the second electrode 700 may each independently comprise TiN and / or Mo. The thickness of the first electrode 600 and the second electrode 700 may each be about 1 nm or greater and / or about 20 nm or less, for example, the thickness of the first electrode 600 and the second electrode 700 may be between 1 nm and 20 nm.

[0070] The capacitor may exhibit substantially no hysteresis behavior. For example, it may have a coercive electric field of about 1 MV / cm or less, depending on the polarization intensity of the external electric field.

[0071] The field-effect transistor and the capacitor can be electrically connected to form a semiconductor device D70. The semiconductor device D70 may have storage characteristics and may be, for example, DRAM.

[0072] Figure 12A This describes the circuit structure of a memory cell that includes a memory device consisting of a semiconductor device and a capacitor. Figure 12B A schematic diagram illustrating a semiconductor device according to an example implementation. Figure 12C This describes the structure of a trench capacitor-type dynamic random access memory (DRAM) according to an example implementation.

[0073] Reference Figure 12A Semiconductor device D70 may be included in a memory device as a memory cell and may include transistor D61 and capacitor D60 electrically connected to, for example, the source 120 of transistor D61. The memory device may include multiple bit lines and multiple word lines, and may further include multiple memory cells. Each word line may be electrically connected to the gate electrode 300 of transistor D61, and each bit line may be electrically connected to the drain 130 of transistor D61. The electrodes of capacitor D60 may be connected to, for example, a voltage controller (not shown). For example, refer to... Figure 12B The semiconductor device D70 may include: a capacitor D60, which includes a ferroelectric layer 220 and antiferroelectric layers 210 and 230; and a field-effect transistor D61, which is electrically connected to the capacitor D60 via a contact 62. One of the first and second electrodes 600 and 700 of the capacitor D60 and one of the source 120 and drain 130 of the transistor D61 may be electrically connected via the contact 62. The contact 62 may include a conductive material such as tungsten, copper, aluminum, polysilicon, etc.

[0074] The field-effect transistor D61 may include: a substrate 100 including a source 120, a drain 130, and a channel 110; and a gate electrode 300 facing the channel 110. A dielectric layer 410 may be present between the substrate 100 and the gate electrode 300. Figure 12B The field-effect transistor D61 shown is an example excluding the thin-film structure 200, but the field-effect transistor may also include, for example, the thin-film structure 200. Figure 1 , 2 The thin-film structure 200 shown in 8, 9A-9B, and 10A-10B. For example, the field-effect transistor may be one of field-effect transistors D10, D20, D30, D40, and / or D50. The source 120, drain 130, channel 110, substrate 100, and gate electrode 300 may be the same as those described above, and the dielectric layer 410 may be the dielectric layer 400 described above.

[0075] The arrangement of capacitor D60 and field-effect transistor D61 can be varied. For example, capacitor D60 can be disposed on substrate 100 or can be a structure embedded in substrate 100. (See reference...) Figure 12C On the semiconductor substrate 100, a field oxide film 821 may be used to define a device isolation region, and a gate electrode 300 and source / drain impurity regions 120 and 130 may be formed in the device isolation region. A dielectric layer 410 may be formed between the gate electrode 300 and the semiconductor substrate 100. The oxide film may be formed as an interlayer insulating film 824. Regions that are not trenches may be capped with trench buffer layers, and a portion of the drain region 130 may be open to form a contact portion.

[0076] Trenches may be formed in the sidewalls of the interlayer insulating film 824, and a sidewall oxide film 825 may be formed over the entire sidewall of the trench. The sidewall oxide film 825 may compensate for damage in the semiconductor substrate caused by etching to form trenches and may serve as a dielectric film between the semiconductor substrate 100 and the first electrode 600. The sidewall portion of the drain region 130, except for the portion of the drain region near the gate electrode 300, may be fully exposed.

[0077] A PN junction (not shown) can be formed in the sidewall portion of the drain region by impurity implantation. A trench can be formed in the drain region 130. The sidewall of the trench near the gate can directly contact the drain region 130, and a PN junction can be formed by implanting additional impurities into the drain region.

[0078] A first electrode 600 may be formed on a portion of the interlayer insulating film 824, the exposed drain region 130, and the surface of the sidewall oxide film 825 in the trench. Except for the portion of the drain region 130 near the gate electrode 300, the first electrode 600 may contact the entire drain region 130 that contacts the upper sidewall of the trench. Next, a thin film structure 200 may be formed along the upper surface of the first electrode 600 as a capacitor dielectric film, and a polycrystalline layer serving as a second electrode 700 may be formed thereon, thereby completing the trench capacitor-type DRAM. Although shown as including the thin film structure 200 only in the capacitor dielectric film, any of the dielectric layer (gate insulating film) 410, the capacitor dielectric film, and / or the interlayer insulating film 824 may, for example, include an embodiment of the thin film structure 200 as described above.

[0079] The semiconductor devices and semiconductor apparatuses described herein can be applied to a variety of electronic devices. For example, the field-effect transistors, capacitors, and / or combinations thereof described above can be used as logic devices and / or memory devices in a variety of electronic devices. The semiconductor devices according to embodiments can be driven with low power, and therefore, meet the requirements for miniaturization and integration of electronic devices. The described semiconductor devices and semiconductor apparatuses can be used, for example, in electronic devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices for arithmetic operations, program execution, temporary data maintenance, etc. The semiconductor devices and semiconductor apparatuses according to some exemplary embodiments can be useful for electronic devices in which large data transmission capacities and continuous data transmission occur.

[0080] Figure 13 and 14 A conceptual diagram illustrating an electronic device structure that can be applied to an electronic device according to some example implementations.

[0081] Reference Figure 13 The electronic device structure 1000 may include a memory cell 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory cell 1010, ALU 1020, and control unit 1030 may be electrically connected to each other. In an exemplary embodiment, the electronic device structure 1000 may be implemented as a single chip including the memory cell 1010, ALU 1020, and control unit 1030. For example, the memory cell 1010, ALU 1020, and control unit 1030 may be directly connected to each other via on-chip interconnects to metal wires. The memory cell 1010, ALU 1020, and control unit 1030 may be monolithically integrated on a substrate to form a single chip. An input / output device 2000 may be connected to the electronic device structure 1000 (chip). In another exemplary embodiment, the memory cell 1010, ALU 1020, and control unit 1030 may be implemented as separate components communicatively coupled together via a bus (not shown).

[0082] The storage unit 1010, ALU 1020, and control unit 1030 may each independently include the semiconductor devices (field-effect transistors, capacitors, and / or the like) described above. For example, ALU 1020 and control unit 1030 may each independently include the field-effect transistors described above, and the storage unit 1010 may include the capacitors, field-effect transistors, and / or combinations thereof described above. The storage unit 1010 may include both main memory and cache memory. The electronic device structure 1000 (chip) may be an on-chip memory processing unit.

[0083] Reference Figure 14 The cache memory 1510, ALU 1520, and control unit 1530 may constitute a central processing unit (CPU) 1500. The cache memory 1510 may be static random access memory (SRAM) and may include one of the field-effect transistors D10-D50 described above. Separately from the CPU 1500, a main memory 1600 and an auxiliary memory 1700 may be provided. The main memory 1600 may be dynamic random access memory (DRAM) and may include the transistors D10-D50 and / or capacitor D60 described above.

[0084] In some implementation examples, the electronic device structure may be implemented in such a way that computing unit devices and storage unit devices are adjacent to each other in a single chip without any distinction between sub-units.

[0085] Figure 15 and 16 This is a schematic diagram illustrating a laminated structure according to some exemplary embodiments. The construction and composition of the thin film structure described above will be described in detail below. Specifically, refer to... Figure 15, the stacked structure T10 may include: a first antiferroelectric layer 21 on a substrate 10, a second antiferroelectric layer 23 facing the first antiferroelectric layer 21 and separated from the first antiferroelectric layer 21, and a ferroelectric layer 22 between the first antiferroelectric layer 21 and the second antiferroelectric layer 23. The first antiferroelectric layer 21 and the second antiferroelectric layer 23 may be in contact with the bottom surface and the top surface of the ferroelectric layer 22 respectively, and may be arranged to cover 80% or more, 85% or more, 90% or more, 95% or more, 98% or more, or 100% of the corresponding surfaces of the ferroelectric layer 22. Additionally, the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 may be sequentially arranged parallel to the substrate 10 in the thickness direction of the thin film. When the stacked structure T10 is applied to a semiconductor device, the substrate 10 may be one of the components of the semiconductor device. For example, when the stacked structure T10 is applied to field effect transistors D10, D20, D30, D40, and D50, the substrate 10 may be a semiconductor substrate 100, a gate electrode 300, channels 110 and 111, a dielectric layer 400, and / or a conductive layer 500. Additionally, when the stacked structure T10 is applied to a capacitor D60, the substrate 10 may be one of the first electrode 600 or the second electrode 700.

[0086] The ferroelectric layer 22 includes a ferroelectric material. As described above, even in the absence of an external electric field, the ferroelectric material has spontaneous polarization and has two stable polarization states in the relationship between charge Q and energy U (see Figure 3B ).

[0087] The first antiferroelectric layer 21 and the second antiferroelectric layer 23 include antiferroelectric materials. The antiferroelectric materials of the first antiferroelectric layer 21 and the second antiferroelectric layer 23 may be the same or different. As described above, the antiferroelectric material does not have a spontaneous polarization state in the absence of an electric field, but may exhibit electrical properties similar to those of the ferroelectric material in a state where there is an electric field with a threshold. Therefore, the antiferroelectric material may have two hysteresis loops (electric hysteresis loops) in the relationship between electric field E and polarization intensity P (see Figure 6A ).

[0088] According to an example embodiment, the ferroelectric material and the antiferroelectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium-zirconium oxide (Hf x Zr 1-x O2, 0 < x < 1), and / or a combination thereof. These metal oxides may exhibit ferroelectric or antiferroelectric properties even in very thin films at the nanometer level and may be applied to existing silicon-based semiconductor device processes, enabling high mass productivity.

[0089] The ferroelectrics and antiferroelectrics can be classified according to their composition, the type and / or ratio of doping elements, and / or crystal structure. For example, ferroelectricity and antiferroelectricity can vary depending on the composition of the metal oxide, and even if the composition of the matrix material (e.g., the metal oxide) is the same, ferroelectricity and antiferroelectricity can vary depending on the crystal structure and / or the type and / or ratio of the dopant material. Here, the type and content of each element can be measured according to methods known in the art. For example, the composition and / or arrangement (configuration) of elements in ferroelectrics and antiferroelectrics can be determined using X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), inductively coupled plasma (ICP), etc.

[0090] In some embodiments, the hafnium content of the ferroelectric layer 22 may be greater than the hafnium content of the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23. For example, the molar ratio of hafnium in the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23 to hafnium in the ferroelectric layer 22 may independently be 0 or greater, 0.05 or greater, 0.1 or greater, 0.15 or greater, 0.2 or greater, and / or 0.3 or greater. The molar ratio of hafnium in the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23 to hafnium in the ferroelectric layer 22 may also be less than 1, 0.8 or less, 0.7 or less, and / or 0.6 or less. Additionally, in some embodiments, the zirconium content of the ferroelectric layer 22 may be less than or equal to the zirconium content of the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23. For example, the molar ratio of zirconium content in ferroelectric layer 22 to zirconium content in first antiferroelectric layer 21 and / or second antiferroelectric layer 23 can be in the range of 0 to 1. For example, the molar ratio of zirconium in first antiferroelectric layer 21 or second antiferroelectric layer 23 to zirconium in ferroelectric layer 22 can be independently 1 or greater, 1.1 or greater, 1.2 or greater, and / or 1.5 or greater. The molar ratio of zirconium in first antiferroelectric layer 21 or second antiferroelectric layer 23 to zirconium in ferroelectric layer 22 can also be independently 100 or less, 75 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, or 10 or less.

[0091] The ferroelectric layer 22 may include hafnium-zirconium oxide. The hafnium-zirconium oxide may be made from Hf... x Zr 1-x O2 (0.2 ≤ x < 1.0) represents the hafnium content. For example, the hafnium content x of the ferroelectric layer 22 can be 0.25 or greater, 0.3 or greater, or 0.4 or greater. The hafnium content x of the ferroelectric layer 22 can also be less than 0.95, less than 0.9, less than 0.8, less than 0.7, or less than 0.6. In addition, the first antiferroelectric layer 21 and the second antiferroelectric layer 23 can each independently include zirconium oxide and / or be composed of Hf x Zr 1-xHafnium-zirconium oxide represented by O2(0 < x < 0.2). For example, each of the first antiferroelectric layer 21 and the second antiferroelectric layer 23 independently has a hafnium element content x of 0.01 or greater, 0.03 or greater, 0.05 or greater, and / or 0.08 or greater, and / or 0.18 or less, 0.15 or less, 0.12 or less, and / or 0.1 or less. The first antiferroelectric layer 21 and / or the second antiferroelectric layer 23 may also include zirconium oxide with a hafnium element content x of 0.

[0092] In addition, the ferroelectric layer 22 and the antiferroelectric layers 21 and 23 may each independently include hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium-zirconium oxide (Hf x Zr 1-x O2, 0 < x < 1.0), and / or a combination thereof (e.g., as a matrix material), and may further include a dopant material (e.g., at least one of C, Si, Ge, Sn, Pb, Al, Y, La, Gd, Mg, Ca, Sr, Ba, Ti, Zr, and / or Hf). The dopant material content of the ferroelectric layer 21 may be less than the dopant material content of the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23. For example, the ferroelectric layer 22 may have a dopant material content that is greater than or equal to 0 atomic %, 0.2 atomic % or greater, 0.5 atomic % or greater, 1 atomic % or greater, 2 atomic % or greater, or 3 atomic % or greater, and / or 10 atomic % or less, 8 atomic % or less, 7 atomic % or less, or 6 atomic % or less compared to the metal element of the matrix material. For example, the ferroelectric layer 22 may have a dopant material content in the range of 0 atomic % to 10 atomic % compared to the metal element of the matrix material. In addition, each of the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23 may independently have a dopant material content of 4 atomic % or greater, 6 atomic % or greater, 7 atomic % or greater, 8 atomic % or greater, and / or 20 atomic % or less, 18 atomic % or less, 15 atomic % or less, or 12 atomic % or less compared to the metal element of the matrix material. For example, both and / or each of the antiferroelectric layers 21 and 23 may have a dopant material content in the range of 4 atomic % to 20 atomic % compared to the metal element of the matrix material.

[0093] The ferroelectric layer 22 and the first and second antiferroelectric layers 21 and 23 may each have different crystal structure distributions. For example, the ferroelectric layer 22 may include an orthorhombic phase, and the first and second antiferroelectric layers 21 and 23 may include a tetragonal phase. For example, in some cases, the ferroelectric layer 22 and the first and second antiferroelectric layers 21 and 23 may each independently include both orthorhombic and tetragonal crystal structures, but the ferroelectric layer 22 may include more orthorhombic crystal structures than tetragonal crystal structures, and the first and second antiferroelectric layers 21 and 23 may include more tetragonal crystal structures than orthorhombic crystal structures. The crystal structure distribution can be confirmed by methods known in the art, such as transmission electron microscopy (TEM), grazing incidence X-ray diffraction (GIXRD), etc.

[0094] The thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 can independently be greater than 0 nm, 0.1 nm or greater, 0.2 nm or greater, 0.3 nm or greater, 0.4 nm or greater, 0.5 nm or greater, 0.6 nm or greater, 0.7 nm or greater, 0.8 nm or greater, 1.0 nm or greater, and / or 1.5 nm or greater. The thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 can also independently be 10 nm or less, 8 nm or less, 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, and / or 1 nm or less. For example, the thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 can be greater than 0 nm and less than or equal to 10 nm. In addition, the thickness ratio of the first antiferroelectric layer 21 and / or the second antiferroelectric layer 23 relative to the ferroelectric layer 22 may independently be greater than 0, greater than 0.05, greater than 0.1, greater than 0.15, greater than 0.2, greater than 0.3, 0.4 or greater, 0.5 or greater, 0.6 or greater, 0.8 or greater, 1.0 or greater, 1.2 or greater, and / or 1.5 or greater, and / or may also be 10 or less, 8 or less, 7 or less, 6 or less, 5 or less, 4 or less, and / or 3 or less. For example, in an example embodiment in which the stacked structure T10 is applied in field-effect transistors D10, D20, D30, D40, and D50, the sum of the thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 may be greater than 0 nm and less than or equal to 5 nm, and / or the thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 may be independently greater than 0 nm and less than or equal to 3 nm, and / or the thickness ratio of the first antiferroelectric layer 21 or the second antiferroelectric layer 23 to the ferroelectric layer 22 may be independently greater than 0 and less than or equal to 3. Furthermore, when the stacked structure T10 is applied in capacitors D60 and D70, the sum of the thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 can be greater than 0 nm and less than or equal to 10 nm, and / or the thicknesses of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 can each be independently greater than 0 nm and less than or equal to 5 nm, and / or the thickness ratio of the first antiferroelectric layer 21 or the second antiferroelectric layer 23 to the ferroelectric layer 22 can be independently greater than 0 and less than or equal to 5. The thicknesses can be measured using methods known in the art, such as an elliptic meter (SE MG-1000, Nano View).

[0095] The boundaries at the interfaces between the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 may be unclear. For example, the boundaries between the first antiferroelectric layer 21 and the ferroelectric layer 22, between the ferroelectric layer 22 and the second antiferroelectric layer 23, and / or between all of them may be unclear. For example, if the first antiferroelectric layer 21, the ferroelectric layer 22, and / or the second antiferroelectric layer 23 have similar compositions and / or have small thicknesses, the boundaries with adjacent layers may not be clearly distinguishable due to, for example, material diffusion between layers.

[0096] The stacked structure T10 may further include a paraelectric layer. Without being bound by any particular theory, the paraelectric layer helps control leakage currents that can occur between crystals in the ferroelectric layer 22 and the first and second antiferroelectric layers 21 and 23. The paraelectric layer may be between the ferroelectric layer 22 and the first antiferroelectric layer 21, and / or between the ferroelectric layer 22 and the second antiferroelectric layer 23. For example, the stacked structure T10 may include a first paraelectric layer between the ferroelectric layer 22 and the first antiferroelectric layer 21 and / or a second paraelectric layer between the ferroelectric layer 22 and the second antiferroelectric layer 23. Without being bound by any particular theory, the paraelectric layer may separate at least one of the first and second antiferroelectric layers 21 and 23 from the ferroelectric layer 22 to control material diffusion between the layers. The paraelectric layer may include a material having a breakdown voltage greater than that of the ferroelectric layer 22 and the first and second antiferroelectric layers 21 and 23. The paraelectric layer may include one or more of the following: aluminum oxide (Al2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon oxide (SiO2), and / or combinations thereof.

[0097] According to an example embodiment, the thin film structure may include a crystalline metal oxide layer containing hafnium. (See also...) Figure 16 The stacked structure T20 may include a crystalline metal oxide layer 30 on the substrate 10, the crystalline metal oxide layer 30 including at least two of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium-zirconium oxide (HfO2). x Zr 1-xO2, where 0 < x < 1), and / or a combination thereof. The crystalline metal oxide layer 30 may have a concentration gradient of hafnium element in the thickness direction. For example, the metal oxide layer 30 may have a first surface layer portion 31, a central portion 32, and a second surface layer portion 33 that are sequentially stacked in the thickness direction, and the hafnium element content of the central portion 32 may be greater than that of the first surface layer portion 31 and / or the second surface layer portion 33. For example, the molar ratio of the hafnium element in the first surface layer portion 31 and / or the second surface layer portion 33 to the hafnium element in the central portion 32 may independently be 0 or greater, 0.05 or greater, 0.1 or greater, 0.15 or greater, 0.2 or greater, and / or 0.3 or greater; and the molar ratio of the hafnium element in the first surface layer portion 31 and / or the second surface layer portion 33 to the hafnium element in the central portion 32 may also independently be less than 1, 0.8 or less, 0.7 or less, and / or 0.6 or less. For example, the molar ratio of the hafnium element in the first surface layer portion 31 and / or the second surface layer portion 33 to the hafnium element in the central portion 32 may independently be between 0 and 1. In addition, the zirconium element content of the central portion 32 may be less than that of the first surface layer portion 31 and / or the second surface layer portion 33. For example, the molar ratio of the zirconium element in the first surface layer portion 31 or the second surface layer portion 33 to the zirconium element in the central portion 32 may independently be greater than 1, greater than 1.1, greater than 1.2, and / or greater than 1.5. The molar ratio of the zirconium element in the first surface layer portion 31 or the second surface layer portion 33 to the zirconium element in the central portion 32 may also independently be 100 or less, 75 or less, 60 or less, 50 or less, 40 or less, 30 or less, 25 or less, 20 or less, and / or 10 or less. For example, the molar ratio of the zirconium element in the first surface layer portion 31 or the second surface layer portion 33 to the zirconium element in the central portion 32 may independently be greater than 1 and less than or equal to 100.

[0098] The first surface layer portion 31, the central portion 32, and the second surface layer portion 33 may each independently include at least two of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium-zirconium oxide (Hf x Zr 1-x O2, where 0 < x < 1), and / or a combination thereof. For example, the first surface layer portion 31 and / or the second surface layer portion 33 may each independently include zirconium oxide (ZrO2) and / or hafnium-zirconium oxide represented by Hf x Zr 1-x O2 (0 < x < 0.2), and the central portion 32 may include hafnium-zirconium oxide represented by Hf x Zr 1-x O2 (0.2 ≤ x < 1).

[0099] The central portion 32 and the first and second surface layer portions 31 and 33 may each have different crystal phase distributions. For example, the central portion 32 may include an orthorhombic crystal phase, and the first and second surface layer portions 31 and 33 may include a tetragonal crystal phase. For example, in some cases, the central portion 32 and the first and second surface layer portions 31 and 33 may each independently include both orthorhombic and tetragonal crystal structures, but the central portion 32 may include more orthorhombic crystal structures than tetragonal crystal structures, and the first and second surface layer portions 31 and 33 may include more tetragonal crystal structures than orthorhombic crystal structures. The crystal structure distribution can be confirmed by methods known in the art, such as transmission electron microscopy (TEM), grazing incidence X-ray diffraction (GIXRD), etc.

[0100] The thickness of the first surface layer portion 31 and the second surface layer portion 33 may be independently 0.5% or greater and 45% or less of the total thickness of the crystalline metal oxide layer 30. For example, the thickness of the first surface layer portion 31 and the second surface layer portion 33 may be independently 1% or greater, 2% or greater, 5% or greater, 7% or greater, 10% or greater, or 15% or greater of the total thickness of the crystalline metal oxide layer 30, and / or may be 40% or less, 35% or less, or 30% or less of the total thickness of the crystalline metal oxide layer 30.

[0101] The thicknesses of the first surface layer portion 31, the central portion 32, and the second surface layer portion 33 may independently be greater than 0 nm, 0.1 nm or greater, 0.2 nm or greater, 0.3 nm or greater, 0.4 nm or greater, 0.5 nm or greater, 0.6 nm or greater, 0.7 nm or greater, 0.8 nm or greater, 1.0 nm or greater, and / or 1.5 nm or greater. The thicknesses of the first surface layer portion 31, the central portion 32, and the second surface layer portion 33 may also independently be 10 nm or less, 8 nm or less, 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, and / or 1 nm or less. Additionally, the thickness ratio of the first surface layer portion 31 or the second surface layer portion 33 relative to the central portion 32 may independently be greater than 0, greater than 0.05, greater than 0.1, greater than 0.15, greater than 0.2, greater than 0.3, 0.4 or greater, 0.5 or greater, 0.6 or greater, 0.8 or greater, 1.0 or greater, 1.2 or greater, and / or 1.5 or greater, and / or may also be 10 or less, 8 or less, 7 or less, 6 or less, 5 or less, 4 or less, and / or 3 or less. For example, in an example embodiment in which the stacked structure T20 is applied in field-effect transistors D10, D20, D30, D40, and D50, the thickness of the crystalline metal oxide layer 30 may be greater than 0 nm and less than or equal to 5 nm, and / or the thicknesses of the first surface layer portion 31, the central portion 32, and the second surface layer portion 33 may each be independently greater than 0 nm and / or less than or equal to 3 nm, and / or the thickness ratio of the first surface layer portion 31 and / or the second surface layer portion 33 relative to the central portion 32 may each be independently greater than 0 and less than or equal to 3. In another example embodiment where the stacked structure T20 is applied in capacitors D60 and D70, the thickness of the crystalline metal oxide layer 30 may be greater than 0 nm and / or less than or equal to 10 nm, and / or the thicknesses of the first surface layer portion 31, the central portion 32, and the second surface layer portion 33 may each be independently greater than 0 nm and / or less than or equal to 5 nm, and / or the thickness ratio of the first surface layer portion 31 and / or the second surface layer portion 33 relative to the central portion 32 may each be independently greater than 0 and / or less than or equal to 5. The thicknesses can be measured using methods known in the art, such as an ellipsometry (SE MG-1000, Nano View).

[0102] The boundary between the first surface layer portion 31 and the central portion 32, and / or between the central portion 32 and the second surface layer portion 33, may not be clearly distinguishable.

[0103] The aforementioned thin-film structure and semiconductor device comprising it can be manufactured by forming an amorphous layer having a desired composition on a substrate and annealing the layer. For example, the thin-film structure can be manufactured by sequentially forming a first amorphous layer, a second amorphous layer, and a third amorphous layer on a substrate, annealing the first amorphous layer to form a first antiferroelectric layer corresponding to a portion of the first surface layer, annealing the second amorphous layer to form a ferroelectric layer corresponding to the central portion, and annealing the third amorphous layer to form a second antiferroelectric layer corresponding to a portion of the second surface layer.

[0104] The composition and / or thickness of the first amorphous layer, the second amorphous layer, and the third amorphous layer may correspond to the composition and / or thickness of the first antiferroelectric layer 21, the ferroelectric layer 22, and the second antiferroelectric layer 23 described above. Furthermore, the composition and / or thickness of the first amorphous layer, the second amorphous layer, and the third amorphous layer may correspond to the composition and / or thickness of the first surface layer portion 31, the central portion 32, and the second surface layer portion 33, respectively. The composition and / or thickness of the first antiferroelectric layer, the ferroelectric layer, the second antiferroelectric layer, the first surface layer portion, the central portion, and the second surface layer portion can be referred to the description above.

[0105] The first amorphous layer, the second amorphous layer, and the third amorphous layer can each be formed by conventional methods known in the art. For example, the first amorphous layer, the second amorphous layer, and the third amorphous layer can each be formed independently by deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or sputtering. Among these, the ALD method has the advantages of forming uniform layers on an atomic basis and can be performed at relatively low temperatures.

[0106] When forming the first, second, and third amorphous layers via ALD, the hafnium source, zirconium source, and oxygen source can each use precursors. For example, the hafnium source can use at least one of the following: Hf(OtBu)4, tetra(ethylmethylamino)hafnium (TEMAH), tetra(dimethylamino)hafnium (TDMAH), tetra(diethylamino)hafnium (TDEAH), and / or combinations thereof, but is not limited thereto. Additionally, the zirconium source can use at least one of the following: Zr(OtBu)4, tetra(ethylmethyl)aminozirconium (TEMAZ), tetra(dimethylamino)zirconium (TDMAZ), tetra(diethylamino)zirconium (TDEAZ), and / or combinations thereof, but is not limited thereto. Furthermore, the oxygen source can use at least one of the following: O3, H2O, O2, N2O, O2 plasma, and / or combinations thereof, but is not limited thereto.

[0107] The boundaries between the first amorphous layer and the second amorphous layer, and / or between the second amorphous layer and the third amorphous layer, may not be clearly distinguishable.

[0108] Annealing of the first, second, and third amorphous layers can be performed under appropriate conditions, such that the first, second, and third amorphous layers can be transformed into a first antiferroelectric layer, a ferroelectric layer, and a second antiferroelectric layer, respectively. For example, the annealing of the first and third amorphous layers can be performed independently under conditions that allow the first and third amorphous layers to crystallize into a tetragonal phase. Furthermore, the annealing of the second amorphous layer can be performed under conditions that allow the second amorphous layer to crystallize into an orthorhombic phase.

[0109] For example, annealing can be performed at temperatures ranging from 400°C to 1100°C, but is not limited to this. Annealing can be performed for 1 nanosecond or more, 1 microsecond or more, 0.001 second or more, 0.01 second or more, 0.05 second or more, 0.1 second or more, 0.5 second or more, 1 second or more, 3 seconds or more, and / or 5 seconds or more, and / or 10 minutes or less, 5 minutes or less, 1 minute or less, and / or 30 seconds or less, but is not limited to this.

[0110] Annealing the first amorphous layer, annealing the second amorphous layer, and annealing the third amorphous layer can each be performed individually, and / or two or more of them can be performed simultaneously. For example, the thin film structure can be manufactured by a method comprising: forming a first amorphous layer on a substrate, forming a second amorphous layer on the first amorphous layer, forming a third amorphous layer on the second amorphous layer, and simultaneously annealing the first amorphous layer, the second amorphous layer, and the third amorphous layer to respectively form a first antiferroelectric layer, a ferroelectric layer, and a second antiferroelectric layer. Alternatively, the thin film structure can be manufactured by a method comprising: forming a first amorphous layer on a substrate, forming a first antiferroelectric layer by annealing the first amorphous layer, forming a second amorphous layer on the first antiferroelectric layer, forming a ferroelectric layer by annealing the second amorphous layer, forming a third amorphous layer on the ferroelectric layer, and annealing the third amorphous layer to form a second antiferroelectric layer.

[0111] Capacitors can be manufactured using the thin-film structure manufacturing methods described above. For example, a method of manufacturing a capacitor may include: forming a first amorphous layer, a second amorphous layer, and a third amorphous layer on a substrate including a first conductive electrode; and annealing the first amorphous layer, the second amorphous layer, and the third amorphous layer to respectively form a first antiferroelectric layer corresponding to a portion of the first surface layer, a ferroelectric layer corresponding to a central portion, and a second antiferroelectric layer corresponding to a portion of the second surface layer. A second electrode spaced apart from the first electrode may be formed on the third amorphous layer. The second electrode may be formed before or after annealing the third amorphous layer.

[0112] The thin-film structure manufacturing method described above can also be used to manufacture field-effect transistors. For example, field-effect transistors can be manufactured by a method similar to that described above for manufacturing capacitors, except that a substrate comprising semiconductor material is used and a gate electrode is formed instead of a second electrode. In manufacturing field-effect transistors, it may further be included that a dielectric layer is formed on the substrate comprising semiconductor material and / or that source and drain electrodes are formed on or in the substrate comprising semiconductor material.

[0113] The following describes specific examples of the thin-film structures and semiconductor devices described above. These specific examples are shown to provide details for comparison between these specific examples and some comparative examples, and should not be construed as limiting the description set forth herein.

[0114] Implementation Method 1: Manufacturing ZrO2 (1nm) / Hf including crystals 0.5 Zr 0.5 Capacitors with thin film structures of O2 (3nm) / ZrO2 (1nm).

[0115] The first electrode is formed by DC sputtering.

[0116] An amorphous ZrO2 layer with a thickness of 1 nm was formed on the first electrode using ALD. An amorphous Hf layer with a thickness of 3 nm was then formed on the amorphous ZrO2 layer using ALD. 0.5 Zr 0.5 O2 layer. In the amorphous Hf 0.5 Zr 0.5 An amorphous ZrO2 layer with a thickness of 1 nm is formed on the O2 layer by ALD. As a result, the amorphous ZrO2 layer is deposited on the amorphous Hf layer. 0.5 Zr 0.5 Above and below the O2 layer, and the amorphous Hf 0.5 Zr 0.5 80% or more of the entire surface of the O2 layer is covered by an amorphous ZrO2 layer.

[0117] A second electrode is formed on the top amorphous ZrO2 layer, facing the first electrode. The second electrode is formed by DC sputtering. TiN is used for both the first and second electrodes.

[0118] The layer is subjected to rapid thermal annealing (RTA) at a temperature of 400°C to 1000°C to produce a ZrO2 (1 nm) / Hf layer including crystals. 0.5 Zr 0.5 Capacitor with O2 (3nm) / ZrO2 (1nm) metal oxide layer (thin film structure).

[0119] Implementation Method 2: Manufacturing ZrO2 (1.5nm) / Hf including crystals 0.5 Zr 0.5 Capacitors with O2 (2nm) / ZrO2 (1.5nm) thin film structures.

[0120] On the first electrode, a 1.5 nm thick amorphous ZrO2 layer and a 2 nm thick amorphous Hf layer are sequentially formed in a manner substantially similar to that in Embodiment 1. 0.5 Zr 0.5 An O2 layer and a 1.5 nm thick amorphous ZrO2 layer are used to fabricate a capacitor, except that: an amorphous ZrO2 layer and an amorphous Hf layer are deposited at a different thickness than in Embodiment 1. 0.5 Zr 0.5 O2 layer.

[0121] Implementation Method 3: Manufacturing ZrO2 (1.75nm) / Hf including crystals 0.5 Zr 0.5 Capacitors with O2 (1.5nm) / ZrO2 (1.75nm) thin film structures.

[0122] On the first electrode, a 1.75 nm thick amorphous ZrO2 layer and a 1.5 nm thick amorphous Hf layer are sequentially formed in a manner substantially similar to that in Embodiment 1. 0.5 Zr 0.5 An O2 layer and a 1.75 nm thick amorphous ZrO2 layer are used to fabricate a capacitor, except that: the amorphous ZrO2 layer and the amorphous Hf layer are deposited at a different thickness than in Embodiment 1. 0.5 Zr 0.5 O2 layer.

[0123] Implementation Method 4: Manufacturing ZrO2 (2nm) / Hf including crystals 0.5 Zr 0.5 Capacitors with O2 (1nm) / ZrO2 (2nm) thin film structures.

[0124] On the first electrode, a 2 nm thick amorphous ZrO2 layer and a 1 nm thick amorphous Hf layer are sequentially formed in a manner substantially similar to that in Embodiment 1.0.5 Zr 0.5 An O2 layer and a 2nm thick amorphous ZrO2 layer are used to fabricate a capacitor, except that: an amorphous ZrO2 layer and an amorphous Hf layer are deposited at a different thickness than in Embodiment 1. 0.5 Zr 0.5 O2 layer.

[0125] Implementation Method 5: Manufacturing ZrO2 (2.25nm) / Hf including crystals 0.5 Zr 0.5 Capacitors with O2 (0.5nm) / ZrO2 (2.25nm) thin film structures.

[0126] On the first electrode, a 2.25 nm thick amorphous ZrO2 layer and a 0.5 nm thick amorphous Hf layer are sequentially formed in a manner substantially similar to that in Embodiment 1. 0.5 Zr 0.5 An O2 layer and a 2.25 nm thick amorphous ZrO2 layer are used to fabricate a capacitor, except that: an amorphous ZrO2 layer and an amorphous Hf layer are deposited at a different thickness than in Embodiment 1. 0.5 Zr 0.5 O2 layer.

[0127] Comparative Example 1: Manufacturing Hf consisting only of crystals 0.5 Zr 0.5 Capacitors using O2 (5nm) thin film

[0128] On the first electrode, a capacitor is fabricated in a manner substantially similar to that in Embodiment 1, except that: an amorphous ZrO2 layer is not formed, and an amorphous Hf layer is formed only with a thickness of 5 nm. 0.5 Zr 0.5 O2 layer.

[0129] Comparative Example 2: Fabrication of a capacitor consisting only of a crystalline ZrO2 (5nm) thin film

[0130] On the first electrode, a capacitor is fabricated in a manner substantially similar to that in Embodiment 1, except that: amorphous Hf is not formed. 0.5 Zr 0.5 An O2 layer is formed, and an amorphous ZrO2 layer is formed with a thickness of only 5 nm.

[0131] Comparative Example 3: Manufacturing Hf including crystallization 0.5 Zr 0.5 Capacitors with O2 (2nm) / ZrO2 (5nm) thin film structures

[0132] On the first electrode, a capacitor is fabricated in a manner substantially similar to that in Embodiment 1, except that: a first amorphous ZrO2 layer with a thickness of 1 nm is not formed, and an amorphous Hf layer with a thickness of 2 nm is sequentially formed on the first electrode.0.5 Zr 0.5 An O2 layer and a 5nm thick amorphous ZrO2 layer.

[0133] Electrical property 1

[0134] The PE hysteresis curves were measured in Embodiment 1, Embodiment 2, Comparative Example 1, and Comparative Example 3, and the anti-electric field is shown in Table 1 below. Referring to Table 1, the first antiferroelectric layer (ZrO2) / ferroelectric layer (Hf) are included. 0.5 Zr 0.5 The capacitors of Embodiments 1 and 2, which consist of a ZrO2 / second antiferroelectric layer (ZrO2) structure, exhibit a low back electric field of less than 1.0 MV / cm in their PE hysteresis curves. Therefore, it is confirmed that, compared to capacitors containing only a ZrO2 / second antiferroelectric layer (ZrO2) structure, the capacitors of Embodiments 1 and 2 have a low back electric field of less than 1.0 MV / cm in their 0.5 Zr 0.5 Comparative Example 1 (O2) and Example 2 (containing only the ferroelectric layer (Hf)) 0.5 Zr 0.5 Compared to Comparative Example 3, which uses an O2) / antiferroelectric layer (ZrO2), the capacitors of Embodiments 1 and 2 exhibit lower hysteresis.

[0135] [Table 1]

[0136]

[0137] Electrical property 2

[0138] The capacitance of the capacitors in Embodiments 1 to 5 and Comparative Examples 1 and 2 was measured and is shown in Table 2. Referring to Table 2, it is confirmed that the capacitors including the first antiferroelectric layer (ZrO2) / ferroelectric layer (Hf)... 0.5 Zr 0.5 The capacitors of embodiments 1 to 5, wherein the thickness ratio of the antiferroelectric layer to the ferroelectric layer is greater than 0 and less than or equal to 10, have a greater than or equal to a structure consisting only of a ferroelectric layer (Hf) / a second antiferroelectric layer (ZrO2). 0.5 Zr 0.5 The capacitor in Comparative Example 1 (O2) has a higher capacitance. Furthermore, it was confirmed that the capacitor only includes the ferroelectric layer (Hf) has a higher capacitance. 0.5 Zr 0.5 Compared to the capacitors of Comparative Example 1 (O2) and Comparative Example 2 (which only includes an antiferroelectric layer (ZrO2), the capacitors of Embodiments 2 to 5, in which the thickness ratio of the antiferroelectric layer to the ferroelectric layer is 0.5 or greater and 10 or less, have higher capacitance.

[0139] [Table 2]

[0140]

[0141] Electrical property 3

[0142] The dielectric constants of the capacitors in Embodiments 2 to 5 and Comparative Examples 1 to 3 were measured and are shown in Table 3. Referring to Table 3, it is confirmed that the dielectric constants of capacitors comprising only the ferroelectric layer (Hf) are... 0.5 Zr 0.5 Comparative Example 1 (containing only antiferroelectric layer (ZrO2)), Comparative Example 2 (containing only antiferroelectric layer (ZrO2)), and Comparative Example 3 (containing only ferroelectric layer (HfO2)) 0.5 Zr 0.5 Compared to the capacitor in Comparative Example 3, which includes a first antiferroelectric layer (ZrO2) / ferroelectric layer (HfO2), the capacitor in Comparative Example 3 with an antiferroelectric layer (ZrO2) / ferroelectric layer (HfO2) is significantly different. 0.5 Zr 0.5 The capacitors of embodiments 2 to 5, wherein the thickness ratio of the antiferroelectric layer to the ferroelectric layer is 0.5 or greater and 10 or less, have a higher dielectric constant and therefore a higher capacitance.

[0143] [Table 3]

[0144]

[0145] Implementation Method 6: Manufacturing p-Si / SiO2 / ZrO2 (0.5nm) / Hf 0.5 Zr 0.5 A capacitor with an O2 (1nm) / ZrO2 (0.5nm) / electrode structure.

[0146] Prepare a polycrystalline silicon (p-Si) substrate and partially oxidize the surface to form a silicon oxide (SiO2) layer.

[0147] An amorphous ZrO2 layer with a thickness of 0.5 nm is formed on the silicon oxide (SiO2) layer by ALD. An amorphous Hf layer with a thickness of 1 nm is then formed on the amorphous ZrO2 layer by ALD. 0.5 Zr 0.5 O2 layer. In the amorphous Hf 0.5 Zr 0.5 An amorphous ZrO2 layer with a thickness of 0.5 nm is formed on the O2 layer by ALD. An electrode is formed on the amorphous ZrO2 layer by DC sputtering. TiN is used for the electrode.

[0148] The resulting structure was subjected to RTA at temperatures ranging from 400°C to 1100°C to produce ZrO2 (0.5 nm) / Hf, including crystalline structures. 0.5 Zr 0.5 Capacitor with O2 (1nm) / ZrO2 (0.5nm) metal oxide layer (thin film structure).

[0149] Comparative Example 4: Fabrication of p-Si / SiO2 / Hf 0.5 Zr 0.5Capacitor with O2(2nm) / electrode structure.

[0150] On the silicon oxide (SiO2) layer, the capacitor is fabricated in a manner substantially similar to that in Embodiment 6, except that: an amorphous ZrO2 layer is not formed, and an amorphous Hf layer is formed only at a thickness of 2 nm. 0.5 Zr 0.5 O2 layer.

[0151] Comparative Example 5: Fabrication of a capacitor with a p-Si / SiO2 / ZrO2 (2nm) / electrode structure.

[0152] A capacitor is fabricated on a silicon oxide (SiO2) layer in a manner substantially similar to that in Embodiment 6, except that amorphous Hf is not formed. 0.5 Zr 0.5 An O2 layer is formed, and an amorphous ZrO2 layer is formed with a thickness of only 2 nm.

[0153] Comparative Example 6: Fabrication of p-Si / SiO2 / Hf 0.5 Zr 0.5 A capacitor with an O2 (1.5nm) / ZrO2 (0.5nm) / electrode structure.

[0154] A capacitor is fabricated on the silicon oxide (SiO2) layer in a manner substantially similar to that in Embodiment 6, except that: an amorphous ZrO2 layer is not formed, and amorphous Hf with a thickness of 1.5 nm is sequentially formed on the silicon oxide (SiO2) layer. 0.5 Zr 0.5 An O2 layer and a 0.5 nm thick amorphous ZrO2 layer.

[0155] Electrical property 4

[0156] The equivalent oxide thickness (EOT) of the capacitors in Embodiment 6 and Comparative Examples 4 to 6 is shown in Table 4. Referring to Table 4, it is confirmed that, compared with capacitors consisting only of the ferroelectric layer (Hf... 0.5 Zr 0.5 Comparative Example 4 (containing only an antiferroelectric layer (ZrO2)), Comparative Example 5 (containing only an antiferroelectric layer (ZrO2)), and Comparative Example 6 (containing only a ferroelectric layer (HfO2)). 0.5 Zr 0.5 Compared to the capacitor of Comparative Example 6 with O2 / antiferroelectric layer (ZrO2), the capacitor of Embodiment 6 has a lower EOT.

[0157] For reference, regarding metal-oxide-silicon (MOS) capacitors having the same structure as in Embodiment 6 and Comparative Examples 4 to 6, as a structure similar to a field-effect transistor, it is known that the performance of a MOS capacitor corresponds to the performance of a field-effect transistor.

[0158] [Table 4]

[0159]

[0160] Implementation Method 7: Manufacturing a product comprising ZrO2 (0.5nm) / Hf 0.5 Zr 0.5 Field-effect transistors with O2 (1nm) / ZrO2 (0.5nm) thin film structures.

[0161] In addition to forming the source and drain electrodes in the polycrystalline silicon (p-Si) substrate, a SiO2 layer, an amorphous ZrO2 layer (0.5 nm), and an amorphous Hf layer are sequentially formed on the polycrystalline silicon (p-Si) substrate in a manner substantially similar to that in Embodiment 6. 0.5 Zr 0.5 An O2 layer (1 nm) and an amorphous ZrO2 layer (0.5 nm) are formed, and TiN is formed as the gate electrode, thereby fabricating a field-effect transistor. Here, the field-effect transistor is fabricated in the form of a Fin-FET using methods known in the art, such as photolithography and etching.

[0162] Implementation Method 8: Manufacturing a product comprising ZrO2 (0.25nm) / Hf 0.5 Zr 0.5 Field-effect transistors with O2 (1.5nm) / ZrO2 (0.25nm) thin film structures.

[0163] On the silicon oxide (SiO2) layer, a 0.25 nm thick amorphous ZrO2 layer and a 1.5 nm thick amorphous Hf layer are sequentially formed in a manner substantially similar to that in Embodiment 7. 0.5 Zr 0.5 O2 layer and 0.25nm thick amorphous ZrO2 layer are used to fabricate field-effect transistors, except for the following: amorphous ZrO2 layer and amorphous Hf 0.5 Zr 0.5 The thickness of the O2 layer varies.

[0164] Comparative Example 7: Manufacturing including Hf 0.5 Zr 0.5 Field-effect transistors with O2 (2nm) thin film structures.

[0165] On the silicon oxide (SiO2) layer, a field-effect transistor is fabricated in a manner substantially similar to that in Embodiment 7, except that: an amorphous ZrO2 layer is not formed, and an amorphous Hf layer is formed only at a thickness of 2 nm. 0.5 Zr 0.5 O2 layer.

[0166] Comparative Example 8: Fabrication of a field-effect transistor including a ZrO2 (2nm) thin film structure.

[0167] Field-effect transistors are fabricated on a silicon oxide (SiO2) layer in a manner substantially similar to that in Embodiment 7, except that amorphous Hf is not formed. 0.5 Zr 0.5 An O2 layer is formed, and an amorphous ZrO2 layer is formed with a thickness of only 2 nm.

[0168] Electrical property 5

[0169] Table 5 shows the subthreshold swing values ​​SS of the field-effect transistors of Embodiments 7, 8, Comparative Example 7, and Comparative Example 8. The subthreshold swing value is the rate of change of the leakage current relative to the gate voltage, and can be obtained by measuring the slope of the Id-Vg characteristic of the transistor (SS = ΔId / ΔVg). The subthreshold swing values ​​SS in Table 5 are values ​​measured at a distance of 0.2 to 0.25 V from the threshold voltage. Referring to Table 5, it is confirmed that, compared with transistors containing only the ferroelectric layer (Hf... 0.5 Zr 0.5 Compared to the field-effect transistors of Comparative Example 7 (which includes only an antiferroelectric layer (ZrO2)) and Comparative Example 8 (which includes only an antiferroelectric layer (ZrO2)), the field-effect transistors of Embodiments 7 and 8 have a lower subthreshold swing value SS.

[0170] [Table 5]

[0171]

[0172]

[0173] Based on the above embodiments, thin-film structures with negative capacitance effects can be provided. Semiconductor devices with low hysteresis, improved capacitance, and / or improved subthreshold swing values ​​(SS) can be provided in response to changes in the polarization intensity of an external electric field. These thin-film structures and semiconductor devices can be applied to various electronic devices, electronic equipment, electronic circuits, etc. Although embodiments have been described in detail above, the scope of the claims is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept defined in the appended claims also fall within the scope of the claims.

[0174] It should be understood that the embodiments described herein are to be considered in the descriptive sense only and are not intended for limiting purposes. The descriptions of features or aspects in each embodiment should be typically considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A multilayered structure, including: Base; and A thin film structure on the substrate, the thin film structure comprising The first antiferroelectric layer on the substrate, The second antiferroelectric layer on the substrate, and The ferroelectric layer between the first antiferroelectric layer and the second antiferroelectric layer The ferroelectric layer is capacitance-matched to at least one of the first antiferroelectric layer and the second antiferroelectric layer. The thicknesses of the first and second antiferroelectric layers are independently in the range of 1.5 nm to 3 nm, and the thickness of the ferroelectric layer is in the range of 0.4 nm to 2 nm. The thickness ratio of the first antiferroelectric layer and / or the second antiferroelectric layer relative to the ferroelectric layer is greater than 0.6 and less than or equal to 5.

2. The stacked structure of claim 1, wherein at least one of the first antiferroelectric layer and the second antiferroelectric layer covers 80% or more of the surface of the ferroelectric layer.

3. The stacked structure as claimed in claim 1, wherein at least one of the first antiferroelectric layer and the second antiferroelectric layer is in direct contact with the ferroelectric layer.

4. The stacked structure according to claim 1, wherein at least one of the ferroelectric layer, the first antiferroelectric layer, and the second antiferroelectric layer independently includes hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium-zirconium oxide Hf x Zr 1-x O2 of at least one kind.

5. The stacked structure of claim 4, wherein the ferroelectric layer comprises Hf with 0.2 ≤ x < 1. x Zr 1-x O2 represents hafnium-zirconium oxide.

6. The stacked structure according to claim 4, wherein each of the first antiferroelectric layer and the second antiferroelectric layer independently includes at least one of zirconia and hafnium-zirconium oxide represented by Hf x x Zr 1-x O2 with 0 < x < 0.

2.

7. The stacked structure as claimed in claim 4, wherein the hafnium content of the ferroelectric layer is greater than the hafnium content of one or more of the first antiferroelectric layer and the second antiferroelectric layer.

8. The stacked structure of claim 4, wherein the molar ratio of hafnium element in at least one of the first antiferroelectric layer and the second antiferroelectric layer to hafnium element in the ferroelectric layer is in the range of 0 to 0.

8.

9. The stacked structure as claimed in claim 4, wherein the zirconium content of the ferroelectric layer is less than the zirconium content of one or more of the first antiferroelectric layer and the second antiferroelectric layer.

10. The stacked structure of claim 4, wherein the molar ratio of zirconium element in the ferroelectric layer to zirconium element in at least one of the first antiferroelectric layer and the second antiferroelectric layer is in the range of 0 to 1.

11. The stacked structure of claim 4, wherein at least one of the ferroelectric layer, the first antiferroelectric layer and the second antiferroelectric layer comprises one or more dopant materials, wherein the dopant materials comprise at least one of C, Si, Ge, Sn, Pb, Al, Y, La, Gd, Mg, Ca, Sr, Ba, Ti, Zr and Hf.

12. The stacked structure of claim 11, wherein the content of dopant material in the ferroelectric layer is less than the content of dopant material in at least one of the first antiferroelectric layer and the second antiferroelectric layer.

13. The stacked structure of claim 11, wherein the ferroelectric layer has a dopant content in the range of 0 atomic% to 10 atomic% compared to the metallic elements of the substrate material.

14. The stacked structure of claim 11, wherein the first antiferroelectric layer and the second antiferroelectric layer each independently have a dopant material content in the range of 4 atomic% to 20 atomic% compared with the metal element content of the substrate material.

15. The stacked structure of claim 1, wherein the ferroelectric layer has an orthorhombic crystal structure, and The first antiferroelectric layer and the second antiferroelectric layer have a tetragonal crystal structure.

16. The stacked structure of claim 1, wherein the thin film structure further comprises a paraelectric layer.

17. The stacked structure of claim 16, wherein the paraelectric layer is between the ferroelectric layer and at least one of the first antiferroelectric layer or the second antiferroelectric layer.

18. The stacked structure of claim 16, wherein the paraelectric layer comprises at least one of the following: aluminum oxide (Al2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and silicon oxide (SiO2).

19. A semiconductor device, comprising a stacked structure as described in any one of claims 1-18.

20. The semiconductor device of claim 19, further comprising: First electrode; and A second electrode spaced apart from the first electrode. The stacked structure is located between the first electrode and the second electrode, and the substrate includes at least one of the first electrode and the second electrode.

21. The semiconductor device of claim 20, wherein, The coercive electric field of the semiconductor device is 1 MV / cm or less, depending on the change in polarization intensity of the external electric field.

22. The semiconductor device of claim 19, further comprising: A semiconductor layer containing source and drain electrodes; and The gate electrode on the semiconductor layer, The thin film structure is located between the semiconductor layer and the gate electrode, and The semiconductor layer or one of the gate electrodes corresponds to the substrate.

23. The semiconductor device of claim 22, wherein the sum of the thicknesses of the first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer is greater than 0 nm and less than or equal to 5 nm.

24. The semiconductor device of claim 22, further comprising: The dielectric layer between the semiconductor layer and the gate electrode.

25. The semiconductor device of claim 24, wherein the dielectric layer comprises a paraelectric layer.

26. The semiconductor device of claim 24, wherein the dielectric layer comprises at least one of the following: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide.

27. The semiconductor device of claim 24, wherein the thickness of the dielectric layer is in the range of 0.1 nm to 5 nm.

28. The semiconductor device of claim 22, wherein, The coercive electric field of the semiconductor device is 1 MV / cm or less, depending on the change in polarization intensity of the external electric field.

29. The semiconductor device of claim 22, wherein the hysteresis window of the semiconductor device at an operating voltage of 1 V in the voltage-to-current curve is 10 mV or less.

30. The semiconductor device of claim 22, wherein the semiconductor device has non-storage characteristics.

31. A semiconductor device comprising the semiconductor device as described in claim 20 or 21, the semiconductor device further comprising: A field-effect transistor includes a semiconductor layer comprising a source and a drain, a dielectric layer on the semiconductor layer, and a gate electrode on the dielectric layer. The field-effect transistor and the semiconductor device are electrically connected to each other.

32. An electronic device comprising a semiconductor device as claimed in any one of claims 19-30 or a semiconductor device as claimed in claim 31.

33. A method for manufacturing a laminated structure, comprising: A first amorphous layer is formed on the substrate; A second amorphous layer is formed on the substrate; A third amorphous layer is formed on the substrate; The first amorphous layer is annealed to form the first antiferroelectric layer; The second amorphous layer is annealed to form a ferroelectric layer; and The third amorphous layer is annealed to form the second antiferroelectric layer. The ferroelectric layer is capacitance-matched to at least one of the first antiferroelectric layer and the second antiferroelectric layer. The thicknesses of the first and second antiferroelectric layers are independently in the range of 1.5 nm to 3 nm, and the thickness of the ferroelectric layer is in the range of 0.4 nm to 2 nm. The thickness ratio of the first antiferroelectric layer and / or the second antiferroelectric layer relative to the ferroelectric layer is greater than 0.6 and less than or equal to 5.

34. The method of claim 33, wherein the first antiferroelectric layer, the ferroelectric layer, and the second antiferroelectric layer are formed parallel to the substrate.

35. The method of claim 34, wherein the first amorphous layer, the second amorphous layer, and the third amorphous layer are sequentially formed on the substrate in the thickness direction of the substrate.

36. The method of claim 33, wherein at least two of the annealing of the first amorphous layer, the annealing of the second amorphous layer, and the annealing of the third amorphous layer are performed simultaneously.

37. The method of claim 33, further comprising: Electrodes are provided on the second antiferroelectric layer.

38. The method of claim 37, wherein the substrate comprises a conductor.

39. The method of claim 37, wherein the stacked structure is included in a capacitor.

40. The method of claim 37, wherein the substrate comprises a semiconductor material.

41. The method of claim 40, further comprising: A source electrode is formed in the substrate; and A drain electrode is formed in the substrate.

42. The method of claim 40, wherein the stacked structure is included in a transistor.

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