Display device

Abstract

A display device includes: a plurality of pixels on a substrate, each of the plurality of pixels including a light-emitting element and a pixel circuit configured to drive the light-emitting element, wherein the pixel circuit of each of the plurality of pixels includes: a first-first transistor configured to control a drive current flowing through the light-emitting element based on a voltage of a first node; a first-second transistor connected in series with the first-first transistor and configured to control the drive current based on a voltage of a second node; a second transistor configured to selectively supply a data voltage to a third node that is a first electrode of the first-first transistor; a third-first transistor connected between the first node and a fourth node that is a second electrode of the first-second transistor; and a third-second transistor connected between the second node and the fourth node.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0066455, filed on June 2, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some aspects of exemplary embodiments of this disclosure relate to display devices. Background Technology

[0004] With the development of an information-oriented society, increasing demands are being placed on display devices for displaying images in various ways. For example, display devices are used in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays, such as liquid crystal displays, field emission displays, and organic light-emitting diode (OLED) displays. In flat panel displays, particularly in OLED displays, images can be displayed without utilizing a backlight unit that provides light to the display panel because each pixel in the display panel can include a self-illuminating element.

[0005] Each of the multiple pixels in a display panel may include multiple thin-film transistors (TFTs). Each TFT can be turned on based on a signal applied to its gate electrode. However, when a TFT switches from an on state to an off state, leakage current may flow due to the electric field between the channel region and the source / drain region of the TFT. Leakage current can reduce pixel brightness.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] Some exemplary embodiments of this disclosure include a display device that can improve image quality by reducing leakage current flowing through transistors in pixel circuitry and prevent or reduce flicker by suppressing pixel brightness degradation during low-frequency driving.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description of exemplary embodiments according to the disclosure.

[0009] According to some exemplary embodiments of this disclosure, a display device includes a plurality of pixels on a substrate, each of the plurality of pixels including a light-emitting element and a pixel circuit for driving the light-emitting element. The pixel circuit of each of the plurality of pixels includes: a first-first transistor that controls a drive current flowing through the light-emitting element based on a voltage of a first node; a first-second transistor connected in series with the first-first transistor and controlling the drive current based on a voltage of a second node; a second transistor that selectively supplies a data voltage to a third node that is a first electrode of the first-first transistor; a third-first transistor connected between the first node and a fourth node that is a second electrode of the first-second transistor; and a third-second transistor connected between the second node and the fourth node.

[0010] According to some example embodiments, the second transistor, the third-first transistor, and the third-second transistor can be turned on based on a first gate signal received from the first gate line.

[0011] According to some example embodiments, the pixel circuit may further include: a first capacitor connected between the first node and the driving voltage line; and a second capacitor connected between the second node and the driving voltage line.

[0012] According to some example embodiments, the first transistor may include: a first electrode extending in a first direction; an active region connected to the first electrode and bent in a second direction intersecting the first direction; a second electrode connected to the active region and bent in the first direction; and a gate electrode on the active region and overlapping the active region in the thickness direction.

[0013] According to some example embodiments, the first-second transistor may include: a first electrode, connected to a second electrode of the first-second transistor and bent in a second direction; an active region, connected to the first electrode of the first-second transistor and bent in a first direction; a second electrode, connected to the active region of the first-second transistor and extending in a first direction; and a gate electrode, on the active region of the first-second transistor and overlapping the active region of the first-second transistor in the thickness direction.

[0014] According to some example embodiments, the pixel circuit may further include capacitor electrodes on the gate electrodes of the first transistor and the gate electrodes of the second transistor. A first capacitor may be formed between the gate electrode of the first transistor and the capacitor electrode. A second capacitor may be formed between the gate electrode of the first transistor and the capacitor electrode.

[0015] According to some example embodiments, the pixel circuit may further include: a fourth-first transistor connected between the first node and the initialization voltage line; and a fourth-second transistor connected between the first node and the second node.

[0016] According to some example embodiments, the fourth-first transistor and the fourth-second transistor can be turned on based on a second gate signal received from the second gate line.

[0017] According to some example embodiments, the pixel circuit may further include: a fifth transistor connected between the third node and the driving voltage line; and a sixth transistor connected between the fourth node and the fifth node, which is the first electrode of the light-emitting element.

[0018] According to some example embodiments, the fifth and sixth transistors can be turned on based on a transmit signal received from the transmit control line.

[0019] According to some example embodiments, the pixel circuit may further include a seventh transistor connected between the initialization voltage line and the fifth node.

[0020] According to some example embodiments, the seventh transistor can be turned on based on a third gate signal received from the third gate line.

[0021] According to some exemplary embodiments of this disclosure, a display device includes a plurality of pixels on a substrate, each of the plurality of pixels including a light-emitting element and a pixel circuit for driving the light-emitting element. The pixel circuit of each of the plurality of pixels includes: a first-first transistor, which controls a drive current flowing through the light-emitting element based on a voltage at a first node; a first-second transistor, connected in series with the first-first transistor and controlling the drive current based on a voltage at a second node; a first capacitor, connected between the first node and a drive voltage line; and a second capacitor, connected between the second node and the drive voltage line.

[0022] According to some example embodiments, the pixel circuit may further include: a second transistor selectively supplying a data voltage to a third node that is a first electrode of the first transistor; a third-first transistor connected between the first node and a fourth node that is a second electrode of the first-second transistor; a third-second transistor connected between the second node and the fourth node; a fourth-first transistor connected between the first node and an initialization voltage line; and a fourth-second transistor connected between the first node and the second node.

[0023] According to some example embodiments, the second transistor, the third-first transistor, and the third-second transistor can be turned on based on a first gate signal received from the first gate line.

[0024] According to some example embodiments, the fourth-first transistor and the fourth-second transistor can be turned on based on a second gate signal received from the second gate line.

[0025] According to some example embodiments, the pixel circuit may further include: a fifth transistor connected between the third node and the driving voltage line; and a sixth transistor connected between the fourth node and the fifth node, which is the first electrode of the light-emitting element.

[0026] According to some example embodiments, the fifth and sixth transistors can be turned on based on a transmit signal received from the transmit control line.

[0027] According to some example embodiments, the pixel circuit may further include a seventh transistor connected between the initialization voltage line and the fifth node.

[0028] According to some example embodiments, the seventh transistor can be turned on based on a third gate signal received from the third gate line.

[0029] According to some example embodiments, the display device includes a first-first transistor and a first-second transistor connected in series, thereby increasing the driving range of the gate voltages of the first-first transistor and the first-second transistor. In the display device, by increasing the driving range of the gate voltages of the first-first transistor and the first-second transistor, the grayscale of the light emitted from the light-emitting element can be controlled more precisely, resulting in relatively improved display quality and relatively improved resolution of the display device. Furthermore, because the display device includes the first-first transistor and the first-second transistor, hysteresis can be reduced, thereby reducing image retention in the display device.

[0030] According to some example embodiments, the display device includes a third-first transistor connected to the gate electrode of a first-first transistor and a third-second transistor connected to the gate electrode of a first-second transistor, thereby minimizing leakage current at the gate electrodes of the first-first transistor and the first-second transistor. In the display device, image quality can be improved by reducing leakage current flowing through the pixel circuit, and flicker can be prevented or reduced by suppressing pixel brightness degradation during low-frequency driving.

[0031] The features of the embodiments according to this disclosure are not limited to the effects described above, and various other effects are included in this specification. Attached Figure Description

[0032] The above and other aspects and features of embodiments of the present disclosure will become more apparent from the accompanying drawings, which describe aspects of some exemplary embodiments of the present disclosure in more detail, in which:

[0033] Figure 1This is a perspective view illustrating a display device according to some example embodiments;

[0034] Figure 2 This is an exploded perspective view illustrating a display device according to some example embodiments;

[0035] Figure 3 This is a plan view of a display panel according to some example embodiments;

[0036] Figure 4 This is a block diagram illustrating a display panel and a display driving unit according to some example embodiments;

[0037] Figure 5 This is a circuit diagram illustrating the pixels of a display device according to some example embodiments;

[0038] Figure 6 It is provided according to some example embodiments. Figure 5 The waveform diagram of the signal of the pixel shown in the figure;

[0039] Figure 7 The illustration shows some example embodiments. Figure 5 The circuit diagram illustrates an example of leakage current in a pixel.

[0040] Figure 8 The illustration shows some example embodiments. Figure 5 The circuit diagram shows another example of leakage current in a pixel illustrated in the figure.

[0041] Figure 9 The diagram illustrates a plan view of the first-first transistor and the first-second transistor of a display device according to some example embodiments; and

[0042] Figure 10 It is based on some example embodiments along Figure 9 The cross-sectional view taken from line I-I'. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, the terms "embodiment" and "implementation" are interchangeable terms, referring to non-limiting examples of one or more apparatuses or methods of the inventive concept disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily mutually exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used in or implemented in another exemplary embodiment without departing from the inventive concept.

[0044] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing example features of different details of how the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0045] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of crosshairs or shading does not express or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific sequence of processes may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously, or may be performed in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0046] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly" on, directly connected to, or directly coupled to another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0048] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another(s) illustrated in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture, in addition to those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Thus, the example term “below” can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein may be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” specify the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or provided values ​​that would be recognized by those skilled in the art.

[0050] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific shapes of the illustrated areas, but will include, for example, deviations in shape due to manufacturing processes. In this way, the areas illustrated in the figures can indeed be schematic, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0051] Some exemplary embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, which can be formed using semiconductor-based or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry systems) for performing other functions. Furthermore, each block, unit, and / or module of some exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of the inventive concept. Furthermore, some of the blocks, units, and / or modules in the example embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the inventive concept.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in common dictionaries shall be interpreted as having meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal manner unless expressly defined herein.

[0053] Figure 1 This is a perspective view illustrating a display device according to some example embodiments. Figure 2 This is an exploded perspective view illustrating a display device according to some example embodiments.

[0054] refer to Figure 1 and Figure 2 The display device 10 includes a cover window 100, a display panel 300, a bracket 600, a main circuit board 700, and a lower cover 900.

[0055] As used herein, the terms “above,” “top,” and “upper surface” refer to the upward direction (i.e., the Z-axis direction) relative to the display device 10. The terms “below,” “bottom,” and “lower surface” refer to the downward direction (i.e., the direction opposite to the Z-axis direction) relative to the display device 10. Furthermore, “left,” “right,” “up,” and “down” indicate the direction when viewing the display device 10 from above. For example, the term “left” indicates the direction opposite to the X-axis direction, the term “right” indicates the X-axis direction, the term “up” indicates the Y-axis direction, and the term “down” indicates the direction opposite to the Y-axis direction.

[0056] Display device 10 is a device for displaying moving images (e.g., video images) or still images (e.g., static images). Display device 10 can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs).

[0057] The display device 10 can have a rectangular shape in a plan view. For example, as shown in the figure. Figure 1 and Figure 2As shown, the display device 10 may have a rectangular shape in a plan view, having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded to have curvature (e.g., a set or predetermined curvature) or may be a right angle. The planar shape of the display device 10 is not limited to a rectangular shape, and may be formed into other polygonal shapes, circular shapes, or elliptical shapes.

[0058] The cover window 100 can be set or arranged on the display panel 300 to cover the top surface of the display panel 300. The cover window 100 can protect the top surface of the display panel 300.

[0059] The cover window 100 may include a transmissive area TA corresponding to the display area DA of the display panel 300 and a non-transmissive area NTA corresponding to the non-display area NDA of the display panel 300. For example, the non-transmissive area NTA may be formed opaquely. As another example, the non-transmissive area NTA may be formed as a patterned decorative layer that can be displayed to the user when the image is not displayed.

[0060] The display panel 300 can be positioned or arranged below the cover window 100. Therefore, the image displayed by the display panel 300 can be viewed from the top surface of the display device 10 through the cover window 100.

[0061] Display panel 300 may be a light-emitting display panel that includes light-emitting elements. For example, display panel 300 may be an organic light-emitting display panel that uses organic light-emitting diodes that include organic light-emitting layers, a micro light-emitting diode display panel that uses micro LEDs, a quantum dot light-emitting display panel that uses quantum dot light-emitting diodes that include quantum dot light-emitting layers, or an inorganic light-emitting display panel that uses inorganic light-emitting diodes that include inorganic semiconductors.

[0062] The display panel 300 may include a display area DA and a non-display area NDA.

[0063] The display area DA can be set or arranged to overlap with the transmissive area TA of the cover window 100. The display area DA may include multiple pixels displaying an image, and the non-display area NDA, which is the outer region of the display area DA, may not display an image. For example, the non-display area NDA may surround the display area DA, but the embodiments according to this disclosure are not limited thereto. The display area DA may occupy a large portion of the display panel 300.

[0064] For example, display panel 300 may include a touch electrode layer for sensing objects such as a human finger or pen. The touch electrode layer may include multiple touch electrodes and may be disposed or arranged on a display layer in which multiple pixels are disposed or arranged.

[0065] The display panel 300 may include a display driver 310, a circuit board 320, a power supply unit 330, and a touch driver 340.

[0066] The display driver 310 can output signals and voltages for driving the display panel 300. For example, the display driver 310 can supply data voltage to the data line. The display driver 310 can supply drive voltage or source voltage to the drive voltage line, and can supply gate control signals to the gate driver.

[0067] The circuit board 320 can be attached to the pad portion of the display panel 300 using an anisotropic conductive film (ACF). The leads of the circuit board 320 can be electrically connected to the pad portion of the display panel 300. For example, the circuit board 320 can be a flexible film such as a flexible printed circuit board, a printed circuit board (PCB), or a chip on film (COF).

[0068] The power supply unit 330 can be disposed or arranged on the circuit board 320 to supply driving voltage to the display driver 310 and the display panel 300. Specifically, the power supply unit 330 can generate a driving voltage and supply it to the driving voltage line, and can generate a common voltage and supply it to the low potential line. For example, the driving voltage can be a high potential voltage for driving the light-emitting element, and the common voltage can be a low potential voltage for driving the light-emitting element.

[0069] The touch driver 340 can be set or arranged on the circuit board 320 to measure the capacitance of the touch electrodes. For example, the touch driver 340 can determine whether a user has touched the object and the location of the user's touch based on changes in the capacitance of the touch electrodes. Here, a user's touch means that an object such as a user's finger or a pen is in direct contact with a surface of the display device 10 that is set or arranged on the touch electrode layer. The touch driver 340 can determine the user's touch location by distinguishing between the portions of the multiple touch electrodes where the user's touch occurs and the portions where the user's touch does not occur.

[0070] The bracket 600 may be positioned or arranged below the display panel 300. The bracket 600 may be made of plastic, metal, or a combination thereof. For example, the bracket 600 may include a first camera hole CMH1 in which a first camera sensor 720 is inserted, a battery hole BH in which a battery is positioned or arranged, and a cable hole CAH through which a cable connected to the display driver 310 or the circuit board 320 passes.

[0071] The main circuit board 700 and the battery 790 can be positioned or arranged below the bracket 600. The main circuit board 700 can be a printed circuit board or a flexible printed circuit board.

[0072] The main circuit board 700 may include a main processor 710, a first camera sensor 720, and a main connector 730. The first camera sensor 720 may be disposed on or arranged on both the top and bottom surfaces of the main circuit board 700, the main processor 710 may be disposed on or arranged on the top surface of the main circuit board 700, and the main connector 730 may be disposed on or arranged on the bottom surface of the main circuit board 700.

[0073] The main processor 710 can control all functions of the display device 10. For example, the main processor 710 can supply digital video data to the display driver 310, causing the display panel 300 to display an image. The main processor 710 can receive touch data from the touch driver 340 and determine the user's touch coordinates, and then execute the application indicated by the icon displayed at the user's touch coordinates.

[0074] The main processor 710 can convert the first image data input from the first camera sensor 720 into digital video data, and output the digital video data to the display driver 310 through the circuit board 320, thereby displaying the image captured by the first camera sensor 720 on the display panel 300.

[0075] The first camera sensor 720 can process image frames of still images or video images obtained by the image sensor and output the image frames to the main processor 710. For example, the first camera sensor 720 can be a CMOS image sensor or a CCD sensor, but embodiments according to this disclosure are not limited thereto. The first camera sensor 720 can be exposed on the lower surface of the lower cover 900 through the second camera hole CMH2 and capture images of backgrounds or objects set or arranged below the display device 10.

[0076] The main connector 730 can be connected to the cable 415 that has passed through the cable hole CAH of the bracket 600. Therefore, the main circuit board 700 can be electrically connected to the display driver 310 or the circuit board 320.

[0077] The battery 790 can be configured or arranged so that it does not overlap with the main circuit board 700 in the third direction (Z-axis direction). The battery 790 can overlap with the battery hole BH of the bracket 600.

[0078] The main circuit board 700 may further include a mobile communication module capable of transmitting and receiving radio signals with at least one of a base station, external terminal, and server in a mobile communication network. The wireless signals may include various types of data, depending on the transmission and reception of voice signals, video call signals, or text / multimedia messages.

[0079] The lower cover 900 can be positioned or arranged below the main circuit board 700 and the battery 790. The lower cover 900 can be secured by fastening it to the bracket 600. The lower cover 900 can form the appearance of the bottom surface of the display device 10. The lower cover 900 can be made of plastic, metal, or a combination thereof.

[0080] The lower cover 900 may include a lower surface of the first camera sensor 720 through which a second camera hole CMH2 is exposed. The location of the first camera sensor 720 and the locations of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the first camera sensor 720 are not limited to... Figure 2 The embodiment is illustrated in the figure.

[0081] Figure 3 This is a plan view of a display panel according to some example embodiments. Figure 4 This is a block diagram illustrating a display panel and a display driving unit according to some example embodiments.

[0082] refer to Figure 3 and Figure 4 The display panel 300 may include a display area DA and a non-display area NDA.

[0083] The display area DA may include multiple pixels SP, a gate line GL, an emission control line EML, a data line DL, and a drive voltage line VDDL connected to the multiple pixels SP.

[0084] A pixel SP can be connected to at least one gate line GL, at least one data line DL, at least one emitter control line EML, and at least one drive voltage line VDDL. Figure 3 and Figure 4 In this embodiment, each pixel SP can be connected to two gate lines GL, one data line DL, one transmit control line EML, and one drive voltage line VDDL, but embodiments according to this disclosure are not limited thereto. For example, each pixel SP can be connected to three or more gate lines GL.

[0085] Each pixel SP may include a light-emitting element, a capacitor, and at least one transistor.

[0086] Pixel SP can receive driving voltage VDD through driving voltage line VDDL. Here, driving voltage VDD can be a high potential voltage used to drive the light-emitting element of pixel SP.

[0087] The gate line GL and the emitter control line EML can extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction) that intersects the first direction (X-axis direction).

[0088] The data line DL and the drive voltage line VDDL can extend in a second direction (Y-axis direction) and can be spaced apart from each other in a first direction (X-axis direction).

[0089] The non-display area NDA can be defined as the remaining area of ​​the display panel 300 excluding the display area DA. The non-display area NDA may include a gate driver 410 for applying gate signals to gate lines GL, a transmit control driver 420 for applying transmit signals to transmit control lines EML, a fan-out line FL connecting data lines DL to the display driver 310, and pads DP connected to the circuit board 320. The display driver 310 and pads DP may be positioned or arranged within the pad area of ​​the display panel 300. Pads DP may be positioned or arranged closer to an edge of the pad area than the display driver 310.

[0090] exist Figure 4 In this context, the display driver 310 may include a timing controller 311 and a data driver 312.

[0091] The timing controller 311 can receive digital video data DATA and timing signals from the circuit board 320. Based on the timing signals, the timing controller 311 can generate a data control signal (DCS) for controlling the operating timing of the data driver 312, a gate control signal (GCS) for controlling the operating timing of the gate driver 410, and a transmit control signal (ECS) for controlling the operating timing of the transmit control driver 420. The timing controller 311 can output the gate control signal (GCS) to the gate driver 410 via the first gate control line (GCL1). The timing controller 311 can output the transmit control signal (ECS) to the transmit control driver 420 via the second gate control line (GCL2). The timing controller 311 can also output the digital video data DATA and the data control signal (DCS) to the data driver 312.

[0092] Data driver 312 converts digital video data DATA into analog data voltage and outputs the analog data voltage to data line DL via fan-out line FL. The gate signal of gate driver 410 selects the pixel SP to which the data voltage is supplied, and the selected pixel SP can receive the data voltage via data line DL.

[0093] exist Figure 3In this configuration, the gate driver 410 can be positioned or arranged outside one side of the display area DA or on the other side of the non-display area NDA. The transmit control driver 420 can be positioned or arranged outside the other side of the display area DA or on the other side of the non-display area NDA. In another example, both the gate driver 410 and the transmit control driver 420 can be positioned or arranged outside one side of the display area DA.

[0094] The gate driver 410 may include a plurality of transistors for generating a gate signal based on the gate control signal GCS, and the emitter control driver 420 may include a plurality of transistors for generating an emitter signal based on the emitter control signal ECS. For example, the transistors of the gate driver 410 and the emitter control driver 420 may be formed in the same layer as the transistors of each pixel SP.

[0095] Figure 5 This is a circuit diagram illustrating the pixels of a display device according to some example embodiments.

[0096] refer to Figure 5 The display panel 300 may include a plurality of pixels SP arranged along k rows (k is a natural number) and j columns (j is a natural number). Each of the pixels SP may be connected to a first gate line GL1, a second gate line GL2, a third gate line GL3, an emit control line EML, a data line DL, a drive voltage line VDDL, and an initialization voltage line VIL.

[0097] Each pixel SP may include a light-emitting element EL and pixel circuitry for driving the light-emitting element EL. The pixel circuitry may include multiple switching elements and multiple capacitors. The multiple switching elements may include first to seventh transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7. The multiple capacitors may include a first capacitor C1 and a second capacitor C2.

[0098] The first transistor ST1 can control the drive current flowing through the light-emitting element EL. The first transistor ST1 may include a first transistor ST1-1 and a first transistor ST1-2 connected in series.

[0099] The first transistor ST1-1 may include a gate electrode, a first electrode, and a second electrode. For example, the first electrode of the first transistor ST1-1 may be a source electrode, and the second electrode of the first transistor ST1-1 may be a drain electrode, but embodiments of this disclosure are not limited thereto. The gate electrode of the first transistor ST1-1 may be connected to a first node N1, the first electrode of the first transistor ST1-1 may be connected to a third node N3, and the second electrode of the first transistor ST1-1 may be connected to the first electrode of the first transistor ST1-2. The first transistor ST1-1 may control the source-drain current ISD (hereinafter referred to as the "drive current") based on a portion of the data voltage (hereinafter referred to as "Vdata") applied to the gate electrode.

[0100] The first-second transistor ST1-2 may include a gate electrode, a first electrode, and a second electrode. For example, the first electrode of the first-second transistor ST1-2 may be a source electrode, and the second electrode of the first-second transistor ST1-2 may be a drain electrode, but embodiments of the present disclosure are not limited thereto. The gate electrode of the first-second transistor ST1-2 may be connected to a second node N2, the first electrode of the first-second transistor ST1-2 may be connected to the second electrode of the first-first transistor ST1-1, and the second electrode of the first-second transistor ST1-2 may be connected to a fourth node N4. The first-second transistor ST1-2 may control the drive current ISD based on another portion of the data voltage Vdata applied to the gate electrode.

[0101] In other words, the first transistor ST1-1 and the first transistor ST1-2 are connected in series to control the drive current ISD. The first transistor ST1-1 can control the drive current ISD based on the voltage of the first node N1, and the first transistor ST1-2 can control the drive current ISD based on the voltage of the second node N2, which is isolated from the first node N1. A portion of the data voltage Vdata applied to the pixel circuit can be applied to the first node N1 through the second transistor ST2, the first transistor ST1, and the third transistor ST3-1. Another portion of the data voltage Vdata can be applied to the second node N2 through the second transistor ST2, the first transistor ST1, and the third transistor ST3-2. The pixel circuit of the display device 10 includes the first transistor ST1-1 and the first transistor ST1-2, thereby increasing the driving range of the gate voltage applied to the first node N1 or the second node N2. In the display device 10, since the driving range of the gate voltage of the first transistor ST1 is increased, the grayscale of the light emitted from the light-emitting element EL can be controlled more precisely, thereby improving the resolution of the display device 10 and enhancing the display quality. Furthermore, since the pixel circuit of the display device 10 includes a first-first transistor ST1-1 and a first-second transistor ST1-2, hysteresis can be reduced, thereby reducing image retention in the display device 10.

[0102] A light-emitting element (EL) can emit light by receiving a drive current (ISD). The emission amount or brightness of the EL can be proportional to the magnitude of the drive current (ISD). The EL can be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed or arranged between the first and second electrodes, but embodiments according to this disclosure are not limited thereto. The first electrode of the EL can be connected to a fifth node (N5). The first electrode of the EL can be connected to the second electrodes of a sixth transistor (ST6) and a seventh transistor (ST7) via the fifth node (N5). For example, the first electrode of the EL can be an anode electrode, and the second electrode of the EL can be a cathode electrode, but embodiments according to this disclosure are not limited thereto.

[0103] The second transistor ST2 can be turned on by a first gate signal on the first gate line GL1 to connect the data line DL to a third node N3, which is the first electrode of the first transistor ST1-1. The second transistor ST2 can be turned on based on the first gate signal to supply the data voltage Vdata to the third node N3. The gate electrode of the second transistor ST2 can be connected to the first gate line GL1, the first electrode of the second transistor ST2 can be connected to the data line DL, and the second electrode of the second transistor ST2 can be connected to the third node N3. The second electrode of the second transistor ST2 can be connected to the first electrode of the first transistor ST1-1 and the second electrode of the fifth transistor ST5 via the third node N3. For example, the first electrode of the second transistor ST2 can be the source electrode, and the second electrode of the second transistor ST2 can be the drain electrode, but embodiments of this disclosure are not limited thereto.

[0104] The third transistor ST3 can be turned on by the first gate signal of the first gate line GL1 to connect the second electrode of the first transistor ST1 to the gate electrode of the first transistor ST1. The third transistor ST3 may include a third-first transistor ST3-1 and a third-second transistor ST3-2.

[0105] The third-first transistor ST3-1 can be turned on by the first gate signal of the first gate line GL1, so that the fourth node N4, which is the second electrode of the first-second transistor ST1-2, is connected to the first node N1, which is the gate electrode of the first-first transistor ST1-1. The gate electrode of the third-first transistor ST3-1 can be connected to the first gate line GL1, the first electrode of the third-first transistor ST3-1 can be connected to the fourth node N4, and the second electrode of the third-first transistor ST3-1 can be connected to the first node N1. The first electrode of the third-first transistor ST3-1 can be connected to the second electrode of the first-second transistor ST1-2, the first electrode of the third-second transistor ST3-2, and the first electrode of the sixth transistor ST6 through the fourth node N4. The second electrode of the third-first transistor ST3-1 can be connected to the second electrode of the fourth-first transistor ST4-1 and the first electrode of the fourth-second transistor ST4-2, and is connected to the gate electrode of the first-first transistor ST1-1 and the first electrode of the first capacitor C1 through the first node N1. For example, the first electrode of the third-first transistor ST3-1 can be the source electrode, and the second electrode of the third-first transistor ST3-1 can be the drain electrode, but the embodiments of this disclosure are not limited thereto.

[0106] The third-second transistor ST3-2 can be turned on by the first gate signal of the first gate line GL1, so that the fourth node N4, which is the second electrode of the first-second transistor ST1-2, is connected to the second node N2, which is the gate electrode of the first-second transistor ST1-2. The gate electrode of the third-second transistor ST3-2 can be connected to the first gate line GL1, the first electrode of the third-second transistor ST3-2 can be connected to the fourth node N4, and the second electrode of the third-second transistor ST3-2 can be connected to the second node N2. The first electrode of the third-second transistor ST3-2 can be connected to the first electrode of the sixth transistor ST6, and is connected to the second electrode of the first-second transistor ST1-2 and the first electrode of the third-first transistor ST3-1 through the fourth node N4. The second electrode of the third-second transistor ST3-2 can be connected to the second electrode of the fourth-second transistor ST4-2, and is connected to the gate electrode of the first-second transistor ST1-2 and the first electrode of the second capacitor C2 through the second node N2. For example, the first electrode of the third-second transistor ST3-2 can be the source electrode, and the second electrode of the third-second transistor ST3-2 can be the drain electrode, but the embodiments according to this disclosure are not limited thereto.

[0107] Therefore, in the pixel circuit of the display device 10, the voltage difference between a portion of the data voltage Vdata and the threshold voltage is sampled by the third-first transistor ST3-1 and applied to the gate electrode of the first-first transistor ST1-1, and the voltage difference between another portion of the data voltage Vdata and the threshold voltage is sampled by the third-second transistor ST3-2 and applied to the gate electrode of the first-second transistor ST1-2, thereby increasing the driving range of the gate voltages of the corresponding first-first transistor ST1-1 and first-second transistor ST1-2. In the display device 10, since the driving range of the gate voltage of the first transistor ST1 is increased, the grayscale of the light emitted from the light-emitting element EL can be controlled more precisely, thereby improving the resolution of the display device 10 and improving the display quality.

[0108] The fourth transistor ST4 can be turned on by the second gate signal of the second gate line GL2 to connect the initialization voltage line VIL to the gate electrode of the first transistor ST1. The fourth transistor ST4 may include a fourth-first transistor ST4-1 and a fourth-second transistor ST4-2.

[0109] The fourth-first transistor ST4-1 can be turned on based on the second gate signal of the second gate line GL2, thereby discharging the first node N1 of the gate electrode of the first-first transistor ST1-1 to the initialization voltage VI. The gate electrode of the fourth-first transistor ST4-1 can be connected to the second gate line GL2, the first electrode of the fourth-first transistor ST4-1 can be connected to the initialization voltage line VIL, and the second electrode of the fourth-first transistor ST4-1 can be connected to the first node N1. The second electrode of the fourth-first transistor ST4-1 can be connected to the second electrode of the third-first transistor ST3-1 and the first electrode of the fourth-second transistor ST4-2, and is connected to the gate electrode of the first-first transistor ST1-1 and the first electrode of the first capacitor C1 through the first node N1. For example, the first electrode of the fourth-first transistor ST4-1 can be the source electrode, and the second electrode of the fourth-first transistor ST4-1 can be the drain electrode, but the embodiments according to this disclosure are not limited thereto.

[0110] The fourth-second transistor ST4-2 can be turned on based on the second gate signal of the second gate line GL2, thereby discharging the second node N2 of the gate electrode of the first-second transistor ST1-2 to the initialization voltage VI. The gate electrode of the fourth-second transistor ST4-2 can be connected to the second gate line GL2, the first electrode of the fourth-second transistor ST4-2 can be connected to the first node N1, and the second electrode of the fourth-second transistor ST4-2 can be connected to the second node N2. The first electrode of the fourth-second transistor ST4-2 can be connected to the second electrodes of the third-first transistor ST3-1 and the fourth-first transistor ST4-1, and is connected to the gate electrode of the first-first transistor ST1-1 and the first electrode of the first capacitor C1 through the first node N1. The second electrode of the fourth-second transistor ST4-2 can be connected to the second electrode of the third-second transistor ST3-2, and is connected to the gate electrode of the first-second transistor ST1-2 and the first electrode of the second capacitor C2 through the second node N2. For example, the first electrode of the fourth-second transistor ST4-2 can be the source electrode, and the second electrode of the fourth-second transistor ST4-2 can be the drain electrode, but the embodiments according to this disclosure are not limited thereto.

[0111] The fifth transistor ST5 can be turned on by the emitter signal of the emitter control line EML to connect the drive voltage line VDDL to the third node N3, which is the first electrode of the first transistor ST1-1. The gate electrode of the fifth transistor ST5 can be connected to the emitter control line EML, the first electrode of the fifth transistor ST5 can be connected to the drive voltage line VDDL, and the second electrode of the fifth transistor ST5 can be connected to the third node N3. The second electrode of the fifth transistor ST5 can be connected to the first electrode of the first transistor ST1-1 and the second electrode of the second transistor ST2 through the third node N3. For example, the first electrode of the fifth transistor ST5 can be the source electrode, and the second electrode of the fifth transistor ST5 can be the drain electrode, but the embodiments according to this disclosure are not limited thereto.

[0112] The sixth transistor ST6 can be turned on by the emitter signal of the emitter control line EML, so that the fourth node N4 of the second electrode of the first-second transistor ST1-2 is connected to the fifth node N5 of the first electrode of the light-emitting element EL. The gate electrode of the sixth transistor ST6 can be connected to the emitter control line EML, the first electrode of the sixth transistor ST6 can be connected to the fourth node N4, and the second electrode of the sixth transistor ST6 can be connected to the fifth node N5. The first electrode of the sixth transistor ST6 can be connected to the first electrode of the third-second transistor ST3-2, and is connected to the second electrodes of the first-second transistor ST1-2 and the first electrode of the third-first transistor ST3-1 through the fourth node N4. The second electrode of the sixth transistor ST6 can be connected to the first electrode of the light-emitting element EL and the second electrode of the seventh transistor ST7 through the fifth node N5. For example, the first electrode of the sixth transistor ST6 can be the source electrode, and the second electrode of the sixth transistor ST6 can be the drain electrode, but the embodiments according to this disclosure are not limited thereto.

[0113] When the fifth transistor ST5, the first-first transistor ST1-1, the first-second transistor ST1-2, and the sixth transistor ST6 are all turned on, the drive current ISD can be supplied to the light-emitting element EL.

[0114] The seventh transistor ST7 can be turned on by the third gate signal of the third gate line GL3 to connect the initialization voltage line VIL to the fifth node N5, which is the first electrode of the light-emitting element EL. By turning on the seventh transistor ST7 based on the third gate signal, the first electrode of the light-emitting element EL can be discharged to the initialization voltage VI. The gate electrode of the seventh transistor ST7 can be connected to the third gate line GL3, the first electrode of the seventh transistor ST7 can be connected to the initialization voltage line VIL, and the second electrode of the seventh transistor ST7 can be connected to the fifth node N5. The second electrode of the seventh transistor ST7 can be connected to the first electrode of the light-emitting element EL and the second electrode of the sixth transistor ST6 through the fifth node N5.

[0115] Each of the first transistor ST1 to the seventh transistor ST7 may include a silicon-based active layer. For example, each of the first transistor ST1 to the seventh transistor ST7 may include an active layer made of low-temperature polycrystalline silicon (LTPS). The active layer made of LTPS can have high electron mobility and excellent conduction characteristics. That is, the pixel circuit of the display device 10 includes the first transistor ST1 to the seventh transistor ST7 with excellent conduction characteristics, so that multiple pixels SP can be driven stably and efficiently.

[0116] Each of the first transistor ST1 to the seventh transistor ST7 can correspond to a p-type transistor. For example, each of the first transistor ST1 to the seventh transistor ST7 can output the current flowing into the first electrode to the second electrode based on the gate low voltage applied to the gate electrode.

[0117] A first capacitor C1 can be connected between the drive voltage line VDDL and the first node N1, which is the gate electrode of the first transistor ST1-1. For example, the first electrode of the first capacitor C1 can be connected to the first node N1, and the second electrode of the first capacitor C1 can be connected to the drive voltage line VDDL, thereby maintaining the potential difference between the drive voltage line VDDL and the gate electrode of the first transistor ST1-1.

[0118] The second capacitor C2 can be connected between the drive voltage line VDDL and the second node N2, which is the gate electrode of the first-second transistor ST1-2. For example, the first electrode of the second capacitor C2 can be connected to the second node N2, and the second electrode of the first capacitor C1 can be connected to the drive voltage line VDDL, thereby maintaining the potential difference between the drive voltage line VDDL and the gate electrode of the first-second transistor ST1-2.

[0119] Figure 6 It is supplied to Figure 5 The waveform diagram of the pixel signal is shown in the figure.

[0120] refer to Figure 6 The display device 10 can be driven by the first time period t1 to the third time period t3 of each frame. The pixel SP can receive the first to third gate signals GS1, GS2 and GS3 and the transmit signal EM.

[0121] Combination Figure 5 refer to Figure 6 The fourth-first transistor ST4-1 and the fourth-second transistor ST4-2 can receive a low-level second gate signal GS2 during the first time period t1 of the Nth frame ("N" is a natural number equal to or greater than 2). The fourth-first transistor ST4-1 can be turned on based on the low-level second gate signal GS2 to supply an initialization voltage VI to the first node N1, which is the gate electrode of the first-first transistor ST1-1. Therefore, the fourth-first transistor ST4-1 can initialize the gate electrode of the first-first transistor ST1-1 during the first time period t1.

[0122] The fourth-second transistor ST4-2 can be turned on based on a low-level second gate signal GS2 to supply an initialization voltage VI to the second node N2, which is the gate electrode of the first-second transistor ST1-2. Therefore, the fourth-second transistor ST4-2 can initialize the gate electrode of the first-second transistor ST1-2 during the first time period t1.

[0123] The second transistor ST2 can receive a low-level first gate signal GS1 during the second time period t2. The second transistor ST2 can be turned on based on the low-level first gate signal GS1 to supply the data voltage Vdata to the third node N3, which is the first electrode of the first transistor ST1-1.

[0124] When the source electrode of the first transistor ST1-1 receives the data voltage Vdata, the source-gate voltage Vsg of the first transistor ST1-1 can correspond to the voltage difference between the data voltage Vdata and the initialization voltage VI (Vdata-VI). Because the source-gate voltage Vsg becomes greater than the first threshold voltage (hereinafter referred to as "Vth1") (Vdata-VI≥Vth1), the first transistor ST1-1 can be turned on. When the first transistor ST1-1 is turned on, the source-gate voltage Vsg of the first transistor ST1-2 can be the voltage obtained by subtracting the first threshold voltage Vth1 and the initialization voltage VI from the data voltage Vdata (Vdata-Vth1-VI). Because the source-gate voltage Vsg of the first transistor ST1-2 becomes greater than the second threshold voltage (hereinafter referred to as "Vth2") (Vdata-Vth1-VI≥Vth2), the first transistor ST1-2 can be turned on.

[0125] When the first transistor ST1-1 and the first transistor ST1-2 are turned on during the second time period t2, the source-drain current ISD of the first transistor ST1-1 and the first transistor ST1-2 can be determined based on the data voltage Vdata, the initialization voltage VI, the first threshold voltage Vth1 of the first transistor ST1-1, and the second threshold voltage Vth2 of the first transistor ST1-2 (ISD = k'*(Vdata-VI-Vth1-Vth2)^2, where k is a constant). When the source-gate voltage Vsg of the first transistor ST1-1 reaches the first threshold voltage Vth1, the first transistor ST1-1 can be turned on, and when the source-gate voltage Vsg of the first transistor ST1-2 reaches the second threshold voltage Vth2, the first transistor ST1-2 can be turned on, so that the source-drain current ISD can be supplied to the fourth node N4. Therefore, the first-first transistor ST1-1 and the first-second transistor ST1-2 are turned on during the second time period t2 to supply the voltage of the third node N3 to the fourth node N4. In this way, when the first-first transistor ST1-1 and the first-second transistor ST1-2 are turned on, the source-drain current ISD and the voltage of the fourth node N4 can be changed. Therefore, the voltage of the fourth node N4 can eventually converge to the voltage obtained by subtracting the first threshold voltage Vth1 and the second threshold voltage Vth2 from the data voltage Vdata (Vdata-Vth1-Vth2).

[0126] The seventh transistor ST7 can receive a low-level third gate signal GS3 during the second time period t2. The seventh transistor ST7 can be turned on based on the low-level third gate signal GS3 to supply the initialization voltage VI to the fifth node N5, which is the first electrode of the light-emitting element EL. Therefore, the seventh transistor ST7 can initialize the first electrode of the light-emitting element EL during the second time period t2.

[0127] The transmit signal EM can have a gate low voltage during the third time period t3. When the transmit signal EM is at a low level, the fifth transistor ST5 and the sixth transistor ST6 can be turned on to supply the drive current ISD to the light-emitting element EL.

[0128] Figure 7 It's a diagram. Figure 5 The circuit diagram illustrates an example of leakage current in a pixel. Figure 8 It's a diagram. Figure 5 The circuit diagram shows another example of leakage current in a pixel illustrated in the figure.

[0129] refer to Figure 7 and Figure 8The third-first transistor ST3-1 can be turned off by receiving a high-level first gate signal GS1. When the third-first transistor ST3-1 is turned off, the leakage current IL3-1 of the third-first transistor ST3-1 can flow. The leakage current IL3-1 of the third-first transistor ST3-1 can accumulate charge in the second electrode of the fourth-first transistor ST4-1 or in the first electrode of the fourth-second transistor ST4-2 to increase the voltage of the first node N1. As the voltage of the first node N1 increases, the leakage current IL4-1 of the fourth-first transistor ST4-1 can flow. Therefore, the voltage of the first node N1 can be balanced by the leakage currents IL3-1 of the third-first transistor ST3-1 and IL4-1 of the fourth-first transistor ST4-1. In the display device 10, the voltage of the first node N1 can be stably maintained by minimizing the difference current (IL3-1-IL4-1) between the leakage currents IL3-1 of the third-first transistor ST3-1 and IL4-1 of the fourth-first transistor ST4-1.

[0130] The third-second transistor ST3-2 can be turned off by receiving a high-level first gate signal GS1. When the third-second transistor ST3-2 is turned off, its leakage current IL3-2 can flow. The leakage current IL3-2 of the third-second transistor ST3-2 can accumulate charge in the second electrode of the fourth-second transistor ST4-2 to increase the voltage of the second node N2. As the voltage of the second node N2 increases, the leakage current IL4-2 of the fourth-second transistor ST4-2 can flow. The leakage current IL4-2 of the fourth-second transistor ST4-2 can accumulate charge in the second electrode of the fourth-first transistor ST4-1 or in the first electrode of the fourth-second transistor ST4-2 to increase the voltage of the first node N1. As the voltage of the first node N1 increases, the leakage current IL4-1 of the fourth-first transistor ST4-1 can flow. Therefore, the voltage of the second node N2 can be balanced by the leakage currents IL3-2 of the third-second transistor ST3-2 and IL4-2 of the fourth-second transistor ST4-2. In the display device 10, the voltage of the second node N2 can be stably maintained by minimizing the difference current (IL3-2-IL4-2) between the leakage current IL3-2 of the third-second transistor ST3-2 and the leakage current IL4-2 of the fourth-second transistor ST4-2.

[0131] Since the display device 10 includes a third-first transistor ST3-1 connected to a first node N1, which is the gate electrode of the first-first transistor ST1-1, and a third-second transistor ST3-2 connected to a second node N2, which is the gate electrode of the first-second transistor ST1-2, the leakage current of the first node N1 and the second node N2 can be minimized. In the display device 10, the voltage of the first node N1 can be stably maintained through a first leakage path through the third-first transistor ST3-1 and the fourth-first transistor ST4-1. Furthermore, the voltage of the second node N2 can be stably maintained through a second leakage path through the third-second transistor ST3-2, the fourth-second transistor ST4-2, and the fourth-first transistor ST4-1. That is, in the display device 10, the voltage of the first node N1, which is the gate electrode of the first-first transistor ST1-1, and the voltage of the second node N2, which is the gate electrode of the first-second transistor ST1-2, can be stably maintained. Therefore, leakage current flowing through the pixel circuit can be reduced to improve the image quality of the display device, and pixel brightness degradation can be suppressed to prevent or reduce flickering.

[0132] Figure 9 This is a plan view illustrating the first-first transistor and the first-second transistor of a display device according to some example embodiments. Figure 10 It is along Figure 9 The cross-sectional view taken from line I-I'.

[0133] refer to Figure 9 and Figure 10 The first transistor ST1-1 may include a first electrode S1-1, an active region ACT1-1, a second electrode D1-1, and a gate electrode G1-1.

[0134] The first electrode S1-1 of the first transistor ST1-1 can extend in a first direction (X-axis direction). One end of the active region ACT1-1 of the first transistor ST1-1 can be connected to the first electrode S1-1, and the other end of the active region ACT1-1 of the first transistor ST1-1 can be bent in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). One end of the second electrode D1-1 of the first transistor ST1-1 can be connected to the active region ACT1-1, and the other end of the second electrode D1-1 of the first transistor ST1-1 can be bent in the first direction (X-axis direction).

[0135] The gate electrode G1-1 of the first transistor ST1-1 can be disposed or arranged on the active region ACT1-1 to overlap with the active region ACT1-1 in the thickness direction. The gate electrode G1-1 of the first transistor ST1-1 may not overlap with the second electrode D1-1 of the first transistor ST1-1 or the first electrode S1-2 of the first transistor ST1-2. A portion of the gate electrode G1-1 of the first transistor ST1-1 may protrude to avoid overlapping with the capacitor electrode CE and be connected to the first connection electrode through the first contact hole CNT1. The gate electrode G1-1 of the first transistor ST1-1 can be connected to the first node N1 through the first connection electrode.

[0136] The first-second transistor ST1-2 may include a first electrode S1-2, an active region ACT1-2, a second electrode D1-2, and a gate electrode G1-2.

[0137] One end of the first electrode S1-2 of the first-second transistor ST1-2 can be connected to the second electrode D1-1 of the first-second transistor ST1-1, and the other end of the first electrode S1-2 of the first-second transistor ST1-2 can be bent in a second direction (Y-axis direction). One end of the active region ACT1-2 of the first-second transistor ST1-2 can be connected to the first electrode S1-2, and the other end of the active region ACT1-2 of the first-second transistor ST1-2 can be bent in a first direction (X-axis direction). The second electrode D1-2 of the first-second transistor ST1-2 can be connected to the active region ACT1-2 to extend in the first direction (X-axis direction).

[0138] The gate electrode G1-2 of the first-second transistor ST1-2 can be disposed or arranged on the active region ACT1-2 to overlap with the active region ACT1-2 in the thickness direction. The gate electrode G1-2 of the first-second transistor ST1-2 may not overlap with the second electrode D1-1 of the first-first transistor ST1-1 or the first electrode S1-2 of the first-second transistor ST1-2. A portion of the gate electrode G1-2 of the first-second transistor ST1-2 may protrude to avoid overlapping with the capacitor electrode CE and be connected to the second connection electrode through the second contact hole CNT2. The gate electrode G1-2 of the first-second transistor ST1-2 can be connected to the second node N2 through the second connection electrode.

[0139] Combination Figure 9 refer to Figure 10 The display panel 300 may include a substrate SUB, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a first gate layer GTL1, an interlayer insulating layer ILD, and a second gate layer GTL2.

[0140] The substrate SUB can be a base substrate and can be made of an insulating material such as a polymer resin. For example, the substrate SUB can be a flexible substrate that can be bent, folded, or rolled up.

[0141] A buffer layer (BF) can be disposed or arranged on a substrate (SUB). For example, the buffer layer (BF) may include multiple inorganic films and may be formed entirely on the upper surface of the substrate (SUB) to block moisture from entering the light-emitting element (EL) through the substrate (SUB).

[0142] The active layer ACTL can be disposed or arranged on the buffer layer BF. The active layer ACTL can be made of silicon-based materials. For example, the active layer ACTL can be formed of low-temperature polycrystalline silicon (LTPS). The first electrode S1-1, active region ACT1-1 and second electrode D1-1 of the first-first transistor ST1-1, and the first electrode S1-2, active region ACT1-2 and second electrode D1-2 of the first-second transistor ST1-2 can be disposed or arranged in the active layer ACTL.

[0143] The gate insulating layer GI can cover the active layer ACTL to insulate the active layer ACTL from the first gate layer GTL1.

[0144] The first gate layer GTL1 can be disposed or arranged on the gate insulating layer GI. The gate electrode G1-1 of the first transistor ST1-1 and the gate electrode G1-2 of the first transistor ST1-2 can be disposed or arranged in the first gate layer GTL1.

[0145] A portion of the gate electrode G1-1 of the first transistor ST1-1 may overlap with the capacitor electrode CE to form the first electrode of the first capacitor C1. A portion of the gate electrode G1-2 of the first transistor ST1-2 may overlap with the capacitor electrode CE to form the first electrode of the second capacitor C2.

[0146] The interlayer insulating layer (ILD) can cover the first gate layer (GTL1) and the gate insulating layer (GI). The interlayer insulating layer (ILD) can insulate the first gate layer (GTL1) from the second gate layer (GTL2).

[0147] The second gate layer GTL2 can be disposed or arranged on the interlayer insulating layer ILD. The capacitor electrode CE can be disposed or arranged in the second gate layer GTL2.

[0148] A portion of capacitor electrode CE may overlap with the gate electrode G1-1 of the first transistor ST1-1 to form the second electrode of the first capacitor C1. Another portion of capacitor electrode CE may overlap with the gate electrode G1-2 of the first transistor ST1-2 to form the second electrode of the second capacitor C2. Capacitor electrode CE may be connected to the drive voltage line VDDL (see example...). Figure 5 (to receive the drive voltage VDD).

[0149] Through the manufacturing process of the display device 10, the display device 10 includes a second electrode D1-1 of the first-first transistor ST1-1 and a first electrode S1-2 of the first-second transistor ST1-2 disposed between the gate electrode G1-1 of the first-first transistor ST1-1 and the gate electrode G1-2 of the first-second transistor ST1-2, such that hydrogen in the active layer ACTL can be released into the interlayer insulating layer ILD. Therefore, the sensitivity of the first-first transistor ST1-1 and the first-second transistor ST1-2 can be reduced. Thus, in the display device 10, the driving range of the gate voltage of the first-first transistor ST1-1 and the first-second transistor ST1-2 can be increased, thereby precisely controlling the output voltage from the light-emitting element EL (see, for example...). Figure 5 The gray level of the emitted light.

[0150] Electronic or electrical devices and / or any other related devices or components according to embodiments of the invention described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of these devices can be processes or threads in one or more computing devices that execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in a computing device using a standard storage device such as, for example, random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of exemplary embodiments of the invention.

[0151] It should be understood that the exemplary embodiments described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: A plurality of pixels on a substrate, each of the plurality of pixels including a light-emitting element and pixel circuitry configured to drive the light-emitting element. The pixel circuit of each of the plurality of pixels includes: The first transistor is configured to control the driving current flowing through the light-emitting element based on the voltage of the first node; The first and second transistors are connected in series with the first and second transistors and are configured to control the drive current based on the voltage of the second node; The second transistor is configured to selectively supply a data voltage to a third node that is the first electrode of the first transistor. A third-first transistor is connected between the first node and a fourth node, which is the second electrode of the first-second transistor, and the third-first transistor is directly connected to the fourth node; and The third-second transistor is connected between the second node and the fourth node.

2. The display device according to claim 1, wherein, The second transistor, the third-first transistor, and the third-second transistor are configured to be turned on based on a first gate signal received from the first gate line.

3. The display device according to claim 1, wherein, The pixel circuit further includes: A first capacitor is connected between the first node and the drive voltage line; and A second capacitor is connected between the second node and the drive voltage line.

4. The display device according to claim 3, wherein, The first transistor includes: The first electrode extends in a first direction; An active region, connected to the first electrode and configured to be bent in a second direction intersecting the first direction; A second electrode, connected to the active region and configured to be bent in the first direction; and A gate electrode is located on the active region and overlaps with the active region in the thickness direction.

5. The display device according to claim 4, wherein, The first and second transistors include: A first electrode, connected to the second electrode of the first-first transistor and configured to be bent in the second direction; The active region is connected to the first electrode of the first-second transistor and is configured to be bent in the first direction; The second electrode is connected to the active region of the first-second transistor and extends in the first direction; and The gate electrode is located on the active region of the first-second transistor and overlaps with the active region of the first-second transistor in the thickness direction.

6. The display device according to claim 5, wherein, The pixel circuit further includes capacitor electrodes on the gate electrodes of the first-first transistor and the second-first transistor, and... The first capacitor is formed between the gate electrode of the first transistor and the capacitor electrode, and the second capacitor is formed between the gate electrode of the first transistor and the capacitor electrode.

7. The display device according to claim 1, wherein, The pixel circuit further includes: The fourth-first transistor is connected between the first node and the initialization voltage line; and The fourth-second transistor is connected between the first node and the second node.

8. The display device according to claim 7, wherein, The fourth-first transistor and the fourth-second transistor are configured to be turned on based on a second gate signal received from the second gate line.

9. The display device according to claim 7, wherein, The pixel circuit further includes: The fifth transistor is connected between the third node and the drive voltage line; and The sixth transistor is connected between the fourth node and the fifth node, which is the first electrode of the light-emitting element.

10. The display device according to claim 9, wherein, The fifth and sixth transistors are configured to turn on based on a transmit signal received from the transmit control line.

11. The display device according to claim 9, wherein, The pixel circuit further includes: The seventh transistor is connected between the initialization voltage line and the fifth node.

12. The display device according to claim 11, wherein, The seventh transistor is configured to turn on based on a third gate signal received from the third gate line.

13. A display device, comprising: A plurality of pixels on a substrate, each of the plurality of pixels including a light-emitting element and pixel circuitry configured to drive the light-emitting element. The pixel circuit of each of the plurality of pixels includes: The first transistor is configured to control the driving current flowing through the light-emitting element based on the voltage of the first node; The first and second transistors are connected in series with the first and second transistors and are configured to control the drive current based on the voltage of the second node; A first capacitor is connected between the first node and the driving voltage line; A second capacitor is connected between the second node and the driving voltage line; The second transistor is configured to selectively supply a data voltage to a third node that is the first electrode of the first transistor. A third-first transistor is connected between the first node and a fourth node, which is the second electrode of the first-second transistor, and the third-first transistor is directly connected to the fourth node; The third-second transistor is connected between the second node and the fourth node; The fourth-first transistor is connected between the first node and the initialization voltage line; and The fourth-second transistor is connected between the first node and the second node.

14. The display device according to claim 13, wherein, The second transistor, the third-first transistor, and the third-second transistor are configured to be turned on based on a first gate signal received from the first gate line.

15. The display device according to claim 13, wherein, The fourth-first transistor and the fourth-second transistor are configured to be turned on based on a second gate signal received from the second gate line.

16. The display device according to claim 13, wherein, The pixel circuit further includes: A fifth transistor is connected between the third node and the drive voltage line; and The sixth transistor is connected between the fourth node and the fifth node, which is the first electrode of the light-emitting element.

17. The display device according to claim 16, wherein, The fifth and sixth transistors are configured to turn on based on a transmit signal received from the transmit control line.

18. The display device according to claim 16, wherein, The pixel circuit further includes: The seventh transistor is connected between the initialization voltage line and the fifth node.

19. The display device according to claim 18, wherein, The seventh transistor is configured to turn on based on a third gate signal received from the third gate line.

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