A subthreshold circuit post-simulation acceleration method and device

Abstract

The present invention provides a subthreshold circuit post-simulation acceleration method and device, the method comprising: reading in a subthreshold circuit netlist containing wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage; analyzing the signal flow in the simulation stimulus to determine a signal streamline network; simplifying the wiring parasitic effects of the signal streamline network; wherein the wiring parasitic effects are related to the operating voltage; performing circuit simulation on a circuit corresponding to the simplified subthreshold circuit netlist, thereby realizing post-simulation of the subthreshold circuit; that is, the operating voltage is used as a calculation factor for the wiring parasitic effects, so when simplifying the wiring parasitic effects, the wiring parasitic effects that can be simplified are accurately simplified, thereby reducing the matrix size of the subthreshold circuit and improving the speed and accuracy of the subthreshold circuit post-simulation.

Description

Technical Field

[0001] The present invention belongs to the technical field of subthreshold circuit post-simulation, and more specifically, particularly relates to a subthreshold circuit post-simulation acceleration method and device. Background Art

[0002] Since the operating voltage of the subthreshold circuit is lower than the threshold voltage of its own device and it operates in the region where the current-voltage changes exponentially, the number of iterations of the subthreshold circuit at each time point in the simulation process is significantly higher than that of the superthreshold circuit; therefore, the simulation speed of the subthreshold circuit is significantly lower than that of the superthreshold circuit.

[0003] Another factor that affects the simulation speed of subthreshold circuits is that the wiring parasitic effects cause the size of the circuit simulation matrix to increase. In order to effectively improve the simulation speed of subthreshold circuits, the wiring parasitic effects need to be simplified.

[0004] The existing parasitic effect simplification technology is independent of the operating voltage; when the simplification technology is applied to subthreshold circuits, parasitic effects that could have been simplified are not simplified, and the matrix scale of the existing parasitic effect simplification technology is still large, which loses the ability to improve the post-simulation speed of the subthreshold circuit; if parasitic effects that cannot be simplified are simplified, it will lead to potential subthreshold circuit post-simulation accuracy problems. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a subthreshold circuit post-simulation acceleration method and device for improving the simulation speed and accuracy of the subthreshold circuit.

[0006] The first aspect of the present application discloses a subthreshold circuit post-simulation acceleration method, comprising:

[0007] Reading in a subthreshold circuit netlist including wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage;

[0008] Analyzing the signal flow in the simulation excitation to determine the signal streamline network;

[0009] Simplifying the parasitic effects of the connection of the signal flow network; wherein the parasitic effects of the connection are related to the operating voltage;

[0010] Circuit simulation is performed on the circuit corresponding to the simplified subthreshold circuit netlist.

[0011] Optionally, in the subthreshold circuit post-simulation acceleration method, the wiring parasitic effect includes: wiring parasitic capacitance; simplifying the wiring parasitic effect of the signal streamline network includes:

[0012] Determining a total value of gate parasitic capacitance of a first device driven by the signal streamline network according to the operating voltage;

[0013] The connection parasitic capacitance of the signal streamline network is simplified according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network.

[0014] Optionally, in the subthreshold circuit post-simulation acceleration method, simplifying the connection parasitic capacitance of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network includes:

[0015] Determine whether a ratio between a first capacitance and a second capacitance satisfies a first preset neglect condition; wherein the first capacitance includes the capacitance of at least one of the parasitic capacitances of the connection, and the second capacitance is the total value of the gate parasitic capacitance of the driven first device;

[0016] If so, the connection parasitic capacitance corresponding to the first capacitance value is deleted from the sub-threshold circuit netlist.

[0017] Optionally, in the subthreshold circuit post-simulation acceleration method, the determining whether the ratio between the first capacitance and the second capacitance satisfies a first preset ignoring condition includes:

[0018] Determine whether the ratio between the first capacitance and the second capacitance is less than a first set value; wherein the first capacitance includes the capacitance of any one of the parasitic capacitances of the connection; or,

[0019] Determine that the ratio between the first capacitance and the second capacitance is less than a second set value; wherein the second capacitance includes the capacitance of N of the parasitic capacitances of the connection; N is an integer greater than 1 and less than n, and n is the total number of parasitic capacitances of the connection; or,

[0020] It is determined that a ratio between the first capacitance and the second capacitance is less than a third set value; wherein the first capacitance includes the capacitance of each of the parasitic capacitances of the connection.

[0021] Optionally, in the subthreshold circuit post-simulation acceleration method, before calculating the total value of the gate parasitic capacitance of each first device driven by the signal streamline network according to the operating voltage, the method further includes:

[0022] Performing temperature analysis on the chip where the subthreshold circuit is located to obtain the temperature distribution of the chip; wherein the temperature distribution of the chip is the temperature of each position on the chip;

[0023] The operating temperature of each of the first components is determined according to the temperature distribution and the position at which each of the first components is arranged in the chip.

[0024] Optionally, in the subthreshold circuit post-simulation acceleration method, calculating the total value of the gate parasitic capacitance of each first device driven by the signal streamline network according to the operating voltage includes:

[0025] The total value of the gate parasitic capacitance of each first device driven by the signal streamline network is determined according to the operating temperature and the operating voltage of each first device.

[0026] Optionally, in the subthreshold circuit post-simulation acceleration method, simplifying the connection parasitic effects of the signal streamline network further includes:

[0027] According to the equivalent resistance value of each subthreshold device in the DC path in the subthreshold circuit when the subthreshold is turned on;

[0028] According to the equivalent resistance value of each of the subthreshold devices when the subthreshold is turned on, the connection parasitic resistance of the signal flow network is simplified.

[0029] Optionally, in the subthreshold circuit post-simulation acceleration method, the connection parasitic resistance of the signal streamline network is simplified according to the equivalent resistance value of each subthreshold device in the DC path of the subthreshold circuit when the subthreshold is turned on, including:

[0030] Determine whether a ratio between a first resistance value and a second resistance value corresponding to the first resistance value satisfies a second preset ignoring condition; wherein the first resistance value includes at least one parasitic resistance of the connection, and the second resistance value includes an equivalent resistance value of the subthreshold device corresponding to the first resistance value when the subthreshold device is subthreshold turned on;

[0031] If so, the connection parasitic resistance corresponding to the first resistance value is deleted from the sub-threshold circuit netlist.

[0032] Optionally, in the subthreshold circuit post-simulation acceleration method, determining whether a ratio between a first resistance value and a second resistance value corresponding thereto satisfies a second preset ignoring condition includes:

[0033] Determine whether the ratio between the first resistance value and the second resistance value corresponding to it is less than a fourth set value; wherein the first resistance value includes the resistance value of any one of the parasitic resistances of the connection; and the second resistance value includes the equivalent resistance value of one of the subthreshold devices corresponding to the first resistance value when the subthreshold is turned on; or,

[0034] Determine whether the ratio between the first resistance value and the second resistance value corresponding to it is less than a fifth set value; wherein the second resistance value includes the resistance values ​​of the M parasitic resistances of the connection; the second resistance value includes the equivalent resistance values ​​of the M subthreshold devices corresponding to the first resistance value when the subthreshold is turned on; M is an integer greater than 1 and less than m, and m is the total number of parasitic resistances of the connection; or,

[0035] Determine whether the ratio between the first resistance value and the corresponding second resistance value is less than a sixth set value; wherein the first resistance value includes the resistance value of each of the parasitic resistances of the connection; and the second resistance value includes the equivalent resistance value of each of the subthreshold devices corresponding to the first resistance value when the subthreshold is turned on.

[0036] The second aspect of the present application discloses a subthreshold circuit post-simulation acceleration device, comprising:

[0037] A reading unit, used for reading in a subthreshold circuit netlist including wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage;

[0038] A determination unit, used to analyze the signal flow in the simulation excitation and determine the signal streamline network;

[0039] A simplified element is used to simplify the connection parasitic effect of the signal flow network; wherein the connection parasitic effect is related to the working voltage;

[0040] The simulation unit is used to simulate the circuit corresponding to the simplified subthreshold circuit netlist.

[0041] It can be seen from the above technical scheme that the present invention provides a subthreshold circuit post-simulation acceleration method, including: reading in a subthreshold circuit netlist containing wiring parasitic effects; wherein the simulation excitation in the subthreshold circuit netlist includes an operating voltage; analyzing the signal flow in the simulation excitation to determine the signal streamline network; simplifying the wiring parasitic effects of the signal streamline network; wherein the wiring parasitic effects are related to the operating voltage; performing circuit simulation on the circuit corresponding to the simplified subthreshold circuit netlist, thereby realizing post-simulation of the subthreshold circuit; that is, the operating voltage is used as a calculation factor for the wiring parasitic effects, so that when simplifying the wiring parasitic effects, the wiring parasitic effects that can be simplified are accurately simplified, thereby reducing the matrix size of the subthreshold circuit and improving the post-simulation speed and accuracy of the subthreshold circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is a flow chart of a subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention;

[0044] Figure 2 is a flow chart of another subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention;

[0045] Figure 3 is a flow chart of another subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention;

[0046] Figure 4 is a flow chart of another subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention;

[0047] Figure 5 is a flow chart of another subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention;

[0048] Figure 6 It is a flow chart of another subthreshold circuit post-simulation acceleration method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0051] An embodiment of the present invention provides a subthreshold circuit post-simulation acceleration method for solving the problem in the prior art that the matrix scale of the existing parasitic effect reduction technology is still large, which fails to improve the subthreshold circuit post-simulation speed; if the parasitic effects that cannot be simplified are simplified, it will lead to potential subthreshold circuit post-simulation accuracy problems.

[0052] See also Figure 1 The subthreshold circuit post-simulation acceleration method comprises:

[0053] S101, read in a subthreshold circuit netlist including wiring parasitic effects.

[0054] It should be noted that the subthreshold circuit netlist includes simulation excitation, wherein the simulation excitation includes an operating voltage; that is, the simulation excitation in the subthreshold circuit netlist includes an operating voltage.

[0055] Of course, the subthreshold circuit netlist may also include other information, which will not be elaborated here one by one. It depends on the actual situation and is within the scope of protection of the application.

[0056] S102, analyzing the signal flow in the simulation excitation to determine the signal streamline network.

[0057] It should be noted that the signal flow comes from the excitation of the circuit simulation input, that is, the simulation excitation, which involves frequency, amplitude, waveform, etc., which will not be repeated here one by one, and are all within the protection scope of this application.

[0058] Specifically, the direction of flow of electrical signals can be regarded as signal flow, such as the direction of current flow, etc. Of course, it can also be other communication signals, which are not specifically limited here and can be determined according to the actual situation, all of which are within the protection scope of this application.

[0059] S103, simplifying the parasitic effects of the connection of the signal streamline network.

[0060] Among them, the connection parasitic effect is related to the operating voltage.

[0061] That is to say, if the working voltage is different, the parasitic effect of the connection will be different; the specific functional relationship between the working voltage and the parasitic capacitance of the connection can be found in the corresponding prior art, which will not be described here one by one, and all are within the protection scope of this application.

[0062] There is a special ModelReduction algorithm for simplification, and its main principle is port equivalence to ensure a certain accuracy.

[0063] There are many simplification technologies, mainly based on momentum matching and Pade approximation. Each simplification technology will not be described one by one here. It depends on the actual situation and is within the protection scope of this application.

[0064] It should be noted that if simplification is not performed, the number of nodes caused by parasitic effects will be large, resulting in a large matrix size for circuit simulation, which will significantly reduce the simulation speed or even make simulation impossible. In other words, simplification is to reduce the number of nodes in the subthreshold circuit, thereby reducing the matrix size in the simulation process of the subthreshold circuit to speed up the simulation speed.

[0065] S104 , performing circuit simulation on the circuit corresponding to the simplified subthreshold circuit netlist.

[0066] It should be noted that circuit simulation can be divided into pre-circuit simulation and post-circuit simulation, collectively referred to as circuit simulation.

[0067] The difference between pre-circuit simulation and post-circuit simulation is that the circuit netlist input by pre-circuit simulation does not include the parasitic effects on the circuit layout, while the circuit netlist input by post-circuit simulation includes the parasitic effects of the wiring on the circuit layout.

[0068] However, the present application performs simulation after simplifying the subthreshold circuit netlist including the parasitic effects of the wiring, thereby realizing post-simulation of the subthreshold circuit.

[0069] In this embodiment, a subthreshold circuit netlist including wiring parasitic effects is read in; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage; the signal flow in the simulation stimulus is analyzed to determine a signal streamline network; the wiring parasitic effects of the signal streamline network are simplified; wherein the wiring parasitic effects are related to the operating voltage; circuit simulation is performed on the circuit corresponding to the simplified subthreshold circuit netlist, thereby realizing post-simulation of the subthreshold circuit; that is, the operating voltage is used as a calculation factor for the wiring parasitic effects, so when simplifying the wiring parasitic effects, the wiring parasitic effects that can be simplified are accurately simplified, thereby reducing the matrix size of the subthreshold circuit and improving the post-simulation speed and accuracy of the subthreshold circuit.

[0070] In practical applications, the parasitic effect of the connection includes: parasitic capacitance of the connection. Of course, the parasitic effect of the connection may also include parasitic resistance; the specific form of the parasitic effect of the connection is not limited here, and it can be determined according to the actual situation, and all are within the protection scope of this application.

[0071] Taking the parasitic effect of the connection including the parasitic capacitance of the connection as an example, step S103, simplifying the parasitic effect of the connection of the signal flow network, is described; see Figure 2 The specific process of step S102 may be:

[0072] S201. Determine, according to an operating voltage, a total value of a gate parasitic capacitance of a first device driven by a signal streamline network.

[0073] It should be noted that the total value of the gate parasitic capacitance of each first device driven by the signal streamline network is used as a factor to determine whether the corresponding wiring parasitic capacitance can be simplified, thereby making the simplification of wiring parasitic effects in the subthreshold voltage more accurate.

[0074] Only the parasitic capacitance of the connection line connected to the gate of the first device will have a corresponding gate parasitic capacitance, but there may be multiple gate parasitic capacitances.

[0075] S202 , simplifying the connection parasitic capacitance of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network.

[0076] It should be noted that the parasitic capacitance of the connection parasitic effect will affect the signal transmission speed, thereby reducing the simulation speed.

[0077] In this embodiment, the parasitic capacitance of the connection is simplified to increase the simulation speed of the subthreshold circuit.

[0078] In practical applications, see Figure 3 The specific process of step S202 may be:

[0079] S301 , determining whether a ratio between a first capacitance and a second capacitance satisfies a first preset ignoring condition.

[0080] The first capacitance includes the capacitance of at least one parasitic capacitance of a connection, and the second capacitance is the total value of the parasitic capacitance of the gate of the first device driven by the signal streamline network.

[0081] That is to say, the capacitance of a connecting parasitic capacitance can be taken as a whole, and the ratio of it to the total value of the gate parasitic capacitance can be used to judge whether it meets the first preset ignoring condition; the capacitance of multiple connecting parasitic capacitances can be taken as a whole, and the ratio of it to the total value of the gate parasitic capacitance can be used to judge whether it meets the first preset ignoring condition; the capacitance of each connecting parasitic capacitance can also be taken as a whole, and the ratio of it to the total value of the gate parasitic capacitance can be used to judge whether it meets the first preset ignoring condition.

[0082] In practical applications, there may be multiple specific processes of step S301. Three cases are described below respectively, as follows:

[0083] (1) Determine whether a ratio between a first capacitance and a second capacitance is less than a first set value; wherein the first capacitance is the capacitance of any parasitic capacitance of a connection.

[0084] That is to say, if the ratio of any parasitic capacitance of a connection as a whole and the total value of the gate parasitic capacitance of the first device driven by the signal streamline network as a whole is less than a first set value, then it is determined that the ratio between the first capacitance and the second capacitance meets the first preset ignoring condition; otherwise, it is determined that the ratio between the first capacitance and the second capacitance does not meet the first preset ignoring condition.

[0085] The value of the first setting value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0086] (2) Determine whether the ratio of the first capacitance to the second capacitance is less than a second set value; wherein the second capacitance is the sum of the capacitances of N parasitic capacitances of the connection; N is an integer greater than 1 and less than n, and n is the total number of parasitic capacitances of the connection.

[0087] That is to say, the sum of the N connecting parasitic capacitances is taken as a whole, and the total value of the gate parasitic capacitance of the first device driven by the signal streamline network is taken as a whole. If the ratio between the two wholes is less than the second set value, it is determined that the ratio between the first capacitance and the second capacitance meets the first preset ignoring condition; otherwise, it is determined that the ratio between the first capacitance and the second capacitance does not meet the first preset ignoring condition.

[0088] The value of the second set value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0089] (3) It is determined that the ratio of the first capacitance to the second capacitance is less than a third set value; wherein the first capacitance is the sum of the capacitances of the parasitic capacitances of each connection.

[0090] That is to say, the sum of the n connecting parasitic capacitances is taken as a whole, and the total value of the gate parasitic capacitance of the first device driven by the signal streamline network is taken as a whole. If the ratio between the two wholes is less than the third set value, it is determined that the ratio between the first capacitance and the second capacitance meets the first preset ignoring condition; otherwise, it is determined that the ratio between the first capacitance and the second capacitance does not meet the first preset ignoring condition.

[0091] The value of the third setting value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0092] The above three situations are actually one situation, but in the actual implementation process, they will be divided into three situations for processing. This is related to the specific content of the parasitic parameter netlist. They will not be described one by one here, and they are all within the protection scope of the application itself.

[0093] The first set value, the second set value, and the third set value are determined according to the required simulation error. When the simulation error is large, the first set value, the second set value, and the third set value are large, and when the simulation error is small, the first set value, the second set value, and the third set value are small.

[0094] If the ratio between the first capacitance and the second capacitance satisfies the first preset ignoring condition, step S302 is executed.

[0095] S302, deleting the parasitic capacitance of the connection corresponding to the first capacitance value in the sub-threshold circuit netlist.

[0096] Specifically, in combination with the three situations listed in the above step S301, step S302 is described as follows:

[0097] (1) If the ratio of any parasitic capacitance of a connection as a whole to the total value of the gate parasitic capacitance of the first device driven by the signal flow network is less than a first set value, the parasitic capacitance of the connection is deleted from the subthreshold circuit netlist.

[0098] (2) If the sum of the parasitic capacitances of each connection is taken as a whole, and the total value of the gate parasitic capacitance of the first device driven by the signal flow network is taken as a whole, if the ratio between the two wholes is less than a second set value, then the parasitic capacitances of each connection are deleted from the subthreshold circuit netlist.

[0099] (3) If the sum of the N parasitic capacitances of the connections is taken as a whole, and the total value of the gate parasitic capacitance of the first device driven by the signal flow network is taken as a whole, if the ratio between the two wholes is less than a third set value, then the N parasitic capacitances of the connections are deleted from the subthreshold circuit netlist.

[0100] In this embodiment, the parasitic effect of the connection is further simplified by connecting parasitic capacitance, thereby improving the accuracy of the simplification of the subthreshold circuit and improving the simulation speed and accuracy of the subthreshold circuit.

[0101] In practical applications, see Figure 4 The operating temperature of each first device will also affect the parasitic effect of the connection accordingly. In order to further improve the accuracy of simplification, before step S301, the following may also be included:

[0102] S401 , performing temperature analysis on a chip where a subthreshold circuit is located to obtain a temperature distribution of the chip.

[0103] The temperature distribution of the chip refers to the temperature of each position on the chip; that is, when determining the position on the chip, the temperature of the position can be determined based on the temperature distribution.

[0104] The purpose of performing temperature analysis on the chip is to determine the operating temperature of each first device. Specifically, the temperature distribution can be obtained through thermal simulation analysis or similar analysis; the specific analysis process will not be described here one by one, and all are within the protection scope of this application.

[0105] S402. Obtain the temperature corresponding to the position of each first device in the chip based on the temperature distribution and the position of each first device in the chip, and use the temperature corresponding to the position of each first device in the chip as the operating temperature of each first device.

[0106] It should be noted that circuit simulation generally specifies a temperature for all components to perform simulation, but does not set different temperatures for each component. However, this application sets the operating temperature for each component based on the temperature distribution on the chip and the location of the component, which can make the simulation more accurate.

[0107] In this embodiment, the operating temperature of each first device is determined, rather than the overall ambient temperature of the chip. If the circuit simulation generally uses the overall ambient temperature of the chip, the temperature is relatively rough and the simulation accuracy is low. However, in this embodiment, the temperature at each first device position on the chip is different, so the temperature at each first device position is used for more accurate simulation.

[0108] Accordingly, the specific working process of the above step S301 may be:

[0109] The total value of the gate parasitic capacitance of each first device driven by the signal streamline network is determined according to the operating temperature and the operating voltage of each first device.

[0110] Specifically, the operating temperature and operating voltage of each first device are substituted into the device CV model formula to calculate the total value of the gate parasitic capacitance corresponding to each first device; the device CV model formula is not specifically limited here and can be determined according to actual conditions, all of which are within the scope of protection of this application.

[0111] In this embodiment, a subthreshold circuit netlist including parasitic effects is read in, a thermal analysis is performed to determine the temperature distribution on the chip, a signal flow network is determined based on the signal flow analysis, and the connection parasitic effects of the signal flow network are simplified; a circuit simulation is performed on the simplified circuit netlist, thereby realizing post-simulation of the subthreshold circuit. Post-simulation of the subthreshold circuit can both accelerate and ensure simulation accuracy.

[0112] In practical applications, see Figure 5 (In Figure 2When the connection parasitic effect may further include the connection parasitic resistance, the above-mentioned step S102 simplifies the connection parasitic effect of the signal flow network, and further includes:

[0113] S501. Simplify the parasitic resistance of the connection of the signal flow network according to the equivalent resistance value of each subthreshold device in the DC path of the subthreshold circuit when the subthreshold is turned on.

[0114] Specifically, subthreshold devices whose operating voltage is lower than the threshold voltage are all subthreshold operations.

[0115] Subthreshold conduction means that the working voltage of the subthreshold device is greater than 2 or 3 times the thermal voltage. The specific value of the thermal voltage is not specifically limited here and can be determined according to the actual situation, which is within the protection scope of this application.

[0116] It should be noted that the parasitic effect of the connection will form an IR voltage drop, where I is the current and R is the resistance. This causes the device operating voltage to fluctuate, and the performance of the subthreshold circuit is significantly affected by the fluctuation of the device operating voltage. Therefore, the operating voltage is introduced as a parameter in the simplification to improve the accuracy of the simplification.

[0117] It should be noted that the subthreshold device is a device that contributes to charging and / or discharging the gate capacitance of the device driven in the signal flow network.

[0118] That is to say, a subthreshold device is a device that contributes to the charging of the gate capacitance of a device driven in a signal streamline network; a subthreshold device is a device that contributes to the discharging of the gate capacitance of a device driven in a signal streamline network; a subthreshold device is a device that contributes to the charging and discharging of the gate capacitance of a device driven in a signal streamline network.

[0119] For details, see Figure 6 The specific process of step S501 may be:

[0120] S601, determining the equivalent resistance value of each subthreshold device in the DC path when the subthreshold is turned on.

[0121] S602: Determine whether the ratio between the first resistance value and its corresponding second resistance value satisfies a second preset ignoring condition.

[0122] The first resistance value includes the resistance value of at least one parasitic resistance of a connection, and the second resistance value includes the equivalent resistance value of the subthreshold device corresponding to the first resistance value when the subthreshold is turned on.

[0123] That is to say, the resistance value of a connecting parasitic resistor can be taken as a whole, and the equivalent resistance value of a subthreshold device corresponding to the first resistance value when it is subthreshold turned on can be taken as a whole, and the ratio of the two wholes can be used to determine whether the second preset ignoring condition is met; the resistance values ​​of multiple connecting parasitic resistors can be taken as a whole, and the equivalent resistance values ​​of multiple subthreshold devices corresponding to the first resistance value when they are subthreshold turned on can be taken as a whole, and the ratio of the two wholes can be used to determine whether the second preset ignoring condition is met; the resistance values ​​of each connecting parasitic resistor can also be taken as a whole, and the equivalent resistance values ​​of each subthreshold device corresponding to the first resistance value when they are subthreshold turned on can be taken as a whole, and the ratio of the two wholes can be used to determine whether the second preset ignoring condition is met.

[0124] The operation of the subthreshold circuit is equivalent to RC charging and discharging. If the proportion of the parasitic resistance of the connection is small, the impact on the product of RC is very small, such as ΔRC / RC=ΔR / R; therefore, the parasitic resistance with a small proportion can be ignored.

[0125] In practical applications, there may be multiple specific processes of step S602. Three cases are described below respectively, as follows:

[0126] (1) Determine whether a ratio between a first resistance value and its corresponding second resistance value is less than a fourth set value.

[0127] The first resistance value includes the resistance value of any parasitic resistance of a connection; the second resistance value includes the equivalent resistance value of a subthreshold device corresponding to the first resistance value when the subthreshold is turned on.

[0128] That is to say, any parasitic resistance of a connection is taken as a whole, and the equivalent resistance value of a subthreshold device corresponding to the parasitic resistance of the connection is taken as a whole when the subthreshold is turned on. If the ratio between the two wholes is less than the fourth set value, it is determined that the ratio between the first resistance value and the second resistance value meets the second preset ignoring condition; otherwise, it is determined that the ratio between the first resistance value and the second resistance value does not meet the second preset ignoring condition.

[0129] The value of the fourth setting value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0130] (2) Determine whether a ratio between the first resistance value and its corresponding second resistance value is less than a fifth set value.

[0131] Among them, the first resistance value includes the sum of the resistance values ​​of M connecting parasitic resistances; the second resistance value includes the equivalent resistance value of M subthreshold devices corresponding to the first resistance value when the subthreshold is turned on; M is an integer greater than 1 and less than m, and m is the total number of connecting parasitic resistances.

[0132] That is to say, the sum of the M parasitic resistances of the connections is taken as a whole, and the total value of the equivalent resistance values ​​of the M subthreshold devices corresponding to the M parasitic resistances when the subthreshold is turned on is taken as a whole. If the ratio between these two wholes is less than the fifth set value, it is determined that the ratio between the first resistance value and the second resistance value meets the second preset ignoring condition; otherwise, it is determined that the ratio between the first resistance value and the second resistance value does not meet the second preset ignoring condition.

[0133] The value of the fifth setting value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0134] (3) Determine whether a ratio between the first resistance value and its corresponding second resistance value is less than a sixth set value.

[0135] The first resistance value includes the sum of the resistance values ​​of the parasitic resistances of each connection; the second resistance value includes the equivalent resistance value of each subthreshold device corresponding to the first resistance value when the subthreshold is turned on.

[0136] That is to say, the sum of the m parasitic resistances of the connections is taken as a whole, and the total value of the equivalent resistance values ​​of the m subthreshold devices corresponding to the m parasitic resistances when the subthreshold is turned on is taken as a whole. If the ratio between these two wholes is less than the sixth set value, it is determined that the ratio between the first resistance value and the second resistance value meets the second preset ignoring condition; otherwise, it is determined that the ratio between the first resistance value and the second resistance value does not meet the second preset ignoring condition.

[0137] The value of the sixth setting value is not specifically limited here and can be determined according to actual conditions, and is within the protection scope of this application.

[0138] The above three situations are actually one situation, but in the actual implementation process, they will be divided into three situations for processing. This is related to the specific content of the parasitic parameter netlist. They will not be described one by one here, and they are all within the protection scope of the application itself.

[0139] The fourth set value, the fifth set value, and the sixth set value are determined according to the required simulation error. When the simulation error is large, the fourth set value, the fifth set value, and the sixth set value are large, and when the simulation error is small, the fourth set value, the fifth set value, and the sixth set value are small.

[0140] If the ratio between the first resistance value and its corresponding second resistance value satisfies the second preset ignoring condition, the process proceeds to step S603.

[0141] S603, deleting the parasitic resistance of the connection corresponding to the first resistance value in the sub-threshold circuit netlist.

[0142] Specifically, in combination with the three situations listed in the above step S301, step S302 is described as follows:

[0143] (1) Any parasitic resistance of a connection is taken as a whole, and the equivalent resistance value of a subthreshold device corresponding to the parasitic resistance of the connection is taken as a whole when the subthreshold is turned on. If the ratio between these two wholes is less than a fourth set value, the parasitic resistance of the connection is deleted from the subthreshold circuit netlist.

[0144] (2) The M parasitic resistances of the wiring are taken as a whole, and the equivalent resistance values ​​of the M subthreshold devices corresponding to the parasitic resistances of the wiring are taken as a whole when the subthreshold is turned on. If the ratio of these two wholes is less than the fifth set value, the M parasitic resistances of the wiring are deleted from the subthreshold circuit netlist.

[0145] (3) The parasitic resistance of each connection is taken as a whole, and the equivalent resistance value of each subthreshold device when the subthreshold is turned on is taken as a whole. If the ratio between these two wholes is less than the sixth set value, then the parasitic resistance of each connection is deleted from the subthreshold circuit netlist.

[0146] In this embodiment, the parasitic effect of the connection is further simplified through the parasitic resistance of the connection, so as to improve the accuracy of the simplification of the subthreshold circuit and improve the simulation speed and accuracy of the subthreshold circuit.

[0147] Another embodiment of the present application also provides a subthreshold circuit post-simulation acceleration device.

[0148] The subthreshold circuit post-simulation acceleration device comprises:

[0149] The reading unit is used to read in the subthreshold circuit netlist including the parasitic effects of the wiring.

[0150] Among them, the simulation stimulus in the subthreshold circuit netlist includes the operating voltage.

[0151] The determination unit is used to analyze the signal flow in the simulation excitation and determine the signal streamline network.

[0152] The simplified element is used to simplify the parasitic effects of the connection of the signal flow network; wherein the parasitic effects of the connection are related to the working voltage.

[0153] The simulation unit is used to simulate the circuit corresponding to the simplified subthreshold circuit netlist.

[0154] The working process and principle of each unit are detailed in the above embodiments. Figure 1-Figure 6 The illustrated embodiments will not be described one by one here, and all are within the protection scope of this application.

[0155] In this embodiment, the reading unit reads in a subthreshold circuit netlist including wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage; the determining unit analyzes the signal flow in the simulation stimulus to determine a signal streamline network; the simple element simplifies the wiring parasitic effects of the signal streamline network; wherein the wiring parasitic effects are related to the operating voltage; the simulation unit performs circuit simulation on the circuit corresponding to the simplified subthreshold circuit netlist, thereby realizing post-simulation of the subthreshold circuit; that is, the operating voltage is used as a calculation factor for the wiring parasitic effects, so when simplifying the wiring parasitic effects, the wiring parasitic effects that can be simplified are accurately simplified, thereby reducing the matrix size of the subthreshold circuit and improving the post-simulation speed and accuracy of the subthreshold circuit.

[0156] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0157] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0158] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A subthreshold circuit post-simulation acceleration method, characterized in that: include: Reading in a subthreshold circuit netlist including wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage; Analyzing the signal flow in the simulation excitation to determine the signal streamline network; Simplifying the parasitic effects of the wiring of the signal streamline network; wherein the parasitic effects of the wiring are related to the operating voltage; the parasitic effects of the wiring include: parasitic capacitance of the wiring; simplifying the parasitic effects of the wiring of the signal streamline network, including: determining the total value of the gate parasitic capacitance of the first device driven by the signal streamline network according to the operating voltage; simplifying the parasitic capacitance of the wiring of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network; simplifying the parasitic capacitance of the wiring of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network, including: determining whether the ratio between the first capacitance and the second capacitance meets the first preset neglect condition; wherein the first capacitance includes the capacitance of at least one of the parasitic capacitances of the wiring, and the second capacitance is the total value of the gate parasitic capacitance of the first device driven by the signal streamline network; if yes, deleting the parasitic capacitance of the wiring corresponding to the first capacitance in the sub-threshold circuit netlist; Circuit simulation is performed on the circuit corresponding to the simplified subthreshold circuit netlist.

2. The subthreshold circuit post-simulation acceleration method according to claim 1, characterized in that: The determining whether the ratio between the first capacitance and the second capacitance satisfies a first preset ignoring condition includes: Determine whether the ratio between the first capacitance and the second capacitance is less than a first set value; wherein the first capacitance is the capacitance of any of the parasitic capacitances of the connection; or, Determine whether the ratio between the first capacitance and the second capacitance is less than a second set value; wherein the first capacitance is the sum of the capacitances of N parasitic capacitances of the connection; N is an integer greater than 1 and less than n, and n is the total number of parasitic capacitances of the connection; or, It is determined whether the ratio of the first capacitance to the second capacitance is less than a third set value; wherein the first capacitance is the sum of the capacitances of the parasitic capacitances of each of the connection lines.

3. The subthreshold circuit post-simulation acceleration method according to claim 1, characterized in that: Before calculating the total value of the gate parasitic capacitance of each first device driven by the signal streamline network according to the operating voltage, the method further includes: Performing temperature analysis on the chip where the subthreshold circuit is located to obtain the temperature distribution of the chip; wherein the temperature distribution of the chip is the temperature of each position on the chip; Based on the temperature distribution and the position where each of the first devices is set in the chip, the temperature corresponding to the position of each of the first devices in the chip is obtained, and the temperature corresponding to the position of each of the first devices in the chip is used as the operating temperature of each of the first devices.

4. The subthreshold circuit post-simulation acceleration method according to claim 3, characterized in that: Calculating the total value of the gate parasitic capacitance of each first device driven by the signal streamline network according to the operating voltage includes: The total value of the gate parasitic capacitance of each first device driven by the signal streamline network is determined according to the operating temperature and the operating voltage of each first device.

5. The subthreshold circuit post-simulation acceleration method according to any one of claims 1 to 4, characterized in that: Simplifying the parasitic effects of the connection of the signal streamline network, further comprising: The connection parasitic resistance of the signal streamline network is simplified according to the equivalent resistance value of each subthreshold device in the DC path in the subthreshold circuit when the subthreshold is turned on.

6. The subthreshold circuit post-simulation acceleration method according to claim 5, characterized in that: According to the equivalent resistance value of each subthreshold device in the DC path in the subthreshold circuit when the subthreshold is turned on, the connection parasitic resistance of the signal flow network is simplified, including: Determine the equivalent resistance value of each subthreshold device on the DC path when the subthreshold device is turned on; Determine whether a ratio between a first resistance value and a second resistance value corresponding to the first resistance value satisfies a second preset ignoring condition; wherein the first resistance value includes the resistance value of at least one parasitic resistance of the connection, and the second resistance value includes the equivalent resistance value of the subthreshold device corresponding to the first resistance value when the subthreshold is turned on; If so, the connection parasitic resistance corresponding to the first resistance value is deleted from the sub-threshold circuit netlist.

7. The subthreshold circuit post-simulation acceleration method according to claim 6, characterized in that: Determining whether a ratio between a first resistance value and a corresponding second resistance value satisfies a second preset ignoring condition includes: Determine whether the ratio between the first resistance value and the second resistance value corresponding to it is less than a fourth set value; wherein the first resistance value includes the resistance value of any one of the parasitic resistances of the connection; and the second resistance value includes the equivalent resistance value of one of the subthreshold devices corresponding to the first resistance value when the subthreshold is turned on; or, Determine whether the ratio between the first resistance value and the second resistance value corresponding to it is less than a fifth set value; wherein the first resistance value includes the sum of the resistance values ​​of the M parasitic resistances of the connection; the second resistance value includes the sum of the equivalent resistance values ​​of the M subthreshold devices corresponding to the first resistance value when the subthreshold is turned on; M is an integer greater than 1 and less than m, and m is the total number of parasitic resistances of the connection; or, Determine whether the ratio between the first resistance value and the second resistance value corresponding to it is less than a sixth set value; wherein the first resistance value includes the sum of the resistance values ​​of each of the parasitic resistances of the connection; and the second resistance value includes the sum of the equivalent resistance values ​​of each of the subthreshold devices corresponding to the first resistance value when the subthreshold is turned on.

8. A subthreshold circuit post-simulation acceleration device, characterized in that: include: A reading unit, used for reading in a subthreshold circuit netlist including wiring parasitic effects; wherein the simulation stimulus in the subthreshold circuit netlist includes an operating voltage; A determination unit, used to analyze the signal flow in the simulation excitation and determine the signal streamline network; A simplified element is used to simplify the parasitic effect of the connection of the signal streamline network; wherein the parasitic effect of the connection is related to the working voltage; the parasitic effect of the connection includes: parasitic capacitance of the connection; simplifying the parasitic effect of the connection of the signal streamline network includes: determining the total value of the gate parasitic capacitance of the first device driven by the signal streamline network according to the working voltage; simplifying the parasitic capacitance of the connection of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network; simplifying the parasitic capacitance of the connection of the signal streamline network according to the total value of the gate parasitic capacitance of the first device driven by the signal streamline network includes: judging whether the ratio between the first capacitance and the second capacitance meets the first preset neglect condition; wherein the first capacitance includes the capacitance of at least one parasitic capacitance of the connection, and the second capacitance is the total value of the gate parasitic capacitance of the first device driven by the signal streamline network; if yes, deleting the parasitic capacitance of the connection corresponding to the first capacitance in the sub-threshold circuit netlist; The simulation unit is used to simulate the circuit corresponding to the simplified subthreshold circuit netlist.

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