Interruption balancing method, device, electronic device and computer-readable storage medium

Abstract

The embodiment of the present application proposes an interrupt balancing method, device, electronic device and readable storage medium. The interrupt balancing method includes: determining a first online core and a second online core with an unbalanced interrupt load; determining the interrupt load to be migrated; calculating the predicted load of each interrupt on the first online core in a future cycle; determining the interrupt to be removed on the first online core according to the predicted load; migrating the interrupt to be removed to the second online core. By calculating the predicted load of each interrupt on the first online core in a future cycle and using it as the basis for determining the interrupt to be migrated, the influence of information lag in interrupt balancing is eliminated, and the real-time performance of interrupt balancing is improved.

Description

[Technical field]

[0001] The embodiments of the present application relate to the technical field of interrupt processing, and in particular to an interrupt balancing method, an interrupt balancing device, an electronic device, and a computer-readable storage medium. [Background technology]

[0002] In the ARM platform, the interrupt controller (GIC) divides interrupts into several different types: software generated interrupt SGI (Software Generated Interrupt), private peripheral shared interrupt PPI (Private Peripheral Interrupt), shared peripheral interrupt SPI (Shared Peripheral Interrupt), and message-based interrupt LPI (locality-specific peripheral interrupts). Among them, the shared peripheral interrupt SPI type of interrupt is not limited to a specific processor core CPUCore, it can be bound to any core in a group of cores. Although SPI interrupts can be shared by multiple cores, in fact, when the Linux Kernel chooses to bind the SPI interrupt to a core, it does not consider the interrupt load on the core, and the SPI interrupt is bound to the first available core by default. When the limited resources on a core cannot meet the interrupt requests that need to be processed centrally, the real-time response of the hardware will inevitably be affected, which will eventually lead to a poor user experience.

[0003] There are some interrupt balancing solutions, such as the open source irqbalance, which have the following shortcomings: In terms of algorithm strategy, the statistics of interrupt load by the open source irqbalance are lagging. Therefore, providing a real-time interrupt balancing method is a technical problem that needs to be solved urgently. [Summary of the invention]

[0004] The embodiments of the present application provide an interrupt balancing method, device, electronic device and computer-readable storage medium. By taking the predicted load of interrupts in a future cycle as the basis for interrupt balancing, the influence of the lag of interrupt statistical information on interrupt balancing is eliminated, and the real-time nature of interrupt balancing is achieved.

[0005] In a first aspect, an embodiment of the present application provides an interrupt balancing method, which is applied to an electronic device using a multi-core processor, wherein the multi-core processor includes at least two online cores, and the method includes:

[0006] Determine a first online core and a second online core with an unbalanced interrupt load, wherein the first online core is an online core to be removed from an interrupt, and the second online core is an online core to be removed from an interrupt;

[0007] Determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core;

[0008] Calculating predicted loads of each interrupt on the first online core in a future cycle;

[0009] Determine, according to the predicted load, an interrupt to be removed from the first online core, wherein the predicted load of the interrupt to be removed is close to or equal to the interrupt load to be migrated;

[0010] Migrate the interrupt to be removed to the second online core.

[0011] In the above interrupt balancing method, by calculating the predicted load of each interrupt on the first online core in a future cycle and using it as the basis for determining the interrupt to be migrated, the influence of information lag in interrupt balancing is eliminated and the real-time performance of interrupt balancing is improved.

[0012] In a possible implementation, determining that there is an interrupt load imbalance between the first online core and the second online core includes:

[0013] Statistics on the interrupt load of each online core in the past cycle;

[0014] A first online core and a second online core having a difference in interrupt load are selected.

[0015] In a possible implementation, determining that there is an interrupt load imbalance between the first online core and the second online core further includes:

[0016] The ratio of the interruption load of the second online core to the interruption load of the first online core is calculated. If the ratio is less than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.

[0017] In a possible implementation manner, determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core includes:

[0018] By formula Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min Interrupt load for the second online core.

[0019] In a possible implementation, the calculating the predicted load of each interrupt on the first online core in a future cycle includes:

[0020] Based on the periodically recorded triggering times of each interrupt on the first online core, the predicted triggering times of each interrupt in a future cycle are calculated by using the EMA algorithm;

[0021] For each interrupt on the first online core, the formula Calculate the predicted load in the next cycle, where L p is the predicted load of the interruption, EMA(x n ) is the predicted triggering number of interrupts in a future cycle, X all is the number of times all interrupts on the first online core are triggered in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

[0022] In a possible implementation, the method is applied to an interrupt balancing performance mode.

[0023] In one possible implementation, the method further includes: calculating interrupt load data, comparing the interrupt load data with a preset first threshold, and when the interrupt load data is greater than the preset first threshold, entering the interrupt balancing performance mode, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.

[0024] In a possible implementation, when in a power saving mode of interrupt balancing, the method includes:

[0025] Determine a third online core, where the third online core is the online core to be interrupted;

[0026] All interrupts on online cores other than the third online core are migrated to the third online core.

[0027] In a possible implementation manner, determining the third online core includes:

[0028] Statistics on the interrupt load of each online core in the past cycle;

[0029] Select the third online core with the largest interrupt load.

[0030] In a possible implementation, when the interrupt load data is less than a preset second threshold, the interrupt balancing power saving mode is entered.

[0031] In a second aspect, an embodiment of the present application further provides an interrupt balancing device, which is applied to an electronic device using a multi-core processor, wherein the multi-core processor includes at least two online cores, and the device includes:

[0032] A first determining module is used to determine a first online core and a second online core with an unbalanced interrupt load, wherein the first online core is an online core to be removed from an interrupt, and the second online core is an online core to be removed from an interrupt;

[0033] A load determination module, configured to determine an interruption load to be migrated according to the interruption loads of the first online core and the second online core;

[0034] A load prediction module, used to calculate the predicted load of each interrupt on the first online core in a future cycle;

[0035] An interrupt determination module, configured to determine an interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is close to or equal to the load of the interrupt to be migrated;

[0036] The first migration module is used to migrate the interrupt to be removed to the second online core.

[0037] In a possible implementation manner, the first determining module includes:

[0038] The first statistical submodule is used to count the interrupt load of each online core in the past cycle;

[0039] The first selection submodule is used to select the first online core and the second online core having a difference in interrupt load.

[0040] In a possible implementation manner, the first determining module further includes:

[0041] The first judgment submodule is used to calculate the ratio of the interruption load of the second online core to the interruption load of the first online core. If the ratio is less than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.

[0042] In a possible implementation, the load determination module is further configured to: Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min Interrupt load for the second online core.

[0043] In a possible implementation, the load prediction module includes:

[0044] A trigger prediction submodule, used for calculating the predicted triggering number of each interrupt in a future cycle by using an EMA algorithm based on the periodically recorded triggering number of each interrupt on the first online core;

[0045] The load prediction submodule is used to calculate the load prediction result of each interruption on the first online core by using the formula Calculate the predicted load in the next cycle, where L p For the predicted load of the interruption, EMA N (x n ) is the predicted triggering number of interrupts in a future cycle, X all is the number of times all interrupts on the first online core are triggered in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

[0046] In a possible implementation manner, the device is applied to an interrupt balancing performance mode.

[0047] In one possible implementation, the device also includes: a performance mode module, which is used to calculate interrupt load data, compare the interrupt load data with a preset first threshold, and enter the interrupt balancing performance mode when the interrupt load data is greater than the preset first threshold, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.

[0048] In a possible implementation, when in a power saving mode of interrupt balancing, the device includes:

[0049] A second determining module is used to determine a third online core, where the third online core is the online core to be interrupted;

[0050] The second migration module is used to migrate all interrupts on online cores other than the third online core to the third online core.

[0051] In a possible implementation manner, the second determining module includes:

[0052] The second statistical submodule is used to count the interrupt load of each online core in the past cycle;

[0053] The second selection submodule is used to select the third online core with the largest interrupt load.

[0054] In a possible implementation, when the interrupt load data is less than a preset second threshold, the interrupt balancing power saving mode is entered.

[0055] In a third aspect, an embodiment of the present application provides an electronic device, comprising: at least one multi-core processor, and at least one memory communicatively connected to the multi-core processor, wherein:

[0056] The memory stores program instructions that can be executed by the multi-core processor, and the multi-core processor calls the program instructions to execute the interrupt balancing method provided in the first aspect.

[0057] The embodiment of the present application further provides an electronic device, comprising: at least one multi-core processor, wherein the multi-core processor is integrated with a memory, wherein:

[0058] The memory stores program instructions that can be executed by the multi-core processor, and the multi-core processor calls the program instructions to execute the interrupt balancing method provided in the first aspect.

[0059] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the interrupt balancing method provided in the first aspect.

[0060] It should be understood that the second to fourth aspects of the embodiments of the present invention are consistent with the technical solutions of the first aspect of the embodiments of the present invention, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be described in detail.

Brief Description of the Drawings

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 A flowchart of an interrupt balancing method provided in an embodiment of the present application;

[0063] Figure 2 A flowchart of another interrupt balancing method provided in an embodiment of the present application;

[0064] Figure 3 A flowchart of another interrupt balancing method provided in an embodiment of the present application;

[0065] Figure 4 A flowchart of another interrupt balancing method provided in an embodiment of the present application;

[0066] Figure 5 A flowchart of another interrupt balancing method provided in an embodiment of the present application;

[0067] Figure 6 A flowchart of another interrupt balancing method provided in an embodiment of the present application;

[0068] Figure 7 A schematic diagram of the structure of an interruption balancing device provided in an embodiment of the present application;

[0069] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. [Specific implementation method]

[0070] In order to better understand the technical solution of this specification, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0071] It should be clear that the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0072] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit this specification. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0073] There are some interrupt balancing solutions in the existing related technologies, such as the open source irqbalance, but they have the following shortcomings: In terms of algorithm strategy, the statistics of interrupt load of the open source irqbalance are lagging.

[0074] Based on the above problems, embodiments of the present application provide an interrupt balancing method, an interrupt balancing device, an electronic device, and a computer-readable storage medium to solve the above problems.

[0075] Figure 1 The present invention provides a flowchart of an interrupt balancing method, which is applied to an electronic device using a multi-core processor, wherein the multi-core processor includes at least two online cores. Figure 1 As shown, the interruption balancing method may include:

[0076] Step 101: determining a first online core and a second online core with an unbalanced interruption load, wherein the first online core is an online core to be interrupted, and the second online core is an online core to be interrupted;

[0077] Step 102: determining an interrupt load to be migrated according to the interrupt loads of the first online core and the second online core;

[0078] Step 103: Calculate the predicted load of each interrupt on the first online core in a future cycle;

[0079] Step 104: determining the interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is close to or equal to the load of the interrupt to be migrated;

[0080] Step 105: Migrate the interrupt to be removed to the second online core.

[0081] It should be noted that the interrupt for balancing in this embodiment can be an SPI shared peripheral interrupt, and SPI can respond on any processor core. The electronic devices mentioned in this embodiment may include but are not limited to the following devices: PC, mobile phone, smart watch, base station, VR device, etc. The multi-core processor used in this embodiment can be an ARM or ARM64 architecture, based on the Linux kernel, including multiple processor cores, and the processor core is divided into an online core and an isolated core according to its working state. The online core means that the core can be used by the process in the user space and can process SPI. The isolated core means that the core is no longer used by the process in the user space and cannot process SPI. Therefore, the processor cores for interrupt balancing in this embodiment are all online cores, and the isolated core cannot participate in interrupt balancing.

[0082] Exemplarily, when performing interrupt balancing, the interrupt balancing program periodically reads the interface file provided by the Linux Kernel to obtain the online or isolated status of each processor core CPU core to determine which cores are online cores to avoid migrating interrupts to inappropriate cores. For example, by reading the interface file / sys / devices / system / cpu / present, you can obtain all available CPUcores in the system, by reading the interface file / sys / devices / system / cpu / core_ctl_isolate, you can obtain the CPUcore Isolated isolation status, and by reading the interface file / sys / devices / system / cpu / online, you can obtain the CPU core Online status. When there is only one CPU core available in the system, there is no need for interrupt balancing. Therefore, the interrupt balancing solution provided in this embodiment is suitable for situations where a multi-core processor includes at least 2 online cores.

[0083] In the above interrupt balancing method, by determining the first online core and the second online core with interrupt load imbalance, wherein the first online core is the online core for interrupts to be removed, and the second online core is the online core for interrupts to be moved in; determining the interrupt load to be migrated; calculating the predicted load of each interrupt on the first online core in a future cycle; determining the interrupt to be removed on the first online core according to the predicted load; and migrating the interrupt to be removed to the second online core, the predicted load of the interrupt in a future cycle is used as the basis for interrupt balancing, thereby eliminating the influence of the interrupt statistical information lag on interrupt balancing and realizing the real-time nature of interrupt balancing.

[0084] In some embodiments, the method of determining in step 101 that the first online core and the second online core have an unbalanced interrupt load may be to directly receive the determination result of other determination programs, or to determine that the first online core and the second online core have an unbalanced interrupt load by calculation.

[0085] Figure 2 A flowchart of another interrupt balancing method provided in an embodiment of the present application is shown as follows: Figure 2 As shown, in Figure 1 In the illustrated embodiment, step 101 may include:

[0086] Step 201: Count the interrupt load of each online core in the past cycle;

[0087] Step 202: Select a first online core and a second online core having a difference in interrupt load.

[0088] It should be noted that the interrupt load of the online core in this embodiment can be represented by the CPU cycles spent on executing the interrupt, which can be directly obtained by reading the / proc / stat file in the interface file provided by the Linux kernel. By periodically reading and saving the / proc / stat file in the interface file provided by the Linux kernel, the CPU cycles spent on executing each interrupt at the current reading time point can be obtained, and the CPU cycles spent on executing each interrupt at the last reading time point can also be obtained. For each interrupt, the CPU cycles corresponding to the current reading time point is subtracted from the CPU cycles at the last reading time point to obtain the interrupt load in the past cycle. Here, one cycle is the time difference between the current reading time point and the last reading time point. The above method is used for calculation for each interrupt, and the interrupt load of each online core in the past cycle can be obtained. The above method is only a feasible method for counting the interrupt load of each online core in the past cycle, but it is not the only method. For example, other performance data can be counted as the interrupt load. Therefore, this embodiment does not limit the above method for counting the interrupt load of each online core in the past cycle.

[0089] In addition, the method for selecting the first online core and the second online core with a difference in interrupt load may be to set a difference threshold, and select two online cores whose interrupt load difference is greater than the difference threshold according to the difference threshold, or to sort the obtained interrupt loads, and select the online core with the largest interrupt load and the online core with the smallest interrupt load as the first online core and the second online core with a difference in interrupt load. This embodiment is not limited to the use of these methods. Therefore, this embodiment does not limit the above method for selecting the first online core and the second online core with a difference in interrupt load.

[0090] Figure 3 A flowchart of another interrupt balancing method provided in an embodiment of the present application is shown as follows: Figure 3 In the interruption balancing method shown, step 101 may further include step 203 .

[0091] Step 203: Calculate the ratio of the interruption load of the second online core to the interruption load of the first online core. If the ratio is less than a preset balance threshold, obtain the first online core and the second online core with load imbalance.

[0092] Here, the degree of imbalance of the interrupt loads of the two online cores is determined by calculating the ratio of the interrupt loads of the two online cores. It is a more scientific determination method to compare with the preset balancing threshold to determine whether interrupt balancing is needed. It can avoid interrupt balancing for some minor imbalances, resulting in waste of equipment power consumption, and the effect of interrupt balancing is not obvious. The above calculation method is illustrated by an example: the interrupt loads of each online core in the past cycle are obtained by statistics, core0: 40000 / S, core1: 26000 / S, core3: 24000 / S, core3: 10000 / S, and the preset balancing threshold is 0.8. According to the statistical results, the interrupt load of core0 is the largest and the interrupt load of core3 is the smallest. The interrupt load ratio of core3 to core0 is calculated to be 10000 / 40000=0.25. Since 0.25 is less than 0.8, it is determined that interrupt balancing is needed for core0 and core3.

[0093] In some embodiments, there are multiple methods for determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core in step 102. For example, half of the difference in the interrupt loads of the two online cores can be set as the interrupt load to be migrated, or 40 percent or 60 percent of the interrupt load difference can be set as the interrupt load to be migrated. The setting can be made according to the requirements of the application scenario. This embodiment does not limit the method for determining the interrupt load to be migrated.

[0094] For example, the formula Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min is the interrupt load of the second online core. Taking half of the difference in the interrupt loads of the two online cores as the interrupt load to be migrated can ensure that the interrupt loads of the two online cores are balanced after migration. For example, the interrupt load of core1 is: 40000 / S, and the interrupt load of core2 is: 10000 / S. Using the formula The interruption load to be migrated is calculated to be: (40000-10000) / 2=15000.

[0095] In some embodiments, step 103 calculates the load of each interrupt on the online core to be removed from the interruption not by a prediction method, but by calculating the current load based on current data. The load calculated in this way will have errors after the interruption is migrated, because the load of the interruption is changing in real time, and may increase or decrease. If the interruption is migrated according to the current load, after we migrate the interruption to the online core to be moved in, the load of the interruption has increased or decreased, which will cause the problem that the interruptions on the two online cores are still unbalanced after the interruption migration. Therefore, this embodiment adopts a method for calculating the predicted load of each interruption on the first online core in the next cycle. There are many methods for predicting the load. For example, the predicted load can be calculated by using an average algorithm based on the number of interruption triggers, or the predicted load can be calculated by using an exponential moving average EMA algorithm based on the number of interruption triggers. This embodiment does not limit the above method for calculating the predicted load of each interruption on the first online core.

[0096] For example, Figure 4 A flowchart of an interrupt balancing method provided by another embodiment of the present application is shown as follows: Figure 4 As shown, in Figure 1 In the illustrated embodiment, step 103 may include:

[0097] Step 301: Based on the periodically recorded triggering times of each interrupt on the first online core, the predicted triggering times of each interrupt in a future cycle are calculated by using an EMA algorithm;

[0098] Step 302: For each interrupt on the first online core, the formula Calculate the predicted load in the next cycle, where L p For the predicted load of the interruption, EMA N (x n ) is the predicted number of interrupt triggers in the next cycle, X all is the number of interrupts triggered on the first online core in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

[0099] It should be noted that, since the Linux Kernel cannot accurately obtain the actual load value of each interrupt, this embodiment uses the number of interrupt triggers within a cycle as the basis for judging the load size of the interrupt. When performing interrupt balancing, the interrupt balancing program will periodically read the interface file provided by the Linux Kernel, count the interrupt type and the current total triggering number of each interrupt on each CPU core, and obtain the average increment of each CPU core per second based on the current statistical data and the previous statistical data, and then predict the load value of each interrupt through the EMA algorithm.

[0100] For example, assuming that the interface file provided by the Linux Kernel is read once every 5 seconds, the current statistical results of the first 4 triggering times of interrupt a on core1 are: data at time point t1: 10s, 1000 times; data at time point t2: 15.1s, 1510 times; data at time point t3: 20s, 2245 times; data at time point t4: 25s, 2745 times; 15.1s is the delay in reading data due to an emergency, but since what we need is the time difference and the difference in the number of triggering times, the delay in reading data will not affect the calculation results.

[0101] Calculate the average number of times interrupt a is triggered per second in period t1-t2: x1 = (1510-1000) / (15.1-10) = 100 times. Similarly, calculate the average number of times interrupt a is triggered per second in period t2-t3: x2 = (2245-1510) / (20-15.1) = 150 times. Calculate the average number of times interrupt a is triggered per second in period t3-t4: x3 = (2745-2245) / (25-20) = 100 times.

[0102] According to the exponential moving average EMA algorithm recursive formula: EMA N (x1) = x1, where N represents the number of cycles, N = 3, then EMA3(x1) = x1 = 100, Then, in the next cycle, the predicted triggering times of interrupt a on core1 is 112.5 times per second. By periodically obtaining the total triggering times of interrupts, calculating the triggering times of interrupts per second in each cycle, and using the EMA algorithm to calculate the predicted triggering times of each interrupt based on the recorded triggering times per second of multiple cycles, the triggering times of the next cycle interrupt can be predicted more accurately, laying the foundation for accurately calculating the interrupt load.

[0103] According to the predicted trigger times, the predicted liabilities in the next cycle can be calculated. The calculation formula is: For example, for interrupt a on the first online core, Lp For the predicted load of interrupt a, EMA N (x n ) is the predicted triggering number of interrupt a in the next cycle, X all is the number of interrupts triggered on the first online core in the past cycle, Δt is the time of a cycle, L all The interrupt load of the first online core in the past cycle. EMA N (x n ) has been obtained in the above steps, X all It is obtained by adding the number of times all interrupts on core1 are triggered in the previous cycle obtained in the above steps. Δt is 5 seconds, L all Expressed as the CPU cycles it takes to execute interrupts, the interrupt load of the first online core in the past cycle can be expressed as: Where t′ represents the time point of the second data reading, t represents the time point of the first data reading, and C′ hardirq , C′ softirq Indicates the CPU cycles spent by hard interrupts and soft interrupts since the second reading of the system startup, C hardirq , C softirq Indicates the CPU cycles spent by hard interrupts and soft interrupts since the first reading of the system startup. The CPU cycles spent on reading hard interrupts and soft interrupts can be directly obtained by reading the / proc / stat file in the interface file provided by the Linux kernel.

[0104] The predicted liability of interrupt a on core 1 is calculated by the above method, and the predicted load of each interrupt on core 1 is calculated in the same way. By using the EMA algorithm to calculate the predicted load of each interrupt on the first online core in the next cycle, accurate basic data can be provided for interrupt balancing, ensuring the accuracy of interrupt balancing.

[0105] In some embodiments, step 104 determines the interrupts to be removed from the first online core according to the predicted load, and selects the interrupts to be removed according to the predicted loads of each interrupt on the first online core calculated in step 103, so that the predicted load of the interrupt to be removed is equal to the load of the interrupt to be migrated calculated in step 102. If there are no completely equal interrupts to be removed, then the interrupt to be removed with the closest value is selected. The interrupt to be removed here can be one or more than one. If more than one interrupt is selected, then the sum of the predicted loads of the more than one interrupts selected needs to be equal to or close to the load of the interrupt to be migrated.

[0106] In some embodiments, step 105 migrates the interrupts to be removed from the first online core to the second online core, and the affinity of these interrupts can be set through the / proc / irq / * / smp_affinity node, and then the interrupts to be migrated are bound to the second online core.

[0107] In some embodiments, interrupt balancing includes a performance mode, and the above interrupt balancing method is applied to the performance mode of interrupt balancing. The performance mode of interrupt balancing mainly sends interrupts to multiple CPU cores when the total interrupt load is high to improve the interrupt processing capability and system real-time performance.

[0108] In some embodiments, a first threshold is preset. When the interruption load data is greater than the preset first threshold, the interruption balancing performance mode is entered. The content of the interruption load data can be multiple, for example, it can be data such as the number of interruptions, the interruption load ratio, etc. This embodiment does not limit the content of the interruption load data.

[0109] For example, Figure 5 A flowchart of another interrupt balancing method provided in an embodiment of the present application is shown as follows: Figure 5 As shown, step 101 includes step 401. Step 401: Calculate interrupt load data, compare the interrupt load data with a preset first threshold, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load. When the interrupt load data is greater than the preset first threshold, enter the interrupt balancing performance mode. The ratio of the interrupt load to the total load can reflect the size of the current interrupt load in the total processor load. If it exceeds the preset first threshold, it means that the total amount of the current interrupt load has reached a certain level and needs to be balanced, then enter the interrupt balancing performance mode.

[0110] In some embodiments, interrupt balancing includes a power saving mode. In performance mode, interrupt balancing increases the possibility of the CPU exiting the Standby / Power Down state, which has a certain impact on system power consumption. Therefore, the power saving mode of interrupt balancing is mainly to concentrate interrupts on one or several cores for processing when the interrupt load is low, thereby reducing power consumption.

[0111] For example, Figure 6 A flowchart of another interrupt balancing method provided in an embodiment of the present application is shown as follows: Figure 6As shown, step 101 includes step 501, step 501: calculating interrupt load data, comparing the interrupt load data with a preset first threshold and a preset second threshold, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load. When the interrupt load data is greater than the preset first threshold, the interrupt balancing performance mode is entered, and when the interrupt load data is less than the preset second threshold, the interrupt balancing power saving mode is entered. When in the interrupt balancing power saving mode, the interrupt balancing method includes:

[0112] Step 601: determining a third online core, where the third online core is an online core to be interrupted;

[0113] Step 602: Migrate all interrupts on online cores other than the third online core to the third online core.

[0114] It should be noted that the third online core can be any online core. After the third online core is determined, all interrupts on other cores can be migrated to the third online core, thereby achieving the purpose of reducing device power consumption.

[0115] Exemplarily, determining the third online core may include: counting the interrupt load of each online core in the past cycle; and selecting the third online core with the largest interrupt load. It is understandable that the third online core may be the online core with the largest interrupt load, so that when migrating interrupts of other cores to the third online core, the time spent is shorter, the power consumption loss is smaller, and it is more suitable for embedded platforms.

[0116] It is understandable that some other parameters can be set in the interrupt balancing method according to the application scenario, such as which cores to balance on, the time interval of balancing, etc. In addition, some other steps can be added to the interrupt balancing method, such as turning on interrupt balancing; checking the number of currently available CPU cores, and exiting interrupt balancing if there is only one available core; controlling whether interrupt balancing runs in the background; controlling whether to output logs, etc., so that the interrupt balancing method can better match the application scenario and user needs.

[0117] The interruption balancing method provided by this embodiment is described below by way of example: the first threshold is preset to be 0.15, the second threshold is preset to be 0.11, and the balancing threshold is 0.8.

[0118] Solution 1: (1) It is counted that the CPU cycles spent on interrupt processing on the CPU in the past cycle is 100,000, and the CPU cycles spent on the CPU processing all tasks is 500,000. The ratio of the interrupt load to the total load is calculated to be 100,000 / 500,000=0.2, which is greater than the preset first threshold, and the performance mode is entered.

[0119] (2) Statistics of the interrupt load of each Core in the past cycle (unit: CPU cycles / S) are as follows: Core0: 40000, Core1: 26000, Core2: 24000, Core3: 10000; According to the statistical results, Core0 has the largest interrupt load, irqload max =40000, Core3 has the smallest interrupt load, irqload min =10000,irqload min / irqload max =0.25, which is less than the balancing threshold of 0.8, so interrupt balancing is required for Core0 and Core3.

[0120] (3) Calculate the interrupt load to be migrated: L d =(irqload max -irqload min ) / 2=15000.

[0121] (4) Traverse all interrupts on Core 0 and calculate the predicted load of each SPI interrupt (unit: CPU cycles / S). The results are as follows: interrupt number 40, predicted load 1000, interrupt number 43, predicted load 18000, interrupt number 52, predicted load 14000, interrupt number 63, predicted load 1000, interrupt number 74, predicted load 300, interrupt number 105, predicted load 2000.

[0122] (5) Traverse all SPI interrupts on Core0 and find that the predicted load of interrupt 52 is closest to the interrupt load to be migrated: L d = 15000. Interrupt migration decision result: Migrate interrupt 52 on Core0 to Core3.

[0123] (6) By setting the / proc / irq / 52 / smp_affinity file node, interrupt 52 is bound to Core3, completing the interrupt migration between Core0 and Core3.

[0124] (7) For the remaining Core1 and Core2, irqload min / irqload max =24000 / 26000=0.923, which is greater than the balancing threshold of 0.8. Therefore, there is no need to interrupt the migration, and the interruption balancing is completed.

[0125] Solution 2: (1) The CPU cycles spent on interrupt processing on the CPU in the past cycle are counted as 100,000, and the CPU cycles spent on processing all tasks on the CPU are 1,000,000. The ratio of the interrupt load to the total load is calculated to be 100,000 / 1,000,000=0.1, which is less than the preset second threshold, and the power saving mode is entered.

[0126] (2) Statistics of the interrupt load of each core in the past cycle (unit: CPU cycles / S) are as follows: Core0: 40000, Core1: 30000, Core2: 20000, Core3: 10000. According to the statistical results, Core0 has the largest interrupt load, and the interrupt balancing decision result is: migrate all SPI interrupts to Core0.

[0127] (3) By setting the / proc / irq / * / smp_affinity file node, all SPI interrupts are bound to Core0 to complete interrupt migration.

[0128] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

[0129] The beneficial effects of the interrupt balancing method provided by this embodiment include: 1. Power-sensitive devices, such as smart watches, can reduce standby power consumption after adopting the interrupt balancing method. 2. Performance-sensitive devices, such as base stations, can improve the interrupt processing capability of the device after adopting the interrupt balancing solution, thereby improving IO throughput. 3. Devices that have requirements for both power consumption and performance, such as smart phones, can reduce power consumption under low load conditions and improve performance under high load conditions by adopting the interrupt balancing solution.

[0130] Figure 7 Schematic diagram of the structure of an interruption equalization device provided in an embodiment of the present application, wherein the interruption equalization device is arranged in an electronic device, such as Figure 7 As shown, the above interruption balancing device may include: a first determination module 71, a load determination module 72, a load prediction module 73, an interruption determination module 74 and a first migration module 75, wherein:

[0131] A first determining module 71 is used to determine a first online core and a second online core with an unbalanced interrupt load, wherein the first online core is an online core to be interrupted and the second online core is an online core to be interrupted;

[0132] A load determination module 72, configured to determine an interrupt load to be migrated according to the interrupt loads of the first online core and the second online core;

[0133] A load prediction module 73, used to calculate the predicted load of each interrupt on the first online core in a future cycle;

[0134] An interrupt determination module 74, configured to determine an interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is close to or equal to the load of the interrupt to be migrated;

[0135] The first migration module 75 is used to migrate the interrupt to be removed to the second online core.

[0136] Wherein, the first determining module 71 includes:

[0137] The first statistical submodule is used to count the interrupt load of each online core in the past cycle;

[0138] The first selection submodule is used to select the first online core and the second online core having a difference in interrupt load.

[0139] Wherein, the first determining module 71 further includes:

[0140] The first judgment submodule is used to calculate the ratio of the interruption load of the second online core to the interruption load of the first online core. If the ratio is less than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.

[0141] The load determination module 72 is further configured to: Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min Interrupt load for the second online core.

[0142] Wherein, the load prediction module 73 includes:

[0143] A trigger prediction submodule, used for calculating the predicted triggering number of each interrupt in a future cycle by using an EMA algorithm based on the periodically recorded triggering number of each interrupt on the first online core;

[0144] The load prediction submodule is used to calculate the load prediction result of each interruption on the first online core by using the formula Calculate the predicted load in the next cycle, where L p For the predicted load of the interruption, EMA N (xn ) is the predicted triggering number of interrupts in a future cycle, X all is the number of interrupts triggered on the first online core in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

[0145] The device is applied to the performance mode of interrupt balancing.

[0146] Among them, the device also includes a performance mode module, which is used to calculate interrupt load data, compare the interrupt load data with a preset first threshold, and enter the interrupt balancing performance mode when the interrupt load data is greater than the preset first threshold. The interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.

[0147] Wherein, when in the power saving mode of interrupt balancing, the device includes:

[0148] A second determining module is used to determine a third online core, where the third online core is the online core to be interrupted;

[0149] The second migration module is used to migrate all interrupts on online cores other than the third online core to the third online core.

[0150] Wherein, the second determining module includes:

[0151] The second statistical submodule is used to count the interrupt load of each online core in the past cycle;

[0152] The second selection submodule is used to select the third online core with the largest interrupt load.

[0153] When the interrupt load data is less than a preset second threshold, the interrupt balancing power saving mode is entered.

[0154] Figure 7 The interruption balancing device provided in the embodiment shown can be used to implement the present invention Figure 1 The technical solution of the method embodiment shown, its implementation principle and technical effects can be further referred to the relevant description in the method embodiment.

[0155] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the electronic device may include: at least one multi-core processor, and at least one memory in communication with the multi-core processor, wherein: the memory stores program instructions that can be executed by the multi-core processor, and the multi-core processor calls the program instructions to execute the instructions of this specification. Figure 1 to Figure 6The illustrated embodiment provides an interruption balancing method.

[0156] In some embodiments, the electronic device may include: at least one multi-core processor, the multi-core processor integrated with a memory, wherein: the memory stores program instructions executable by the multi-core processor, and the multi-core processor calls the program instructions to execute Figure 1 to Figure 6 The illustrated embodiment provides an interruption balancing method.

[0157] The electronic device may be a smart electronic device such as a smart phone, a tablet computer or a laptop computer, and the present embodiment does not limit the form of the electronic device.

[0158] For example, Figure 8 Taking a smart phone as an example, a schematic diagram of the structure of an electronic device is shown. Figure 8 As shown, the electronic device 100 may include a multi-core processor 110, an external memory interface 120, an internal memory 121, an antenna 1, an antenna 2, a mobile communication module 130, a wireless communication module 140, a camera 150, a display screen 160, a button 170, etc.

[0159] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0160] The multi-core processor 110 includes two or more processor cores, and may also include one or more processing units, for example: the multi-core processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and / or a neural-network processing unit (neural-network processing unit, NPU), etc. Among them, different processing units may be independent devices, or may be integrated in one or more processors.

[0161] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0162] A memory may also be provided in the multi-core processor 110 for storing instructions and data. In some embodiments, the memory in the multi-core processor 110 is a cache memory. The memory may store instructions or data that have just been used or are cyclically used by the multi-core processor 110. If the multi-core processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the multi-core processor 110, and thus improves the efficiency of the system.

[0163] The electronic device 100 includes multiple external devices, such as a camera 150, a display screen 160, and a button 170. The multiple external devices are respectively connected to the multi-core processor 110 for communication. Each external device has its own interrupt request IRQ. Based on the IRQ, the multi-core processor 110 can distribute the corresponding request to the corresponding hardware driver. The driver that handles the interrupt needs to run on the multi-core processor 110. Therefore, when an interrupt occurs, the multi-core processor 110 will temporarily stop the current program and execute the interrupt request instead. When multiple interrupt requests are bound to a processor core at the same time, the limited resources on this processor core cannot meet the interrupt requests that need to be processed centrally. The multi-core processor 110 executes various functional applications and data processing by running the program stored in the internal memory 121, such as executing the present application Figure 1 to Figure 6 The interrupt balancing method provided by the illustrated embodiment performs interrupt balancing on interrupt requests that need to be processed centrally.

[0164] In some embodiments, the multi-core processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0165] The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 130, the wireless communication module 140, the modem processor and the baseband processor.

[0166] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0167] The mobile communication module 130 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 100. The mobile communication module 130 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 130 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 130 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 130 can be set in the multi-core processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 130 can be set in the same device as at least some of the modules of the multi-core processor 110.

[0168] The modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 160. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the multi-core processor 110 and be set in the same device as the mobile communication module 130 or other functional modules.

[0169] The wireless communication module 140 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 140 can be one or more devices integrating at least one communication processing module. The wireless communication module 140 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the multi-core processor 110. The wireless communication module 140 can also receive the signal to be sent from the multi-core processor 110, modulate the frequency of the signal, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0170] In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 130, and the antenna 2 is coupled to the wireless communication module 140, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include a global positioning system (GPS), a global navigation satellite system (GLONASS), a Beidou navigation satellite system (BDS), a quasi-zenith satellite system (QZSS) and / or a satellite based augmentation system (SBAS).

[0171] The electronic device 100 implements the display function through a GPU, a display screen 160, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 160 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The multi-core processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0172] The display screen 160 is used to display images, videos, etc. The display screen 160 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 160, where N is a positive integer greater than 1.

[0173] The electronic device 100 can realize the shooting function through the ISP, the camera 150, the video codec, the GPU, the display screen 160 and the application processor.

[0174] The ISP is used to process the data fed back by the camera 150. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. The ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP can be set in the camera 150.

[0175] The camera 150 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 150, where N is a positive integer greater than 1.

[0176] The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

[0177] Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0178] NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. Through NPU, applications such as intelligent cognition of electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0179] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the multi-core processor 110 through the external memory interface 120 to implement a data storage function, such as storing music, video and other files in the external memory card.

[0180] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area can store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory and may also include a non-volatile memory.

[0181] The key 170 includes a power key, a volume key, etc. The key 170 may be a mechanical key or a touch key. The electronic device 100 may receive key input and generate key signal input related to user settings and function control of the electronic device 100.

[0182] The present application provides a computer-readable storage medium storing computer instructions, which enables the computer to execute the instructions in this specification. Figure 1 to Figure 6 The illustrated embodiment provides an interruption balancing method.

[0183] The above-mentioned computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0184] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0185] The program code embodied on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0186] Computer program code for performing the operations of the present specification may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0187] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0188] In the description of the embodiments of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0189] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this specification, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0190] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of this specification includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of this specification belong.

[0191] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0192] It should be noted that the terminals involved in the embodiments of the present application may include but are not limited to personal computers (PCs), personal digital assistants (PDAs), wireless handheld devices, tablet computers, mobile phones, MP3 players, MP4 players, etc.

[0193] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0194] In addition, each functional unit in each embodiment of this specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0195] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0196] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. An interruption balancing method, characterized in that: Applied to an electronic device using a multi-core processor, the multi-core processor includes at least 2 online cores, the method includes: Determine a first online core and a second online core with an unbalanced interrupt load, wherein the first online core is an online core to be removed from an interrupt, and the second online core is an online core to be removed from an interrupt; Determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core; Calculating predicted loads of each interrupt on the first online core in a future cycle; Determine, according to the predicted load, an interrupt to be removed from the first online core, wherein the predicted load of the interrupt to be removed is close to or equal to the interrupt load to be migrated; Migrating the interrupt to be removed to the second online core; The calculating of the predicted load of each interrupt on the first online core in a future cycle includes: Based on the periodically recorded triggering times of each interrupt on the first online core, the predicted triggering times of each interrupt in a future cycle are calculated by using the EMA algorithm; For each interrupt on the first online core, the formula Calculate the predicted load in the next cycle, where L p For the predicted load of the interruption, EMA N (x n ) is the predicted triggering number of interrupts in a future cycle, X all is the number of interrupts triggered on the first online core in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

2. The method according to claim 1, characterized in that The determining of the first online core and the second online core having an interrupt load imbalance comprises: Statistics on the interrupt load of each online core in the past cycle; A first online core and a second online core having a difference in interrupt load are selected.

3. The method according to claim 2, characterized in that The determining that there is an interrupt load imbalance between the first online core and the second online core further includes: The ratio of the interruption load of the second online core to the interruption load of the first online core is calculated. If the ratio is less than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.

4. The method according to claim 1, characterized in that: The determining the interrupt load to be migrated according to the interrupt loads of the first online core and the second online core comprises: By formula Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min Interrupt load for the second online core.

5. The method according to claim 1, characterized in that The method is applied to the performance mode of interrupt balancing.

6. The method according to claim 5, characterized in that Also includes: Calculate interrupt load data, compare the interrupt load data with a preset first threshold, and enter the interrupt balancing performance mode when the interrupt load data is greater than the preset first threshold, wherein the interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.

7. The method according to claim 1, 5 or 6, characterized in that: When in the power saving mode of interrupt balancing, the method comprises: Determine a third online core, where the third online core is the online core to be interrupted; All interrupts on online cores other than the third online core are migrated to the third online core.

8. The method according to claim 7, characterized in that Determining the third online core comprises: Statistics on the interrupt load of each online core in the past cycle; Select the third online core with the largest interrupt load.

9. The method according to claim 7, characterized in that: When the interrupt load data is less than a preset second threshold, the interrupt balancing power saving mode is entered.

10. An interruption balancing device, characterized in that: Applicable to an electronic device using a multi-core processor, the multi-core processor includes at least 2 online cores, and the device includes: A first determining module is used to determine a first online core and a second online core with an unbalanced interruption load, wherein the first online core is an online core to be removed from an interruption, and the second online core is an online core to be removed from an interruption; A load determination module, configured to determine an interruption load to be migrated according to the interruption loads of the first online core and the second online core; A load prediction module, used to calculate the predicted load of each interrupt on the first online core in a future cycle; An interrupt determination module, configured to determine an interrupt to be removed from the first online core according to the predicted load, wherein the predicted load of the interrupt to be removed is close to or equal to the load of the interrupt to be migrated; A first migration module, used for migrating the interrupt to be removed to the second online core; The load prediction module includes: A trigger prediction submodule, used for calculating the predicted triggering number of each interrupt in a future cycle by using an EMA algorithm based on the periodically recorded triggering number of each interrupt on the first online core; The load prediction submodule is used to calculate the load prediction result of each interruption on the first online core by using the formula Calculate the predicted load in the next cycle, where L p For the predicted load of the interruption, EMA N (x n ) is the predicted triggering number of interrupts in a future cycle, X all is the number of interrupts triggered on the first online core in the past cycle, Δt is the time of a cycle, L all is the interrupt load of the first online core in the past cycle.

11. The device according to claim 10, characterized in that The first determining module comprises: The first statistical submodule is used to count the interrupt load of each online core in the past cycle; The first selection submodule is used to select the first online core and the second online core having a difference in interrupt load.

12. The device according to claim 11, characterized in that The first determining module also includes: The first judgment submodule is used to calculate the ratio of the interruption load of the second online core to the interruption load of the first online core. If the ratio is less than a preset balance threshold, the first online core and the second online core with unbalanced load are obtained.

13. The device according to claim 10, characterized in that The load determination module is also used to, through the formula Calculate the interruption load to be migrated, where L d The interrupt load to be migrated, irqload max The interrupt load of the first online core, irqload min Interrupt load for the second online core.

14. The device according to claim 10, characterized in that The device is applied to the performance mode of interrupt balancing.

15. The device according to claim 14, characterized in that It also includes a performance mode module, which is used to calculate interrupt load data, compare the interrupt load data with a preset first threshold, and enter the interrupt balancing performance mode when the interrupt load data is greater than the preset first threshold. The interrupt load data represents the ratio of the interrupt load processed by the multi-core processor to the total load.

16. The device according to claim 10, 14 or 15, characterized in that When in the power saving mode of interrupt balancing, the device comprises: A second determining module is used to determine a third online core, where the third online core is the online core to be interrupted; The second migration module is used to migrate all interrupts on online cores other than the third online core to the third online core.

17. The device according to claim 16, characterized in that The second determining module comprises: The second statistical submodule is used to count the interrupt load of each online core in the past cycle; The second selection submodule is used to select the third online core with the largest interrupt load.

18. The device according to claim 16, characterized in that When the interrupt load data is less than a preset second threshold, the interrupt balancing power saving mode is entered.

19. An electronic device comprising: At least one multi-core processor, and at least one memory communicatively connected to the multi-core processor, wherein: The memory stores program instructions that can be executed by the multi-core processor, and the multi-core processor can execute the interrupt balancing method as claimed in any one of claims 1 to 9 by calling the program instructions.

20. An electronic device, comprising: At least one multi-core processor having an integrated memory, wherein: The memory stores program instructions that can be executed by the multi-core processor, and the multi-core processor can execute the interrupt balancing method as claimed in any one of claims 1 to 9 by calling the program instructions.

21. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the interruption balancing method according to any one of claims 1 to 9.

Images