Internal voltage generator and smart card comprising the same

Abstract

An internal voltage generator of a smart card and a smart card including the same are provided. The internal voltage generator can include a mode detector generating a mode signal indicating a contact mode or a contactless mode, a low dropout (LDO) regulator including an error amplifier, wherein the LDO regulator, in response to the mode signal: in the contact mode, drives the error amplifier with a second driving voltage to generate an error voltage, and adjusts the second driving voltage based on the error voltage to generate a first output voltage, and in the contactless mode, drives the error amplifier with a first driving voltage to generate the error voltage, and adjusts the second driving voltage based on the error voltage to generate the first output voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0084735, filed on July 9, 2020, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The embodiments of this disclosure generally relate to smart cards, and more specifically, to the internal voltage generator of a smart card. Background Technology

[0004] Smart cards, also known as chip cards or integrated circuit (IC) cards, can be categorized into contact cards, contactless cards, and hybrid cards (or "hybrid cards") based on how they are used. Contact cards include contact terminals on their surface, to which an external power source is supplied. Contactless cards include contact terminals, such as an antenna, that receive radio frequency signals to generate power voltage and data signals. Hybrid cards can operate as contact cards in contact mode and as contactless cards in contactless mode. Any of the above types of smart cards may also include a fingerprint sensor for fingerprint authentication, allowing secure data communication, such as payment requests. Summary of the Invention

[0005] Example embodiments provide an internal voltage generator in a smart card to perform fingerprint authentication. Example embodiments also provide a smart card including an internal voltage generator capable of stably providing an output voltage in both contact and contactless modes.

[0006] According to some example embodiments, the internal voltage generator of a smart card (e.g., with fingerprint authentication capability) includes a pattern detector, a switched capacitor circuit, and a low dropout (LDO) regulator. The pattern detector generates a pattern signal indicating one of a contact mode and a contactless mode, wherein the smart card provides an input voltage by directly contacting an external card reader in contact mode, or by receiving an input voltage from the card reader without directly contacting it in contactless mode. The switched capacitor circuit generates a first drive voltage and a second drive voltage based on a rectified voltage obtained by rectifying the input voltage, wherein the level of the second drive voltage is lower than the level of the first drive voltage. The LDO regulator includes an error amplifier. In the contact mode, the LDO regulator drives the error amplifier with the second drive voltage to generate an error voltage and adjusts the second drive voltage based on the error voltage to generate a first output voltage; and in the contactless mode, it drives the error amplifier with the first drive voltage to generate an error voltage and adjusts the second drive voltage based on the error voltage to generate the first output voltage.

[0007] According to some example embodiments, a smart card performing fingerprint authentication includes a connection interface and a smart card chip. The connection interface, which may or may not be in direct contact with an external card reader, provides a voltage received from the card reader as an input voltage. The smart card chip is coupled to the connection interface via a first power terminal and a second power terminal. The smart card chip includes an internal voltage generator, a fingerprint sensor, and a processor. The internal voltage generator generates a first driving voltage and a second driving voltage based on the input voltage, adjusts the second driving voltage based on the second driving voltage to generate a first output voltage in contact mode, or adjusts the second driving voltage based on the first driving voltage to generate the first output voltage in contactless mode based on a mode signal, and adjusts the first driving voltage to generate the second output voltage without considering the mode signal. The mode signal indicates one of a contact mode and a contactless mode, and the smart card provides the input voltage in direct contact with an external card reader in contact mode, or in contactless mode without contact with an external card reader. The voltage level of the second driving voltage is lower than the voltage level of the first driving voltage. The fingerprint sensor operates based on the second output voltage and generates a fingerprint image signal based on the input fingerprint. The processor operates based on the first output voltage and performs fingerprint authentication based on the fingerprint image signal.

[0008] According to some example embodiments, the internal voltage generator of a smart card configured to perform fingerprint authentication includes a pattern detector, a switched capacitor circuit, and a low dropout (LDO) regulator. The pattern detector generates a pattern signal indicating one of a contact mode or a contactless mode, and the smart card provides an input voltage in contact with an external card reader in contact mode, or in contactless mode without direct contact with an external card reader. The switched capacitor circuit generates a first drive voltage and a second drive voltage based on a rectified voltage obtained by rectifying the input voltage, wherein the level of the second drive voltage is lower than the level of the first drive voltage. The LDO regulator includes an error amplifier, a first power transistor, and a second power transistor. In contact mode, the LDO regulator drives the error amplifier with the second drive voltage to generate an error voltage, and adjusts the second drive voltage based on the error voltage to generate a first output voltage using the first power transistor; while in contactless mode, the error amplifier is driven with the first drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage to generate the first output voltage using the second power transistor.

[0009] In some aspects, the internal voltage generator of the smart card performing fingerprint authentication and the smart card including the generator may include an LDO regulator. In contact mode and contactless mode, the LDO regulator drives an error amplifier with a second drive voltage and a first drive voltage having different voltage levels, respectively. A first power transistor implemented with a PMOS transistor adjusts the second drive voltage based on the first error voltage to provide a first output voltage in contact mode, and a second power transistor implemented with an NMOS transistor adjusts the second drive voltage based on the first error voltage to provide a first output voltage in contactless mode. Therefore, the LDO regulator can stably provide a first output voltage to the logic block in both contact mode and contactless mode. Attached Figure Description

[0010] The above and other features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a view illustrating a smart card system according to some example embodiments.

[0012] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram illustrating an example of a smart card in a smart card system.

[0013] Figure 3 An example embodiment is shown. Figure 2 An example of a rectifier in a smart card chip.

[0014] Figure 4 An example embodiment is shown. Figure 2 An example of a pattern detector in a smart card chip.

[0015] Figure 5 This illustrates an example embodiment. Figure 2 A block diagram of an example of an internal voltage generator in a smart card chip.

[0016] Figure 6 This illustrates an example embodiment. Figure 5 A circuit diagram of an example of the first switched capacitor in the internal voltage generator.

[0017] Figure 7 This illustrates an example embodiment. Figure 5 A circuit diagram of another example of the first switched capacitor in the internal voltage generator.

[0018] Figure 8 It shows Figure 6 Example operation of the first switched capacitor converter.

[0019] Figure 9 It shows Figure 6 Example operation of the first switched capacitor converter.

[0020] Figure 10 This illustrates an example embodiment. Figure 5 A circuit diagram of an example LDO regulator in an internal voltage generator.

[0021] Figure 11 This illustrates an example embodiment. Figure 10 Circuit diagram of an LDO regulator.

[0022] Figure 12 This illustrates, according to an example embodiment, in contact mode. Figure 11 Example operation of an LDO regulator.

[0023] Figure 13 This illustrates, according to an example embodiment, in contactless mode. Figure 11 Example operation of an LDO regulator.

[0024] Figure 14 This illustrates an example embodiment. Figure 5 A circuit diagram of an example voltage regulator in an internal voltage generator.

[0025] Figure 15 This illustrates an example embodiment. Figure 10 A circuit diagram of an example error amplifier in an LDO regulator.

[0026] Figure 16 and 17 This is a schematic diagram illustrating an example of communication signals for a Type A interface used in the International Organization for Standardization (ISO / IEC) 14442 standard.

[0027] Figure 18 This is a view showing an example of a frame and pause of a Type A interface according to the ISO / IEC 14442 standard.

[0028] Figure 19 An example embodiment is shown. Figure 2 An example of a fingerprint recognition sensor in a smart card chip.

[0029] Figure 20 This is a flowchart illustrating a method for operating a smart card according to an example embodiment.

[0030] Figure 21 An example of a smart card according to an example embodiment is shown.

[0031] Figure 22 This is a cross-sectional view showing an example of a smart card according to an exemplary embodiment.

[0032] Figure 23 This illustrates an example embodiment. Figure 22 A block diagram illustrating an example of the circuit layer of a smart card.

[0033] Figure 24 This is a circuit diagram illustrating an example of a protection device according to an exemplary embodiment.

[0034] Figure 25A This is a cross-sectional view showing a smart card including a portion of a sensor according to an example embodiment.

[0035] Figure 25B This is a cross-sectional view showing a smart card that includes a portion of a sensor according to an example embodiment and on which backside polishing may be performed during a backside attack.

[0036] Figure 26 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0037] Example embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals denote the same elements.

[0038] Figure 1 This is a schematic diagram illustrating a smart card system 10 according to some example embodiments. The smart card system 10 may include a card reader 20 and a smart card 50.

[0039] The card reader 20 may include a card reader chip 30 and an antenna 21. The card reader chip 30 may include a card slot 31. When the smart card 50 is in contact with the card slot 31, the card slot 31 provides voltage to the smart card 50 and exchanges data with the smart card 50. When the smart card 50 is inserted into the card slot 31, the card reader chip 30 provides operating voltage to the smart card 50, identifies the smart card 50, and exchanges secure data, such as payment data or confidential data, with the smart card 50.

[0040] The smart card 50 may include a connection interface 60 and a smart card chip 100. The connection interface 60 may include an antenna 61 (e.g., a coil antenna) and contact terminals 63.

[0041] The smart card 50 can communicate with the card reader 20 in a contactless manner via the antenna 61, receive operating voltage from the card reader 20, and exchange security data with the card reader 20. When the smart card 50 is inserted into the card slot 31, the smart card 50 can receive operating voltage through the contact terminal 63 and exchange security data with the card reader 20 through the contact terminal 63.

[0042] When the smart card 50 communicates with the card reader 20 in a contactless manner, the smart card 50 can receive the operating voltage and exchange security data with the card reader 20 in an electromagnetic form through antennas 21 and 61.

[0043] The smart card 50 may include a fingerprint sensor 270, and the fingerprint sensor 270 may be used to perform user authentication on security data, such as for making payments in a contactless manner.

[0044] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram illustrating an example of a smart card 50 in a smart card system. The smart card 50 may include a connection interface 60 and a smart card chip 100. The smart card chip 100 can be connected to the connection interface 60 via a first power terminal L1 and a second power terminal L2. The connection interface 60 may include a resonant circuit unit 70. The resonant circuit unit 70 may include a resonant circuit 71 with an antenna L (an example of an antenna 61), a first capacitor C1, and a filter 73 with a second capacitor C2 and a third capacitor C3 to provide induced voltages induced in response to electromagnetic waves EMW to the first and second power terminals L1 and L2. The connection interface 60 may further include contact terminals 63 that can directly contact the card reader 20. This direct contact can occur when the smart card 50 is inserted into a card slot 31, for example, the slot of the card reader 20. The direct contact can be direct electrical contact. When the smart card 50 is contactlessly coupled to the card reader 20 (e.g., when the smart card 50 is placed near the card reader but not inserted into the card slot 31 of the card reader 20), the resonant circuit unit 70 can provide the induced voltage induced in response to the electromagnetic wave EMW to the smart chip 100 as the input voltage VIN on the first power terminal L1 and the second power terminal L2. The contactless mode can be referred to as the electromagnetic coupling state between the smart card 50 and the card reader 20, or as the state of providing an input voltage from the card reader to the smart card without "direct contact," and vice versa. Note that the configuration of the resonant circuit unit 70 can be modified in other embodiments.

[0045] The smart card chip 100 can receive an input voltage VIN from the resonant circuit unit 70 via the first power terminal L1 and the second power terminal L2. The smart card chip 100 can receive the input voltage VIN provided by the resonant circuit unit 70 in contact mode, and can also receive the input voltage VIN provided by the contact terminal 63 in contactless mode.

[0046] The smart card chip 100 may include a rectifier 210, an internal voltage generator (IVGC) 300, a pattern detector 260, a processor 240, a memory 250, a demodulator 251, a modulator 253, a fingerprint sensor 270, a light-emitting diode 290, and a logic block (LCB) 295.

[0047] The rectifier 210 can generate a rectified voltage VREC by rectifying the input voltage VIN, where the rectified voltage VREC is a direct current (DC) voltage.

[0048] The internal voltage generator 300 can generate a first drive voltage (e.g., based on the mode signal MDS) by using the rectified voltage VREC. Figure 5 The VDD1 shown in the figure) and a second drive voltage having a level lower than the first drive voltage (e.g., Figure 5 VDD2 in the first drive voltage and VOUT2 can be generated based on the first drive voltage and the second drive voltage.

[0049] The mode signal MDS can indicate either a contact mode or a non-contact mode (at any given time). For example, when the mode signal MDS is at a first voltage level, it indicates a contact mode, while when the mode signal MDS is at a different second voltage level, it indicates a non-contact mode. The internal voltage generator 300 can, based on the mode signal MDS, adjust the second drive voltage based on the second drive voltage to generate a first output voltage VOUT1 in contact mode, adjust the second drive voltage based on the first drive voltage to generate the first output voltage VOUT1 in non-contact mode, and adjust the first drive voltage independently of the mode signal MDS to generate a second output voltage VOUT2 (e.g., adjusting the first drive voltage in the same manner to generate VOUT2 in any of the multiple possible states of the mode signal MDS).

[0050] The internal voltage generator 300 can provide a first output voltage VOUT1 to the processor 240 and logic block 295, and can provide a second output voltage VOUT2 to the fingerprint sensor 270 and light-emitting diode 290.

[0051] The mode detector 260 can receive an input voltage VIN as a "contact voltage" in contact mode and an input voltage VIN as a "non-contact voltage" in non-contact mode. It can compare the contact voltage and the non-contact voltage and output a mode signal MDS indicating one of the contact or non-contact modes based on the comparison result. In an example embodiment, the mode detector 260 can provide a power switch control signal PCS to the internal voltage generator 300 based on the contact or non-contact mode.

[0052] In one example embodiment, the pattern detector 260 may be included within the internal voltage generator 300. In another example embodiment, the pattern detector 260 may be located outside the internal voltage generator 300.

[0053] The processor 240 can control the overall operation of the smart card chip 100.

[0054] When performing a signal receiving operation, demodulator 251 generates received data RND by demodulating the signals provided from connection interface 60 through first and second power terminals L1 and L2, and provides the received data RND to processor 240. Processor 240 can store the received data RND in memory 250.

[0055] When performing a signal transmission operation, the processor 240 reads output data from the memory 250 and encodes the output data to provide transmission data TND to the modulator 253. The modulator 253 can modulate the transmission data TND to provide modulated signals to the first and second power supply terminals L1 and L2. For example, the modulator 253 can generate a modulated signal by performing load modulation relative to the transmission data TND.

[0056] The processor 240 can provide a switching control signal SCS to the internal voltage generator 300.

[0057] Memory 250 can store the user's original fingerprint registered through a preprocessing operation. Fingerprint sensor 270 can generate a fingerprint image signal based on the user's input fingerprint during a secure data exchange operation (e.g., a payment operation) in contactless mode, and can provide the fingerprint image signal to processor 240. Processor 240 can compare the fingerprint image signal with the user's original fingerprint and can determine whether the user's input fingerprint is genuine or forged based on the comparison result. When processor 240 determines that the user's input fingerprint matches the user's original fingerprint, processor 240 can indicate successful user authentication by controlling LED 295 to light up, while simultaneously performing user authentication on the secure data associated with the secure data exchange operation. When processor 240 determines that the user's input fingerprint does not match the user's original fingerprint, processor 240 can indicate the mismatch via LED 295.

[0058] Figure 3 An example embodiment is shown. Figure 2 An example of a rectifier 210 in a smart card chip. Here, rectifier 210 may include a first diode 211 and a second diode 212.

[0059] The first diode 211 may have an anode connected to the first power supply terminal L1 and a cathode connected to the output node 213. The second diode 212 may have an anode connected to the second power supply terminal L2 and a cathode connected to the output node 213. In contact mode, the first and second diodes 211 and 212 can be connected to each other via... Figure 2 The contact voltage VDDC provided by contact terminal 63 is rectified to provide a rectified voltage VREC to the internal voltage generator 300. In contactless mode, the first diode 211 and the second diode 212 can jointly rectify the voltage. Figure 2 The resonant unit 70 provides a contactless voltage VDDU to supply a rectified voltage VREC to the internal voltage generator 300.

[0060] Figure 4 An example embodiment is shown. Figure 2 An example of a pattern detector 260 in a smart card chip. The pattern detector 260 may include a comparator 261 and a switch control signal generator (SCSG) 263.

[0061] Comparator 261 compares the contact voltage VDDC and the contactless voltage VDDU by comparing the voltage applied to its positive input (connected to terminal L1) with a reference voltage VREFC applied to its negative input. Based on the comparison result, comparator 261 outputs a mode signal MDS indicating one of the contact or contactless modes. When the smart card 100 is connected in a contactless manner, the voltage level of the contactless voltage VDDU is greater than the reference voltage VREFC, and comparator 261 can output a mode signal MDS with a first logic level (e.g., logic high). When the smart card 100 is connected in a contact manner, the voltage level of the contact voltage VDDC is less than the reference voltage VREFC, and comparator 261 can output a mode signal MDS with a second logic level (e.g., logic low).

[0062] The switch control signal generator 263 can determine the logic level of the power switch control signal PCS, including the first power switch control signal PCS1 and the second power switch control signal PCS2, based on the mode signal MDS, and can provide the first power switch control signal PCS1 and the second power switch control signal PCS2 to the internal voltage generator 300. The switch control signal generator 263 can generate the first power switch control signal PCS1 and the second power switch control signal PCS2 based on the mode signal MDS, such that the first power switch control signal PCS1 and the second power switch control signal PCS2 have complementary logic levels.

[0063] Figure 5 This illustrates an example embodiment. Figure 2A block diagram of an example of an internal voltage generator in a smart card chip.

[0064] like Figure 5 As shown, the internal voltage generator 300 may include a switched capacitor circuit 305, a low dropout (LDO) regulator 330, and a voltage regulator 380. The switched capacitor circuit 305 may include a first switched capacitor (SC) converter 310 and a second switched capacitor (SC) converter 320.

[0065] The switched capacitor circuit 305 can receive a rectified voltage VREC and can generate a first drive voltage VDD1 and a second drive voltage VDD2 by converting the rectified voltage VREC. A first switched capacitor converter 310 can convert the rectified voltage VREC into the first drive voltage VDD1 based on a switch control signal SCS, and a second switched capacitor converter 320 can convert the first drive voltage VDD1 into the second drive voltage VDD2 based on the switch control signal SCS. The switched capacitor circuit 305 can provide the first drive voltage VDD1 and the second drive voltage VDD2 to the LDO regulator 330, and can also provide the first drive voltage VDD1 to the voltage regulator 380.

[0066] The rectified voltage VREC can have a first voltage level, the first drive voltage VDD1 can have a second voltage level lower than the first voltage level, and the second drive voltage VDD2 can have a third voltage level lower than the second voltage level. In an embodiment, the second voltage level can correspond to half of the first voltage level, and the third voltage level can correspond to half of the second voltage level.

[0067] The LDO regulator 330 may include an error amplifier. Based on the mode signal MDS and the power switch control signal PCS, the LDO regulator 330 can drive the error amplifier with a second drive voltage VDD2 to generate an error voltage, and can adjust the second drive voltage VDD2 based on the error voltage to generate a first output voltage VOUT1 in contact mode. Based on the mode signal MDS and the power switch control signal PCS, the LDO regulator 330 can drive the error amplifier with a first drive voltage VDD1 to generate an error voltage, and can adjust the second drive voltage VDD2 based on the error voltage to generate a first output voltage VOUT1 in non-contact mode.

[0068] The voltage regulator 380 can independently adjust the first drive voltage VDD1 to generate the second output voltage VOUT2, independent of the mode signal MDS.

[0069] In an embodiment, the internal voltage generator 300 may further include a mode detector 260. The mode detector 260 may generate a mode based on the input voltage VIN, as shown in the reference... Figure 4The aforementioned mode signal MDS and power switch control signal PCS.

[0070] Figure 6 This illustrates an example embodiment. Figure 5 A circuit diagram of an example of the first switched capacitor in the internal voltage generator.

[0071] like Figure 6 As shown, the first switched capacitor converter 310a may include first, second, third and fourth switches 311, 312, 313 and 314 and capacitor 315.

[0072] A first switch 311 is connected between a first node N11 and a second node N12 that receive the rectified voltage VREC, and is switched in response to a first switch control signal SCS1. A capacitor 315 is coupled between the second node N12 and a third node N13. A second switch 312 is connected between the second node N12 and a fourth node N14 that provides the first drive voltage VDD1, and is switched in response to a second switch control signal SCS2.

[0073] The third switch 313 is connected between the third node N13 and the ground voltage VSS, and is switched in response to the second switch control signal SCS2. The fourth switch 314 is connected between the third node N13 and the fourth node N14, and is switched in response to the first switch control signal SCS1.

[0074] The first switch control signal SCS1 and the second switch control signal SCS2 can have the same logic level. The first switch 311 and the fourth switch 314 can be turned on in response to the first switch control signal SCS1 with a low level, and can be turned off in response to the first switch control signal SCS1 with a high level. The second switch 312 and the third switch 313 can be turned off in response to the second switch control signal SCS2 with a low level, and can be turned on in response to the second switch control signal SCS2 with a high level.

[0075] Figure 7 This illustrates an example embodiment. Figure 5 A circuit diagram of another example of the first switched capacitor in the internal voltage generator.

[0076] like Figure 7 As shown, the first switched capacitor converter 310b may include p-channel metal-oxide-semiconductor (PMOS) transistors 316 and 319, n-channel metal-oxide-semiconductor (NMOS) transistors 317 and 318, and capacitor 315.

[0077] PMOS transistor 316 is connected between the first node N11 and the second node N12, which receive the rectified voltage VREC, and is turned on / off in response to the first switch control signal SCS1. NMOS transistor 317 is connected between the second node N12 and the fourth node N14, which provides the first drive voltage VDD1, and is turned on / off in response to the second switch control signal SCS2. Capacitor 315 is coupled between the second node N12 and the third node N13.

[0078] NMOS transistor 318 is connected between the third node N13 and the ground voltage VSS, and is turned on / off in response to the second switch control signal SCS2. PMOS transistor 319 is connected between the third node N13 and the fourth node N14, and is turned on / off in response to the first switch control signal SCS1.

[0079] Figure 6 and 7 They are shown respectively Figure 5 An example of the first switched capacitor converter 310 is given, and the configuration of the second switched capacitor converter 320 may be the same as that of the first switched capacitor converter 310.

[0080] Figure 8 Figure 6 shows an example operation of the first switched capacitor converter.

[0081] Figure 7 The operation of the first switched capacitor converter 310b can be combined with Figure 6 The operation is the same as that of the first switched capacitor converter 310a in the series.

[0082] like Figure 8 As shown, during the first stage, when the first switch 311 and the fourth switch 314 are turned on and the second switch 312 and the third switch 313 are turned off, the voltage VCAP is stored in the capacitor 315 based on the rectified voltage VREC, and the first drive voltage VDD1 is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

[0083] Figure 9 It shows Figure 6 Example operation of the first switched capacitor converter.

[0084] Figure 7 The operation of the first switched capacitor converter 310b can be combined with Figure 6 The operation is the same as that of the first switched capacitor converter 310a in the series.

[0085] like Figure 9As shown, when the first switch 311 and the fourth switch 314 are open and the second switch 312 and the third switch 313 are open during the second phase, the voltage VCAP stored in the capacitor 315 during the first phase decreases linearly, and a first drive voltage VDD1 is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

[0086] Figure 10 This illustrates an example embodiment. Figure 5 A circuit diagram of an example LDO regulator in an internal voltage generator.

[0087] refer to Figure 10 The LDO regulator 330 may include a voltage selector 331, a polarity selector 340, an error amplifier 350, a first power switch 361, a first power transistor (PT1) 365, a second power switch 363, a second power transistor (PT2) 367, and a feedback circuit 370.

[0088] The voltage selector 360 can provide one of the first drive voltage VDD1 and the second drive voltage VDD2 to the power supply terminal 360 of the error amplifier 350 as the error amplifier power supply voltage VEA in response to the mode signal MDS.

[0089] The polarity selector 340 can provide a reference voltage VREF and a feedback voltage VFB1 to the negative and positive input terminals of the error amplifier 350, or to the positive and negative input terminals of the error amplifier 350, respectively, based on the mode signal MDS.

[0090] An error amplifier 350, connected between power supply terminal 360 and ground voltage VSS, amplifies the difference between feedback voltage VFB1 and reference voltage VREF to output a first error voltage EV1 to first node N21. First node N21 may correspond to the output of error amplifier 350. Power supply terminal 360 may receive one of a first drive voltage VDD1 and a second drive voltage VDD2. The first error voltage EV1 may also be referred to as the error voltage. The feedback voltage VFB1 may also be referred to as the first feedback voltage.

[0091] A first power switch 361 can be connected between a first node N21 and a first power transistor 365, and can be switched in response to a first power switch control signal PCS1. The first power transistor 365 can be connected between a second drive voltage VDD2 and an output node NO that provides a first output voltage VOUT1.

[0092] The second power switch 363 can be connected between the first node N21 and the second power transistor 367, and can be switched in response to the second power switch control signal PCS2. The second power transistor 367 can be connected in parallel with the first power transistor 365 between the second drive voltage VDD2 and the output node NO. The second power transistor 367 can be of a different type than the first power transistor 365.

[0093] Feedback circuit 370 is connected between output node NO and ground voltage VSS, and can divide the first output voltage VOUT1 to provide feedback voltage VFB1. Feedback circuit 370 includes a first feedback resistor RF1 and a second feedback resistor RF2 connected in series between output node NO and ground voltage VSS. The first feedback resistor RF1 and the second feedback resistor RF2 are connected to each other at feedback node FN1, and feedback circuit 370 provides the voltage at feedback node FN1 as feedback voltage VFB1.

[0094] Figure 11 This illustrates an example embodiment. Figure 10 The circuit diagram of the LDO regulator 330 is shown below. Here, the voltage selector 331 may include a multiplexer 332. In contactless mode, the multiplexer 332 can select the first drive voltage VDD1 based on the mode signal MDS from the first drive voltage VDD1 and the second drive voltage VDD2 to provide the error amplifier power supply voltage VEA. In contact mode, the multiplexer 332 can select the second drive voltage VDD2 based on the mode signal MDS from the first drive voltage VDD1 and the second drive voltage VDD2 to provide the error amplifier power supply voltage VEA.

[0095] The polarity selector 340 can be implemented using a crossbar switch, and in contact mode, it can provide a reference voltage VREF and a feedback voltage VFB1 to the negative and positive input terminals of the error amplifier 350 respectively based on the mode signal MDS, and in non-contact mode, it can provide a reference voltage VREF and a feedback voltage VFB1 to the positive and negative input terminals of the error amplifier 350 respectively based on the mode signal MDS.

[0096] The first power transistor 365 can be a PMOS transistor 366, with its source coupled to the second driving voltage VDD2, its gate coupled to the first power switch 361, and its drain coupled to the output node NO. The second power transistor 367 can be an NMOS transistor 368, with its drain coupled to the second driving voltage VDD2, its gate coupled to the second power switch 363, and its source coupled to the output node NO.

[0097] In contact mode, the first power switch 361 is turned on in response to the first power switch control signal PCS1 to apply the first error voltage EV1 to the gate of the first power transistor 365, and the second power switch 363 is turned off in response to the second power switch control signal PCS2 to disconnect the output of the error amplifier 350 from the gate of the second power transistor 367.

[0098] In contactless mode, the first power switch 361 is turned off in response to the first power switch control signal PCS1 to disconnect the output of the error amplifier 350 from the gate of the first power transistor 365, and the second power switch 363 is turned on in response to the second power switch control signal PCS2 to apply the first error voltage EV1 to the gate of the second power transistor 367.

[0099] Figure 12 The example embodiment shows the contact mode. Figure 11 Example operation of an LDO regulator.

[0100] refer to Figure 12 In contact mode, the mode signal MDS has a second logic level (low level). Multiplexer 332 selects the second drive voltage VDD2 from the first drive voltage VDD1 and the second drive voltage VDD2 based on the mode signal MDS, to provide the second drive voltage VDD2 to the power supply terminal 360 of error amplifier 350. Polarity selector 340 provides the reference voltage VREF and feedback voltage VFB1 to the positive and negative input terminals of error amplifier 350, respectively, based on the mode signal MDS. The first power switch 361 is turned on, and the second power switch 363 is turned off.

[0101] Error amplifier 350, driven by a second drive voltage VDD2, amplifies the difference between the reference voltage VREF and the first feedback voltage VFB1 to apply a first error voltage EV1 to the gate of the first power transistor 365. The first power transistor 365 adjusts the second drive voltage VDD2 based on the first error voltage EV1 to... Figure 2 The processor 240 and logic block 295 provide the first output voltage VOUT1.

[0102] When the voltage level of the first output voltage VOUT1 decreases in contact mode, the voltage level of the first feedback voltage VFB1 decreases. The voltage level of the first error voltage EV1 decreases in response to the decrease in the voltage level of the first feedback voltage VFB1. In response to the decrease in the voltage level of the first error voltage EV1, the current flowing from the first power transistor 365 to the output node NO increases, therefore, the voltage level of the first output voltage VOUT1 increases.

[0103] When the voltage level of the first output voltage VOUT1 increases in contact mode, the voltage level of the first feedback voltage VFB1 also increases. The voltage level of the first error voltage EV1 increases in response to the increase in the voltage level of the first feedback voltage VFB1. The current flowing from the first power transistor 365 to the output node NO decreases in response to the increase in the voltage level of the first error voltage EV1; therefore, the voltage level of the first output voltage VOUT1 decreases.

[0104] Therefore, in contact mode, the first output voltage VOUT1 follows the reference voltage VREF through the regulation operation of the first power transistor 365 implemented by the PMOS transistor 366.

[0105] Figure 13 The example embodiment shows a contactless mode. Figure 11 Example operation of an LDO regulator.

[0106] refer to Figure 13 In contact mode, the mode signal MDS has a first logic level (high level). Multiplexer 332 selects the first drive voltage VDD1 from the first drive voltage VDD1 and the second drive voltage VDD2 based on the mode signal MDS, to provide the first drive voltage VDD1 to the power supply terminal 360 of error amplifier 350. Polarity selector 340 provides the reference voltage VREF and feedback voltage VFB1 to the negative and positive input terminals of error amplifier 350, respectively, based on the mode signal MDS. The first power switch 361 is open, and the second power switch 363 is closed.

[0107] Error amplifier 350, driven by a first drive voltage VDD1, amplifies the difference between the reference voltage VREF and the first feedback voltage VFB1 to apply a first error voltage EV1 to the gate of the second power transistor 367. The second power transistor 367 adjusts the second drive voltage VDD2 based on the first error voltage EV1 to... Figure 2 The processor 240 and logic block 295 provide the first output voltage VOUT1.

[0108] When the voltage level of the first output voltage VOUT1 decreases in contactless mode, the voltage level of the first feedback voltage VFB1 decreases. The voltage level of the first error voltage EV1 increases in response to the decrease in the voltage level of the first feedback voltage VFB1. In response to the decrease in the voltage level of the first error voltage EV1, the current flowing from the second power transistor 367 to the output node NO increases, therefore, the voltage level of the first output voltage VOUT1 increases.

[0109] When the voltage level of the first output voltage VOUT1 increases in contactless mode, the voltage level of the first feedback voltage VFB1 also increases. The voltage level of the first error voltage EV1 decreases in response to the increase in the voltage level of the first feedback voltage VFB1. The current flowing from the second power transistor 367 to the output node NO decreases in response to the decrease in the voltage level of the first error voltage EV1, therefore, the voltage level of the first output voltage VOUT1 decreases.

[0110] Therefore, in contactless mode, the first output voltage VOUT1 follows the reference voltage VREF through the regulation operation of the second power transistor 367 implemented by the NMOS transistor 368.

[0111] In other words, in contact mode, error amplifier 350 is driven by the second drive voltage VDD2 to apply the first error voltage EV1 to the gate of PMOS transistor 366, and in contactless mode, error amplifier 350 is driven by the first drive voltage VDD1 to apply the first error voltage EV1 to the gate of NMOS transistor 368. Therefore, the gate-drain voltage of PMOS transistor 366 is different from the gate-source voltage of NMOS transistor 368.

[0112] In a conventional internal voltage generator, the error amplifier is driven by a second drive voltage VDD2, and a PMOS power transistor regulates the second drive voltage VDD2 to provide a first output voltage VOUT1 to logic block 295. Therefore, because the difference between the second drive voltage VDD2 and the first output voltage VOUT1 is very small, and the drain-source voltage of the PMOS transistor is too small, the first output voltage VOUT1 may not have a stable level.

[0113] According to the example embodiment, the LDO regulator 330 drives the error amplifier 350 with a first drive voltage VDD1 greater than the second drive voltage VDD2, and the second power transistor 367, implemented with an NMOS transistor 368, adjusts the second drive voltage VDD2 based on the first error voltage EV1 to provide a first output voltage VOUT1. Therefore, the gate-source voltage of the NMOS transistor 368 is sufficient, so the first output voltage VOUT1 can have a stable level.

[0114] Figure 14 This illustrates an example embodiment. Figure 5 A circuit diagram of an example voltage regulator in an internal voltage generator.

[0115] like Figure 14 As shown, the voltage regulator 380 may include an error amplifier 381, a power transistor 382, ​​and a feedback circuit 383.

[0116] Error amplifier 381 may have a negative (-) input terminal for receiving reference voltage VREF and a positive (+) input terminal for receiving second feedback voltage VFB2. Error amplifier 381 may amplify the difference between the second feedback voltage VFB2 and the reference voltage VREF to output a second error voltage EV2 to the gate of power transistor 382.

[0117] The power transistor 382 may be a PMOS transistor having a source coupled to a first drive voltage VDD1, a gate receiving a second error voltage EV2, and a drain coupled to an output node NO2, and may adjust the first drive voltage VDD1 based on the second error voltage EV2 to provide a second output voltage VOUT2 at the output node NO2.

[0118] Feedback circuit 383 is connected between output node NO2 and ground voltage VSS, and can divide the second output voltage VOUT2 to provide a second feedback voltage VFB2. Feedback circuit 383 includes feedback resistors RF3 and RF4 connected in series between output node NO2 and ground voltage VSS. Feedback resistors RF3 and RF4 are connected to each other at feedback node FN2, and feedback circuit 383 provides the voltage at feedback node FN2 as the second feedback voltage VFB2.

[0119] In voltage regulator 380, power transistor 382, ​​implemented using a PMOS transistor, regulates the first drive voltage VDD1 to provide a second output voltage VOUT2. Therefore, the voltage level of the second output voltage VOUT2 is equal to or greater than the first output voltage VOUT1. Voltage regulator 380 can... Figure 2 The fingerprint sensor 270 and LED 290 in the smart card 50 provide a second output voltage VOUT2. Since the fingerprint sensor 270 and LED 290 are used to perform fingerprint authentication of payment data in contactless mode, the power consumption in the smart card 50 increases. The fingerprint sensor 270 and LED 290 operate based on the second output voltage VOUT2, which has a relatively high voltage level, thus ensuring stable operation.

[0120] Figure 15 This illustrates an example embodiment. Figure 10 A circuit diagram of an example error amplifier in an LDO regulator. In this example, the error amplifier 350 may include a folded cascode amplifier 350a and a source follower 350b.

[0121] The folded common-source common-gate amplifier 350a may include PMOS transistors MP1 to MP7, NMOS transistors MN1 to MN4, resistor R11, and capacitor C11.

[0122] PMOS transistor MP1 is connected between the power supply voltage VEA and node N23, and has a gate that receives a first bias voltage VB1. Therefore, PMOS transistor MP1 can operate as a current source. PMOS transistor MP3 is connected between nodes N23 and N28, and has a gate coupled to the negative input terminal 351. PMOS transistor MP2 is connected between nodes N23 and N29, and has a gate coupled to the positive input terminal 352.

[0123] PMOS transistor MP4 is connected between the power supply voltage EVA and node N25, and has a gate that receives a first bias voltage VB1. PMOS transistor MP5 is connected between the power supply voltage EVA and node N26, and has a gate that receives a first bias voltage VB1. Resistor R11 and capacitor C11 are connected in series between nodes N25 and N26. PMOS transistor MP6 is connected between nodes N25 and N24, and has a gate that receives a second bias voltage VB2. PMOS transistor MP7 is connected between nodes N26 and N27, and has a gate that receives a second bias voltage VB2.

[0124] NMOS transistor MN1 is connected between nodes N24 and N28 and has a gate that receives a third bias voltage VB3. NMOS transistor MN2 is connected between nodes N27 and N29 and has a gate that receives a third bias voltage VB3. NMOS transistor MN3 is connected between node N28 and ground voltage VSS and has a gate that receives a fourth bias voltage VB4. NMOS transistor MN4 is connected between node N29 and ground voltage VSS and has a gate that receives a fourth bias voltage VB4.

[0125] The source follower 350b may include PMOS transistors 353 and 354, NMOS transistors 355 and 356, and resistor R22.

[0126] PMOS transistor 353 is connected between the supply voltage VEA and node N21 and has a gate that receives a first bias voltage VB1. PMOS transistor 354 is connected between node N21 and node N22 and has a gate coupled to node N27. Resistor R22 is connected between node N21 and NMOS transistor 356. NMOS transistor 355 is connected between node N22 and ground voltage VSS and has a gate that receives a fourth bias voltage VB4. NMOS transistor 356 is connected between resistor R22 and ground voltage VSS and has a gate coupled to node N22.

[0127] refer to Figure 15Assume that the current drive capabilities of PMOS transistors MP1, MP4, MP5 and 353 are the same, the current drive capabilities of PMOS transistors MP2 and MP3 are the same, the current drive capabilities of PMOS transistors MP6, MP7 and 354 are the same, the current drive capabilities of NMOS transistors MN1, MN2 and 356 are the same, and the current drive capabilities of NMOS transistors MN3, MN4 and 355 are the same.

[0128] A first bias voltage VB1 is applied to each gate of PMOS transistors MP1 and 353, thus currents of equal magnitude flow into nodes N23 and N21. The difference between the reference voltage applied to the negative input terminal 351 and the first feedback voltage VFB1 applied to the positive input terminal 352 produces a voltage difference at nodes N27 and N24, and provides a first error voltage EV1 at node N21 corresponding to the voltage difference at nodes N27 and N24.

[0129] Generally, smart cards, or integrated circuit (IC) cards, are shaped to allow thin semiconductor devices to be attached to a plastic card the same size as a credit card. Smart cards can be broadly categorized into contact IC cards, contactless IC cards (CICC), and remotely coupled communication cards (RCCC). In connection with CICC, ISO (International Organization for Standardization) and IEC (International Electrotechnical Commission) have formed a dedicated global standardization system.

[0130] In particular, the international standard ISO / IEC 14443 specifies the physical characteristics, radio frequency power and signal interface, initialization and anti-collision, and transmission protocol of contactless cards. According to ISO / IEC 14443, contactless integrated circuit cards contain integrated circuits that perform data processing and / or storage functions. The possibilities of contactless card technology allow for signal exchange via inductive coupling with a nearby coupling device (i.e., a card reader), and enable power supply to the card without the use of current-carrying elements (i.e., without an ohmic path from the external interface device to the integrated circuit contained within the card). The card reader generates an excitation radio frequency (RF) field that is coupled to the card to transmit power and is modulated for communication. The carrier frequency fc of the RF operating field is 13.56 MHz + 7 kHz.

[0131] Figure 16 and 17 This is a schematic diagram illustrating an example of communication signals used in a Type A interface of the ISO / IEC 14442 standard, and Figure 18 This is a schematic diagram illustrating an example of a frame and pause in a Type A interface of the ISO / IEC 14442 standard.

[0132] Figure 16The signal transmitted from the card reader to the contactless IC card is shown, and Figure 17 The signal transmitted from the contactless IC card to the card reader is shown.

[0133] The ISO / IEC 14443 protocol describes two communication signal interfaces, Type A and Type B. Under Communication Signal Interface Type A, communication from the card reader to the contactless smart card utilizes the ASK 100% modulation principle and a modified Miller code principle in the radio frequency operating field. The transmission bit rate from the card reader to the contactless smart card is fc / 128, i.e., 106 kbps (kb / s). The transmission from the contactless smart card to the card reader is encoded using Manchester code principles and then modulated using the On-Off Keying (OOK) principle. Currently, cards managed by Type A communication signal interfaces in subways and buses use ASK modulated signals received from the card reader to generate timing at constant time intervals, and receive and transmit data one bit at a time.

[0134] When data is transmitted from the smart card to the card reader, the card reader supplies a stable power supply to the smart card.

[0135] Figure 18 The image shows a Type A data frame from the ISO / IEC 14443 standard. Figure 18 A short frame including start bit S, data bits b1-b7 and end bit E is shown.

[0136] Figure 19 An example embodiment is shown. Figure 2 An example of a fingerprint recognition sensor in a smart card chip.

[0137] like Figure 19 As shown, the fingerprint recognition sensor 270 may include a lens 271 and an image sensor 272, and the image sensor 272 may include a pixel array 273.

[0138] Lens 271 can focus reflected light from the user's finger 80 onto the pixel array 273 of image sensor 272. Image sensor 272 can generate a fingerprint image signal based on the reflected light and can direct it to... Figure 2 The processor 240 in the middle provides the fingerprint image signal.

[0139] Processor 240 can compare the fingerprint image signal with the user's original fingerprint and determine whether the user's input fingerprint is forged based on the comparison result. When processor 240 determines that the user's input fingerprint matches the user's original fingerprint, processor 240 can indicate that the user authentication is successful by controlling LED 295 to light up, and at the same time perform user authentication on the payment data associated with the payment operation.

[0140] Figure 20This is a flowchart illustrating a method for operating a smart card according to an example embodiment.

[0141] like Figures 1 to 20 As shown, the switched capacitor circuit 305 in the internal voltage generator 300 of the smart card 50 generates a first driving voltage VDD1 and a second driving voltage VDD2 based on the input voltage VDD1, wherein VDD2 is less than VDD1 (operation S510). The switched capacitor circuit 305 can receive a rectified voltage VREC obtained by rectifying the input voltage, and can generate the first driving voltage VDD1 and the second driving voltage VDD2 by converting the rectified voltage VREC.

[0142] The mode detector 260 in the smart card 50 determines whether the smart card 50 receives the input voltage VIN in contact mode (operation S520) and generates a mode signal MDS indicating one of contact mode and contactless mode.

[0143] When the smart card 50 receives the input voltage VIN in contact mode (Yes in S520), the LDO regulator 330 drives the error amplifier 350 with the second drive voltage VDD2 to generate the first error voltage EV1 (operation S530). The first power transistor 365, implemented with the PMOS transistor 366, adjusts the second drive voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 (operation S540).

[0144] When the smart card 50 receives the input voltage VIN in contactless mode (not in S520), the LDO regulator 330 drives the error amplifier 350 with the first drive voltage VDD1 to generate the first error voltage EV1 (operation S550). The second power transistor 367, implemented with NMOS transistor 368, adjusts the second drive voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 (operation S560).

[0145] Therefore, in the method of operating a smart card according to the example embodiment, the LDO regulator 330 drives the error amplifier 350 with a second drive voltage VDD2 and a first drive voltage VDD1 having different voltage levels in contact mode and contactless mode, respectively. A first power transistor 365, implemented with a PMOS transistor 366, adjusts the second drive voltage VDD2 based on the first error voltage EV1 to provide a first output voltage VOUT1 in contact mode, and a second power transistor 367, implemented with an NMOS transistor 368, adjusts the second drive voltage VDD2 based on the first error voltage EV1 to provide the first output voltage VOUT1 in contactless mode. Therefore, the LDO regulator 330 can stably provide the first output voltage VOUT1 to the logic circuit block 290 in both contact mode and contactless mode.

[0146] Figure 21 An example of a smart card according to an exemplary embodiment is shown. In this example, smart card 50 may include an integrated circuit 85, an antenna 61, a fingerprint sensor 270, and a light-emitting diode 290 formed in a substrate 101.

[0147] Antenna 61 can be coupled to integrated circuit 85. Integrated circuit 85 may include... Figure 2 The components of the smart card chip 100, besides the fingerprint recognition sensor 270 and the light-emitting diode 290, also include... Figure 1 The contact terminal 63 can be included in the integrated circuit 85.

[0148] Figure 22 This is a cross-sectional view illustrating an example structure of a smart card according to an exemplary embodiment. The smart card 50 may include a substrate 101, a plurality of trench capacitors TC disposed in the substrate 101, a circuit layer 120 disposed on the front side FS of the substrate 101, and a protective layer 130 disposed on top of the circuit layer 120. In the exemplary embodiment, the protective layer 130 may be provided as an active shield. The protective layer 130 may include a plurality of wires disposed on the circuit layer 120 and insulating layers on the plurality of wires.

[0149] Figure 23 This illustrates an example embodiment. Figure 22 A block diagram of an example of the circuit layer of a smart card. Circuit layer 120 may include a sensor 121, a frequency detector (FD) 122, a processor 123, a cryptographic module (ENC_M) 124, a random number generator (RNG) 125, a communication module (COMM) 126, a memory (MEM) 127, a fingerprint sensor (FSR) 128, and an internal voltage generator (IVGC) 129.

[0150] The processor 123, memory 127, fingerprint sensor 128, and internal voltage generator 129 can respectively correspond to Figure 2 The processor 240, memory 250, fingerprint sensor 270, and internal voltage generator 300 are included, and the password module 124, random number generator 125, and communication module 126 can correspond to... Figure 2 The logic circuit block 295 in the middle.

[0151] like Figure 22 and 23 As shown, sensor 121 may include multiple trench capacitors TC. When the lower region of a trench capacitor TC is removed, the capacitance of the affected trench capacitor TC may change during back-side polishing. (Back-side polishing is a malicious attack in which a target transistor is accessed by polishing the back of the chip).

[0152] Frequency detector 122 can be connected to the output of sensor 121 and detect the frequency of the output signal of sensor 121. When the frequency of the detected output signal is outside a predetermined range, frequency detector 122 can activate an alarm signal by, for example, generating a logic "high" control signal and providing the generated control signal to processor 123.

[0153] For example, if a logic "high" control signal is received from the frequency detector 122, the processor 123 can invalidate the data stored in the memory 127 of the smart card 50, or initialize the functionality of the cryptographic module 124 or the random number generator 125 in the smart card 50. In this way, the smart card 50 can be reset, and security information can be protected from backdoor attacks.

[0154] Figure 24 This is a circuit diagram illustrating an example of a protection device 135 according to an exemplary embodiment. The protection device 135 can be used to protect a smart card 50 from back-end attacks.

[0155] The protection device 135 can protect the smart card 50 from back-end attacks to prevent the leakage, interception or theft of important information, such as secret data or keys stored in a memory (not shown) arranged on the front of the smart card 50.

[0156] like Figure 24 As shown, the protection device 135 may include a sensor 121 and a frequency detector 122. The sensor 121 may include first to third capacitors C1 to C3. According to an embodiment, at least one capacitor selected from the first to third capacitors C1 to C3 may be a trench capacitor formed in the substrate. Therefore, when back-side polishing is performed during back-side attack, the lower region of the trench capacitor is removed, and thus, the capacitance of the trench capacitor is changed.

[0157] Sensor 121 may further include a detection circuit DC that detects capacitance changes in the first to third capacitors C1 to C3. According to an embodiment, the detection circuit DC may be a ring oscillator comprising first, second, and third PMOS transistors M1, M3, and M5, and first, second, and third NMOS transistors M2, M4, and M6. The first PMOS transistor M1 and the first NMOS transistor M2 may form a first inverter INV1, the second PMOS transistor M3 and the second NMOS transistor M4 may form a second inverter INV2, and the third PMOS transistor M5 and the third NMOS transistor M6 may form a third inverter INV3.

[0158] Therefore, sensor 121 can be a ring oscillator, which includes first to third inverters INV1 to INV3 connected in series and first to third capacitors C1 to C3, i.e., a multi-stage ring oscillator. Feedback related to the voltage at the output terminal OUT of the ring oscillator is transmitted to the input terminal IN.

[0159] A first capacitor C1 can be connected to the output terminal of the first inverter INV1, a second capacitor C2 can be connected to the output terminal of the second inverter INV2, and a third capacitor C3 can be connected to the output terminal of the third inverter INV3. Although not shown, a first resistor can be connected between the first inverter INV1 and the first capacitor C1, a second resistor can be connected between the second inverter INV2 and the second capacitor C2, and a third resistor can be connected between the third inverter INV3 and the third capacitor C3.

[0160] Frequency detector 122 can be connected to the output terminal OUT of sensor 121 to detect the frequency of the output signal of sensor 121. During operation, the lower region of at least one of the first to third capacitors C1 to C3 may be removed due to back-side polishing performed during back-side attack, and therefore the capacitance of at least one of the first to third capacitors C1 to C3 may be altered.

[0161] For example, when the capacitance decreases, the frequency of the output signal from sensor 121 may increase. In an embodiment, frequency detector 122 can detect the change in capacitance by detecting the frequency or frequency change of the output signal OUT from the same terminal.

[0162] For example, when the frequency of the output signal OUT detected by the frequency detector 122 is outside a predetermined range, a control signal can be provided. Figure 23 The processor 123 is configured in the processor. In an embodiment, the frequency detector 122 can generate a logic "low" control signal when the detected frequency is within a predetermined range, and a logic "high" control signal when the detected frequency is outside the predetermined range. The frequency detector 122 can provide the generated control signal to the processor 123. For example, when the predetermined range is set to about 14 MHz to about 26 MHz, and the detected frequency is greater than 26 MHz, the frequency detector 122 can generate a logic "high" control signal and provide the generated control signal to the processor 123.

[0163] When processor 123 receives a logic "high" control signal from frequency detector 122, processor 123 can invalidate data stored in memory 127 or initialize the functionality of password module 124. In an embodiment, in response to activation of the frequency detector signal, smart card 50 can be reset and security information can be protected from backdoor attacks; activation of the frequency detector signal can also reflect changes in capacitance in the ring oscillator.

[0164] Figure 25A This is a cross-sectional view illustrating the structure of a smart card including a portion of a sensor according to an example embodiment. The smart card 50 includes a substrate 101, a trench capacitor TC in the substrate 101, and an inverter INV at the front side FS of the substrate 101. According to this embodiment, the trench capacitor TC may be from... Figure 24 One of the first to third capacitors C1 to C3 shown is selected, and the inverter INV can be from... Figure 24 Choose one of the first to third inverters INV1 to INV3 shown.

[0165] Substrate 101 may be a semiconductor substrate having a first height H1 between the front side FS and the back side BS, and may include, for example, silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium, and gallium arsenide. For example, substrate 101 may be a p-type semiconductor substrate. An isolation layer 102 defining a plurality of active regions is disposed in substrate 101. The isolation layer 102 may be provided by performing, for example, a shallow trench isolation (STI) process. An n-type well 103 may be disposed in a portion of substrate 101.

[0166] A trench capacitor TC is disposed in a substrate 101 and has a second height H2 extending from the front side FS of the substrate 101. The second height H2 is smaller than the first height H1. According to an embodiment, the second height H2 may be modified due to back-side polishing, which may be performed, for example, against back-side attacks.

[0167] A first gate G1 and source 104a and drain 104b disposed on both sides of the first gate G1 can form a PMOS transistor PM. A second gate G2 and drain 104c and source 104d disposed on both sides of the second gate G2 can form an NMOS transistor NM. Each of the first and second gates G1 and G2 may include a gate insulating layer 105 and a gate electrode 106.

[0168] The first source contact 107a can be located on the source 104a of the PMOS transistor PM, and the power supply voltage VDD can be applied to the first source contact 107a. The first drain contact 107b can be located on the drain 104b of the PMOS transistor PM, and the second drain contact 107c can be located on the drain 104b of the NMOS transistor NM, and the first and second drain contacts 107a and 107b can be electrically connected to each other via the first wire ML1. The second source contact 107d can be located on the source 104d of the NMOS transistor NM. The second source contact 107d can be grounded.

[0169] The first gate contact 108a can be disposed on the first gate G1, and the second gate contact 108b can be disposed on the second gate G2, and the first and second gate contacts 108a and 108b can be electrically connected to each other via the second wire ML2. However, the above structure of the inverter INV is only an example and can be modified in various ways in other embodiments.

[0170] Figure 25B This is a cross-sectional view of a smart card including a portion of a sensor according to an example embodiment, and which may undergo "back-polishing" during a back-side attack. When back-polishing is performed during a back-side attack on the smart card 50', a predetermined depth may be removed from the back side of the substrate 101. Therefore, the lower end of the trench capacitor TC may be cut. In this case, the second height H2' of the trench capacitor TC may be altered. Consequently, as the dielectric material of the trench capacitor TC decreases, the capacitance of the trench capacitor TC may decrease, and the frequency of the sensor's output signal may increase.

[0171] Figure 26 This is a block diagram illustrating an electronic device according to an example embodiment.

[0172] like Figure 26 As shown, the electronic device 1000 includes an application processor 1110, a smart card 1200, a storage device 1120, a user interface 1130, and a power supply 1140. In some embodiments, the electronic system 1000 may be a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a laptop computer, etc.

[0173] Application processor 1110 can control the overall operation of electronic system 1000. Application processor 1110 can execute applications, such as web browsers, game applications, video players, etc. In some embodiments, application processor 1110 may include single-core or multi-core processors. For example, application processor 1110 may be a multi-core processor, such as a dual-core processor, quad-core processor, hexa-core processor, etc. Application processor 1110 may include internal or external cache memory.

[0174] Storage device 1120 can store data required for the operation of electronic system 1000. For example, storage device 1120 can store a boot image for booting electronic system 1000, output data to be output to external devices, and input data received from external devices. For example, storage device 1120 can be electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM).

[0175] The smart card 1200 may include a connection interface 1210 and a smart card chip 1220. It can receive voltage from an external card reader via the connection interface 1210 in a contact or contactless manner, and can exchange data with the external card reader. The smart card 1200 can use... Figure 2 50 smart cards.

[0176] Therefore, the smart card 1200 may include an LDO regulator. In contact and contactless modes, the LDO regulator drives the error amplifier with a second drive voltage and a first drive voltage, each with different voltage levels. In contact mode, a first power transistor implemented with a PMOS transistor adjusts the second drive voltage based on the first error voltage to provide the first output voltage; in contactless mode, a second power transistor implemented with an NMOS transistor adjusts the second drive voltage based on the first error voltage to provide the first output voltage. Therefore, the LDO regulator can stably provide the first output voltage to the logic block in both contact and contactless modes.

[0177] The user interface 1130 may include at least one input device, such as a keyboard or touchscreen, and at least one output device, such as a speaker or display device. The power supply 1140 may provide power voltage to the electronic system 1000.

[0178] In some embodiments, the electronic device 1000 may further include an image processor and / or a storage device, such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), or an optical disk.

[0179] In some embodiments, electronic device 1000 and / or components of electronic device 1000 may be packaged in various forms, such as package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package die, wafer-type die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stacked package (WSP).

[0180] The foregoing description is illustrative of the inventive concept and should not be construed as limiting it. While several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the appended claims and their equivalents.

Claims

1. An internal voltage generator for a smart card, the internal voltage generator comprising: A pattern detector is configured to generate a pattern signal indicating one of a contact mode and a contactless mode. The smart card is configured to provide an input voltage when in direct contact with an external card reader in the contact mode, and to provide an input voltage without direct contact with an external card reader in the contactless mode. The switched capacitor circuit is configured to generate a first drive voltage and a second drive voltage based on a rectified voltage obtained through a rectified input voltage, wherein... The second driving voltage is less than the first driving voltage; and A low-dropout LDO regulator, comprising an error amplifier, wherein the LDO regulator is operable in response to the mode signal to: In the contact mode, the error amplifier is driven by the second drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage using a first power transistor to generate a first output voltage. In the non-contact mode, the error amplifier is driven by the first drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage using a second power transistor to generate a first output voltage.

2. The internal voltage generator according to claim 1, wherein, The error amplifier is connected between a power supply terminal and a ground voltage terminal and is configured to amplify the difference between the feedback voltage and the reference voltage to output the error voltage. The power supply terminal receives one of the first drive voltage and the second drive voltage, and the LDO regulator includes: A polarity selector is configured to provide each of a reference voltage and a feedback voltage between the positive and negative input terminals of the error amplifier based on the polarity of the mode signal. A first power transistor is connected between a second drive voltage terminal and an output node to provide a first output voltage; A first power switch is connected between the output of the error amplifier and the gate of the first power transistor. The second power transistor is connected in parallel with the first power transistor between the second drive voltage terminal and the output node. The conductive channel type of the second power transistor is different from that of the first power transistor. A second power switch is connected between the output of the error amplifier and the gate of the second power transistor; as well as A feedback circuit, connected between the output node and the ground voltage, is configured to divide the first output voltage to provide a feedback voltage.

3. The internal voltage generator according to claim 2, wherein, The first power transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, with its source coupled to the second driving voltage, its gate coupled to the first power switch, and its drain coupled to the output node. The second power transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, with its drain coupled to the second driving voltage, its gate coupled to the second power switch, and its source coupled to the output node.

4. The internal voltage generator according to claim 3, wherein, The gate-drain voltage of the first power transistor is different from the gate-source voltage of the second power transistor.

5. The internal voltage generator according to claim 2, wherein, In the contact mode, The first power switch is turned on in response to a first power switch control signal and applies the error voltage to the gate of the first power transistor. The second power switch is turned off in response to the second power switch control signal, and disconnects the output of the error amplifier from the gate of the second power transistor.

6. The internal voltage generator according to claim 2, wherein, In the non-contact mode, The first power switch is turned off in response to a first power switch control signal, and the output of the error amplifier is disconnected from the gate of the first power transistor. The second power switch is turned on in response to a second power switch control signal and applies the error voltage to the gate of the second power transistor.

7. The internal voltage generator according to claim 2, wherein, The polarity selector is configured to provide the reference voltage and the feedback voltage to the negative and positive input terminals of the error amplifier, respectively, based on the mode signal in the contact mode.

8. The internal voltage generator according to claim 2, wherein, The polarity selector is configured to provide the reference voltage and the feedback voltage to the positive and negative input terminals of the error amplifier, respectively, based on the mode signal in the contactless mode.

9. The internal voltage generator according to claim 2, further comprising: A voltage selector is configured to provide one of the first drive voltage and the second drive voltage to the power supply terminal of the error amplifier in response to the mode signal.

10. The internal voltage generator according to claim 9, wherein, The voltage selector: Configured to provide the second drive voltage to the power supply terminal of the error amplifier based on the mode signal in the contact mode, and It is configured to provide the first drive voltage to the power supply terminal of the error amplifier based on the mode signal in the non-contact mode.

11. The internal voltage generator according to claim 2, wherein, The feedback circuit includes a first feedback resistor and a second feedback resistor connected in series between the output node and the ground voltage. The first feedback resistor and the second feedback resistor are connected to each other at the feedback node, and The feedback circuit is configured to provide the voltage of the feedback node as the feedback voltage.

12. The internal voltage generator according to claim 1, further comprising: A voltage regulator is configured to regulate the first drive voltage to generate a second output voltage, and in, The switched capacitor circuit includes: A first switched capacitor converter is configured to convert a rectified voltage into a first drive voltage; and The second switched capacitor converter is configured to convert the first drive voltage into a second drive voltage, and Wherein, the first driving voltage is less than the rectified voltage, and the second driving voltage is less than the first driving voltage.

13. The internal voltage generator according to claim 12, wherein, The first switched capacitor converter includes: A first switch, connected between a first node and a second node receiving the rectified voltage, is configured to be switched in response to a first switch control signal; A capacitor, coupled between the second node and the third node; A second switch, connected between the second node and a fourth node providing the first drive voltage, is configured to be switched in response to a second switch control signal; A third switch, connected between the third node and the ground voltage, is configured to be switched in response to a second switch control signal; as well as A fourth switch, connected between the third node and the fourth node, is configured to be switched in response to a first switch control signal.

14. The internal voltage generator according to claim 13, wherein, When the first switch and the fourth switch are turned on in response to the first switch control signal, and the second switch and the third switch are turned off in response to the second switch control signal, the rectified voltage is stored in the capacitor, and When the first switch and the fourth switch are turned off in response to the first switch control signal, and the second switch and the third switch are turned on in response to the second switch control signal, the capacitor is configured to provide a rectified voltage stored in the capacitor as the first drive voltage.

15. A smart card configured to perform fingerprint authentication, the smart card comprising: The connection interface is configured to provide a voltage received from an external card reader as an input voltage in both a contact mode where the connection interface is in direct contact with the card reader and a contactless mode where the connection interface is not in direct contact with the card reader. A smart card chip, coupled to the connection interface via a first power terminal and a second power terminal, wherein the smart card chip includes: The internal voltage generator is configured as follows: A first driving voltage and a second driving voltage are generated based on the input voltage, wherein the second driving voltage is less than the first driving voltage; In contact mode, a first output voltage is generated by adjusting the second drive voltage based on the second drive voltage using a first power transistor; and in non-contact mode, a first output voltage is generated by adjusting the second drive voltage based on the first drive voltage using a second power transistor. In each of the contact mode and the non-contact mode, the first drive voltage is adjusted to generate the second output voltage; A fingerprint recognition sensor, which operates based on the second output voltage, is configured to generate a fingerprint image signal based on an input fingerprint; and A processor that operates based on the first output voltage, the processor being configured to perform fingerprint authentication based on the fingerprint image signal.

16. The smart card according to claim 15, wherein, The internal voltage generator includes: A mode detector is connected to the connection interface via the first power terminal and the second power terminal, and is configured to generate a mode signal based on the input voltage in each of the contact mode and the non-contact mode, wherein the state of the mode signal indicates the contact mode or the non-contact mode. A switched capacitor circuit is configured to generate the first drive voltage and the second drive voltage based on a rectified voltage obtained through a rectified input voltage; and A low-dropout LDO regulator, comprising an error amplifier, wherein the LDO regulator is based on the mode signal: In the contact mode, the error amplifier is driven by the second drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage to generate a first output voltage. In the contactless mode, the error amplifier is driven by the first driving voltage to generate an error voltage, and the second driving voltage is adjusted based on the error voltage to generate a first output voltage. The internal voltage generator further includes a voltage regulator configured to adjust the first drive voltage to generate the second output voltage.

17. The smart card according to claim 16, wherein, The error amplifier is connected between a power supply terminal and a ground voltage terminal and is configured to amplify the difference between the feedback voltage and the reference voltage to output the error voltage. The power supply terminal receives one of the first drive voltage and the second drive voltage, and the LDO regulator includes: A polarity selector is configured to provide each of a reference voltage and a feedback voltage between the positive and negative input terminals of the error amplifier based on the polarity of the mode signal. A first power transistor is connected between a second drive voltage terminal that provides the second drive voltage and an output node that provides the first output voltage; A first power switch is connected between the output of the error amplifier and the gate of the first power transistor. A second power transistor is connected in parallel with the first power transistor between the second drive voltage terminal and the output node, and the second power transistor is different from the first power transistor. A second power switch is connected between the output of the error amplifier and the gate of the second power transistor; as well as A feedback circuit, connected between the output node and the ground voltage, is configured to divide the first output voltage to provide the divided first output voltage as a feedback voltage.

18. The smart card according to claim 17, wherein, The first power transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, with its source coupled to the second drive voltage terminal, its gate coupled to the first power switch, and its drain coupled to the output node. The second power transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, with its drain coupled to the second drive voltage terminal, its gate coupled to the second power switch, and its source coupled to the output node.

19. The smart card according to claim 18, wherein, In the contact mode, The first power switch is turned on in response to a first power switch control signal and applies the error voltage to the gate of the first power transistor. The second power switch is turned off in response to a second power switch control signal, and the output of the error amplifier is disconnected from the gate of the second power transistor. In the non-contact mode, The first power switch is turned off in response to the first power switch control signal, and the output of the error amplifier is disconnected from the gate of the first power transistor. The second power switch is turned on in response to the second power switch control signal and applies the error voltage to the gate of the second power transistor.

20. An internal voltage generator configured to perform fingerprint authentication on a smart card, the internal voltage generator comprising: A pattern detector is configured to generate a pattern signal indicating one of a contact mode and a contactless mode. The smart card is configured to provide an input voltage while in direct contact with an external card reader in the contact mode, and to provide an input voltage without direct contact with an external card reader in the contactless mode. A switched capacitor circuit is configured to generate a first drive voltage and a second drive voltage based on a rectified voltage obtained through a rectified input voltage, wherein the second drive voltage is less than the first drive voltage. as well as A low-dropout LDO regulator includes an error amplifier, a first power transistor, and a second power transistor with a different channel type than the first power transistor, wherein the LDO regulator is operable based on a mode signal for: In the contact mode, the error amplifier is driven by the second drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage using the first power transistor to generate a first output voltage. In the non-contact mode, the error amplifier is driven by the first drive voltage to generate an error voltage, and the second drive voltage is adjusted based on the error voltage using the second power transistor to generate a first output voltage.

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