Display panel and manufacturing method thereof

Abstract

This invention discloses a display panel and its fabrication method. In one specific embodiment, the fabrication method includes: forming a display panel comprising a display area and a bending area, wherein the display area is formed as an active region, a gate, a first source / drain electrode of a thin-film transistor formed on a substrate, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending into the bending area; the bending area is formed as a blocking structure formed on the substrate and a groove formed through the insulating layers; wherein the projection of the blocking structure on the substrate covers the projection of the groove on the substrate. This embodiment avoids abnormal phenomena such as black spots on the source / drain electrodes after etching of the source / drain layers, which is beneficial to the stability and effectiveness of the displayed image.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to a display panel and a method for manufacturing the same. Background Technology

[0002] To reduce the power consumption of the driver IC, existing OLED display devices use low-temperature polycrystalline oxide (LTPO) technology in their pixel circuits to reduce leakage current in the driver transistors during the light-emitting stage, thereby achieving the goal of reducing power consumption.

[0003] The inventors discovered that, in order to save on masking processes, existing LTPO products undergo etching of the bending region simultaneously with vias in the display area. However, when the source / drain layer is deposited after over-etching the flexible substrate in the bending region, the volatile gases generated by the flexible substrate react with the metal in the source / drain layer, leading to abnormalities in the film quality. Specifically, materials such as Ti / Al / Ti react with organic matter to form polymers. These polymers may contaminate the source / drain layer deposition chamber, causing voids in the chamber. Furthermore, these polymers remain after etching the source / drain layer, resulting in abnormal phenomena such as black spots. Summary of the Invention

[0004] The purpose of this invention is to provide a display panel and a method for manufacturing the same, so as to solve at least one of the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] The first aspect of the present invention provides a method for manufacturing a display panel, comprising:

[0007] Forming a display panel including a display area and a bending area, wherein

[0008] The display area is formed as including an active region, a gate, a first source / drain electrode of a thin-film transistor formed on a substrate, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending to the bending region.

[0009] The bending region is formed as including a barrier structure formed on the substrate and a groove formed through each of the insulating layers; wherein the projection of the barrier structure on the substrate overlaps the projection of the groove on the substrate.

[0010] The method for manufacturing a display panel provided by the first aspect of the present invention can effectively prevent the reaction between the gas volatilization of the flexible substrate and the metal of the first source and drain electrode caused by the opening of the groove during the formation of the first source and drain electrode without adding a mask process. This is achieved by setting a blocking structure in the bending area, thereby avoiding the formation of holes in the source and drain layer deposition chamber and avoiding abnormal phenomena such as black spots on the source and drain electrodes after etching of the source and drain layer. This is beneficial to the stability and effectiveness of the display screen in the display area.

[0011] Optionally, the display panel forming the display area and the bending area includes:

[0012] A first metal light-shielding structure is formed at the location where the display area is to be formed on the substrate, and a second metal light-shielding structure is formed at the location where the bending area is to be formed, wherein the second metal light-shielding structure is the blocking structure;

[0013] A first insulating layer is formed to cover the first metal light-shielding structure and the second metal light-shielding structure.

[0014] An active region of a thin-film transistor is formed on the first insulating layer at a position corresponding to the first metal light-shielding structure.

[0015] A second insulating layer is formed, covering the active region and the exposed first insulating layer;

[0016] The gate of the thin-film transistor is formed on the second insulating layer at the location corresponding to the active region;

[0017] A third insulating layer is formed, covering the gate and the exposed second insulating layer;

[0018] A first via is formed in the display area, extending from the third insulating layer to the active area, and a groove is formed in the bending area, extending from the third insulating layer to the second metal light-shielding structure.

[0019] The first source / drain electrode of the thin-film transistor is electrically connected to the active region through the first via.

[0020] Optionally, it also includes:

[0021] Remove the exposed portion of the second metal light-shielding structure.

[0022] Optionally, the first source / drain electrode forming the thin-film transistor is electrically connected to the active region through the first via, including:

[0023] A source / drain electrode material layer is deposited, the source / drain electrode material layer covering the first via and the groove;

[0024] The source / drain electrode material layer is patterned to form the first source / drain electrode, and the source / drain electrode material layer covering the groove is removed while the first source / drain electrode is patterned and formed.

[0025] Optionally, the first source / drain electrode forming the thin-film transistor is electrically connected to the active region through the first via, including...

[0026] A source / drain electrode material layer is deposited, the source / drain electrode material layer covering the first via and the groove;

[0027] The source and drain electrode material layer is patterned to form the first source and drain electrode and the sidewalls in the groove, as well as the exposed portion of the second metal light-shielding structure, forming the bent area traces.

[0028] Optionally, it also includes:

[0029] A fourth insulating layer is formed to cover the display area and the bending area;

[0030] A light-emitting element functional layer is formed on the fourth insulating layer of the display area, including an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer of the light-emitting element electrically connected to one of the first source and drain electrodes through a second via in the fourth insulating layer.

[0031] Optionally, it also includes:

[0032] A fourth insulating layer is formed to cover the display area and the bending area;

[0033] A second via is formed in the display area, penetrating from the fourth insulating layer to the third insulating layer;

[0034] The second source / drain electrode of the thin-film transistor is formed and electrically connected to the first source / drain electrode through the second via.

[0035] A fifth insulating layer is formed, covering the display area and the bending area;

[0036] A light-emitting element functional layer is formed on the fifth insulating layer of the display area, including an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer of the light-emitting element electrically connected to one of the second source and drain electrodes through a third via in the fifth insulating layer.

[0037] Optionally, the display panel forming the display area and the bending area includes:

[0038] A first metal light-shielding structure is formed at the location where the display area is to be formed on the substrate, and a second metal light-shielding structure is formed at the location where the bending area is to be formed, wherein the second metal light-shielding structure is the blocking structure;

[0039] A first insulating layer is formed to cover the first metal light-shielding structure and the second metal light-shielding structure.

[0040] The active region of the first thin-film transistor is formed on the first insulating layer at the position corresponding to the first metal light-shielding structure;

[0041] A second insulating layer is formed to cover the active region of the first thin-film transistor and the exposed first insulating layer;

[0042] The gate of the first thin-film transistor is formed on the second insulating layer at the location corresponding to the active region of the first thin-film transistor.

[0043] A third insulating layer is formed, covering the gate of the first thin-film transistor and the exposed second insulating layer;

[0044] An active region of a second thin-film transistor is formed on the third insulating layer, wherein the projection of the active region of the second thin-film transistor onto the substrate does not overlap with the projection of the active region of the first thin-film transistor.

[0045] A fourth insulating layer is formed, covering the active region of the second thin-film transistor and the exposed third insulating layer;

[0046] The gate of the second thin-film transistor is formed on the fourth insulating layer at the location corresponding to the active region of the second thin-film transistor;

[0047] A fifth insulating layer is formed, covering the gate of the second thin-film transistor and the exposed fourth insulating layer;

[0048] A first via is formed in the display area, extending from the fifth insulating layer to the active area of ​​the second thin-film transistor, and a first groove is formed in the bending area, extending from the fifth insulating layer to the third insulating layer.

[0049] A second via is formed in the display area, extending from the fifth insulating layer to the active area of ​​the first thin-film transistor, and a second groove is formed in the bending area, extending from the third insulating layer to the second metal light-shielding structure, wherein the first groove and the second groove are aligned in the projection direction of the substrate.

[0050] The first source / drain electrode of the second thin-film transistor is formed and electrically connected to the active region of the second thin-film transistor through the first via, and the first source / drain electrode of the first thin-film transistor is formed and electrically connected to the active region of the first thin-film transistor through the second via.

[0051] Optionally, the first thin-film transistor is a low-temperature polycrystalline silicon thin-film transistor;

[0052] The second thin-film transistor is an oxide thin-film transistor.

[0053] A second aspect of the present invention provides a display panel,

[0054] The display panel includes a display area and a bending area, wherein

[0055] The thin-film transistor in the display area includes an active region, a gate, a first source / drain electrode, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending into the bending region;

[0056] The bending region includes a barrier structure formed on the substrate and a groove formed through each of the insulating layers; wherein the projection of the barrier structure on the substrate overlaps the projection of the groove on the substrate.

[0057] Optionally, the groove extends through the second metal light-shielding structure, and the display panel further includes:

[0058] The blocking structure formed on the exposed portion and the bend area wiring on the sidewall of the groove.

[0059] A third aspect of the present invention provides a display panel,

[0060] The display panel includes a display area and a bending area, wherein

[0061] The thin-film transistor in the display area includes an active region, a gate, a first source / drain electrode, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending into the bending region;

[0062] The bending region includes a patterned barrier structure formed on the substrate and a groove formed through each of the insulating layers; wherein the projection of the patterned barrier structure on the substrate surrounds the projection of the groove on the substrate.

[0063] The beneficial effects of this invention are as follows:

[0064] To address the technical problems existing in the current technology, the present invention provides a display panel and its manufacturing method. By setting a blocking structure in the bending area, the display panel can effectively avoid the reaction between the gas volatilization of the flexible substrate and the metal of the first source and drain electrode caused by the grooves opened during the formation of the first source and drain electrode without adding a mask process. This avoids the formation of holes in the source and drain layer deposition chamber and avoids abnormal phenomena such as black spots on the source and drain electrodes after the source and drain layer is etched, which is beneficial to the stability and effectiveness of the display screen. Attached Figure Description

[0065] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0066] Figure 1 This diagram illustrates the presence of pores in the source / drain layer deposition chamber of LTPO products in the prior art.

[0067] Figure 2 This diagram illustrates an abnormal black dot pattern appearing in the display area of ​​an existing LTPO product.

[0068] Figure 3 This diagram shows a cross-sectional view of step S1 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0069] Figure 4 This diagram shows a cross-sectional view of step S2 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0070] Figure 5 This diagram shows a cross-sectional view of step S3 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0071] Figure 6 This diagram shows a cross-sectional view of step S4 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0072] Figure 7 This diagram shows a cross-sectional view of step S5 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0073] Figure 8 This diagram shows a cross-sectional view of step S6 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0074] Figure 9 This diagram shows a cross-sectional view of step S7 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0075] Figure 10 This diagram shows a cross-sectional view of step S8 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0076] Figure 11 This diagram shows a cross-sectional view of step S9 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0077] Figure 12 This diagram shows a cross-sectional view of step S10 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0078] Figure 13 This diagram shows a cross-sectional view of step S11 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0079] Figure 14 This diagram shows a cross-sectional view of step S12 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0080] Figure 15 This diagram shows a cross-sectional view of step S13 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0081] Figure 16 This diagram shows a cross-sectional view of step S14 in the manufacturing process of a display panel according to an embodiment of the present invention.

[0082] Figure 17 This diagram shows a cross-sectional view of step S9 in the manufacturing process of a display panel according to another embodiment of the present invention.

[0083] Figure 18 This diagram shows a cross-sectional view of step S10 in the manufacturing process of a display panel according to another embodiment of the present invention.

[0084] Figure 19 This diagram shows a cross-sectional view of step S11 in the manufacturing process of a display panel according to another embodiment of the present invention.

[0085] Figure 20 This diagram shows a cross-sectional view of step S12 in the manufacturing process of a display panel according to another embodiment of the present invention.

[0086] Figure 21 This diagram shows a cross-sectional view of step S13 in the manufacturing process of a display panel according to another embodiment of the present invention.

[0087] Figure 22 This diagram shows a cross-sectional view of step S14 in the manufacturing process of a display panel according to another embodiment of the present invention. Detailed Implementation

[0088] In this invention, "on," "formed on," and "set on" can mean that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0089] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or portions, these components, members, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or portion from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the invention.

[0090] In this invention, unless otherwise stated, the term "co-layer arrangement" refers to two layers, components, members, elements, or portions that can be formed by the same fabrication process (e.g., patterning process), and that these two layers, components, members, elements, or portions are generally formed of the same material. For example, co-layer arrangement of two or more functional layers means that these co-layered functional layers can be formed using the same material layer and the same fabrication process, thereby simplifying the fabrication process of the display substrate.

[0091] In this invention, unless otherwise stated, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "one-step patterning process" refers to a process of forming patterned layers, components, or parts using a single photomask.

[0092] To reduce the power consumption of the driver IC, the pixel circuits of existing OLED display devices use Low Temperature Polycrystalline Oxide (LTPO) technology. This means that a pixel circuit includes both Low Temperature Poly-Silicon (LTPS) thin-film transistors and oxide thin-film transistors to reduce leakage current of the driver transistors during the light-emitting stage, thereby achieving the goal of reducing power consumption.

[0093] Existing LTPO products manufactured using the technology include an LTPO display panel comprising a display area and a bending area. The display area is formed as an active region, a gate, a first source / drain electrode of a thin-film transistor formed on a flexible substrate, and insulating layers for electrically isolating the active region, gate, and first source / drain electrode, with each insulating layer extending into the bending area. A metal light-shielding structure is typically formed at the location on the flexible substrate where the display area is to be formed. To save on masking processes, the etching process of the bending area is performed simultaneously with the vias in the display area. However, when the source / drain electrode is deposited after etching the flexible substrate layer in the bending area, volatile gases are generated due to the flexible substrate. These volatile gases react with the metal of the source / drain layer, leading to abnormalities in the source / drain layer film. Specifically, materials such as Ti / Al / Ti react with organic matter to form polymers. These polymers may contaminate the source / drain layer deposition chamber, causing voids in the deposition chamber. Figure 1 As shown, the polymer remains after the source / drain layer is etched, resulting in abnormal phenomena such as black spots. Figure 2 As shown, this results in various dot-like defects and poor reliability in the display area, affecting the display effect.

[0094] In view of this, the present invention provides a method for preparing a display substrate and the display substrate thereof.

[0095] The following describes the preparation method of the display substrate and the display substrate of some embodiments of the present invention through several specific examples.

[0096] Example 1

[0097] One embodiment of the present invention provides a method for preparing a display substrate, the method comprising:

[0098] Step S1: Provide a substrate 1011, form a first metal light-shielding structure 10 at the location where the display area 101 is to be formed on the substrate 1011, and form a second metal light-shielding structure 11 at the location where the bending area is to be formed, wherein the second metal light-shielding structure 11 is a blocking structure.

[0099] For example, when the display substrate is a flexible display substrate, the provided substrate 1011 can be a flexible substrate such as polyimide (PI), polyethylene naphthalate (PEN), or thermoplastic polyester (PET). When the display substrate is a rigid substrate, the substrate 1011 can be a rigid substrate such as glass or quartz. This embodiment will be described using the formation of a flexible display substrate as an example.

[0100] The flexible substrate 1011 in this embodiment includes a first polyimide layer 1011A, a first barrier layer 1011B, and a second polyimide layer 1011C, such as Figure 3 As shown, a display area 101 and a bending area 201 are first formed on a flexible substrate 1011. A first metal light-shielding structure 10 is formed at the location where the display area 101 is to be formed on the flexible substrate 1011. This structure is used to prevent the thin-film transistor from experiencing threshold voltage shifts, which is beneficial to the stability of the displayed image. A second metal light-shielding structure 11 is formed at the location where the bending area 201 is to be formed on the flexible substrate 1011. This structure acts as a barrier to prevent the gas from the flexible substrate from evaporating and reacting with the metal of the source and drain electrodes when the source and drain electrodes of the thin-film transistor are formed. This prevents abnormalities in the source and drain electrode films and avoids phenomena such as black spots.

[0101] Step S2: A first insulating layer 1012 is formed on a substrate 1011 by deposition or other methods. The first insulating layer 1012 covers the first metal light-shielding structure 10 and the second metal light-shielding structure 11. The active region 1021 of the first thin film transistor is formed on the first insulating layer 1012 at the position corresponding to the first metal light-shielding structure 10 using a patterning process.

[0102] For example, a single patterning process includes the formation of photoresist, exposure, development, and etching.

[0103] For example, the first insulating layer 1012 includes a second barrier layer 1012A and a first buffer layer 1012B, such as Figure 4As shown, the first insulating layer 1012 covers the first metal light-shielding structure 10 and the second metal light-shielding structure 11.

[0104] For example, the second barrier layer 1012A and the first buffer layer 1012B can be formed on the entire surface of the substrate 1011. For example, the second barrier layer 1012A can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the first buffer layer 1012B can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The barrier layer helps to prevent water and oxygen from entering the OLED from the bottom. The buffer layer improves the quality of subsequent material deposition.

[0105] For example, the active region 1021 can be made of materials such as polycrystalline silicon and metal oxide. When the active region is made of polycrystalline silicon, the corresponding thin-film transistor is a low-temperature poly-silicon (LTPS) thin-film transistor. When the active region is made of materials such as metal oxide, the corresponding thin-film transistor is an oxide thin-film transistor.

[0106] In one possible implementation, the first thin-film transistor is a low-temperature poly-silicon (LTPS) thin-film transistor, and the second thin-film transistor is an oxide thin-film transistor.

[0107] In this embodiment, the active region pattern of the LTPS thin film transistor is made of low-temperature polycrystalline silicon, and the LTPS thin film transistor is a top-gate structure with the gate located above its active region pattern.

[0108] For example, the active region material of an oxide transistor can be a metal oxide such as IGZO (Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide). In this embodiment, an IGZO thin-film transistor is selected. The IGZO thin-film transistor has a dual-gate structure, with the two gates located above and below its active region pattern, respectively.

[0109] Step S3: A first gate insulating layer 1013 is formed on the active region 1021 by deposition or other means, covering the active region 1021 and the exposed first buffer layer 1012B, as shown below. Figure 5 As shown. The gate 1022 of the LTPS thin film transistor is formed on the first gate insulating layer 1013 at a position above the active region 1021 of the first thin film transistor.

[0110] For example, the first gate insulating layer 1013 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; the gate 1022 of the LTPS thin film transistor is made of metals or alloys such as aluminum, titanium, and cobalt. During fabrication, a gate material layer is first formed by sputtering or evaporation, and then the gate material layer is patterned to form a patterned gate 1022.

[0111] Step S4: A second gate insulating layer 1014A is formed on the gate 1022 of the LTPS thin film transistor by deposition or other means, covering the gate 1022 of the LTPS thin film transistor and the exposed first gate insulating layer 1013, as shown below. Figure 6 As shown. The first gate 1032 of the IGZO thin film transistor is formed on the second gate insulating layer 1014A at a position below the active region 1031 of the IGZO thin film transistor.

[0112] For example, the second gate insulating layer 1014A can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The material of the first gate 1032 of the IGZO thin film transistor includes metals or alloys such as aluminum, titanium, and cobalt. During fabrication, a gate material layer is first formed by sputtering or evaporation, and then a patterning process is performed on the gate material layer to form the patterned first gate 1032 of the IGZO thin film transistor.

[0113] The projections of the active region 1031 of the IGZO thin film transistor and the active region 1021 of the LTPS thin film transistor onto the flexible substrate do not overlap.

[0114] Step S5: A second buffer layer 1014B is formed on the first gate 1032 of the IGZO thin film transistor by deposition or other methods. An active region 1031 of the IGZO thin film transistor is then formed on the second buffer layer 1014B at the position corresponding to the first gate 1032 using a patterning process. Figure 7 As shown.

[0115] For example, the second buffer layer 1014B can be formed on the entire surface of the first gate 1032 of the IGZO thin film transistor. For example, the second buffer layer 1014B can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0116] Step S6: A third gate insulating layer 1015 is formed on the active region 1031 of the IGZO thin film transistor by deposition or other means, covering the active region 1031 and the exposed second buffer layer 1014B. A second gate 1033 of the IGZO thin film transistor is formed on the third gate insulating layer 1015 at a position corresponding to the position above the active region 1031 of the IGZO thin film transistor. Figure 8 As shown.

[0117] For example, the third gate insulating layer 1015 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The material of the second gate 1033 of the IGZO thin film transistor includes metals or alloys such as aluminum, titanium, and cobalt. During fabrication, a gate material layer is first formed by sputtering or evaporation, and then a patterning process is performed on the gate material layer to form the patterned second gate 1033 of the IGZO thin film transistor.

[0118] Step S7: An interlayer dielectric layer 1016 is formed on the second gate 1033 of the IGZO thin film transistor by deposition or other means, covering the second gate 1033 and the exposed third gate insulating layer 1015; the interlayer dielectric layer 1016 is etched in the display area to penetrate into the active region 1031 of the IGZO thin film transistor to form a first via exposing the active region 1031 of the IGZO thin film transistor; the interlayer dielectric layer 1016 is etched in the bending region to penetrate into the second buffer layer 1014B to form a first groove exposing the second buffer layer 1014B, as shown. Figure 9 As shown.

[0119] For example, the interlayer dielectric layer 1016 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the upper opening length of the first groove is greater than the lower opening length of the first groove.

[0120] Step S8: Etch the interlayer dielectric layer 1016 in the display area, penetrating into the active region 1021 of the LTPS thin film transistor to form a second via exposing the active region 1021 of the LTPS thin film transistor; etch the second buffer layer 1014B in the bending region, penetrating into the second barrier layer 1012B to form a second groove exposing the second metal light-shielding structure 11, as shown. Figure 10 As shown, the first groove and the second groove are aligned in the projection direction of the substrate.

[0121] For example, the lower opening length of the first groove is greater than the upper opening length of the second groove, and the upper opening length of the second groove is greater than the lower opening length of the second groove.

[0122] Step S9: Form the first source / drain electrode of the IGZO thin film transistor, which is electrically connected to the active region 1031 of the IGZO thin film transistor through the first via, and form the first source / drain electrode of the LTPS thin film transistor, which is electrically connected to the active region 1021 of the LTPS thin film transistor through the second via.

[0123] In one possible implementation, step S9 includes:

[0124] Step S91: Deposit a source / drain electrode material layer, wherein the source / drain electrode material layer covers the first via, the second via, the first groove, and the second groove;

[0125] Step S92: Pattern the source / drain electrode material layer to form the first source / drain electrode of the IGZO thin film transistor and the first source / drain electrode of the LTPS thin film transistor. Simultaneously, while patterning the first source / drain electrode of the IGZO thin film transistor and the first source / drain electrode of the LTPS thin film transistor, remove the source / drain electrode material layer covering the first and second grooves. Figure 11 As shown.

[0126] For example, after the source and drain electrode material layers are deposited and cover the first via, the second via, the first groove, and the second groove, the source and drain electrode material layers in the bending region are covered on the exposed second metal light-shielding structure 11 and do not directly contact the flexible substrate 1011. Since the material of the second metal light-shielding structure 11 is metal, which is different from the material of the flexible substrate, the second metal light-shielding structure does not generate volatile gases during the deposition of the source and drain electrode materials. This avoids the formation of holes in the source and drain layer deposition chamber, the etching of the source and drain electrode materials in the first groove and the second groove, and also avoids abnormal phenomena such as black spots on the source and drain electrodes after the source and drain layer is etched.

[0127] In one possible implementation, the preparation method further includes:

[0128] Remove the exposed second metal light-shielding structure 11.

[0129] Step S10: Form a first planarization layer 1017 to cover the display area 101 and the bending area 201; form a third via at the position of the first source / drain electrode of the IGZO thin film transistor corresponding to the first planarization layer 1017; and form a fourth via at the position of the first source / drain electrode of the LTPS thin film transistor corresponding to the first planarization layer 1017.

[0130] Specifically, a planarization layer material, such as an organic material, with a thickness of approximately 1–3 μm, is deposited to cover the aforementioned film layers. Then, using a patterning process, the layers are patterned to form a third via at the location corresponding to the first source / drain electrode of the IGZO thin-film transistor, and a fourth via at the location corresponding to the first source / drain electrode of the LTPS thin-film transistor. Figure 12 As shown. The position of the third opening corresponds to the position of the first opening, and the position of the fourth opening corresponds to the position of the second opening.

[0131] Step S11: Form the second source / drain electrode of the LTPS thin film transistor and electrically connect it to the first source / drain electrode of the LTPS thin film transistor through a fourth via; form the second source / drain electrode of the IGZO thin film transistor and electrically connect it to the first source / drain electrode of the IGZO thin film transistor through a third via.

[0132] Specifically, a source / drain electrode material layer is deposited, covering the third and fourth vias. Then, the source / drain electrode material layer is patterned to form the second source / drain electrode of the LTPS thin-film transistor, which is electrically connected to the first source / drain electrode of the LTPS thin-film transistor through the fourth via. The second source / drain electrode of the IGZO thin-film transistor is then formed, electrically connected to the first source / drain electrode of the IGZO thin-film transistor through the third via. Figure 13 As shown.

[0133] Step S12: Form a second planarization layer 1018, covering the display area 101 and the bending area 201; form an opening in the second planarization layer 1018 corresponding to the second source electrode position of the LTPS thin film transistor, such as... Figure 14 As shown.

[0134] Step S13: Forming a light-emitting element functional layer in the second planarization layer 1018, including:

[0135] Step 131: Deposit the anode metal layer of the OLED in the openings of the second planarization layer 1018 and pattern it to form the anode 1041 (the anode 1041 is connected to the second source electrode of the LTPS thin film transistor), as shown. Figure 15 As shown, for example, the anode material includes metal oxides such as ITO and IZO, or metals such as Ag, Al, and Mo, or their alloys.

[0136] Step S132: Form a pixel boundary layer around the anode using a patterning process. Specifically, deposit a pixel boundary layer material, for example, with a thickness of about 1 to 2 μm. Form a pixel boundary layer in the display area using a patterning process. For example, the material of the pixel boundary layer may include negative photoresist, polyimide, epoxy resin and other organic insulating materials.

[0137] Step S133: A light-emitting layer is formed on the anode 1041 in the opening of the pixel defining layer by means of inkjet printing or vapor deposition, wherein the material of the light-emitting layer is an organic material;

[0138] Step S44: Forming a cathode. The cathode is formed on the entire surface of the OLED display substrate, for example. The cathode material may include metals such as Mg, Ca, Li or Al or their alloys, or metal oxides such as IZO or ZTO, or organic materials with conductive properties such as PEDOT / PSS (poly(3,4-ethylenedioxythiophene / polystyrene sulfonate)).

[0139] In this configuration, the anodes corresponding to each pixel are isolated from each other, while the cathodes corresponding to each pixel are connected to each other.

[0140] An auxiliary light-emitting layer that facilitates the emission of light from the light-emitting layer can also be formed between the anode 1041 and the light-emitting layer, and between the light-emitting layer and the cathode. This auxiliary light-emitting layer may include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. For example, an organic material layer may be used as the auxiliary light-emitting layer.

[0141] Step S14: After the OLED device is formed, an encapsulation layer 1019 can be formed, such as... Figure 16 As shown.

[0142] For example, the encapsulation layer can be an inorganic encapsulation layer or an organic encapsulation layer.

[0143] For example, inorganic encapsulation layers are formed using methods such as deposition. Organic encapsulation layers are formed using inkjet printing.

[0144] For example, inorganic encapsulation layers can be formed using inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, while organic encapsulation layers can be formed using organic materials such as polyimide (PI) and epoxy resin. The combination of inorganic and organic encapsulation layers forms a composite encapsulation layer, which provides multiple layers of protection for the functional structure of the display area, resulting in better encapsulation performance.

[0145] The embodiments of the present invention do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the examples above.

[0146] It should be noted that there can be one or more thin-film transistors, and this invention does not limit this.

[0147] Those skilled in the art should understand that although the above steps are described in the order of S1-S14, it does not mean that they must be performed in this order, as long as they do not violate logic.

[0148] Example 2

[0149] Another embodiment of the present invention provides a display substrate, which can be fabricated using the fabrication method described in Embodiment 1. Figure 16 As shown, the display substrate includes:

[0150] The display area 101 and the bending area 201 are formed on the flexible substrate, wherein

[0151] The display area includes a first metal light-shielding structure 10 formed on a substrate, an active region 1021 of an LTPS thin-film transistor, a gate 1022 of an LTPS thin-film transistor, a first source / drain electrode of an LTPS thin-film transistor, a second source / drain electrode of an LTPS thin-film transistor, an active region 1031 of an IGZO thin-film transistor, a first gate 1032 of an IGZO thin-film transistor, a second gate 1033 of an IGZO thin-film transistor, a first source / drain electrode of an IGZO thin-film transistor, a second source / drain electrode of an IGZO thin-film transistor, and an insulating layer for electrically isolating the first metal light-shielding structure 10, the active region 1021 of an LTPS thin-film transistor, the gate 1022 of an LTPS thin-film transistor, the first source / drain electrode of an LTPS thin-film transistor, the second source / drain electrode of an LTPS thin-film transistor, the active region 1031 of an IGZO thin-film transistor, the first gate 1032 of an IGZO thin-film transistor, the second gate 1033 of an IGZO thin-film transistor, the first source / drain electrode of an IGZO thin-film transistor, and the second source / drain electrode of an IGZO thin-film transistor, each insulating layer extending into the bending region;

[0152] The bending region includes a portion of the barrier structure 11 formed on the substrate and a first groove and a second groove formed through each of the insulating layers. The barrier structure is patterned in the bending region. When the first source / drain electrode material layer is deposited, the first source / drain electrode material layer is deposited on the barrier structure 11. The barrier structure 11 is made of a metallic material, which is different from the material of the flexible substrate. When the source / drain electrode material is deposited, the barrier structure 11 does not generate volatile gases, thereby avoiding the formation of holes in the source / drain layer deposition chamber. After etching the first source / drain electrode material layer of the first groove and the second groove, etching the barrier structure 11 exposed by the second barrier layer will not cause gas volatilization from the flexible substrate, resulting in abnormal film quality of the first source / drain electrode material, holes in the source / drain layer deposition chamber, and various point defects and reliability problems in the display area.

[0153] Example 3

[0154] Another embodiment of the present invention provides a method for preparing a display substrate, the method comprising:

[0155] Steps S1-S8 are the same as those provided in Embodiment 1 of the present invention, and will not be repeated here.

[0156] Step S9': Form the first source / drain electrode of the IGZO thin film transistor, which is electrically connected to the active region 1031 of the IGZO thin film transistor through the first via, and form the first source / drain electrode of the LTPS thin film transistor, which is electrically connected to the active region 1021 of the LTPS thin film transistor through the second via.

[0157] In one possible implementation, step S9' includes:

[0158] Step S91: Deposit a source / drain electrode material layer, wherein the source / drain electrode material layer covers the first via, the second via, the first groove, and the second groove;

[0159] Step S92': Pattern the source and drain electrode material layer to form the first source and drain electrodes of the LTPS thin film transistor, the first source and drain electrodes of the IGZO thin film transistor, the sidewalls in the groove, and the bent area traces on the exposed second metal light-shielding structure, as shown. Figure 17 As shown.

[0160] For example, after the deposited source and drain electrode material layer covers the first via, the second via, the first groove, and the second groove, the bending region includes the blocking structure 11 formed on the substrate, the bending region traces in the first groove and the second groove formed through the insulating layers, and the sidewalls of the first groove and the second groove. The bending region features a patterned barrier structure. During the deposition of the first source / drain electrode material layer, this layer is deposited on the barrier structure, not the flexible substrate, avoiding black spots in the LTPO product. The first source / drain electrode material layer is then deposited directly on the barrier structure. During etching, both the first source / drain electrode material layer and the barrier structure in the bending region are preserved. Because the barrier structure is made of A-Si, Mo, and other low-resistivity metals, unlike the first source / drain electrode material (e.g., Ti / Al / Ti or aluminum alloy), two or more stress-neutral layers exist in the cross-section of the first and second grooves in the bending region. By retaining the bend region encapsulation layer and the second planarization layer, and controlling the MDL adhesive thickness, the bending region traces can be located in a low-stress area, preventing stress concentration and subsequent metal trace cracks. Alternatively, stress concentration layers can be placed near the barrier structure layer, allowing stress release through barrier structure layer fracture (because the barrier structure and the second source / drain electrode material layer are connected by the first planarization layer, cracks caused by stress release in the barrier structure layer will not propagate upwards).

[0161] Step S10': Form a first planarization layer 1017, covering the display area 101 and the bending area 201.

[0162] A third via is formed at the position of the first source / drain electrode of the IGZO thin film transistor on the first planarization layer 1017, and a fourth via is formed at the position of the first source / drain electrode of the LTPS thin film transistor on the first planarization layer 1017.

[0163] Specifically, a planarization layer material, such as an organic material, with a thickness of approximately 1–3 μm, is deposited to cover the aforementioned film layers. Then, using a patterning process, the layers are patterned to form a third via at the location corresponding to the first source / drain electrode of the IGZO thin-film transistor, and a fourth via at the location corresponding to the first source / drain electrode of the LTPS thin-film transistor. Figure 18 As shown. The position of the third opening corresponds to the position of the first opening, and the position of the fourth opening corresponds to the position of the second opening.

[0164] Step S11': Form the second source / drain electrode of the LTPS thin film transistor and electrically connect it to the first source / drain electrode of the LTPS thin film transistor through a fourth via; form the second source / drain electrode of the IGZO thin film transistor and electrically connect it to the first source / drain electrode of the IGZO thin film transistor through a third via.

[0165] Specifically, a source / drain electrode material layer is deposited, covering the third and fourth vias. Then, the source / drain electrode material layer is patterned to form the second source / drain electrode of the LTPS thin-film transistor, which is electrically connected to the first source / drain electrode of the LTPS thin-film transistor through the fourth via. The second source / drain electrode of the IGZO thin-film transistor is then formed, electrically connected to the first source / drain electrode of the IGZO thin-film transistor through the third via. Figure 19 As shown.

[0166] Step S12: Form a second planarization layer 1018, covering the display area 101 and the bending area 201; form an opening in the second planarization layer 1018 corresponding to the second source electrode position of the LTPS thin film transistor, such as... Figure 20 As shown.

[0167] Step S13': Forming a light-emitting element functional layer in the second planarization layer 1018, including:

[0168] Step 131: Deposit the anode metal layer of the OLED in the openings of the second planarization layer 1018 and pattern it to form the anode 1041 (the anode 1041 is connected to the second source electrode of the LTPS thin film transistor), as shown. Figure 21 As shown, for example, the anode material includes metal oxides such as ITO and IZO, or metals such as Ag, Al, and Mo, or their alloys.

[0169] Step S132: Form a pixel boundary layer around the anode using a patterning process. Specifically, deposit a pixel boundary layer material, for example, with a thickness of about 1 to 2 μm. Form a pixel boundary layer in the display area using a patterning process. For example, the material of the pixel boundary layer may include negative photoresist, polyimide, epoxy resin and other organic insulating materials.

[0170] Step S133: A light-emitting layer is formed on the anode 1041 in the opening of the pixel defining layer by means of inkjet printing or vapor deposition, wherein the material of the light-emitting layer is an organic material;

[0171] Step S134': Forming a cathode. The cathode is formed on the entire surface of an OLED display substrate, for example. The cathode material may include metals such as Mg, Ca, Li or Al or their alloys, or metal oxides such as IZO or ZTO, or organic materials with conductive properties such as PEDOT / PSS (poly(3,4-ethylenedioxythiophene / polystyrene sulfonate)).

[0172] In this configuration, the anodes corresponding to each pixel are isolated from each other, while the cathodes corresponding to each pixel are connected to each other.

[0173] An auxiliary light-emitting layer that facilitates the emission of light from the light-emitting layer can also be formed between the anode 1041 and the light-emitting layer, and between the light-emitting layer and the cathode. This auxiliary light-emitting layer may include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. For example, an organic material layer may be used as the auxiliary light-emitting layer.

[0174] Step S14: After the OLED device is formed, an encapsulation layer 1019 can be formed, such as... Figure 22 As shown.

[0175] For example, the encapsulation layer can be an inorganic encapsulation layer or an organic encapsulation layer.

[0176] For example, inorganic encapsulation layers are formed using methods such as deposition. Organic encapsulation layers are formed using inkjet printing.

[0177] For example, inorganic encapsulation layers can be formed using inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, while organic encapsulation layers can be formed using organic materials such as polyimide (PI) and epoxy resin. The combination of inorganic and organic encapsulation layers forms a composite encapsulation layer, which provides multiple layers of protection for the functional structure of the display area, resulting in better encapsulation performance.

[0178] The embodiments of the present invention do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the examples above.

[0179] It should be noted that there can be one or more thin-film transistors, and this invention does not limit this.

[0180] Example 4

[0181] Another embodiment of the present invention provides a display substrate, which can be fabricated using the fabrication method described in Embodiment 3. Figure 22 As shown, the display substrate includes:

[0182] The display area 101 and the bending area 201 are formed on the flexible substrate, wherein

[0183] The display area includes a first metal light-shielding structure 10 formed on a substrate, an active region 1021 of an LTPS thin-film transistor, a gate 1022 of an LTPS thin-film transistor, a first source / drain electrode of an LTPS thin-film transistor, a second source / drain electrode of an LTPS thin-film transistor, an active region 1031 of an IGZO thin-film transistor, a first gate 1032 of an IGZO thin-film transistor, a second gate 1033 of an IGZO thin-film transistor, a first source / drain electrode of an IGZO thin-film transistor, a second source / drain electrode of an IGZO thin-film transistor, and an insulating layer for electrically isolating the first metal light-shielding structure 10, the active region 1021 of an LTPS thin-film transistor, the gate 1022 of an LTPS thin-film transistor, the first source / drain electrode of an LTPS thin-film transistor, the second source / drain electrode of an LTPS thin-film transistor, the active region 1031 of an IGZO thin-film transistor, the first gate 1032 of an IGZO thin-film transistor, the second gate 1033 of an IGZO thin-film transistor, the first source / drain electrode of an IGZO thin-film transistor, and the second source / drain electrode of an IGZO thin-film transistor, each insulating layer extending into the bending region;

[0184] The bending region includes a barrier structure 11 formed on the substrate, a first groove and a second groove formed through the insulating layers, and bending region traces on the sidewalls of the first groove and the second groove. The display substrate has a patterned barrier structure in the bending region. When depositing the first source / drain electrode material layer, the first source / drain electrode material layer is deposited on the barrier structure instead of the flexible substrate, avoiding the generation of black spots in LTPO products. Then, the first source / drain electrode material layer is deposited directly on the barrier structure. During etching of the first source / drain electrode material layer, the first source / drain electrode material layer and the barrier structure in the bending region are retained. The first planarization layer is then coated, and the barrier structure 11 is retained. Because the barrier structure is made of A-Si and Mo and other low-resistance metals, which are different from the first source / drain electrode material layer material such as Ti / Al / Ti or aluminum alloy, there are two or more stress-neutral layers in the cross-section of the first and second grooves in the bending region. By retaining the bending region encapsulation layer and the second planarization layer and controlling the MDL coating thickness, the bending region traces can be located in a low-stress area, avoiding stress concentration that could lead to cracks in the metal traces. Alternatively, stress concentration layers can be placed near the barrier structure layer, and stress release can be achieved by the fracture of the barrier structure layer (because the material between the barrier structure and the second source / drain electrode material layer is the first planarization layer material, the cracks generated by stress release in the barrier structure layer will not propagate upwards).

[0185] The display substrate provided in the embodiments of the present invention, or the display substrate obtained by the preparation method provided in the embodiments of the present invention, can be used in a display device. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of the present invention do not limit this.

[0186] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A method for manufacturing a display panel, characterized in that, include: Forming a display panel including a display area and a bending area, wherein The display area is formed as including an active region, a gate, a first source / drain electrode of a thin-film transistor formed on a substrate, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending to the bending region. The bending region is formed as including a barrier structure formed on the substrate and a groove formed through each of the insulating layers; wherein the projection of the barrier structure on the substrate covers the projection of the groove on the substrate; The display panel comprising a display area and a bending area includes: A first metal light-shielding structure is formed at the location where the display area is to be formed on the substrate, and a second metal light-shielding structure is formed at the location where the bending area is to be formed, wherein the second metal light-shielding structure is the blocking structure; A first insulating layer is formed to cover the first metal light-shielding structure and the second metal light-shielding structure. An active region of a thin-film transistor is formed on the first insulating layer at a position corresponding to the first metal light-shielding structure. A second insulating layer is formed, covering the active region and the exposed first insulating layer; The gate of the thin-film transistor is formed on the second insulating layer at the location corresponding to the active region; A third insulating layer is formed, covering the gate and the exposed second insulating layer; A first via is formed in the display area, extending from the third insulating layer to the active area, and a groove is formed in the bending area, extending from the third insulating layer to the second metal light-shielding structure. The first source / drain electrode of the thin-film transistor is electrically connected to the active region through the first via. The first source / drain electrode forming the thin-film transistor is electrically connected to the active region through the first via, including: A source / drain electrode material layer is deposited, the source / drain electrode material layer covering the first via and the groove; Pattern the source and drain electrode material layer to form the first source and drain electrode and the sidewalls in the groove, as well as the exposed portion of the second metal light-shielding structure, with bent area traces; The blocking structure is made of a different material than the source / drain electrode material layer. The blocking structure is made of A-Si or a low-resistance metal, and the source / drain electrode material layer is made of Ti / Al / Ti or an aluminum alloy so that there are two or more stress-neutral layers on the cross-section of the groove. The bending region also includes a second planarization layer, an encapsulation layer, and MDL adhesive on the side of the source / drain electrode material layer away from the substrate so that the wiring in the bending region is located in a low-stress area.

2. The production method according to claim 1, characterized by, Also includes: A fourth insulating layer is formed to cover the display area and the bending area; A light-emitting element functional layer is formed on the fourth insulating layer of the display area, including an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer of the light-emitting element electrically connected to one of the first source and drain electrodes through a second via in the fourth insulating layer.

3. The production method according to claim 1, characterized by, Also includes: A fourth insulating layer is formed to cover the display area and the bending area; A second via is formed in the display area, penetrating from the fourth insulating layer to the third insulating layer; The second source / drain electrode of the thin-film transistor is formed and electrically connected to the first source / drain electrode through the second via. A fifth insulating layer is formed, covering the display area and the bending area; A light-emitting element functional layer is formed on the fifth insulating layer of the display area, including an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer of the light-emitting element electrically connected to one of the second source and drain electrodes through a third via in the fifth insulating layer.

4. The preparation method according to claim 1, characterized in that, The display panel comprising a display area and a bending area includes: A first metal light-shielding structure is formed at the location where the display area is to be formed on the substrate, and a second metal light-shielding structure is formed at the location where the bending area is to be formed, wherein the second metal light-shielding structure is the blocking structure; A first insulating layer is formed to cover the first metal light-shielding structure and the second metal light-shielding structure. The active region of the first thin-film transistor is formed on the first insulating layer at the position corresponding to the first metal light-shielding structure; A second insulating layer is formed to cover the active region of the first thin-film transistor and the exposed first insulating layer; The gate of the first thin-film transistor is formed on the second insulating layer at the location corresponding to the active region of the first thin-film transistor. A third insulating layer is formed, covering the gate of the first thin-film transistor and the exposed second insulating layer; An active region of a second thin-film transistor is formed on the third insulating layer, wherein the projection of the active region of the second thin-film transistor onto the substrate does not overlap with the projection of the active region of the first thin-film transistor. A fourth insulating layer is formed, covering the active region of the second thin-film transistor and the exposed third insulating layer; The gate of the second thin-film transistor is formed on the fourth insulating layer at the location corresponding to the active region of the second thin-film transistor; A fifth insulating layer is formed, covering the gate of the second thin-film transistor and the exposed fourth insulating layer; A first via is formed in the display area, extending from the fifth insulating layer to the active area of ​​the second thin-film transistor, and a first groove is formed in the bending area, extending from the fifth insulating layer to the third insulating layer. A second via is formed in the display area, extending from the fifth insulating layer to the active area of ​​the first thin-film transistor, and a second groove is formed in the bending area, extending from the third insulating layer to the second metal light-shielding structure, wherein the first groove and the second groove are aligned in the projection direction of the substrate. The first source / drain electrode of the second thin-film transistor is formed and electrically connected to the active region of the second thin-film transistor through the first via, and the first source / drain electrode of the first thin-film transistor is formed and electrically connected to the active region of the first thin-film transistor through the second via.

5. The preparation method according to claim 4, characterized in that, The first thin-film transistor is a low-temperature polycrystalline silicon thin-film transistor; The second thin-film transistor is an oxide thin-film transistor.

6. A display panel, characterized in that, The display panel includes a display area and a bending area, wherein The thin-film transistor in the display area includes an active region, a gate, a first source / drain electrode, and insulating layers for electrically isolating the active region, the gate, and the first source / drain electrode, the insulating layers extending into the bending region; The bending region includes a barrier structure formed on the substrate and a groove formed through each of the insulating layers; wherein the projection of the barrier structure on the substrate overlaps the projection of the groove on the substrate; The display panel also includes: a first metal light-shielding structure located in the display area and a second metal light-shielding structure located in the bending area. The first metal light-shielding structure and the second metal light-shielding structure are on the same layer and disposed between the substrate and each insulating layer. The second metal light-shielding structure is the blocking structure. The groove extends through the second metal light-shielding structure, and the display panel further includes: A barrier structure and a bend trace are formed on the exposed portion and the sidewall of the groove. The barrier structure and the bend trace are made of different materials. The barrier structure is made of A-Si or a low-resistance metal, and the bend trace is made of Ti / Al / Ti or an aluminum alloy to create two or more stress-neutral layers on the cross-section of the groove. The bend trace also includes a second planarization layer, an encapsulation layer, and an MDL coating on the side of the bend trace away from the substrate to place the bend trace in a low-stress region.

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