Gate driver and display device including the same

Abstract

This invention relates to a gate driver and a display device including the gate driver. The gate driver includes a first stage and a second stage. Each of the first and second stages includes an output circuit, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The output circuit outputs a scan signal, a carry signal, and an inverted carry signal based on the voltages of the first and second nodes. The first stage further includes a first input circuit that controls the voltages of the first node and the second node of the first stage based on a start pulse and a signal supplied to the second input terminal. The second stage further includes a second input circuit that controls the voltages of the first node and the second node of the second stage based on a first carry signal, a first inverted carry signal, and a signal supplied to the second input terminal. The second stage is grounded to the first stage.

Description

[0001] This application claims priority and all rights to Korean Patent Application No. 10-2020-0092561, filed on July 24, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a gate driver and a display device including the gate driver. Background Technology

[0003] Display devices typically include a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, a transmitter driver for supplying transmit control signals to transmit control lines, and pixels connected to the data lines, scan lines, and transmit control lines.

[0004] The scan driver and transmit driver may include stages that generate scan signals and transmit control signals. Each stage may include multiple transistors and capacitors and can generate an output signal in which the input signal is offset based on multiple clock signals. Summary of the Invention

[0005] In the stages of the scan driver and transmit driver of a display device, when the generation of output signals stops, for example, when the output signal (gate signal, scan signal, or transmit control signal) is output at a low level, the capacitors in the stage may be repeatedly charged / discharged by the clock signal supplied to the stage, and therefore, the current generated by the capacitors may affect the transient time and waveform of the clock signal.

[0006] Embodiments of this disclosure provide a gate driver including a first stage that outputs an inverted carry signal using a start pulse and a second stage that outputs a gate signal based on the carry signal and the inverted carry signal.

[0007] Another embodiment of this disclosure provides a display device including the gate driver.

[0008] In embodiments of this disclosure, a gate driver includes a first stage and a second stage. In this embodiment, each of the first and second stages includes an output circuit, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The output circuit outputs a scan signal, a carry signal, and an inverted carry signal based on the voltages of the first and second nodes. The scan signal and carry signal are output from the first output terminal, and the inverted carry signal is output from the second output terminal. In this embodiment, the first stage further includes a first input circuit that controls the voltages of the first node and the second node of the first stage based on a start pulse and a signal supplied to the second input terminal of the first stage. In this embodiment, the second stage further includes a second input circuit that controls the voltages of the first node and the second node of the second stage based on a first carry signal and a first inverted carry signal supplied from the output circuit of the first stage and a signal supplied to the second input terminal of the second stage. In this embodiment, the second stage is subordinately connected to the first stage.

[0009] According to an embodiment, the first input circuit may include: a first input transistor connected between a first input terminal of the first stage to which a start pulse is supplied and a first node of the first stage, and including a gate electrode connected to a second input terminal of the first stage; a second input transistor connected between a second input terminal of the first stage and a second node of the first stage, and having a gate electrode connected to the first node of the first stage; and a third input transistor connected between a first power supply and a second node of the first stage, and including a gate electrode connected to the second input terminal of the first stage.

[0010] According to an embodiment, the second input circuit may include: a first transistor connected between a first input terminal of the second stage supplied with a first carry signal and a first node of the second stage, and including a gate electrode connected to a second input terminal of the second stage; and a second transistor connected between an additional input terminal of the second stage supplied with a first inverted carry signal and a second node of the second stage, and including a gate electrode connected to a second input terminal of the second stage.

[0011] According to an embodiment, each of the first and second stages may further include: a control circuit that controls a low-level voltage of the third node based on a signal supplied to the third input terminal; and a stabilizing circuit electrically connected between the first or second input circuit and an output circuit including a fourth node, wherein the stabilizing circuit can limit the voltage drop of the first node and the voltage drop of the second node.

[0012] According to an embodiment, the output circuit may include: a fourth transistor connected between a first power supply and a first output terminal, and including a gate electrode connected to a third node; a fifth transistor connected between a second power supply and the first output terminal, and including a gate electrode connected to a fourth node; a sixth transistor connected between the fourth node and the fifth node, and including a gate electrode connected to a third input terminal; a seventh transistor connected between the fifth node and the third input terminal, and including a gate electrode connected to a sixth node; an eighth transistor connected between the second power supply and the fourth node, and including a gate electrode connected to a first node; a first capacitor connected between the fifth node and the sixth node; and a second capacitor connected between the second power supply and the fourth node.

[0013] According to an embodiment, the second output terminal can be connected to the fifth node.

[0014] According to an embodiment, the second output terminal can be connected to the fourth node.

[0015] According to an embodiment, the stabilizing circuit may include: a tenth transistor connected between a first node and a third node, and including a gate electrode that receives a voltage from a first power supply; and an eleventh transistor connected between a second node and a sixth node, and including a gate electrode that receives a voltage from the first power supply.

[0016] According to an embodiment, the control circuit may include: a ninth transistor, including a first electrode connected to a third input terminal and a gate electrode connected to a third node; and a third capacitor connected between a second electrode of the ninth transistor and the gate electrode of the ninth transistor.

[0017] According to an embodiment, each of the first and second stages may further include: an initialization circuit that supplies the voltage of the second power source to the first node during an initialization period.

[0018] According to an embodiment, the second-stage initialization circuit may include: a twelfth transistor connected between the second power supply and the first node, and including a gate electrode for receiving a reset signal.

[0019] According to an embodiment, the second-stage initialization circuit may further include: a thirteenth transistor connected between the fourth node and the fourth input terminal supplied with a reset signal, and including a gate electrode connected to the fourth input terminal or the first power supply.

[0020] According to an embodiment, the initialization circuit of the first stage may include: a twelfth transistor connected between the second power supply and the first node, and including a gate electrode for receiving a reset signal.

[0021] According to an embodiment, the initialization circuit of the first stage may further include: a thirteenth transistor connected between the twelfth transistor and the second power supply, and including a gate electrode connected to the third input terminal.

[0022] According to an embodiment, the second-stage initialization circuit may include: a twelfth transistor and a thirteenth transistor connected in series between the second power supply and the first node, and a fourteenth transistor and a fifteenth transistor connected in series between the first power supply and the fourth node. In this embodiment, the gate electrode of the twelfth transistor may be connected to one of the second input terminal and the third input terminal, and the gate electrode of the thirteenth transistor may be connected to the other of the second input terminal and the third input terminal. In this embodiment, the gate electrode of the fourteenth transistor may be connected to one of the second input terminal and the third input terminal, and the gate electrode of the fifteenth transistor may be connected to the other of the second input terminal and the third input terminal.

[0023] According to the embodiment, the first stage and the second stage can simultaneously output a scan signal with a high level during the initialization period. The second input terminal of the first stage and the third input terminal of the second stage can receive a first clock signal, and the third input terminal of the first stage and the second input terminal of the second stage can receive a second clock signal.

[0024] According to an embodiment, the control circuit may further include: a sixteenth transistor connected between the second power supply and the second electrode of the ninth transistor, and including a gate electrode connected to the second node.

[0025] According to an embodiment, the control circuit may further include: a sixteenth transistor and a seventeenth transistor connected in series between the first input terminal and the gate electrode of the ninth transistor, and an eighteenth transistor connected between the gate electrode of the ninth transistor and the third node, and including a gate electrode connected to the gate electrode of the ninth transistor.

[0026] According to an embodiment, the control circuit may further include: a nineteenth transistor connected between the second power supply and the second electrode of the ninth transistor, and including a gate electrode connected to the second node.

[0027] In embodiments of this disclosure, a display device includes: a pixel; a gate driver including a first stage and a second stage; and a data driver that supplies data signals to the pixel via data lines. In this embodiment, each of the first and second stages includes an output circuit, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The output circuit outputs a scan signal, a carry signal, and an inverted carry signal based on the voltages of the first and second nodes. The scan signal and carry signal are output from the first output terminal, and the inverted carry signal is output from the second output terminal. In this embodiment, the first stage further includes: a first input circuit that controls the voltages of the first node and the second node of the first stage based on a start pulse and a signal supplied to the second input terminal of the first stage. In this embodiment, the second stage further includes: a second input circuit that controls the voltages of the first node and the second node of the second stage based on a first carry signal and a first inverted carry signal supplied from the output circuit of the first stage and a signal supplied to the second input terminal of the second stage. In this embodiment, the second stage can be connected to the first stage from ground.

[0028] Embodiments of a gate driver and a display device including the gate driver may include a first stage that outputs a carry signal and an inverted carry signal based on a start pulse, and a second stage that outputs a scan signal (and / or a transmit control signal) based on the carry signal and the inverted carry signal. In these embodiments, the remaining stages, which are subordinately connected to the second stage and sequentially output the scan signal (and / or the transmit control signal), may have the same structure as the second stage.

[0029] Therefore, in these embodiments, when the corresponding output signal (carry signal and scan signal) of each of the second to nth (where n is an integer greater than 2) levels is low, the voltage of the second node can be stably maintained at a high level.

[0030] Therefore, undesirable charging / discharging operations of the first capacitor can be effectively prevented during periods when the output signal is output at a low level, and thus, power consumption for canceling the charging / discharging operation can be reduced. In these embodiments, changes in equivalent impedance due to the charging / discharging of the capacitor can be prevented or minimized. Therefore, the rise / fall rates of the first clock signal, the second clock signal, and the output signal can be improved, and voltage ripple can be reduced.

[0031] Therefore, in these embodiments, the gate driver (scan driver and / or emit driver) can be stably applied to high-speed driving and can improve the image quality of the display device. Attached Figure Description

[0032] The above and other features of this disclosure will become more apparent from the further detailed description of embodiments thereof with reference to the accompanying drawings, wherein:

[0033] Figure 1 This is a block diagram illustrating a display device according to an embodiment;

[0034] Figure 2A This is a block diagram illustrating a scan driver (gate driver) according to an embodiment of the present disclosure;

[0035] Figure 2B It is a diagram. Figure 2A A block diagram of an embodiment of the scan driver;

[0036] Figure 3 It is a diagram. Figure 2A Circuit diagram of an embodiment of the first and second stages included in the scan driver;

[0037] Figure 4 The diagram is for driving. Figure 3 The signal timing diagram of an embodiment of the first-stage signal;

[0038] Figure 5 The diagram is for driving. Figure 3 The signal timing diagram of an embodiment of the second-level signal;

[0039] Figure 6 The diagram illustrates the driving process during the initialization phase. Figure 2A A signal timing diagram of an embodiment of the scan driver signals;

[0040] Figure 7 The diagram illustrates the driving process during the initialization phase. Figure 2A Signal timing diagrams of alternative embodiments of the scan driver signals;

[0041] Figure 8 It is a diagram. Figure 3 Circuit diagram of an alternative embodiment of the second level;

[0042] Figure 9 It is a diagram. Figure 3 A circuit diagram of another alternative embodiment of the second stage;

[0043] Figure 10 It is a diagram. Figure 3 A circuit diagram of another alternative embodiment of the second stage;

[0044] Figure 11 It is a diagram. Figure 3 Circuit diagram of an alternative embodiment of the first level;

[0045] Figure 12 It is a diagram. Figure 2ACircuit diagrams of alternative embodiments of the first and second stages included in the scan driver;

[0046] Figure 13 The diagram is for driving. Figure 12 The signal timing diagram of an embodiment of the second-level signal;

[0047] Figure 14 It is a diagram. Figure 12 Circuit diagram of an alternative embodiment of the second level;

[0048] Figure 15 It is a diagram. Figure 12 A circuit diagram of another alternative embodiment of the second stage;

[0049] Figure 16 It is a diagram. Figure 12 Circuit diagram of an alternative embodiment of the first level;

[0050] Figure 17 It is a diagram. Figure 2A A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver;

[0051] Figure 18 The diagram is for driving. Figure 17 The signal timing diagram of an embodiment of the second-level signal;

[0052] Figure 19 It is a diagram. Figure 17 Circuit diagram of an alternative embodiment of the second level;

[0053] Figure 20 It is a diagram. Figure 17 Circuit diagram of an alternative embodiment of the first level;

[0054] Figure 21 It is a diagram. Figure 2A A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver;

[0055] Figure 22 The diagram is for driving. Figure 21 The signal timing diagram of an embodiment of the second-level signal;

[0056] Figure 23 It is a diagram. Figure 21 Circuit diagram of an alternative embodiment of the second level;

[0057] Figure 24 It is a diagram. Figure 21 Circuit diagram of an alternative embodiment of the first level;

[0058] Figure 25 This is a block diagram illustrating a scan driver according to an alternative embodiment of the present disclosure;

[0059] Figure 26 It is a diagram. Figure 25 Circuit diagram of an embodiment of the first and second stages included in the scan driver;

[0060] Figure 27 The diagram illustrates the driving process during the initialization phase. Figure 25 A signal timing diagram of an embodiment of the scan driver signals;

[0061] Figure 28A and Figure 28B It is a diagram. Figure 26 Circuit diagram of an alternative embodiment of the first level;

[0062] Figure 29 It is a diagram. Figure 26 Circuit diagram of an alternative embodiment of the second level;

[0063] Figure 30 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver;

[0064] Figure 31 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver; and

[0065] Figure 32 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver. Detailed Implementation

[0066] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the text, the same reference numerals denote the same elements.

[0067] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be intermediate elements between them. Conversely, when an element is referred to as being "directly" on another element, there are no intermediate elements.

[0068] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of this document.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated feature, region, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0070] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, relative terms are intended to include different orientations of the device. For example, if a device in one of the figures is flipped, an element described as being “down” to the other element will subsequently be oriented “up” to the other element. Thus, the term “down” may include both “down” and “up” orientations depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “under” the other element will subsequently be oriented “above” the other element. Thus, the term “below” or “under” may include both “up” and “down” orientations.

[0071] Given the measurements discussed and the errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), the terms "approximately" or "about" as used herein include the values ​​and mean within an acceptable range of deviation from the specific values ​​as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations or within ±30%, 20%, 10%, or 5% of the stated value.

[0072] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly stated herein.

[0073] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same parts, and any repeated descriptions of the same parts will be omitted or simplified.

[0074] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0075] Reference Figure 1 An embodiment of the display device 1000 may include a pixel unit 100, a scan driver 200 (or a first gate driver), an emission driver 300 (or a second gate driver), a data driver 400, and a timing controller 500.

[0076] In an embodiment, the scan driver 200 and the transmit driver 300 may be partially defined by a single gate driver. Hereinafter, for ease of description, embodiments in which the scan driver 200 and the transmit driver 300 are jointly defined (or collectively referred to as) a gate driver will be described in detail.

[0077] The display device 1000 can display images at various drive frequencies (image refresh rate or screen refresh rate) depending on the driving conditions. The drive frequency is the frequency at which data signals are essentially written to the driving transistors of the pixels PX. The drive frequency is also referred to, for example, as the screen scan rate or screen refresh rate, and represents the frequency at which the display screen refreshes per second. The display device 1000 can display images according to various drive frequencies.

[0078] Pixel unit 100 displays an image. Pixel unit 100 may include pixels PX connected to data lines DL1 to DLm, scan lines SL1 to SLn, and transmit control lines EL1 to ELn. Pixel PX can receive voltages from a first driving power supply VDD, a second driving power supply VSS, and an initialization power supply from the outside.

[0079] In this embodiment, pixel PX can be connected to at least one scan line SLi, at least one data line DLj, and at least one emission control line ELi, depending on the pixel circuit structure. Pixel PX may include a driving transistor, a plurality of switching transistors implemented by at least one of n-type transistors and p-type transistors, and a light-emitting element.

[0080] The timing controller 500 can receive input control signals and input image signals from an image source such as an external graphics device. Based on the input image signals, the timing controller 500 generates image data RGB suitable for the operating conditions of the pixel unit 100 and provides the image data RGB to the data driver 400. The timing controller 500 can generate a first control signal SCS for controlling the drive timing of the scan driver 200, a second control signal ECS for controlling the drive timing of the transmit driver 300, and a third control signal DCS for controlling the drive timing of the data driver 400, based on the input control signals, and can provide the first control signal SCS, the second control signal ECS, and the third control signal DCS to the scan driver 200, the transmit driver 300, and the data driver 400, respectively.

[0081] The scan driver 200 can receive a first control signal SCS from the timing controller 500. The scan driver 200 can supply scan signals to scan lines SL1 to SLn in response to the first control signal SCS. The first control signal SCS may include a start pulse for the scan signals and multiple clock signals.

[0082] The transmit driver 300 can receive a second control signal ECS from the timing controller 500. The transmit driver 300 can supply transmit control signals to transmit control lines EL1 to ELn in response to the second control signal ECS. The second control signal ECS may include a start pulse for the transmit control signal and multiple clock signals.

[0083] The data driver 400 can receive a third control signal DCS from the timing controller 500. In response to the third control signal DCS, the data driver 400 can convert the image data RGB into an analog data signal (data voltage) and supply the data signal to the data lines DL1 to DLm.

[0084] In an embodiment, such as Figure 1 As shown, each of the scan driver 200 and the transmit driver 300 may be a single configuration, but this disclosure is not limited thereto. Alternatively, the scan driver 200 may include a plurality of scan drivers that respectively supply at least one of scan signals of different waveforms. In embodiments, at least a portion of the scan driver 200 and the transmit driver 300 may be integrated into a single drive circuit or module, etc.

[0085] In an embodiment, the display device 1000 may further include a power supply. The power supply can supply the voltage of a first driving power supply VDD and a second driving power supply VSS used to drive the pixel PX to the pixel unit 100.

[0086] Figure 2AThis is a block diagram illustrating a scan driver (gate driver) according to an embodiment of the present disclosure.

[0087] exist Figure 2A For ease of illustration and description, four stages and the scan signals output from them are shown.

[0088] exist Figure 2A The diagram shows a scan driver 200 for a gate driver, but the emit driver 300 for a gate driver can have the same characteristics as... Figure 2A The structure of the scan driver 200 shown is basically the same.

[0089] Reference Figure 2A An embodiment of the scan driver 200 may include multiple stages ST1 to ST4. Stages ST1 to ST4 may be connected to corresponding scan lines SL1 to SL4 respectively, and may output scan signals based on clock signals CLK1 and CLK2.

[0090] The first stage ST1 and the second stage ST2 can have different circuit configurations. The second stage ST2 can be connected from ground to the first stage ST1. The third stage ST3 can be connected from ground to the second stage ST2, and the fourth stage ST4 can be connected from ground to the third stage ST3. In this embodiment, the first stage ST1 to the fourth stage ST4 can be cascaded to each other. The second stage ST2 to the fourth stage ST4 can have substantially the same configuration.

[0091] In this embodiment, the structure of the scan driver 200 can also be applied to the reference. Figure 1 The transmit driver 300 is described above. In this embodiment, scan lines SL1 to SL4 can be replaced by transmit control lines.

[0092] Each of stages ST1 to ST4 may include first input terminals 101 and 201, second input terminals 102 and 202, third input terminals 103 and 203, fourth input terminals 104 and 204, first output terminals 105 and 205, and second output terminals 106 and 206. In an embodiment, the second stages ST2 to the fourth stages ST4 may further include a fifth input terminal 208 (or an additional input terminal).

[0093] The first input terminal 101 of the first stage ST1 can receive the start pulse SSP. The first input terminals 201 of the second stage ST2 to the fourth stage ST4 can receive the carry signals CR1 to CR3 of the previous stage.

[0094] The second input terminal 102 of the first stage ST1 can receive the first clock signal CLK1, and the third input terminal 103 can receive the second clock signal CLK2.

[0095] In one embodiment, the second input terminal 202 of the 2kth stage (where k is an integer greater than 1) can receive the second clock signal CLK2, and the third input terminal 203 can receive the first clock signal CLK1. In another embodiment, the second input terminal 202 of the 2k+1th stage can receive the first clock signal CLK1, and the third input terminal 203 of the 2k+1th stage can receive the second clock signal CLK2.

[0096] During normal driving of the image display, the first clock signal CLK1 and the second clock signal CLK2 have the same period and non-overlapping phases. In one embodiment, for example, the second clock signal CLK2 can be set to a signal offset from the first clock signal CLK1 by approximately half a period.

[0097] The fourth input terminal 104 can receive a reset signal RST. The reset signal RST can be a global signal or a common signal, and can be supplied to all levels ST1 to ST4.

[0098] Output signals OUT1 to OUT4 and carry signals CR1 to CR4 can be output to the first output terminals 105 and 205. Output signals OUT1 to OUT4 and carry signals CR1 to CR4 can be substantially the same as each other. In an embodiment, output signals OUT1 to OUT4 can be provided as scan signals to the first scan lines SL1 to the fourth scan lines SL4.

[0099] In one embodiment, the first carry signal CR1 generated in the first stage ST1 can be supplied to the first input terminal 201 of the second stage ST2. In this embodiment, the second carry signal CR2 generated in the second stage ST2 can be supplied to the first input terminal 201 of the third stage ST3.

[0100] Inverted carry signals CRB1 to CRB4 can be output to the second output terminals 106 and 206. The inverted carry signals CRB1 to CRB4 can each have a waveform different from the carry signals CR1 to CR4. In one embodiment, the first inverted carry signal CRB1 can be supplied to the fifth input terminal 208 of the second stage ST2. In this embodiment, the second inverted carry signal CRB2 can be supplied to the fifth input terminal 208 of the third stage ST3.

[0101] In the embodiment, stages ST1 to ST4 receive a first power supply ( Figure 3 The voltage of VGL) and the second power supply ( Figure 3 The voltage of the first power supply (VGH). The voltage of the first power supply and the voltage of the second power supply can have a DC voltage level. The voltage of the second power supply can be set to be greater than the voltage of the first power supply.

[0102] In this embodiment, the first stage ST1 can be the initial stage that receives the start pulse SSP, and the second stage ST2 can be any stage other than the first stage ST1.

[0103] Figure 2B It is a diagram. Figure 2A A block diagram of an embodiment of the scan driver.

[0104] exist Figure 2B In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 2A The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. In embodiments, except for the configuration in which the first stage ST1 is not connected to the scan line, Figure 2B The 200A scan driver can have the same features as... Figure 2A The configuration of the scan driver 200 is basically the same or similar.

[0105] Reference Figure 2B The scan driver 200A may include multiple levels ST1 to ST4.

[0106] The first stage ST1 and the second stage ST2 can have different circuit configurations. The second stage ST2 through the fourth stage ST4 can have substantially the same circuit configuration.

[0107] The first output terminal 105 of the first stage ST1 can be electrically connected to the first input terminal 201 of the second stage ST2. The first stage ST1 may not output a gate signal (e.g., a scan signal), and the second stage ST2 may be connected to the first scan line SL1 and may output a first scan signal (or output signal OUT1). In this embodiment, the first stage ST1 may only perform the function of generating a first carry signal CR1 and a first inverted carry signal CRB1 supplied to the second stage ST2 based on a start pulse.

[0108] In this embodiment, the scan signal can be output from a stage with the same structure, and the waveform of the scan signal supplied to the scan line can be consistent.

[0109] Figure 3 It is a diagram. Figure 2A Circuit diagrams of embodiments of the first and second stages included in the scan driver.

[0110] Reference Figure 2A and Figure 3 The embodiments of the first stage ST1 and the second stage ST2 may respectively include input circuits 11 and 21, output circuits 12 and 22, control circuits 14 and 24, stabilization circuits 15 and 25, and initialization circuits 16 and 26.

[0111] In this embodiment, the k-th level (where k is an integer greater than 2) can have the same configuration as the second level ST2, and any repeated detailed descriptions of it will be omitted.

[0112] The first clock signal CLK1 can be supplied to the second input terminal 102 of the first stage ST1, and the second clock signal CLK2 can be supplied to the second input terminal 202 of the second stage ST2.

[0113] First, the first stage ST1 will be described in detail. The first stage ST1 may include a first input circuit 11, a first output circuit 12, a first control circuit 14, a first stabilization circuit 15, and a first initialization circuit 16.

[0114] The first input circuit 11 can control the voltage of the first node NN1 and the voltage of the second node NN2 based on the start pulse SSP supplied to the first input terminal 101 and the first clock signal CLK1 supplied to the second input terminal 102. The first input circuit 11 may include a first transistor T1 (or a first input transistor), a second transistor T2 (or a second input transistor), and a third transistor T3 (or a third input transistor).

[0115] A first transistor T1 may be connected between a first input terminal 101 and a first node NN1. The first transistor T1 may include a gate electrode connected to a second input terminal 102. When the first clock signal CLK1 has a gate on level (e.g., low level), the first transistor T1 may be turned on to electrically connect the first input terminal 101 and the first node NN1 to each other.

[0116] The second transistor T2 can be connected between the second input terminal 102 and the second node NN2. The second transistor T2 may include a gate electrode connected to the first node NN1. The second transistor T2 can be turned on or off based on the voltage of the first node NN1.

[0117] In one embodiment, the second transistor T2 may include a plurality of sub-transistors connected in series with each other. Each of the sub-transistors may include a gate electrode commonly connected to the first node NN1 (e.g., a transistor having sub-transistors will be referred to as a transistor with a dual-gate structure). Therefore, in this embodiment, current leakage due to the second transistor T2 can be minimized. However, this is merely exemplary, and at least one of the remaining transistors, as well as the second transistor T2, may have a dual-gate structure.

[0118] The third transistor T3 can be connected between the first power supply VGL and the second node NN2. The gate electrode of the third transistor T3 can be connected to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the third transistor T3 can be turned on to supply the voltage of the first power supply VGL to the second node NN2.

[0119] The first output circuit 12 can output a first output signal OUT1, a first carry signal CR1, and a first inverted carry signal CRB1 based on the voltage of the first node NN1 and the voltage of the second node NN2. The voltage of the first power supply VGL can correspond to the low level of the output signals OUT1 and OUT2, and the voltage of the second power supply VGH can correspond to the high level of the output signals OUT1 and OUT2. The output signals OUT1 and OUT2 can serve as a display device (e.g., Figure 1 The output of the transmission control signal or scanning signal in the display device 1000.

[0120] In an embodiment, the first output circuit 12 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The first output circuit 12 may further include a first capacitor C1 and a second capacitor C2.

[0121] A fourth transistor T4 can be connected between the first power supply VGL and the first output terminal 105. The gate electrode of the fourth transistor T4 can be connected to the third node NN3. The fourth transistor T4 can be turned on or off in response to the voltage of the third node NN3 electrically connected to the first node NN1. When the fourth transistor T4 is turned on, the first output signal OUT1 and the first carry signal CR1 supplied to the first output terminal 105 can have a low level (e.g., the gate turn-off voltage of an n-type transistor).

[0122] The fifth transistor T5 can be connected between the second power supply VGH and the first output terminal 105. The gate electrode of the fifth transistor T5 can be connected to the fourth node NN4. The fifth transistor T5 can be turned on or off in response to the voltage of the fourth node NN4 electrically connected to the sixth node NN6. Here, when the fifth transistor T5 is turned on, the first output signal OUT1 supplied to the first output terminal 105 can have a high level (e.g., the gate on-state voltage of an n-type transistor).

[0123] The first capacitor C1 can be connected between the fifth node NN5 and the sixth node NN6.

[0124] The sixth transistor T6 can be connected between the fifth node NN5 and the fourth node NN4. The gate electrode of the sixth transistor T6 can be connected to the third input terminal 103. The sixth transistor T6 can be turned on in response to the gate conduction level (e.g., low level) of the second clock signal CLK2 supplied to the third input terminal 103.

[0125] The seventh transistor T7 can be connected between the fifth node NN5 and the third input terminal 103. The gate electrode of the seventh transistor T7 can be connected to the sixth node NN6. The seventh transistor T7 can be turned on or off in response to the voltage of the sixth node NN6.

[0126] The eighth transistor T8 can be connected between the second power supply VGH and the fourth node NN4. The gate electrode of the eighth transistor T8 can be connected to the first node NN1. The eighth transistor T8 can be turned on or off in response to the voltage of the first node NN1.

[0127] The second capacitor C2 can be connected between the second power supply VGH and the fourth node NN4. The second capacitor C2 can be charged with the voltage applied to the fourth node NN4 and stably maintain the voltage of the fourth node NN4.

[0128] The sixth transistor T6 through the eighth transistor T8, the first capacitor C1, and the second capacitor C2 can control the voltage of the fourth node NN4. The eighth transistor T8 can supply the voltage of the second power supply VGH to the fourth node NN4 based on the voltage of the first node NN1. The sixth transistor T6 and the seventh transistor T7 can transmit the voltage supplied to the second node NN2 through the fifth node NN5 to the fourth node NN4 based on the second clock signal CLK2 supplied to the third input terminal 103.

[0129] When the voltage of the second node NN2 is high, for example, the voltage of the fourth node NN4 can stably have a gate turn-off level (or a high level), and therefore, the fifth transistor T5 can be completely turned off.

[0130] In this embodiment, the second output terminal 106 can be connected to the fifth node NN5. Therefore, the voltage of the fifth node NN5 can be supplied to the second stage ST2 as the first inverted carry signal CRB1.

[0131] The first control circuit 14 can control the low-level voltage of the third node NN3 based on the signal supplied to the third input terminal 103. In an embodiment, the first control circuit 14 may include a ninth transistor T9 and a third capacitor C3.

[0132] The ninth transistor T9 may include a first electrode connected to the third input terminal 103 and a gate electrode connected to the third node NN3.

[0133] The third capacitor C3 can be connected between the second electrode and the gate electrode of the ninth transistor T9.

[0134] When the voltage of the third node NN3 is low (that is, when the first output signal OUT1 is low), the first control circuit 14 can periodically reduce the voltage of the third node NN3 by using the coupling of the third capacitor C3 according to the change of the second clock signal CLK2.

[0135] The first stabilizing circuit 15 can be electrically connected between the first input circuit 11 and the first output circuit 12. The first stabilizing circuit 15 can limit the voltage drop at the first node NN1 and the voltage drop at the second node NN2.

[0136] In the embodiment, when the voltage drop of the third node NN3 is large (see...), Figure 4 (2L), the first stabilizing circuit 15 can be used as a resistor. Therefore, even if the voltage change of the third node NN3 is large, it can effectively prevent the amplitude of the drain-source voltage of the first transistor T1 from suddenly increasing, and can protect the first transistor T1 connected to the first node NN1.

[0137] In this embodiment, when the voltage of the sixth node NN6 drops significantly due to the coupling of the first capacitor C1, the first stabilizing circuit 15 can be used as a resistor. Therefore, the second transistor T2 and the third transistor T3 connected to the second node NN2 can be protected.

[0138] In an embodiment, the first stabilizing circuit 15 may include a tenth transistor T10 and an eleventh transistor T11.

[0139] The tenth transistor T10 can be connected between the first node NN1 and the third node NN3. The gate electrode of the tenth transistor T10 can be connected to the first power supply VGL. Therefore, the tenth transistor T10 can be in the on state. Thus, because the voltage of the first node NN1 is not lower than the voltage of the first power supply VGL, the bias stress that can be applied to the first transistor T1 can be reduced. In one embodiment, for example, the voltage of the first node NN1 can be equal to or greater than the sum of the absolute value of the voltage of the first power supply VGL and the threshold voltage of the tenth transistor T10.

[0140] The eleventh transistor T11 can be connected between the second node NN2 and the sixth node NN6. The gate electrode of the eleventh transistor T11 can be connected to the first power supply VGL. Therefore, the eleventh transistor T11 can be in the on state. Therefore, because the voltage of the second node NN2 is not lower than the voltage of the first power supply VGL, the bias stress that can be applied to the second transistor T2 and the third transistor T3 can be reduced. Therefore, the second transistor T2 and the third transistor T3 can be protected from voltage fluctuations at the sixth node NN6. In one embodiment, for example, the voltage of the second node NN2 can be equal to or greater than the sum of the absolute value of the voltage of the first power supply VGL and the threshold voltage of the eleventh transistor T11.

[0141] The first initialization circuit 16 can supply the voltage of the second power supply VGH to the first node NN1 during the initialization period. In an embodiment, the first initialization circuit 16 may include a twelfth transistor T12.

[0142] The twelfth transistor T12 can be connected between the second power supply VGH and the first node NN1. The gate electrode of the twelfth transistor T12 can be connected to the fourth input terminal 104 that receives the reset signal RST. When the twelfth transistor T12 is turned on, the voltage of the first node NN1 can be initialized to the voltage of the second power supply VGH.

[0143] The configuration of the second level ST2 will be described in detail below.

[0144] The second stage ST2 may include a second input circuit 21, a second output circuit 22, a second control circuit 24, a second stabilization circuit 25, and a second initialization circuit 26.

[0145] The second input circuit 21 can control the voltage of the first node N1 and the voltage of the second node N2 based on the first carry signal CR1 and the first inverted carry signal CRB1 supplied from the first output circuit 12 of the first stage ST1 and the second clock signal CLK2 supplied to the second input terminal 202. The second input circuit 21 may include a first transistor M1 and a second transistor M2.

[0146] The first transistor M1 can be connected between the first input terminal 201 and the first node N1. The gate electrode of the first transistor M1 can be connected to the second input terminal 202. The function of the first transistor M1 can be substantially the same as that of the first transistor T1 in the first input circuit 11.

[0147] The second transistor M2 can be connected between the fifth input terminal 208 and the second node N2. The gate electrode of the second transistor M2 can be connected to the second input terminal 202. That is, unlike the second node NN2 of the first stage ST1, the voltage of the second node N2 can correspond to the first inverted carry signal CRB1.

[0148] The second output circuit 22 can output a second output signal OUT2, a second carry signal CR2, and a second inverted carry signal CRB2 based on the voltage of the first node N1 and the voltage of the second node N2.

[0149] In this embodiment, the second output terminal 206 can be connected to the fifth node N5. Therefore, the voltage of the fifth node N5 can be supplied to the third stage ST3 as the second inverted carry signal CRB2.

[0150] Because the configuration and function of the second output circuit 22 are substantially the same as those of the first output circuit 12, any repeated detailed descriptions thereof will be omitted. In an embodiment, the second output circuit 22 may include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second output circuit 22 may further include a first capacitor C1 and a second capacitor C2.

[0151] The second control circuit 24 can control the low-level voltage of the third node N3 based on the first clock signal CLK1 supplied to the third input terminal 203. In an embodiment, the second control circuit 24 may include a ninth transistor M9 and a third capacitor C3. Because the configuration and function of the second control circuit 24 are substantially the same as those of the first control circuit 14, any repeated detailed description thereof will be omitted.

[0152] The second stabilizing circuit 25 can be electrically connected between the second input circuit 21 and the second output circuit 22. The second stabilizing circuit 25 can limit the voltage drop at the first node N1 and the voltage drop at the second node N2.

[0153] Because the configuration and function of the second stabilizing circuit 25 are substantially the same as those of the first stabilizing circuit 15, any repeated detailed descriptions thereof will be omitted. In an embodiment, the second stabilizing circuit 25 may include a tenth transistor M10 and an eleventh transistor M11.

[0154] The following text will refer to Figure 4 and Figure 5 Describe in detail the operation and function of ST1 and ST2.

[0155] Figure 4 The diagram is for driving. Figure 3 The signal timing diagram of an embodiment of the first-level signal.

[0156] Reference Figure 1 , Figure 3 and Figure 4 The first clock signal CLK1 and the second clock signal CLK2 are supplied with different timings from each other. In one embodiment, for example, the second clock signal CLK2 is configured to be a signal delayed or offset by half a cycle (e.g., a horizontal time period) from the first clock signal CLK1.

[0157] The high level H (or high voltage) of the start pulse SSP can correspond to the voltage of the second power supply VGH, and the low level L (or low voltage) of the start pulse SSP can correspond to the voltage of the first power supply VGL. In one embodiment, for example, the voltage of the first power supply VGL can be approximately -8 volts (V), and the voltage of the second power supply VGH can be approximately 10V. However, this is merely exemplary, and the voltage levels of the start pulse are not limited thereto. In this embodiment, for example, the voltages of the first power supply VGL and the second power supply VGH can be set according to the type of transistor and the operating environment of the display device, etc.

[0158] In an embodiment, the low level L of the third node NN3 can be similar to a value obtained by adding the absolute value of the threshold voltage of the tenth transistor T10 to the voltage of the first power supply VGL. However, since the threshold voltage of the tenth transistor T10 is very small compared to the voltage of the first power supply VGL, it is assumed that the low level L of the third node NN3, the voltage of the first power supply VGL, the low level L of the start pulse SSP, and the low level L of the gate signal are substantially the same or similar to each other.

[0159] In addition, 2-low level 2L can be a voltage level similar to twice the voltage of the first power supply VGL, that is, 2×VGL.

[0160] In an embodiment, the start pulse SSP may have a waveform for the output of a transmit control signal or a waveform for the output of a scan signal. That is, during a frame period, the start pulse SSP and the first output signal OUT1 may overlap with multiple gate-on periods and the gate-off periods of clock signals CLK1 and CLK2.

[0161] In this embodiment, when clock signals CLK1 and CLK2 are supplied, the voltage of the first power supply VGL (the voltage of the low level L or the gate turn-on voltage) is supplied to each of the second input terminal 102 and the third input terminal 103, and when clock signals CLK1 and CLK2 are not supplied, the voltage of the second power supply VGH (the voltage of the high level H or the gate turn-off voltage) is supplied to each of the second input terminal 102 and the third input terminal 103.

[0162] At the first time point t1, the second time point t2, and the third time point t3, the initial pulse SSP has a high level H. At the fourth time point t4, the fifth time point t5, and the sixth time point t6, the initial pulse SSP has a low level L.

[0163] The first clock signal CLK1 can be supplied to the second input terminal 102 at a first time point t1. The first transistor T1 and the third transistor T3 can be turned on in response to the first clock signal CLK1.

[0164] When the first transistor T1 is turned on, the high level H of the start pulse SSP can be supplied to the first node NN1. Therefore, the voltage of the first node NN1 and the voltage of the third node NN3 can be changed to a high level H. Therefore, the eighth transistor T8 and the ninth transistor T9 can be turned off by the high level H of the third node NN3.

[0165] When the third transistor T3 is turned on, the voltage of the first power supply VGL can be supplied to the second node NN2 and can be supplied to the sixth node NN6 through the eleventh transistor T11. At the first time point t1, the seventh transistor T7 can be turned on by the low level (e.g., L) voltage of the sixth node NN6, and the high level H of the second clock signal CLK2 can be supplied to one terminal of the first capacitor C1 (that is, the fifth node NN5).

[0166] At this time, because the sixth transistor T6 is in the off state, the voltage of the fourth node NN4 can maintain the voltage of the second power supply VGH (that is, the high level H).

[0167] At the second time point t2, the second clock signal CLK2 can be supplied to the third input terminal 103. The sixth transistor T6 can be turned on in response to the second clock signal CLK2. Because the voltage of the fifth node NN5 can be reduced by the second clock signal CLK2 at the second time point t2, the voltage of the sixth node NN6 can be reduced to a low level 2L through the coupling of the first capacitor C1, and a current path can be formed through the seventh transistor T7 and the sixth transistor T6. Therefore, the voltage of the fourth node NN4 can be reduced, and the fifth transistor T5 can be turned on by the voltage of the fourth node NN4.

[0168] When the fifth transistor T5 is turned on, the voltage of the second power supply VGH can be supplied to the first output terminal 105. Therefore, the first output signal OUT1 and the first carry signal CR1 can be output at a high level H.

[0169] In this embodiment, because the voltage of the fifth node NN5 is reduced by the second clock signal CLK2, a low-level L voltage can be supplied to the second output terminal 106. Therefore, the first inverted carry signal CRB1 can be output at a low level L at the second time point t2.

[0170] Subsequently, when the supply of the second clock signal CLK2 is stopped, the voltage of the fifth node NN5 can be changed to a high level by the seventh transistor T7, which is then turned on due to the voltage of the sixth node NN6. Therefore, the first inverted carry signal CRB1 can be output at a high level H. Figure 4 In this process, the waveform of the first inverted carry signal CRB1 can be basically the same as the voltage change of the fifth node NN5.

[0171] In this embodiment, when the second clock signal CLK2 is supplied to the third input terminal 103 again at the third time point t3, the sixth transistor T6 can be turned on. The voltage of the fifth node NN5 can be reduced again by the current path between the seventh transistor T7 and the sixth transistor T6, and a low-level L voltage can be supplied to the second output terminal 106. Therefore, the first inverted carry signal CRB1 can be output at a low level L again at the third time point t3.

[0172] As described above, during the period when the start pulse SSP is supplied at a high level H, the first inverted carry signal CRB1 can be synchronized with the waveform of the second clock signal CLK2, repeating high level H and low level L, and can be output. Furthermore, the first stage ST1 can output a first output signal OUT1 and a first carry signal CR1 at a high level H according to the supply of the start pulse SSP (i.e., high level H). Thereafter, before the fourth time point t4, the start pulse SSP can again change to a low level L.

[0173] In this embodiment, because the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap (that is, the low level L of the first clock signal CLK1 and the low level L of the second clock signal CLK2 do not overlap), the voltages of the fifth node NN5 and the first inverted carry signal CRB1 can remain at a high level H after the fourth time point t4.

[0174] At the fourth time point t4, a first clock signal CLK1 can be supplied, and the first transistor T1 and the third transistor T3 can be turned on in response to the first clock signal CLK1.

[0175] When the first transistor T1 is turned on, the low level L of the start pulse SSP can be supplied to the first node NN1. The voltage of the third node NN3 can be changed to a low level L by the tenth transistor T10, which is in the on state. Therefore, the fourth transistor T4 can be turned on at the fourth time point t4 by the low level L of the third node NN3.

[0176] At this time, because a low level L with an amplitude similar to that of the first power supply VGL is supplied to the gate electrode of the fourth transistor T4, the first output signal OUT1 output to the first output terminal 105 through the fourth transistor T4 can have an intermediate level M. The intermediate level M can be higher than the voltage of the first power supply VGL. In one embodiment, for example, the intermediate level M can be a voltage of approximately VGL + 2|Vth|, where Vth represents the threshold voltage.

[0177] In addition, the low-level L voltage of the third node NN3 can be supplied to the gate electrode of the ninth transistor T9 and a terminal of the third capacitor C3.

[0178] In this embodiment, at the fourth time point t4, the eighth transistor T8 can be turned on by the low-level voltage L of the first node NN1. When the eighth transistor T8 is turned on, the voltage of the second power supply VGH can be supplied to the fourth node NN4 and the fifth transistor T5 can be turned off. Thereafter, the high-level voltage H of the fourth node NN4 can be maintained until the second time point t2 of the next frame returns again.

[0179] At the fifth time point t5, the supply of the first clock signal CLK1 can be stopped. At this time, the second transistor T2 can be turned on by the low-level voltage L of the first node NN1. Therefore, the high level of the first clock signal CLK1 can be supplied to the second node NN2 through the second transistor T2, and the voltage of the second node NN2 can be changed to a high level H.

[0180] Furthermore, at the sixth time point t6, the second clock signal CLK2 can be supplied to the third input terminal 103 again. At the sixth time point t6, the second clock signal CLK2 can be supplied by the ninth transistor T9 in the on state to the terminal between the third capacitor C3 and the ninth transistor T9. Therefore, the voltage of the third node NN3 can be reduced to a 2-low level 2L due to the coupling of the third capacitor C3.

[0181] Therefore, since the 2-low level 2L is supplied to the gate electrode of the fourth transistor T4, the first output signal OUT1 and the first carry signal CR1 output to the first output terminal 105 can be changed to low level L at the sixth time point t6.

[0182] Subsequently, during the period when the first output signal OUT1 and the first carry signal CR1 are at a low level L, the voltage of the second node NN2 can swing according to the first clock signal CLK1. That is, as Figure 4 As shown, during the period after the sixth time point t6, the voltage of the second node NN2 can oscillate periodically due to the influence of the second transistor T2, which is turned on by the low-level voltage L of the first node NN1.

[0183] In this embodiment, such as Figure 4 As shown, during the period after the sixth time point t6, the voltage of the third node NN3 can periodically decrease to the 2-low level 2L due to the influence of the ninth transistor T9, which is turned on by the low level L of the third node NN3, and the third capacitor C3, which is discharged / charged by the second clock signal CLK2.

[0184] Figure 5 The diagram is for driving. Figure 3 The signal timing diagram of an embodiment of the second-level signal.

[0185] exist Figure 5 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 4 The components described are the same as those described above, and any repeated detailed descriptions of these components will be omitted. For example, it can be understood that... Figure 4 The first time point t1 to the sixth time point t6 is related to Figure 5 The same time points from the first time point t1 to the sixth time point t6.

[0186] Reference Figures 3 to 5 The second stage ST2 can operate based on the first carry signal CR1 and the first inverted carry signal CRB1. Figure 5 The operation of the second stage ST2 based on the starting pulse SSP and the output of the first stage ST1 are shown.

[0187] At the first time point t1, the voltage of the third node N3 of the second stage ST2 can be reduced to a low level 2L. That is, the voltage of the third node N3 can fluctuate according to the change of the first clock signal CLK1 due to the influence of the ninth transistor M9, which is turned on by the low level L of the third node N3, and the third capacitor C3, which is charged / discharged by the first clock signal CLK1 (that is, the operation of the second control circuit 24).

[0188] At the second time point t2, the second clock signal CLK2 can be supplied to the second input terminal 202. The first transistor M1 and the second transistor M2 can be turned on in response to the second clock signal CLK2. Therefore, the high level H of the first carry signal CR1 can be supplied to the first node N1, and the low level L of the first inverted carry signal CRB1 can be supplied to the second node N2.

[0189] Before the seventh time point t7, between the second time point t2 and the third time point t3, the supply of the second clock signal CLK2 is stopped. As described above, the first inverted carry signal CRB1 can have the same waveform as the second clock signal CLK2. Therefore, even if the first inverted carry signal CRB1 changes to a high level H before the seventh time point t7, the voltage of the second node N2 can remain at a low level L.

[0190] At the seventh time point t7, the first clock signal CLK1 can be supplied to the third input terminal 203. The sixth transistor M6 can be turned on in response to the first clock signal CLK1. Since the operation of the first output circuit 12 of the first stage ST1 and the second output circuit 22 of the second stage ST2 are essentially the same, any repeated detailed descriptions will be omitted.

[0191] The voltage of the fourth node N4 can be reduced by the sixth transistor M6 and the seventh transistor M7, which are turned on at the seventh time point t7, and the fifth transistor M5 can be turned on by the voltage of the fourth node N4.

[0192] When the fifth transistor M5 is turned on, the voltage of the second power supply VGH can be supplied to the first output terminal 205. Therefore, the second output signal OUT2 and the second carry signal CR2 can be output at a high level H.

[0193] In this embodiment, because the voltage of the fifth node N5 is reduced by the first clock signal CLK1, a low-level L voltage can be supplied to the second output terminal 206. Therefore, the second inverted carry signal CRB2 can be output at a low level L. During the periods when the voltage of the second node N2 has a low level L (including the third time point t3, the fourth time point t4, and the fifth time point t5), the waveform of the second inverted carry signal CRB2 can be substantially the same as the voltage change of the fifth node N5.

[0194] At the sixth time point t6, the second clock signal CLK2 can be supplied to the second input terminal 202 again, and the first transistor M1 and the second transistor M2 can be turned on in response to the second clock signal CLK2.

[0195] When the first transistor M1 is turned on, the low level L of the first carry signal CR1 can be supplied to the first node N1. The voltage of the third node N3 can be changed to a low level L by the tenth transistor M10, which is in the on state. Therefore, the fourth transistor M4 can be turned on by the low level L of the third node N3. At this time, because a low level L with an amplitude similar to that of the first power supply VGL is supplied to the gate electrode of the fourth transistor M4, the second output signal OUT2 output to the first output terminal 205 can have an intermediate level M. In addition, the low level L of the third node N3 can be supplied to the gate electrode of the ninth transistor M9 and one terminal of the third capacitor C3.

[0196] In this embodiment, at the sixth time point t6, the eighth transistor M8 can be turned on by the low-level voltage L of the first node N1. When the eighth transistor M8 is turned on, the voltage of the second power supply VGH can be supplied to the fourth node N4 and the fifth transistor M5 can be turned off.

[0197] Subsequently, at the eighth time point t8, the first clock signal CLK1 can be supplied to the third input terminal 203 again. At the eighth time point t8, the first clock signal CLK1 can be supplied by the ninth transistor M9 in the on state to the terminal between the third capacitor C3 and the ninth transistor M9. Therefore, the voltage of the third node N3 can be reduced to the 2-low level 2L due to the coupling of the third capacitor C3.

[0198] Therefore, since the 2-low level 2L is supplied to the gate electrode of the fourth transistor M4, the second output signal OUT2 and the second carry signal CR2 output to the first output terminal 205 can be changed to the low level L.

[0199] Subsequently, due to the influence of the ninth transistor M9, which is turned on by the low-level L voltage of the third node N3, and the third capacitor C3, which is charged / discharged by the second clock signal CLK2, the voltage of the third node N3 can periodically decrease to the low level 2L during the period after the sixth time point t6.

[0200] In this embodiment, as described above, the second stage ST2 can output a second output signal OUT2 in which the first output signal OUT1 is offset and a second inverted carry signal CRB2 in which the first inverted carry signal CRB1 is offset.

[0201] In this embodiment, the first inverted carry signal CRB1, supplied to the fifth input terminal 208, remains at a high level H after the fourth time point t4. Therefore, even if the second transistor M2 is periodically turned on in response to the second clock signal CLK2 after the sixth time point t6, the high level H voltage can be supplied only to the second node N2.

[0202] Therefore, unlike the voltage change of the second node NN2 in the first stage, the voltage of the second node N2 can be maintained at a high level H in the period after the sixth time point t6, and the voltage of the second node N2 and the voltage of the sixth node N6 can be maintained at relatively constant values.

[0203] When the output signal corresponding to the output of the remaining stage with the same configuration as the second stage ST2 is at a low level L, the voltage of the second node N2 can be stably maintained at a high level H.

[0204] Therefore, during the period when the second output signal OUT2 is output at a low level L, undesirable charging / discharging operations of the first capacitor C1 are effectively prevented, and thus, the power consumption for canceling the charging / discharging operation can be reduced. In this embodiment, by preventing or minimizing the change in equivalent impedance caused by the charging / discharging of the first capacitor C1, the rise / fall rates of the first clock signal CLK1, the second clock signal CLK2, and the output signals (e.g., OUT2 and CR2) can be improved, and voltage ripple can be reduced.

[0205] Therefore, the gate driver including the scan driver according to the embodiments of this disclosure can be stably applied to high-speed driving and can improve image quality.

[0206] Figure 6 The diagram illustrates the driving process during the initialization phase. Figure 2A The signal timing diagram of an embodiment of the scan driver signal, and Figure 7 The diagram illustrates the driving process during the initialization phase. Figure 2A Another embodiment of the signal timing diagram of the scan driver.

[0207] Reference Figure 2A , Figure 3 , Figure 6 and Figure 7 The output signals OUT1 to OUT4 can be output at a high level H during the initialization period P1.

[0208] In this embodiment, initialization circuits 16 and 26 may supply the voltage of the second power supply VGH to the first nodes NN1 and N1 during the initialization period P1. The initialization period P1 may be the period during which the display device 1000 is initially driven, which is the period before the pixel PX is substantially driven. All signals prior to the initialization period P1 may have a ground level GND. During the initialization period P1, a high-level start pulse SSP may be supplied.

[0209] In an embodiment, such as Figure 6As shown, a first clock signal CLK1 and a second clock signal CLK2 with a low level L can be supplied during the initialization period P1. In one embodiment, for example, the length of the initialization period P1, in which both the first clock signal CLK1 and the second clock signal CLK2 have a low level L, can be set to be longer than the period in which the first clock signal CLK1 and / or the second clock signal CLK2 have a low level L (e.g., Figure 4 The length of the period between the fourth time point t4 and the fifth time point t5 is long.

[0210] In this embodiment, the low-level L reset signal RST can be simultaneously supplied to the first stage ST1 to the fourth stage ST4 through the fourth input terminals 104 and 204 during the initialization period P1.

[0211] The twelfth transistor T12 of the first stage ST1 and the twelfth transistor M12 and thirteenth transistor M13 of the second stage ST2 can be turned on by a low-level L reset signal RST. Therefore, the voltages of the first nodes NN1 and N1 can be changed to a high level H. During the initialization period P1, the voltages of the first nodes NN1 and N1 can be initialized to a high level H, and the voltages of the second nodes NN2 and N2 can be initialized to a low level L. Therefore, during the initialization period P1, all stages ST1 to ST4 included in the scan driver 200 can simultaneously output high-level H scan signals.

[0212] Subsequently, when the starting pulse SSP changes to a low level L, the output signals OUT1 to OUT4, which are synchronously output to scan lines SL1 to SL4 with the first clock signal CLK1 or the second clock signal CLK2, can be sequentially changed to a low level L.

[0213] exist Figure 6 In this process, the output signals OUT1 to OUT4 sequentially decrease from a high level H to a low level L, but this disclosure is not limited thereto. In one embodiment, for example, the output signals OUT1 to OUT4 can be... Figure 4 The step form shown is reduced.

[0214] In this embodiment, when an image is displayed, initialization circuits 16 and 26 do not affect the operation of stages ST1 and ST2, and can perform actions such as... Figure 4 and Figure 5 The driver shown.

[0215] In an embodiment, such as Figure 3As shown, the first output terminal 105 of the first stage ST1 can be connected to the first input terminal 201 of the second stage ST2, and the second output terminal 106 of the first stage ST1 can be connected to the fifth input terminal 208 of the second stage ST2. A high-level H first carry signal CR1 can be supplied to a third node N3 through the first node N1 of the second stage ST2. Similarly, a high-level H second carry signal CR2 can be supplied to the supplied third stage ST3.

[0216] The carry signal at high level H may not be fully transmitted to the final stage due to the slave connection of stages ST1 to ST4 and the resistance-capacitor (RC) delay at the initial stage of drive. In this case, the fourth transistor M4 and the fifth transistor M5 may be turned on simultaneously in the predetermined stage. Therefore, the voltage level of the output signal may be reduced, and abnormal emission phenomena such as flickering of pixel PX may occur.

[0217] In embodiments of this disclosure, initialization circuits 16 and 26 directly transmit the voltage of the second power supply VGH to the first nodes NN1 and N1 during the initialization period P1, and therefore, the high-level voltage H can be immediately supplied to the first nodes NN1 and N1 and the third nodes NN3 and N3. Consequently, the fourth transistors T4 and M4 can be completely turned off during the initialization period P1, effectively preventing flickering caused by unintentional emission of pixel PX.

[0218] In an embodiment, such as Figure 7 As shown, a first clock signal CLK1 and a second clock signal CLK2 with a high level H can be supplied during the initialization period P1.

[0219] In this embodiment, all transistors except those in initialization circuits 16 and 26 are turned off, and therefore, unwanted operation of stages ST1 to ST4 and unwanted current inflow / current changes can be effectively prevented. In this embodiment, the first nodes NN1 and N1 can be initialized to a high-level voltage H by the conduction of initialization circuits 16 and 26.

[0220] Figure 8 It is a diagram. Figure 3 Circuit diagram of an alternative embodiment of the second level.

[0221] exist Figure 8 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, aside from the configuration of the thirteenth transistor M13, Figure 8 The second level ST2_1 can have the same Figure 3 The configuration of the second-level ST2 is basically the same or similar.

[0222] Reference Figure 6 and Figure 8 An embodiment of the second-level ST2_1 may include a second input circuit 21, a second output circuit 22, a second control circuit 24, a second stabilization circuit 25, and a second initialization circuit 26A.

[0223] The second initialization circuit 26A can supply the voltage of the second power supply VGH to the first node N1 during the initialization period P1. The second initialization circuit 26A may include a twelfth transistor M12 and a thirteenth transistor M13.

[0224] The thirteenth transistor M13 can be connected between the fourth node N4 and the first power supply VGL. During the initialization period P1, the thirteenth transistor M13 can be turned on in response to the reset signal RST, and the voltage of the first power supply VGL can be supplied to the fourth node N4. Therefore, the fifth transistor M5 can be turned on, and thus, the second output voltage OUT2 with a high level H can be supplied to the first output terminal 205.

[0225] The second-level ST2_1 driver can be referenced. Figure 5 The drivers described are essentially the same.

[0226] Figure 9 It is a diagram. Figure 3 A circuit diagram of another alternative embodiment of the second stage.

[0227] exist Figure 9 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the configuration of the sixteenth transistor M16, Figure 9 The second level ST2_2 can have the same as Figure 3 The configuration of the second-level ST2 is basically the same or similar.

[0228] Reference Figure 5 and Figure 9 The second-level ST2_2 embodiment may include a second input circuit 21, a second output circuit 22, a second control circuit 24A, a second stabilization circuit 25, and a second initialization circuit 26.

[0229] In an embodiment, the second control circuit 24A may include a ninth transistor M9, a third capacitor C3, and a sixteenth transistor M16.

[0230] The sixteenth transistor M16 can be connected between the second electrode of the ninth transistor M9 and the second power supply VGH. The gate electrode of the sixteenth transistor M16 can be connected to the second node N2.

[0231] When the sixteenth transistor M16 is turned on, the voltage of the second power supply VGH can be supplied to the second electrode of the ninth transistor M9.

[0232] In other words, when the second-level ST2_2 starts (for example, Figure 6 During the initialization period P1) and / or when the second output signal OUT2 (high level H) is output, the sixteenth transistor M16 can stably supply the voltage of the second power supply VGH to the second electrode of the ninth transistor M9 and one terminal of the third capacitor C3. Therefore, when the second output signal OUT2 (high level H) is output, the voltage of the third node N3 can be stably maintained at the high level H, and the fourth transistor M4 can be in a completely off state.

[0233] The second control circuit 24A can also be applied to... Figure 9 The second level ST2_1.

[0234] Figure 10 It is a diagram. Figure 3 A circuit diagram of another embodiment of the second stage.

[0235] exist Figure 10 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 and Figure 9 The same components as those described above will be omitted, and any repeated detailed descriptions of these components will be omitted. Furthermore, except for omitting the thirteenth transistor M13, Figure 10 The second level ST2_3 can have the same Figure 9 The configuration of the second-level ST2_2 is basically the same or similar.

[0236] Reference Figure 6 and Figure 10 The second-level ST2_3 embodiment may include a second input circuit 21, a second output circuit 22, a second control circuit 24A, a second stabilization circuit 25, and a second initialization circuit 26B.

[0237] In the embodiment, because the second initialization circuit 26B generally operates to supply a high-level voltage to the first node N1, the second initialization circuit 26B may have [details omitted]. Figure 3 and Figure 9 The configuration of the thirteenth transistor M13 allows for a reduction in the manufacturing cost and size of the scan driver (gate driver).

[0238] In addition, the second initialization circuit 26B can also be applied to Figure 3 The second level ST2 and Figure 9 The second level ST2_2.

[0239] Figure 11It is a diagram. Figure 3 Circuit diagram of an alternative embodiment of the first stage.

[0240] exist Figure 11 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the configuration of the sixteenth transistor T16, Figure 11 The first level ST1_1 can have the same as Figure 3 The configuration of the first-level ST1 is basically the same or similar.

[0241] Reference Figure 4 and Figure 11 An embodiment of the first stage ST1_1 may include a first input circuit 11, a first output circuit 12, a first control circuit 14A, a first stabilization circuit 15, and a first initialization circuit 16.

[0242] In an embodiment, the first control circuit 14A may include a ninth transistor T9, a third capacitor C3, and a sixteenth transistor T16.

[0243] The sixteenth transistor T16 can be connected between the seventh node NN7 and the second power supply VGH. The gate electrode of the sixteenth transistor T16 can be connected to the second node NN2.

[0244] When the sixteenth transistor T16 is turned on, the voltage of the second power supply VGH can be supplied to the seventh node NN7.

[0245] In other words, when the first-level ST1_1 starts (for example, Figure 6 During the initialization period P1) and / or when the first output signal OUT1 (high level H) is output, the sixteenth transistor T16 can stably supply the voltage of the second power supply VGH to the seventh node NN7. Therefore, when the first output signal OUT1 (high level H) is output, the voltage of the third node NN3 can be stably maintained at the high level H, and the fourth transistor T4 can be in a completely off state.

[0246] Figure 12 It is a diagram. Figure 2A Circuit diagrams of alternative embodiments of the first and second stages included in the scan driver.

[0247] exist Figure 12 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the second output terminals 106A and 206A, Figure 12 The first stage ST1A and the second stage ST2A can have the same Figure 3The configurations of the first-level ST1 and the second-level ST2 are basically the same or similar.

[0248] Reference Figure 12 The embodiments of the first stage ST1A and the second stage ST2A may respectively include input circuits 11 and 21, output circuits 12A and 22A, control circuits 14 and 24, stabilization circuits 15 and 25, and initialization circuits 16 and 26.

[0249] The configuration of the second-level ST2A can also be applied to the k-th level (where k is an integer greater than 2).

[0250] In one embodiment, the first output circuit 12A can be connected to the second output terminal 106A of the first stage ST1A. In another embodiment, for example, the second output terminal 106A can be connected to the fourth node NN4. Therefore, the voltage of the fourth node NN4 can be supplied to the fifth input terminal 208 of the second stage ST2A as a first inverted carry signal CRB1.

[0251] In this embodiment, the second output circuit 22A can be connected to the second output terminal 206A of the second stage ST2A. In one embodiment, for example, the second output terminal 206A can be connected to the fourth node N4. Therefore, the voltage of the fourth node N4 can be output as the second inverted carry signal CRB2.

[0252] Figure 13 The diagram is for driving. Figure 12 The signal timing diagram of an embodiment of the second-level signal.

[0253] Reference Figure 12 and Figure 13 The first stage ST1A can output the first output signal OUT1, the first carry signal CR1, and the first inverted carry signal CRB1, and the second stage ST2A can output the second output signal OUT2, the second carry signal CR2, and the second inverted carry signal CRB2.

[0254] The first inverted carry signal CRB1 corresponds to the voltage of the fourth node NN4 of the first stage ST1A. Similarly, the second inverted carry signal CRB2 corresponds to the voltage of the fourth node N4 of the second stage ST2A. In this embodiment, the voltage at the fourth node N4 of the second stage ST2A can be removed. Figure 5 The pulse switching (oscillation) of the first inverted carry signal CRB1 and the second inverted carry signal CRB2 during the time period between the second time point t2 and the sixth time point t6 shown.

[0255] therefore, Figure 12 The ST1A and ST2A can be compared Figure 3 The ST1 and ST2 series have reduced power consumption.

[0256] Figure 14 It is a diagram. Figure 12 Circuit diagram of an alternative embodiment of the second level.

[0257] exist Figure 14 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 10 and Figure 12 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, except that the configuration of the thirteenth transistor M13 is omitted, Figure 14 The second-level ST2A_1 can have the same Figure 12 The configuration of the second-level ST2A is basically the same or similar.

[0258] Reference Figure 6 and Figure 14 An embodiment of the second-level ST2A_1 may include a second input circuit 21, a second output circuit 22A, a second control circuit 24, a second stabilization circuit 25, and a second initialization circuit 26B.

[0259] In an embodiment, the second initialization circuit 26B may have [a feature omitted]. Figure 3 and Figure 9 The configuration of the thirteenth transistor M13. Therefore, the manufacturing cost of the scan driver (gate driver) can be reduced.

[0260] In addition, the second initialization circuit 26B can also be applied to Figure 15 The second level ST2A_2. In another alternative embodiment, Figure 8 The second initialization circuit 26A can also be applied to the second stage ST2A_1 to replace the second initialization circuit 26B.

[0261] Figure 15 It is a diagram. Figure 12 A circuit diagram of another alternative embodiment of the second stage.

[0262] exist Figure 15 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 9 and Figure 12 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the configuration of the sixteenth transistor M16, Figure 15 The second-level ST2A_2 can have the same Figure 12 The configuration of the second-level ST2A is basically the same or similar.

[0263] Reference Figure 5 and Figure 15An embodiment of the second-level ST2A_2 may include a second input circuit 21, a second output circuit 22A, a second control circuit 24A, a second stabilization circuit 25, and a second initialization circuit 26.

[0264] In one embodiment, the second control circuit 24A may include a ninth transistor M9, a third capacitor C3, and a sixteenth transistor M16. The sixteenth transistor M16 may be connected between the second electrode of the ninth transistor M9 and the second power supply VGH. The gate electrode of the sixteenth transistor M16 may be connected to the second node N2.

[0265] Therefore, when the second output signal OUT2 outputs a high level H, the voltage of the third node N3 can be stably maintained at a high level H, and the fourth transistor M4 can be in a completely off state.

[0266] The second control circuit 24A can also be applied to... Figure 14 The second level ST2A_1.

[0267] Figure 16 It is a diagram. Figure 12 Circuit diagram of an alternative embodiment of the first stage.

[0268] exist Figure 16 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 11 and Figure 12 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the configuration of the sixteenth transistor T16, Figure 16 The first level ST1A_1 can have the same as Figure 12 The configuration of the first-level ST1A is basically the same or similar.

[0269] Reference Figure 4 and Figure 16 An embodiment of the first stage ST1A_1 may include a first input circuit 11, a first output circuit 12A, a first control circuit 14A, a first stabilization circuit 15, and a first initialization circuit 16.

[0270] In an embodiment, the first control circuit 14A may include a ninth transistor T9, a third capacitor C3, and a sixteenth transistor T16.

[0271] The sixteenth transistor T16 can be connected between the seventh node NN7 and the second power supply VGH. The gate electrode of the sixteenth transistor T16 can be connected to the second node NN2. Therefore, when the first output signal OUT1 outputs a high level H, the voltage of the third node NN3 can be stably maintained at a high level H, and the fourth transistor T4 can be in a completely off state.

[0272] Figure 17 It is a diagram. Figure 2A A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver.

[0273] exist Figure 17 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repetitive detailed descriptions of these components will be omitted or simplified. Furthermore, apart from control circuits 14B and 24B, Figure 17 The first stage ST1B and the second stage ST2B can have the same Figure 3 The configurations of the first-level ST1 and the second-level ST2 are basically the same or similar.

[0274] Reference Figure 17 The embodiments of the first stage ST1B and the second stage ST2B may respectively include input circuits 11 and 21, output circuits 12 and 22, control circuits 14B and 24B, stabilization circuits 15 and 25, and initialization circuits 16 and 26.

[0275] The configuration of the second-level ST2B can also be applied to the k-th level (where k is an integer greater than 2).

[0276] The first level, ST1B, will be described in detail below.

[0277] The first control circuit 14B may include a ninth transistor T9, a third capacitor C3, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18.

[0278] The sixteenth transistor T16 and the seventeenth transistor T17 can be connected in series between the first input terminal 101 and the seventh node NN7. The gate electrode of the sixteenth transistor T16 can be connected to the second input terminal 102, and the gate electrode of the seventeenth transistor T17 can be connected to the second power supply VGL.

[0279] The sixteenth transistor T16 can be turned on in response to the first clock signal CLK1 and can supply the start pulse SSP to the seventh node NN7.

[0280] The seventeenth transistor T17 can perform essentially the same function as the tenth transistor T10 of the first stabilizing circuit 15. That is, the seventeenth transistor T17 can be in a conducting state and can reduce the bias stress on the sixteenth transistor T16 caused by voltage changes at the seventh node NN7. According to an embodiment, the seventeenth transistor T17 can be omitted.

[0281] The eighteenth transistor T18 can be connected between the seventh node NN7 and the third node NN3. The gate electrode of the eighteenth transistor T18 can be connected to the seventh node NN7.

[0282] In one embodiment, for example, the eighteenth transistor T18 may have a diode shape connecting the third node NN3 to the seventh node NN7. Therefore, current does not flow from the seventh node NN7 to the third node NN3. Thus, in a reverse diode connection state where the voltage of the seventh node NN7 is higher than the voltage of the third node NN3, the voltage of the third node NN3 can remain relatively constant.

[0283] When a high-level signal is supplied to the first input terminal 101, the voltage of the seventh node NN7 does not affect the third node NN3 because the eighteenth transistor T18 is used as a reverse diode.

[0284] The eighteenth transistor T18 can operate as a charge pump. In one embodiment, for example, the voltage at the seventh node NN7, which has a form similar to an alternating current (AC) voltage due to the coupling (charging / discharging) of the third capacitor C3, can be converted into a form such as a DC voltage at the third node NN3 by the eighteenth transistor T18.

[0285] Therefore, despite the voltage variation at the seventh node NN7, the voltage at the third node NN3 can be maintained at a constant level (e.g., 2-low level) by the charge pump operation of the eighteenth transistor T18.

[0286] The second-level ST2B may include a second input circuit 21, a second output circuit 22, a second control circuit 24B, a second stabilization circuit 25, and a second initialization circuit 26.

[0287] The second control circuit 24B may include a ninth transistor M9, a third capacitor C3, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. Since the configuration and operation of the ninth transistor M9, the third capacitor C3, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are substantially the same as those of the ninth transistor T9, the third capacitor C3, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 of the first control circuit 14B, any repeated detailed descriptions will be omitted.

[0288] The sixteenth transistor M16 and the seventeenth transistor M17 can be connected between the first input terminal 201 and the seventh node N7. The gate electrode of the sixteenth transistor M16 can be connected to the second input terminal 202, and the gate electrode of the seventeenth transistor M17 can be connected to the second power supply VGL.

[0289] The eighteenth transistor M18 can be connected between the seventh node N7 and the third node N3. The gate electrode of the eighteenth transistor M18 can be connected to the seventh node N7.

[0290] Therefore, despite the voltage variation at the seventh node N7, the voltage at the third node N3 can be maintained at a constant level (e.g., 2-low level) by the charge pump operation of the eighteenth transistor M18.

[0291] Figure 18 The diagram is for driving. Figure 17 The signal timing diagram of an embodiment of the second-level signal.

[0292] exist Figure 18 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 5 The components described are the same as those described above, and any repeated detailed descriptions of these components will be omitted. Furthermore, except for the voltage at the third node N3 after the eighth time point t8, Figure 18 The driver can be with Figure 5 The timing diagrams are basically the same or similar.

[0293] Reference Figure 17 and Figure 18 The first stage ST1B can output the first output signal OUT1, the first carry signal CR1, and the first inverted carry signal CRB1, and the second stage ST2B can output the second output signal OUT2, the second carry signal CR2, and the second inverted carry signal CRB2.

[0294] The following describes an embodiment of the second-level ST2B driver. In this embodiment, the driver from the first time point t1 to the sixth time point t6 can be referenced. Figure 5 The drivers described are essentially the same.

[0295] As described above, the second control circuit 24B can control the voltage of the third node N3 after the eighth time point t8.

[0296] For reference Figure 5 The charging / discharging of the third capacitor C3 can be repeated by the voltage change of the first clock signal CLK1 supplied to the third input terminal 203 after the eighth time point t8, and the voltage waveform of the seventh node N7 can be changed according to the first clock signal CLK1.

[0297] In this embodiment, when the voltage of the seventh node N7 is higher than the voltage of the third node N3, the third node N3 is unaffected by the voltage change of the seventh node N7 because the eighteenth transistor M18 becomes a reverse diode connection. Therefore, after the eighth time point t8, the voltage of the third node N3 can be maintained at a low level 2L due to the parasitic capacitance of the fourth transistor M4.

[0298] In this embodiment, it is possible to remove in Figure 5 The voltage switching (swinging) of the third node N3 of the second stage ST2B during the period after the eighth time point t8 shown. The same drive can be performed in the first stage ST1B having the same first control circuit 14B as the second control circuit 24B.

[0299] therefore, Figure 17 The ST1B and ST2B can be compared Figure 3 The ST1 and ST2 stages have reduced power consumption. Furthermore, the low-level L output signals OUT1 and OUT2 can be output stably, thus improving image quality.

[0300] Figure 19 It is a diagram. Figure 17 Circuit diagram of an alternative embodiment of the second level.

[0301] exist Figure 19 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 and Figure 17 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the nineteenth transistor M19, Figure 19 The second-level ST2B_1 can have the same Figure 17 The configuration of the second-level ST2B is basically the same or similar.

[0302] Reference Figure 18 and Figure 19 An embodiment of the second-level ST2B_1 may include a second input circuit 21, a second output circuit 22, a second control circuit 24C, a second stabilization circuit 25, and a second initialization circuit 26.

[0303] In an embodiment, the second control circuit 24C may include a ninth transistor M9, a third capacitor C3, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19.

[0304] The nineteenth transistor M19 can be connected between the second power supply VGH and the eighth node N8. One electrode of the ninth transistor M9 and one electrode of the third capacitor C3 can be connected to the eighth node N8. The gate electrode of the nineteenth transistor M19 can be connected to the second node N2. When the nineteenth transistor M19 is turned on, the voltage of the second power supply VGH can be supplied to the eighth node N8.

[0305] When stage ST2B_1 is started and / or when the high-level second output signal OUT2 is output, the nineteenth transistor M19 can stably supply the voltage of the second power supply VGH to the second node N8. In one embodiment, for example, the voltage of the eighth node N8 can be initialized to the voltage of the second power supply VGH before operation for image display.

[0306] According to the embodiment, the second initialization circuit 26 can be composed of... Figure 8 The second initialization circuit 26A or Figure 10 The second initialization circuit 26B is replaced.

[0307] Figure 20 It is a diagram. Figure 17 Circuit diagram of an alternative embodiment of the first stage.

[0308] exist Figure 20 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 and Figure 17 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the nineteenth transistor T19, Figure 20 The first level ST1B_1 can have the same as Figure 17 The configuration of the first-level ST1B is basically the same or similar.

[0309] Reference Figure 20 An embodiment of the first-level ST1B_1 may include a first input circuit 11, a first output circuit 12, a first control circuit 14C, a first stabilization circuit 15, and a first initialization circuit 16.

[0310] In an embodiment, the first control circuit 14C may include a ninth transistor T9, a third capacitor C3, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19.

[0311] The nineteenth transistor T19 can be connected between the second power supply VGH and the eighth node NN8. One electrode of the ninth transistor T9 and one electrode of the third capacitor C3 can be connected to the eighth node NN8. The gate electrode of the nineteenth transistor T19 can be connected to the second node NN2. When the nineteenth transistor T19 is turned on, the voltage of the second power supply VGH can be supplied to the eighth node NN8.

[0312] When stage ST1B_1 is started and / or when the first output signal OUT1 is high, the nineteenth transistor T19 can stably supply the voltage of the second power supply VGH to the eighth node NN8. In one embodiment, for example, the voltage of the eighth node NN8 can be initialized to the voltage of the second power supply VGH before operation for image display.

[0313] Figure 21 It is a diagram. Figure 2A A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver.

[0314] exist Figure 21 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 12 and Figure 17 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the second output terminals 106A and 206A, Figure 21 The first-stage ST1C and the second-stage ST2C can have the same characteristics as... Figure 17 The configurations of the first-level ST1B and the second-level ST2B are basically the same or similar.

[0315] Reference Figure 21 The embodiments of the first-level ST1C and the second-level ST2C may respectively include input circuits 11 and 21, output circuits 12A and 22A, control circuits 14B and 24B, stabilization circuits 15 and 25, and initialization circuits 16 and 26.

[0316] The configuration of the second-level ST2 can also be applied to the k-th level (where k is an integer greater than 2).

[0317] In one embodiment, the second output terminal 106A of the first stage ST1C can be connected to the fourth node NN4. In this embodiment, the second output terminal 206A of the second stage ST2C can be connected to the fourth node N4.

[0318] Figure 22 The diagram is for driving. Figure 21 The signal timing diagram of an embodiment of the second-level signal.

[0319] Reference Figure 21 and Figure 22 The first-stage ST1C can output the first output signal OUT1, the first carry signal CR1, and the first inverted carry signal CRB1, and the second-stage ST2C can output the second output signal OUT2, the second carry signal CR2, and the second inverted carry signal CRB2.

[0320] In one embodiment, the first inverted carry signal CRB1 may correspond to the voltage of the fourth node NN4 of the first stage ST1C. In this embodiment, the second inverted carry signal CRB2 may correspond to the voltage of the fourth node N4 of the second stage ST2C. In this embodiment, the voltage at the fourth node N4 of the second stage ST2C can be removed. Figure 18 The pulse switching (oscillation) of the first inverted carry signal CRB1 and the second inverted carry signal CRB2 during the time period between the second time point t2 and the sixth time point t6 shown.

[0321] therefore, Figure 21 The ST1C and ST2C can be compared Figure 3 , Figure 12 and Figure 17 The ST1, ST2, ST1A, ST2A, ST1B and ST2B series have reduced power consumption.

[0322] Figure 23 It is a diagram. Figure 21 Circuit diagram of an alternative embodiment of the second level.

[0323] exist Figure 23 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 17 , Figure 19 and Figure 21 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the nineteenth transistor M19, Figure 23 The second-level ST2C_1 can have the same Figure 21 The configuration of the second-level ST2C is basically the same or similar.

[0324] Reference Figure 22 and Figure 23 An embodiment of the second-level ST2C_1 may include a second input circuit 21, a second output circuit 22A, a second control circuit 24C, a second stabilization circuit 25, and a second initialization circuit 26.

[0325] In an embodiment, the second control circuit 24C may include a ninth transistor M9, a third capacitor C3, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, and a nineteenth transistor M19.

[0326] When stage ST2C_1 is started and / or when the high-level second output signal OUT2 is output, the nineteenth transistor M19 can stably supply the voltage of the second power supply VGH to the eighth node N8.

[0327] According to the embodiment, the second initialization circuit 26 can be composed of... Figure 8 The second initialization circuit 26A or Figure 10The second initialization circuit 26B is replaced.

[0328] Figure 24 It is a diagram. Figure 21 Circuit diagram of an alternative embodiment of the first stage.

[0329] exist Figure 24 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 17 , Figure 20 and Figure 21 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the nineteenth transistor T19, Figure 24 The first-level ST1C_1 can have the same as Figure 21 The configuration of the first-level ST1C is basically the same or similar.

[0330] Reference Figure 24 An embodiment of the first-level ST1C_1 may include a first input circuit 11, a first output circuit 12A, a first control circuit 14C, a first stabilization circuit 15, and a first initialization circuit 16.

[0331] In an embodiment, the first control circuit 14C may include a ninth transistor T9, a third capacitor C3, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19.

[0332] When stage ST1C_1 is started and / or when the first output signal OUT1 is high, the nineteenth transistor T19 can stably supply the voltage of the second power supply VGH to the eighth node NN8.

[0333] Figure 25 This is a block diagram illustrating a scan driver according to an alternative embodiment of the present disclosure.

[0334] exist Figure 25 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 2A The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, in addition to the fourth input terminal that receives the reset signal RST, Figure 25 The scan driver 200B can have the same as Figure 2A The configuration of the scan driver 200 is basically the same or similar.

[0335] Reference Figure 25 An embodiment of the scan driver 200B may include multiple stages ST1 to ST4. Stages ST1 to ST4 may be connected to predetermined scan lines SL1 to SL4 respectively, and may output scan signals according to clock signals CLK1 and CLK2.

[0336] The first stage ST1 and the second stage ST2 can have different circuit configurations.

[0337] Each of stages ST1 to ST4 may include first input terminals 101 and 201, second input terminals 102 and 202, third input terminals 103 and 203, first output terminals 105 and 205, and second output terminals 106 and 206. That is, as referenced above... Figure 2A Compared to the embodiments described above, in Figure 25 In stages ST1 to ST4, the equipment used for receiving can be removed. Figure 2A The reset signal RST Figure 2A The fourth input terminals 104 and 204.

[0338] Therefore, the configuration for generating the reset signal can be omitted, and power consumption can be further reduced.

[0339] Figure 26 It is a diagram. Figure 25 Circuit diagrams of embodiments of the first and second stages included in the scan driver.

[0340] exist Figure 26 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from initialization circuits 16A and 26A, Figure 17 The first-stage ST1D and the second-stage ST2D can have the same characteristics as... Figure 3 The configurations of the first-level ST1 and the second-level ST2 are basically the same or similar.

[0341] Reference Figure 25 and Figure 26 The embodiments of the first-stage ST1D and the second-stage ST2D may respectively include input circuits 11 and 21, output circuits 12 and 22, control circuits 14 and 24, stabilization circuits 15 and 25, and initialization circuits 16A and 26A.

[0342] The configuration of the second-level ST2D can also be applied to the k-th level (where k is an integer greater than 2).

[0343] First, the first level ST1D will be described.

[0344] In this embodiment, the first initialization circuit 16A may include a twelfth transistor T12 and a thirteenth transistor T13. The twelfth transistor T12 and the thirteenth transistor T13 may be connected in series between the second power supply VGH and the first node NN1. The gate electrode of the twelfth transistor T12 may be connected to the second node NN2, and the gate electrode of the thirteenth transistor T13 may be connected to the third input terminal 103.

[0345] During normal driving, when the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap, the first initialization circuit 16A is not electrically connected to the second power supply VGH and the first node NN1. The first initialization circuit 16A can supply the voltage of the second power supply VGH to the first node NN1 during the initialization period.

[0346] The second level of ST2D will be described below.

[0347] In an embodiment, the second initialization circuit 26A may include twelfth transistor M12 to fifteenth transistor M15.

[0348] The twelfth transistor M12 and the thirteenth transistor M13 can be connected in series between the second power supply VGH and the first node N1. The gate electrodes of the twelfth transistor M12 and the thirteenth transistor M13 can be connected to different ones of the second input terminal 202 and the third input terminal 203, respectively. In one embodiment, for example, the gate electrode of the twelfth transistor M12 can be connected to the third input terminal 203, and the gate electrode of the thirteenth transistor M13 can be connected to the second input terminal 202. Therefore, during normal drive when the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap, the conduction periods of the twelfth transistor M12 and the thirteenth transistor M13 do not overlap.

[0349] The fourteenth transistor M14 and the fifteenth transistor M15 can be connected in series between the fourth node N4 and the first power supply VGL. The gate electrodes of the fourteenth transistor M14 and the fifteenth transistor M15 can be connected to different ones of the second input terminal 202 and the third input terminal 203, respectively. In one embodiment, for example, the gate electrode of the fourteenth transistor M14 can be connected to the third input terminal 203, and the gate electrode of the fifteenth transistor M15 can be connected to the second input terminal 202. Therefore, during normal drive when the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap, the conduction period of the fourteenth transistor M14 does not overlap with the conduction period of the fifteenth transistor M15.

[0350] As described above, the scan driver 200B can include initialization circuits 16A and 26A driven during the initialization period without a reset signal.

[0351] Figure 27 The diagram illustrates the driving process during the initialization phase. Figure 25 A signal timing diagram of an embodiment of the scanning driver signals.

[0352] Reference Figures 25 to 27The first clock signal CLK1 and the second clock signal CLK2, which are low level L, can be supplied during the initialization period P1.

[0353] In the embodiment, initialization circuits 16A and 26A can supply the voltage of the second power supply VGH to the first nodes NN1 and N1 during the initialization period P1.

[0354] The twelfth transistor T12 and the thirteenth transistor T13 of the first initialization circuit 16A can be turned on simultaneously during the initialization period P1, and the voltage of the second power supply VGH can be supplied to the first node NN1.

[0355] The twelfth transistor M12 and the thirteenth transistor M13 of the second initialization circuit 26A can also be turned on simultaneously during the initialization period P1, and the voltage of the second power supply VGH can be supplied to the first node N1. The fourteenth transistor M14 and the fifteenth transistor M15 can also be turned on simultaneously during the initialization period P1, and the voltage of the first power supply VGL can be supplied to the fourth node N4.

[0356] In this embodiment, as described above, the voltage of the first node N1 can be initialized to a high level H during the initialization period P1 without a reset signal.

[0357] Figure 28A and Figure 28B It is a diagram. Figure 26 Circuit diagram of an alternative embodiment of the first stage.

[0358] In addition to the initialization circuit Figure 28A and Figure 28B The first-level ST1D_1 and ST1D_2 can have the same as Figure 26 The configuration of the first-level ST1D is basically the same or similar.

[0359] Reference Figure 28A An embodiment of the first-stage ST1D_1 may include a first input circuit 11, a first output circuit 12, a first control circuit 14, and a first stabilization circuit 15. In this embodiment, the first-stage ST1D_2 does not include an initialization circuit, and the initialization period of the first-stage ST1D_1 may be omitted.

[0360] Reference Figure 28B Alternative embodiments of the first-stage ST1D_2 may include a first input circuit 11, a first output circuit 12, a first control circuit 14, a first stabilization circuit 15, and a first initialization circuit 16B.

[0361] In this embodiment, the first initialization circuit 16B may consist of only the twelfth transistor T12. That is, it can be removed. Figure 26 The thirteenth transistor T13 can be used to implement the first stage ST1D_1, which has a simpler structure.

[0362] Figure 29 It is a diagram. Figure 26 Circuit diagram of an alternative embodiment of the second level.

[0363] Reference Figure 29 An embodiment of the second-level ST2D_1 may include a second input circuit 21, a second output circuit 22, a second control circuit 24, and a second stabilizing circuit 25.

[0364] In this embodiment, the initialization circuit can be omitted in the second-level ST2D_1.

[0365] In the embodiment, the second output circuit 22 in the second stage ST2D_1 can be... Figure 12 The second output circuit 22A can be replaced. Furthermore, the second control circuit 24 can be replaced by... Figure 15 The second control circuit 24A, Figure 17 The second control circuit 24B or Figure 19 The second control circuit 24C was replaced.

[0366] Figure 30 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver.

[0367] exist Figure 30 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 12 and Figure 26 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the second output terminals 106A and 206A, Figure 30 The first stage ST1D_3 and the second stage ST2D_3 can have the same Figure 26 The configurations of the first-level ST1D and the second-level ST2D are basically the same or similar.

[0368] Reference Figure 30 In one embodiment, the second output terminal 106A of the first stage ST1D_3 can be connected to the fourth node NN4. In this embodiment, the second output terminal 206A of the second stage ST2D_3 can be connected to the fourth node N4. Therefore, it is possible to perform... Figure 13 The timing diagram is similar to the driver.

[0369] Figure 31 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver.

[0370] exist Figure 31 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 17 and Figure 26 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from control circuits 14B and 24B, Figure 31 The first-level ST1D_4 and the second-level ST2D_4 can have the same Figure 26 The configurations of the first-level ST1D and the second-level ST2D are basically the same or similar.

[0371] Reference Figure 31 An embodiment of the first-level ST1D_4 may include a first control circuit 14B, and an embodiment of the second-level ST2D_4 may include a second control circuit 24B. Therefore, it is possible to perform... Figure 18 The timing diagram is similar to the driver.

[0372] Figure 32 It is a diagram. Figure 25 A circuit diagram of another alternative embodiment of the first and second stages included in the scan driver.

[0373] exist Figure 32 In the figures, the same reference numerals are used in conjunction with the reference figures. Figure 3 , Figure 17 , Figure 21 and Figure 26 The components described herein are identical, and any repeated detailed descriptions of these components will be omitted. Furthermore, apart from the second output terminals 106A and 206A, Figure 31 The first stage ST1D_5 and the second stage ST2D_5 can have the same Figure 30 The configurations of the first-level ST1D_4 and the second-level ST2D_4 are basically the same or similar.

[0374] Reference Figure 32 In one embodiment, the second output terminal 106A of the first stage ST1D_5 can be connected to the fourth node NN4. In this embodiment, the second output terminal 206A of the second stage ST2D_5 can be connected to the fourth node N4. Therefore, it is possible to perform... Figure 22 The timing diagram is similar to the driver.

[0375] As described above, the gate driver and display device including the gate driver according to embodiments of the present disclosure may include a first stage that outputs a carry signal and an inverted carry signal based on a start pulse, and a second stage that outputs a scan signal (and / or a transmit control signal) based on the carry signal and the inverted carry signal. In these embodiments, the remaining stages, which are dependently connected to the second stage and sequentially output scan signals (and / or transmit control signals), may have the same structure as the second stage.

[0376] Therefore, in these embodiments, when the corresponding output signal (carry signal and scan signal) of each of the second to nth (where n is an integer greater than 2) levels is low, the voltage of the second node can be stably maintained at a high level.

[0377] Therefore, in these embodiments, undesirable charging / discharging operations of the first capacitor can be effectively prevented during periods when the output signal is output at a low level, and thus, power consumption for canceling the charging / discharging operation can be reduced. In these embodiments, by preventing or minimizing changes in equivalent impedance due to the charging / discharging of the capacitor, the rise / fall rates of the first clock signal, the second clock signal, and the output signal can be improved, and voltage ripple can be reduced.

[0378] Therefore, in these embodiments, the gate driver (scan driver and / or emit driver) can be stably applied to high-speed driving and can improve the image quality of the display device.

[0379] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0380] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A gate driver, comprising: Level 1 and Level 2 Each of the first and second stages includes an output circuit, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The output circuit outputs a scan signal, a carry signal, and an inverted carry signal based on the voltages of the first and second nodes. The scan signal and the carry signal are output from the first output terminal, and the inverted carry signal is output from the second output terminal. The second input terminal of the first stage and the third input terminal of the second stage receive a first clock signal, and the third input terminal of the first stage and the second input terminal of the second stage receive a second clock signal. The first level further includes: A first input circuit, the first input circuit comprising: A first input transistor is connected between the first input terminal of the first stage, which is supplied with a start pulse, and the first node of the first stage, and includes a gate electrode connected to the second input terminal of the first stage. A second input transistor is connected between the second input terminal of the first stage and the second node of the first stage, and includes a gate electrode connected to the first node of the first stage; and A third input transistor is connected between the first power supply and the second node of the first stage, and includes a gate electrode connected to the second input terminal of the first stage. The second level further includes: The second input circuit controls the voltage of the first node of the second stage and the voltage of the second node of the second stage based on the first carry signal and the first inverted carry signal supplied from the output circuit of the first stage and the signal supplied to the second input terminal of the second stage. The second-level subordinate location is connected to the first-level location.

2. The gate driver of claim 1, wherein, The second input circuit includes: A first transistor is connected between the first input terminal of the second stage, which is supplied with the first carry signal, and the first node of the second stage, and includes a gate electrode connected to the second input terminal of the second stage; and The second transistor is connected between the additional input terminal of the second stage, which is supplied with the first inverted carry signal, and the second node of the second stage, and includes a gate electrode connected to the second input terminal of the second stage.

3. A gate driver, comprising: Level 1 and Level 2 Each of the first and second stages includes an output circuit, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The output circuit outputs a scan signal, a carry signal, and an inverted carry signal based on the voltages of the first and second nodes. The scan signal and the carry signal are output from the first output terminal, and the inverted carry signal is output from the second output terminal. The first level further includes: A first input circuit controls the voltage of the first node of the first stage and the voltage of the second node of the first stage based on a start pulse and a signal supplied to the second input terminal of the first stage. The second level further includes: The second input circuit controls the voltage of the first node of the second stage and the voltage of the second node of the second stage based on the first carry signal and the first inverted carry signal supplied from the output circuit of the first stage and the signal supplied to the second input terminal of the second stage. Wherein, the second level is connected to the first level from its subordinate territory, and Each of the first level and the second level further includes: A control circuit that controls the low-level voltage of the third node based on a signal supplied to the third input terminal; and A stabilizing circuit is electrically connected between the first input circuit or the second input circuit and the output circuit including the fourth node, wherein the stabilizing circuit limits the voltage drop of the first node and the voltage drop of the second node.

4. The gate driver of claim 3, wherein, The output circuit includes: A fourth transistor is connected between the first power supply and the first output terminal, and includes a gate electrode connected to the third node; The fifth transistor is connected between the second power supply and the first output terminal, and includes a gate electrode connected to the fourth node; A sixth transistor is connected between the fourth and fifth nodes and includes a gate electrode connected to the third input terminal; A seventh transistor is connected between the fifth node and the third input terminal, and includes a gate electrode connected to the sixth node; An eighth transistor is connected between the second power supply and the fourth node, and includes a gate electrode connected to the first node; A first capacitor is connected between the fifth node and the sixth node; and The second capacitor is connected between the second power source and the fourth node.

5. The gate driver of claim 4, wherein, The second output terminal is connected to the fifth node.

6. The gate driver of claim 4, wherein, The second output terminal is connected to the fourth node.

7. The gate driver according to claim 4, wherein, The stabilizing circuit includes: A tenth transistor, connected between the first node and the third node, and including a gate electrode that receives the voltage of the first power supply; and The eleventh transistor is connected between the second node and the sixth node, and includes a gate electrode that receives the voltage of the first power supply.

8. The gate driver according to claim 3, wherein, The control circuit includes: The ninth transistor includes a first electrode connected to the third input terminal and a gate electrode connected to the third node; and A third capacitor is connected between the second electrode of the ninth transistor and the gate electrode of the ninth transistor.

9. The gate driver of claim 3, wherein, Each of the first level and the second level further includes: An initialization circuit that supplies the voltage of a second power source to the first node during an initialization period.

10. The gate driver of claim 9, wherein, The second-level initialization circuit includes: The twelfth transistor is connected between the second power supply and the first node, and includes a gate electrode for receiving a reset signal.

11. The gate driver of claim 10, wherein, The second-level initialization circuit further includes: The thirteenth transistor is connected between the fourth node and the fourth input terminal to which the reset signal is supplied, and includes a gate electrode connected to the fourth input terminal or the first power supply.

12. The gate driver of claim 9, wherein, The initialization circuit of the first stage includes: The twelfth transistor is connected between the second power supply and the first node, and includes a gate electrode for receiving a reset signal.

13. The gate driver of claim 12, wherein, The initialization circuit of the first stage further includes: The thirteenth transistor is connected between the twelfth transistor and the second power supply, and includes a gate electrode connected to the third input terminal.

14. The gate driver according to claim 9, wherein, The second-level initialization circuit includes: The twelfth and thirteenth transistors are connected in series between the second power supply and the first node; and The fourteenth and fifteenth transistors are connected in series between the first power supply and the fourth node. The gate electrode of the twelfth transistor is connected to one of the second input terminal and the third input terminal, and the gate electrode of the thirteenth transistor is connected to the other of the second input terminal and the third input terminal. The gate electrode of the fourteenth transistor is connected to one of the second input terminal and the third input terminal, and the gate electrode of the fifteenth transistor is connected to the other of the second input terminal and the third input terminal.

15. The gate driver according to claim 9, wherein, The first stage and the second stage simultaneously output the scan signal with a high level during the initialization period.

16. The gate driver of claim 8, wherein, The control circuit further includes: The sixteenth transistor is connected between the second power supply and the second electrode of the ninth transistor, and includes a gate electrode connected to the second node.

17. The gate driver according to claim 8, wherein, The control circuit further includes: The sixteenth and seventeenth transistors are connected in series between the first input terminal and the gate electrode of the ninth transistor; and The eighteenth transistor is connected between the gate electrode of the ninth transistor and the third node, and includes a gate electrode connected to the gate electrode of the ninth transistor.

18. The gate driver according to claim 17, wherein, The control circuit further includes: The nineteenth transistor is connected between the second power supply and the second electrode of the ninth transistor, and includes a gate electrode connected to the second node.

19. A display device, comprising: Pixel; The gate driver according to any one of claims 1-18; as well as A data driver that supplies data signals to the pixel via a data line.

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