Electrical energy harvesting and signal generation for memory devices

Abstract

This application is directed to electrical energy harvesting and signal generation for memory devices. One or more inductors can be included in or coupled with a memory device and used to provide current for various operations of the memory device based on energy harvested by the inductor(s). An inductor can harvest energy based on current routed through the inductor or based on electrically inductive coupling with a second inductor through which current is routed. After harvesting energy, the inductor can provide current, and the current provided by the inductor can be used to drive an access line or otherwise as part of performing one or more operations at the memory device. Such techniques can improve energy efficiency or improve drive strength of signals of the memory device, among other benefits.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 941,107, filed July 28, 2020, entitled “Inductive Energy Harvesting and Signal Generation for a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to inductive energy harvesting and signal generation for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmable to one of two supported states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), NAND, NOR, etc. Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored values ​​for a long time even without an external power supply. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from an external power source. FeRAM can achieve densities similar to volatile memory but can be non-volatile because it uses ferroelectric capacitors as storage devices. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even without an external power supply. Summary of the Invention

[0006] Describe a method. The method may include: harvesting energy associated with a memory device using an inductor; routing current from the inductor to components of the memory device, wherein the routed current is based on the energy harvested using the inductor; and operating the components of the memory device based on the routed current.

[0007] Describe an apparatus. The apparatus may include: a first array circuit system located within a memory device and coupled to a switching component; a second array circuit system located within the memory device and coupled to the switching component; and an inductor coupled to the switching component, wherein the switching component is operable to: couple the inductor to the first array circuit system when reading or writing to a first set of one or more memory cells coupled to the first array circuit system; and couple the inductor to the second array circuit system when reading or writing to a second set of one or more memory cells coupled to the second array circuit system.

[0008] Describe an apparatus. The apparatus may include: a first array circuit system located within a memory device, wherein the first array circuit system includes a first set of one or more memory cells; an inductor coupled to the first array circuit system and to a first voltage reference; a second array circuit system located within the memory device, wherein the second array circuit system includes a second set of one or more memory cells; and a second inductor coupled to the second array circuit system and to a second voltage reference, wherein the second inductor is inductively coupled to the first inductor. Attached Figure Description

[0009] Figure 1 Examples of systems for inductive energy harvesting and signal generation for supporting memory devices, as disclosed herein, are provided.

[0010] Figure 2 This describes an example of a memory die that supports inductive energy harvesting and signal generation for a memory device, as illustrated in the examples disclosed herein.

[0011] Figures 3 to 6 Examples of circuits for inductive energy harvesting and signal generation for supporting memory devices, as disclosed herein.

[0012] Figure 7 A block diagram of a memory device supporting inductive energy harvesting and signal generation according to aspects of this disclosure is shown.

[0013] Figures 8 to 13 The flowchart illustrates one or more methods for inductive energy harvesting and signal generation for supporting memory devices, based on examples disclosed herein. Detailed Implementation

[0014] An inductor can harvest energy, for example, based on current routing through a circuit. The inductor can then act as a current source based on the harvested energy. For memory devices, an inductor can be included in or coupled to the memory device and used to provide current for various operations of the memory device based on the harvested energy. The inductor can harvest energy based on current routing through it or based on inductive coupling with a second inductor through which the current is routed. After harvesting the energy, the inductor can provide current, and the current provided by the inductor can be used to drive access lines or otherwise as part of performing one or more operations at the memory device. This can provide benefits such as improved energy efficiency of the memory device or increased drive strength of signals used to operate the memory device, as well as other benefits that may be understood by those skilled in the art.

[0015] Initially in reference Figures 1 to 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figures 3 to 6 The features of this disclosure are described in the context of the circuit described. These and other features of this disclosure are provided by reference to [reference needed]. Figures 7 to 13 The device diagrams and flowcharts related to inductive energy harvesting and signal generation of the memory device are further illustrated and described with reference to the device diagrams and flowcharts.

[0016] Figure 1 This document describes an example of a system 100 supporting inductive energy harvesting and signal generation for a memory device, based on examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110). System 100 may illustrate one type of memory that can utilize the techniques and structures described herein; however, the techniques and structures described herein can be implemented in any type of memory.

[0017] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0018] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes within a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other examples. In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0019] Memory device 110 may be a separate device or component operable to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configurable to work with at least one or more host devices of different types. Communicating between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock communication and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0020] Memory device 110 may be operable to store data of components of host device 105. In some instances, memory device 110 may act as a slave-type device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0021] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other via bus 135.

[0022] Processor 125 may be operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0023] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of ROM, flash memory, or other non-volatile memory.

[0024] Memory device 110 may include device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package. In some cases, multiple memory dies 160 may be stacked vertically within memory device 170 to form one or more die stacks.

[0025] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0026] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data on host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0027] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the operations described for device memory controller 155 or local memory controller 165 or both.

[0028] External memory controller 120 may be operable to enable communication of one or more of the information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret the communication exchanged between a component of host device 105 and memory device 110. In some instances, the functionality of external memory controller 120, or another component of system 100 or host device 105, or as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, or another component of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0029] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0030] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed via channel 115 using single data rate (SDR) signaling or dual data rate (DDR) signaling. In SDR signaling, one modulation symbol of the signal (e.g., signal level) may be recorded for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, both modulation symbols of the signal (e.g., signal levels) may be recorded for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0031] In some instances, CA channel 186 may be operable to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the command. For example, the command carried by CA channel 186 may carry a read command with the address of the desired data. In some instances, CA channel 186 may contain any number of signal paths to decode one or more of the address and command data (e.g., eight or nine signal paths).

[0032] In some cases, memory device 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities. Channel 115 may be configured to support communication between host device 105 and memory device 110 according to associated protocols (e.g., exchanging or otherwise conveying control, address, data, and other signals between memory device 110 and host device 105). Examples of possible protocols include, but are not limited to, Serial Advanced Technology Attachment (SATA) interface, UFS interface, eMMC interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, USB interface, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), DDR, DIMM interface (e.g., DIMM socket interface supporting DDR), Open NAND Flash Interface (ONFI), Low Power Double Data Rate (LPDDR), Non-Volatile Memory High Speed ​​(NVMe) Protocol Interface, Non-Volatile Memory Host Controller Interface Specification (NVMHCIS), and the like.

[0033] In some instances, memory device 110 may include one or more inductors coupled to one or more components of memory device 110. The inductors may harvest energy, for example, based on current routed through circuitry of memory device 110. The inductors may then act as current sources based on the harvested energy. For example, the inductors may be used to provide current for various operations of memory device 110 based on the harvested energy. The inductors may harvest energy based on current routed through the inductor or based on inductive coupling with a second inductor through which the current is routed. As an example, after harvesting energy, the inductors may provide current, and the current provided by the inductors may be used to drive access lines or otherwise as part of performing one or more operations (e.g., read operations, write operations, etc.) for accessing memory array 170 of memory device 110. Such inductor-supported operations may provide benefits such as improved energy efficiency of memory device 110 or increased drive strength of signals used to operate memory device 110, and other benefits.

[0034] Figure 2 This describes an example of a memory die 200 that supports inductor energy harvesting and signal generation for a memory device, as disclosed herein. The memory die 200 may be a reference. Figure 1 An example of the memory die 160 described herein. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 illustrates one type of memory that can utilize the techniques and structures described herein; however, the techniques and structures described herein can be implemented in any type of memory.

[0035] The memory die 200 may include memory cells 205 programmable to store different states, such as memory states, which may be referred to herein as memory values. Although Figure 2 The example memory cell 205 described herein may belong to a certain type (e.g., ferroelectric memory cell), but it should be understood that memory cell 205 may belong to any type.

[0036] In some cases, memory cell 205 can be programmable to store two memory values, denoted as logic 0 and logic 1. In some cases, memory cell 205 can be programmable to store more than two memory values. Alternatively or additionally, memory cell 205 can be programmable to store memory states based on analog or random operations (e.g., related to neural networks), where memory states correspond to information other than logic 0 or logic 1. In some instances, memory cell 205 may comprise capacitive memory elements, ferroelectric memory elements, material memory elements, resistive elements, selectable memory elements, finite memory elements, or any combination thereof. In some instances, memory cell 205 (e.g., multilevel memory cells, such as flash NAND multilevel cell (MLC), three-level cell (TLC), or four-level cell (QLC)) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). Memory cell 205 may be arranged in an array, as shown in the reference. Figure 1 The memory array 170 is described.

[0037] The collection of memory cells 205 may be a portion of a memory segment of memory die 200 (e.g., comprising an array of memory cells 205), wherein in some instances, a memory segment may refer to a contiguous tile of memory cells 205 (e.g., a contiguous collection of elements of a semiconductor chip). In some instances, a memory segment may refer to a minimum collection of memory cells 205 that can be biased in an access operation, or a minimum collection of memory cells 205 sharing a common node (e.g., a common board line, a collection of board lines biased to a common voltage). Although a single memory segment of memory die 200 is shown, various embodiments of memory devices according to the examples disclosed herein may have collections of memory segments. In one illustrative example, memory die 200 or its sub-segments (e.g., the core of a multi-core memory device, the chip of a multi-chip memory device) may comprise 32 “memory banks” and each memory bank may comprise 32 segments. Thus, memory die 200 or its sub-segments according to the illustrative example may comprise 1,024 memory segments. In some instances, memory cells 205 may be connected in a serial string (e.g., in a NAND configuration), wherein the serial string may be coupled to bit line 215 or form a portion of bit line 215.

[0038] exist Figure 2As illustrated in the examples, memory cell 205 may store charge representing a programmable memory value in capacitor 240 (e.g., storing charge in a capacitor, capacitive memory element, or capacitive storage element). In one example, charged and uncharged capacitor 240 may each represent two memory values. In another example, positively charged and negatively charged capacitor 240 may each represent two memory values. In some examples, such as FeRAM architectures, memory cell 205 may include capacitor 240 having an insulating (e.g., non-conductive) layer between the terminals of the capacitor, which is made of ferroelectric material. Different levels of polarization of capacitor 240 may represent different memory values ​​(e.g., supporting two or more memory values ​​in a given memory cell 205). In some examples, the ferroelectric material has nonlinear polarization properties.

[0039] Capacitor 240 may be an example of a ferroelectric capacitor. Memory cell 205 may further include a switching assembly 245. A first node of capacitor 240 may be coupled to switching assembly 245, and a second node of capacitor 240 may be coupled to board line 220. Switching assembly 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components. In some instances, switching assembly 245 may serve as a storage component of the memory cell (e.g., capacitor 240 may not be present). For example, multiple switching assemblies 245 may be connected to each other in a serial manner (e.g., as a string, possibly in a NAND configuration), where different switching assemblies 245 correspond to (e.g., act as) individual storage elements.

[0040] In some instances, memory cell 205 may include a material portion, which may be referred to as a memory element, memory storage element, selectable memory element, or selectable memory storage element. The material portion may have variable and configurable resistance or another characteristic representing different memory values. For example, materials that may be in a crystalline or amorphous atomic configuration (e.g., capable of maintaining a crystalline or amorphous state over the ambient operating temperature range of memory die 200) may have different resistances depending on the atomic configuration. A more crystalline state of material (e.g., a single crystal, which may be a collection of relatively large, substantially crystalline grains) may have a relatively low resistance and is alternatively referred to as a “SET” memory value. A more amorphous state of material (e.g., a completely amorphous state, which may be a distribution of relatively small, substantially amorphous grains) may have a relatively high resistance and is alternatively referred to as a “RESET” memory value. Therefore, a voltage applied to such memory cell 205 may result in different currents depending on whether the material portion of memory cell 205 is in a more crystalline or more amorphous state. Therefore, the magnitude of the current generated by applying the read voltage to the memory cell 205 can be used to determine the memory value stored by the memory cell 205.

[0041] In some instances, the memory element may be configured with crystalline and amorphous regions (e.g., different degrees of atomic order and disorder) at various ratios that can produce intermediate resistance, which can represent different memory values ​​(e.g., supporting two or more memory values ​​in the corresponding memory cell 205). Additionally, in some instances, the material or memory element may have more than two atomic configurations, such as an amorphous configuration and two different crystalline configurations. Although described herein with reference to the resistance of different atomic configurations, the memory device may use another characteristic of the memory element to determine the stored memory value corresponding to an atomic configuration or combination of atomic configurations.

[0042] In some cases, a more amorphous memory element may be associated with a threshold voltage. In some instances, current may flow through a more amorphous memory element when a voltage greater than the threshold voltage is applied across it. In some instances, current may not flow through a more amorphous memory element when a voltage less than the threshold voltage is applied across it. In some cases, a more crystalline memory element may not be associated with a threshold voltage (e.g., it may be associated with a zero threshold voltage). In some instances, current may flow through a more crystalline memory element in response to a non-zero voltage applied across it.

[0043] In some cases, materials in both more amorphous and more crystalline states can be associated with threshold voltage. For example, selectable or limited memories can be based on the difference in threshold voltage between memory cells in different programming states (e.g., by means of different compositional distributions). The memory value of a memory cell 205 having such a memory element can be set by biasing or heating the memory element over time to a temperature profile that supports the formation of a specific atomic configuration or combination of atomic configurations.

[0044] Memory die 200 may comprise a three-dimensional (3D) memory array, wherein multiple two-dimensional (2D) memory arrays (e.g., stacks, hierarchies) are formed one on top of the other. In various instances, such an array may be divided into a collection of memory segments, each of which may be arranged within a stack or hierarchy, distributed across multiple stacks or hierarchies, or any combination thereof. This arrangement can increase the number of memory cells 205 that can be placed or created on a single die or substrate compared to a 2D array, which in turn can reduce manufacturing costs or increase the performance of the memory die 200, or both. Stacks or hierarchies may be separated by an electrically insulating material. Each stack or hierarchy may be aligned or positioned such that memory cells 205 can be substantially aligned with each other across each stack, thereby forming a stack of memory cells 205.

[0045] The memory die 200 may include access lines (e.g., word lines 210, bit lines 215, and board lines 220) arranged in a grid-like pattern. Access lines may be conductive lines coupled to memory cells 205 and used for accessing memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, bit lines 215 may be referred to as column lines or number lines. References to access lines, row lines, column lines, word lines, number lines, bit lines, or board lines, or the like, are interchangeable without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210, bit lines 215, and / or board lines 220. In some instances, bit lines 215 may extend at least partially in a vertical direction (e.g., in a dimension corresponding to the die height), such as in a 3D flash NAND configuration.

[0046] Memory cell 205 can be read and written by activating or selecting access lines (such as word line 210, bit line 215, and / or word line 220). Individual memory cell 205 can be accessed at their intersection by biasing word line 210, bit line 215, and board line 220 (e.g., by applying voltage to word line 210, bit line 215, or board line 220). Activating or selecting word line 210, bit line 215, or board line 220 may involve applying voltage to the respective line.

[0047] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 receives a row address from local memory controller 265 and activates word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates bit line 215 based on the received column address. Board driver 235 receives a board address from local memory controller 265 and activates board line 220 based on the received board address.

[0048] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to bit line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from bit line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to bit line 215.

[0049] In some cases (e.g., where memory cell 205 includes NAND memory cells), multiple switching components 245 may be arranged in series, each corresponding to a different memory cell 205, and selection can be achieved by placing some switching components 245 in a bypass mode via their control gate and by sensing the conductivity state of one or more other switching components 245 (which are not in a bypass mode). Furthermore, when sensing the conductivity state of a memory cell 205 selected in this manner (e.g., switching component 245), a search (e.g., scan) for a threshold voltage of the selected memory cell 205 can be performed. For example, the voltage at which the transition from a non-conductive state to a conductive state (or vice versa) occurs in the selected memory cell 205 can be used to determine the logic value stored by the memory cell 205.

[0050] Word line 210 may be a wire electrically connected to the memory cell 205 for accessing the memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of a switching component 245 of the memory cell 205 and may be operable to control the switching component 245 of the memory cell. In some architectures, word line 210 may be electrically connected to the node of a capacitor in the memory cell 205, and the memory cell 205 may not include a switching component. In some architectures, word line 210 may be electrically connected to the switching component 245, and the switching component 245 may serve as a storage component of the memory cell 205 (e.g., based on the amount of charge present or absent in the floating gate contained in the switching component 245).

[0051] Bit line 215 may be a wire connecting memory cell 205 to sensing component 250. In some architectures, memory cell 205 may be selectively coupled to bit line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be operable to selectively couple and / or isolate capacitor 240 of memory cell 205 and bit line 215. In some architectures, memory cell 205 may be electrically connected to bit line 215 (e.g., constantly).

[0052] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the memory value of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output of memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 via bit line 215 with reference 255 (e.g., reference voltage). The detected memory value of memory cell 205 can be provided as an output of sensing component 250 (e.g., provided to input / output 260) and can indicate the detected memory value to another component of memory device 110 including memory die 200.

[0053] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may be located in the same location as the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target bit line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0054] The local memory controller 265 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, activation operations, erase operations, or programming operations, and others. In some instances, access operations may be performed by the local memory controller 265 in response to various access commands (e.g., from host device 105) or otherwise coordinated by the local memory controller 265. The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0055] The local memory controller 265 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmable to store a desired memory value. The local memory controller 265 can identify the target memory cell 205 on which a write operation will be performed. The local memory controller 265 can identify target word lines 210, target bit lines 215, and target board lines 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word lines 210, target bit lines 215, and target board lines 220 (e.g., apply a voltage to word lines 210, bit lines 215, or board lines 220) to access the target memory cell 205. The local memory controller 265 can apply a specific signal (e.g., a write pulse) to bit line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. The pulse used for the write operation may contain one or more voltage levels over a duration.

[0056] The local memory controller 265 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During a read operation, a memory value stored in the memory cell 205 of the memory die 200 can be determined. The local memory controller 265 can identify a target memory cell 205 on which a read operation will be performed. The local memory controller 265 can identify a target word line 210, a target bit line 215, and a target board line 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word line 210, the target bit line 215, and the target board line 220 (e.g., by applying a voltage to the word line 210, the bit line 215, or the board line 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 250 in response to a bias access line. The sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the memory value stored in the memory cell 205.

[0057] In some instances, memory die 200 may include or be coupled to one or more inductors. For example, inductors may be coupled to one or more components of memory die 200. Inductors may harvest energy, for example, based on current routed through components of memory die 200 (e.g., row decoder 225, column decoder 230, board driver 235, sensing component 250, etc.). Inductors may then act as current sources based on the harvested energy. For example, inductors may be used to provide current for various operations of memory die 200 based on the harvested energy. Inductors may harvest energy based on current routed through the inductor or based on inductive coupling with a second inductor through which the current is routed. After harvesting energy, the inductor can provide current, which can be used to drive access lines (e.g., word lines 210, bit lines 215, board lines 220, etc.) or otherwise as part of performing one or more operations (e.g., read operations, write operations, programming operations, etc.) for accessing the memory array of the memory die 200. Such inductor-supported operations can provide benefits such as improved energy efficiency of the memory die 200 or increased drive strength of signals used to operate the memory die 200, as well as other benefits.

[0058] Figure 3 This describes an example of a circuit 300 supporting inductor energy harvesting and signal generation for a memory device, as disclosed herein. In some examples, circuit 300 may include, as referenced... Figure 1 and 2The described memory die or memory device refers to one or more aspects. For example, each circuit 300 may include one or more components 325, wherein each component 325 may include memory array 170 or one or more portions of memory array 170, as referenced. Figure 1 and 2 As described.

[0059] In some instances, component 325 may represent the word line used for the selected word line (e.g., as referenced). Figure 2 The gate of the access transistor or driver for the described word line 210. Alternatively, component 325 may represent a set of bit lines coupled to a memory cell (e.g., as described in reference 210). Figure 2 The bit line 215 described is coupled to memory cell 205.

[0060] Circuit 300-a can be coupled to a power source (e.g., an external power supply for a memory die) via power pins 305-a and 305-b and ground pins 310-a and 310-b. Power pins 305-a and 305-b can be coupled to distributor 320-a. For example, power pin 305-b can be directly coupled to distributor 320-a, and power pin 305-a can be coupled to distributor 320-a via inductor 315-a. Inductor 315-a can harvest energy based on the current flowing through it along the route from power pin 305-a to distributor 320-a.

[0061] Distributor 320-a (e.g., a switching assembly, which may refer to a component containing one or more switches and operable to selectively couple and decouple two or more nodes) can switch the connection of components 325-a and 325-b. For example, distributor 320-a can initially route current to component 325-a via inductor 315-a. Based on the routed current, inductor 315-a can receive and harvest energy. Distributor 320-a can switch the connection of component 325-a such that current is routed to component 325-a from a direct connection to power pin 305-b. Distributor 320-a can additionally route current to component 325-b based on the energy harvested in inductor 315-a. Inductor 315-a can continue to deliver current based on the harvested energy. Therefore, based on the switching, component 325-b can receive a current boost from the controlled amount of charge provided by inductor 315-a.

[0062] In some instances, the switching at distributor 320-a can be dynamic, based on non-overlapping power boost requirements for components 325-a and 325-b. That is, components 325-a and 325-b can provide current boost to each other via distributor 320-a. In some instances, the current boost can represent the ratio of a portion of the current received from inductor 315-a to a portion of the current received from power pin 305-b. This ratio can be dynamically changed or controlled by a power controller or distributor (such as distributor 320-a). In some instances, each component 325 can operate in at least one of two modes, which can be referred to as a power demand mode and a power supply mode. In the power supply mode, component 325 can power inductor 315-a, for example, by sensing current flowing through inductor 315-a, which can harvest and store energy in the form of current. In a power demand mode, component 325 may be coupled to one or more inductors 315 (e.g., including inductor 315-a) containing harvested and stored energy, thus providing energy to component 325 based on the coupling. Each component 325 may provide a signal to a power controller, wherein the signal delivers and requests the mode (e.g., power demand mode or power supply mode). The power controller or distributor may thus provide coupling with inductors 315. For example, an inductor 315 with depleted energy may be coupled to component 325 in a power supply mode, and an inductor with harvested or stored energy may be coupled to component 325 in a power demand mode. In some instances, circuit 300-a may include an additional component 325 (not shown) coupled to an additional inductor 315 (not shown) via distributor 320-a to provide an additional non-overlapping opportunity window for boosting the current to component 325.

[0063] An alternative configuration is illustrated in circuit 300-b, wherein inductor 315-b and distributor 320-b may be coupled to ground pins 310-c and 310-d. In an example where component 325 represents a bit line coupled to a memory cell, circuit 300-a may implement current boosting via inductor 315-a and distributor 320-a, wherein current boosting enables components 325-a and 325-b (e.g., bit lines) to efficiently deposit positive charges onto the memory cell. Similarly, circuit 300-b may implement current boosting via inductor 315-b and distributor 320-b, wherein current boosting enables components 325-c and 325-d to efficiently deposit negative charges onto the memory cell.

[0064] In some instances, circuits 300-a and 300-b can be combined to provide a current boost for depositing positive or negative charges onto memory cells. Such a combined circuit (not shown) may include a first set of distributors 320 (e.g., one or more of distributors 320) and a first set of inductors 315 coupled to a set of power pins 305, and a second set of distributors 320 and a second set of inductors 315 coupled to a set of ground pins 310. The set of inductors 315 can harvest energy from current spikes in the power supply at power pins 305 and ground pins 310 via electromagnetic induction.

[0065] The inductor 315 described herein can be located at various locations within the system. In some instances, the inductor 315 may be contained within a memory die (e.g., as referenced). Figure 2 The memory die 200 described herein, or the inductor 315 may be included in the memory package (e.g., as referenced). Figure 1 The inductor 315 is located in the described memory device 110, but not on the same die as other parts of the circuit 300. Alternatively, the inductor 315 may be external to the memory package, but coupled to a portion of the circuit 300. For example, the inductor 315 may be located on the printed circuit board (PCB) to which the memory package is mounted.

[0066] In some instances, the inductor 315 of circuit 300 may be coupled to a capacitive element (e.g., a capacitive element of a memory device or memory array) to store charge based on the harvested energy. The stored charge can be used, for example, to boost current to component 325 based on commands from the memory controller of the memory device.

[0067] In some instances, inductor 315 may be coupled to distributor 320 at two nodes. A first node may correspond to a first end of inductor 315, and a second node may correspond to a second end of inductor 315. Distributor 320 may couple component 325 to the first node to provide a current boost in a first current direction, or distributor 320 may couple component 325 to the second node to provide a current boost in a second current direction, where the second current direction may be the reverse of the first current direction. Therefore, an inductor 315 at a single pin (e.g., power pin 305 or ground pin 310) allows component 325 (e.g., a bit line) to efficiently deposit charges of positive or negative values ​​onto memory cells.

[0068] Figure 4 This describes an example of a circuit 400 supporting inductor energy harvesting and signal generation for a memory device, as disclosed herein. In some examples, circuit 400 may include components as described in the references. Figure 1 and 2The described memory die or memory device refers to one or more aspects. For example, each circuit 400 may include one or more components 425, wherein each component 425 may include memory array 170 or one or more portions of memory array 170, as referenced. Figure 1 and 2 As described.

[0069] In some instances, component 425 may represent the word line used for the selected word line (e.g., as referenced). Figure 2 The gate of the access transistor or driver for the described word line 210. Alternatively, component 425 may represent a set of bit lines coupled to a memory cell (e.g., as described in reference 210). Figure 2 The bit line 215 described is coupled to memory cell 205.

[0070] Circuit 400-a can be coupled to a power source (e.g., an external power source) via power pins 405-a and 405-b and ground pins 410-a and 410-b. Power pins 405-a and 405-b can be coupled to components 425-a and 425-b. For example, power pin 405-b can be directly coupled to component 425-b, and power pin 405-a can be coupled to component 425-a via inductor 415-a. Inductor 415-a can harvest energy based on the current flowing through it along the route from power pin 405-a to component 425-a. In some instances, inductor 415-a can be included within power pin 405-a, or inductor 415-a can be used to generate an electromagnetic field that can be coupled to power pin 405-a. This configuration may eliminate the need for energy harvesting at inductor 415-a.

[0071] Inductor 415-a may be inductively coupled to inductor 415-b. For example, each of inductors 415-a and 415-b may include wire wound around shaft 430-a in a coil. Alternatively or additionally, inductors 415-a and 415-b may include material configured to enhance the generation of an electromagnetic field for coupling inductor 415. Inductor 415-a may be located very close to inductor 415-b. When a routed current passes through inductor 415-a, the routed current may generate a magnetic field around the coiled wire of inductor 415-a. The magnetic field around inductor 415-a may pass through the coiled wire of inductor 415-b, which may induce a voltage or current in inductor 415-b. Inductor 415-b may thus act as a voltage or current source for component 425-b. For example, inductor 415-b can boost current to component 425-b when acting as a voltage source.

[0072] In some instances, energy harvested at inductor 415 can be stored in the magnetic field of the wire surrounding inductor 415. Alternatively, inductor 415 of circuit 400 can be coupled to a capacitive element (e.g., a capacitive element of a memory device or memory array) to store charge based on the harvested energy. The stored charge or energy in the magnetic field can be used, for example, to boost current to component 425 based on commands from the memory controller of the memory device.

[0073] An alternative configuration is illustrated in circuit 400-b, wherein inductor 415-c may be coupled to ground pin 410-c. Inductor 415-c may be inductively coupled to inductor 415-d, which in some cases may act as a voltage or current source for component 425-d. In an example where component 425 represents a bit line coupled to a memory cell, circuit 400-a may implement current boosting via inductor 415-a or inductor 415-b, wherein current boosting enables components 425-a and 425-b (e.g., bit lines) to efficiently deposit positive charges onto the memory cell. Similarly, circuit 400-b may implement current boosting via inductor 415-c or inductor 415-d, wherein current boosting enables components 425-c and 425-d to efficiently deposit negative charges onto the memory cell.

[0074] In some instances, circuits 400-a and 400-b can be combined to provide a current boost for depositing positive or negative charges onto memory cells. This combined circuit (not shown) may include a first set of inductors 415 (e.g., one or more of inductors 415) coupled to a set of power pins 405, and a second set of inductors 415 coupled to a set of ground pins 410. The set of inductors 415 can harvest energy from current spikes in the power supply at power pins 405 and ground pins 410 via electromagnetic induction. Multiple current spikes in a chip (which may contain one or more circuits 400) can generate fluctuations in the electromagnetic field, which can lead to electromagnetic interference (EMI) in various blocks and components (e.g., component 425) inside or outside the chip (or both). Therefore, EMI can induce unwanted parasitic electromagnetic coupling within components. This can pose challenges in chip designs aimed at reducing EMI. By providing inductive coupling at each power pin 405, the electromagnetic field can be reduced and converted into an additional energy source. Therefore, the techniques described herein can result in an overall reduction in electromagnetic interference beyond energy harvesting. In some instances, instead of one-to-one inductive coupling between inductors 415 (e.g., inductive coupling between inductor 415-a and inductor 415-b), it is possible to reduce electromagnetic interference by routing inductors 415 (e.g., on the chip surface, around the chip, and other instances) to couple fewer secondary inductors 415 to power pin 405.

[0075] The inductor 415 described herein can be located at various locations within the system. In some instances, the inductor 415 may be contained within a memory die (e.g., as referenced). Figure 2 The memory die 200 described herein, or the inductor 415 may be included in the memory package (e.g., as referenced). Figure 1 The inductor 415 is located in the described memory device 110, but not on the same die as the rest of the circuit 400. Alternatively, the inductor 415 may be external to the memory package, but coupled to a portion of the circuit 400. For example, the inductor 415 may be located on the PCB to which the memory package is mounted.

[0076] In some instances, inductor 415 may be coupled to component 425 at two nodes 435. For example, node 435-a may correspond to a first end of inductor 415-b, and node 435-b may correspond to a second end of inductor 415-b. Inductor 415-b may be selectively configured to route current in a first current direction (e.g., from node 435-a to node 435-b) or in a second current direction (e.g., from node 435-b to node 435-a). Thus, inductor 415b may be configured to efficiently deposit charges of positive or negative values ​​onto memory cells coupled to component 425-b. Similarly, inductor 415-d may be coupled to component 425-d at nodes 435-c and 435-d, wherein inductor 415-d may be configured to efficiently deposit charges of positive or negative values ​​onto memory cells coupled to component 425-d.

[0077] Figure 5 This describes an example of a circuit 500 supporting inductor energy harvesting and signal generation for a memory device, as disclosed herein. In some examples, circuit 500 may include components as described in the references. Figure 1 and 2 The described memory die or memory device refers to one or more aspects. For example, circuit 500 may include one or more memory cells 525, wherein memory cells 525 may be included in one or more memory arrays 170, as referenced. Figure 1 and 2 As described.

[0078] Circuit 500 may be coupled to a power source (e.g., an external power source) via power pin 505 and ground pins 510-a and 510-b. Circuit 500 may be coupled to an additional voltage source via nodes 506-a and 506-b. In some instances, node 506-a may be coupled to a first voltage source having a first voltage level, and node 506-b may be coupled to a second voltage source having a second voltage level different from the first voltage level. Alternatively, node 506-a may be referred to as a pull node, and node 506-b may be referred to as a push node. The voltage level of node 506 may be configured to pull or push negative or positive charges through components of circuit 500. Node 506 may be coupled to distributor 520-a (e.g., a switching assembly).

[0079] Inductor 515-a can be coupled to power pin 505 and ground pin 510-b via acceleration circuit system 545. In some instances, acceleration circuit system 545 may include a current source. Alternatively, acceleration circuit system may include, as referenced... Figure 1 and 2 The described memory die or one or more components of the memory device. Inductor 515-a can harvest energy based on the current routed through inductor 515-a by acceleration circuit system 545.

[0080] Inductor 515-a may be inductively coupled to inductor 515-b. For example, each of inductors 515-a and 515-b may contain wire wound around shaft 530-a in a coil. Inductor 515-a may be located very close to inductor 515-b. When a routed current passes through inductor 515-a, the routed current can generate a magnetic field around the coiled wire of inductor 515-a. The magnetic field around inductor 515-a can pass through the coiled wire of inductor 515-b, which can induce a voltage in inductor 515-b.

[0081] The inductor 515 described herein can be located at various locations within the system. In some instances, the inductor 515 may be contained within a memory die (e.g., as referenced). Figure 2 The memory die 200 described herein, or the inductor 515 may be included in the memory package (e.g., as referenced). Figure 1 The inductor 515 is located in the described memory device 110, but not on the same die as other parts of the circuit 500. Alternatively, the inductor 515 may be external to the memory package, but coupled to a portion of the circuit 500. For example, the inductor 515 may be located on the PCB to which the memory package is mounted.

[0082] Inductor 515-b may be coupled to switching circuit systems 540-a and 540-b. Switching circuit systems 540-a and 540-b may be configured to selectively couple either node of inductor 515-b to distributor 520-a and the other node of inductor 515-b to distributor 520-b, such that inductor 515-b can provide a boost current (e.g., based on an induced voltage attributable to the inductive coupling with inductor 515-a) flowing in a first current direction (e.g., from switching circuit system 540-a to switching circuit system 540-b) or a second current direction (e.g., from switching circuit system 540-b to switching circuit system 540-a) to efficiently provide energy or charge to another component of circuit 500. For example, distributor 520-a may include a capacitor plate on which charge may be deposited based on a boost current from inductor 515-b. In another example, inductor 515-b can boost current to distributor 520-b. Distributor 520-b may include a collection of sense amplifiers 550 coupled to memory cell 525. In some examples, inductor 515-b can boost current to memory cell 525 during operations performed at the memory device, such as read operations, write operations, etc.

[0083] In some instances, circuit 500 may be configured to perform read operations on memory cell 525-a. Inductor 515-b can provide a current boost, allowing charge stored in memory cell 525-a to be transferred via distributor 520-b, wherein inductor 515-b can be coupled to node 506-a via distributor 520-a (e.g., pull node). Sensing amplifier 550-a in distributor 520-b can sense the charge during transfer to determine the memory value stored in memory cell 525-a. In some instances, the transferred charge may be deposited on the capacitor plate of distributor 520-a, whereby the charge can be reused for subsequent operations of circuit 500.

[0084] After the charge is transferred, the direction of the current through inductor 515-b can be electrically reversed using the switching circuitry systems 540-a and 540-b. In some instances, distributor 520-a can decouple inductor 515-b from node 506-a and couple inductor 515-b to node 506-b (e.g., by pushing the node). Based on the reversal and coupling, the current in inductor 515-b can flow through sense amplifier 550-a to memory cell 525-a to restore the charge in memory cell 525-a as part of the write-back operation. In this way, the energy spent on the read operation can be partially reused for the write-back operation.

[0085] In some instances, memory cells 525 may belong to different rows of the memory array. Multiple inductors 515 may be associated with distributor 520-b (e.g., row buffers or row decoders, such as those mentioned in the reference). Figure 2 The described line decoder 225 is coupled (e.g., multiplexed) such that during operations performed at the memory device (e.g., read operations, write operations, etc.), a single inductor 515 (e.g., inductor 515-b) can be coupled to a single memory cell (e.g., memory cell 525-a).

[0086] In some instances, inductor 515-b may be selectively coupled to a plurality of memory cells 525 (e.g., memory cells 525-a to 525-n) via distributor 520-b. The memory cells may store different types of data. For example, memory cells 525-a to 525-b may store memory values ​​as positive charges, and memory cell 525-n may store memory values ​​as negative charges. Distributor 520-b may selectively couple inductor 515-b to memory cells 525 that store the same type of data to prevent previously sensed different types of data from canceling each other out at sense amplifier 550. In an instance read operation, distributor 520-b may couple inductor 515-b to memory cells 525-a and 525-b to transfer positive charge through sense amplifiers 550-a and 550-b to determine a memory value, and then decouple inductor 515-b from memory cells 525-a and 525-b and couple inductor 515-b to memory cell 525-n to transfer negative charge through sense amplifier 550-n to determine a memory value.

[0087] In some instances, distributor 520-b may use sense amplifier 550 to separate memory cell 525 based on the stored memory value. For example, distributor 520-b may provide a reference data value to sense amplifier 550 by coupling sense amplifier 550 to a common wire or bus (not shown). In some instances, the reference data value may be a +1 value, a -1 value, or another value corresponding to identifiable data. Based on the reference data value, distributor 520-b may configure sense amplifier 550 to pass the memory value of memory cell 525 to inductor 515-b during operation when the memory value equals the reference data value. In some instances, distributor 520-b may provide multiple reference data values ​​to sense amplifier 550. For example, memory cell 525 may be a multi-state memory cell, wherein each memory cell 525 may be configured to store multiple memory values ​​simultaneously.

[0088] In some instances, such as reference Figure 2The access line of the described word line 210 can be activated to couple memory cell 525 to sense amplifier 550. Based on the activated access line, sense amplifier 550 can amplify data stored in memory cell 525 and transfer charge from memory cell 525 storing a memory value that matches a reference data value to inductor 515-b. In some instances, sense amplifier 550 coupled to memory cell 525 storing a memory value that does not match a reference data value can retain, amplify, and isolate charge transferred from memory cell 525. For example, sense amplifier 550 can perform a write-back operation to recover charge transferred from memory cell 525.

[0089] In some instances, the potential across inductor 515-b, attributed to the charge transferred from memory cell 525 via sensing amplifier 550, can induce a current through inductor 515-b. The intensity of the induced current can be based on the number of coupled memory cells 525 and the memory value they store. The current through inductor 515-b can be increased to a peak value, and the direction of the current through inductor 515-b can be reversed to direct the current back to the coupled sensing amplifier 550. Alternatively, distributor 520-b can couple inductor 515-b to a second set of sensing amplifiers 550 and can direct current to memory cells 525 corresponding to the second set of sensing amplifiers 550 as part of an operation performed at the memory device. In some instances, node 506 or inductive coupling with inductor 515-a can be used to enhance the current through inductor 515-b. In some instances, the induced current in inductor 515-b can be used for other operations at the memory device, such as analog or mixed-signal calculations (e.g., analog group counting).

[0090] Figure 6 This describes an example of a circuit 600 supporting inductor energy harvesting and signal generation for a memory device, as disclosed herein. In some examples, circuit 600 may include components as described in the references. Figure 1 and 2 The described memory die or memory device refers to one or more aspects. For example, circuit 600 may include one or more memory cells 625, wherein memory cells 625 may be included in one or more memory arrays 170, as referenced. Figure 1 and 2 As described.

[0091] Circuit 600 may be coupled to a ground reference (e.g., the ground of a memory device or memory array) via ground pin 605. Circuit 600 may be coupled to an additional voltage source via nodes 606-a and 606-b. In some instances, node 606-a may be coupled to a first voltage source having a first voltage level, and node 606-b may be coupled to a second voltage source having a second voltage level different from the first voltage level. Alternatively, node 606-a may be referred to as a pull node, and node 606-b may be referred to as a push node. The voltage level of node 606 may be configured to pull or push negative or positive charges through components of circuit 600. Nodes 606-a and 606-b may be coupled to distributor 620-a (e.g., a switching assembly). In some instances, circuit 600 may also be coupled to an additional voltage source via nodes 606-c and 606-d, wherein node 606-c may be coupled to a first voltage source, and node 606-d may be coupled to a second voltage source. Nodes 606-c and 606-d can be coupled to distributor 620-b.

[0092] Distributor 620-a may be coupled to inductor 615-a, which may be coupled to switching circuit systems 640-a and 640-b. Switching circuit systems 640-a and 640-b may be configured to selectively couple either node of inductor 615-a to distributor 620-a and another node of inductor 615-a to distributor 620-c, such that inductor 615-a may provide a current boost in a first current direction (e.g., from switching circuit system 640-a to switching circuit system 640-b) or a second current direction (e.g., from switching circuit system 640-b to switching circuit system 640-a) to efficiently deposit charge onto another component of circuit 600. For example, distributor 620-a may include a capacitor plate on which charge may be deposited based on a current boost from inductor 615-b. In some instances, circuit 600 may also include an inductor 615-b coupled to distributor 620-b and switching circuit systems 640-c and 640-d. In some instances, inductor 615-b and distributor 620-b may be used additionally or alternatively to implement the operation described herein, which includes inductor 615-a and distributor 620-a.

[0093] The inductor 615 described herein can be located at various locations within the system. In some instances, the inductor 615 may be contained within a memory die (e.g., as referenced). Figure 2 The memory die 200 described herein, or the inductor 615 may be included in the memory package (e.g., as referenced). Figure 1The inductor 615 is located in the described memory device 110, but not on the same die as the rest of the circuit 600. Alternatively, the inductor 615 may be external to the memory package, but coupled to a portion of the circuit 600. For example, the inductor 615 may be located on the PCB to which the memory package is mounted.

[0094] In some instances, inductor 615-a may boost current to distributor 620-c. Distributor 620-c may include a collection of sense amplifiers 650 coupled to memory cell 625. In some instances, inductor 615-a may boost current to memory cell 625 during operations performed at the memory device, such as read operations, write operations, etc.

[0095] In some instances, circuit 600 may be configured to perform read operations on memory cell 625-a. Inductor 615-a may provide a current boost, allowing charge stored in memory cell 625-a to be transferred to inductor 615-a via distributor 620-c, wherein inductor 615-a may be coupled to node 606-a (e.g., pull node) via distributor 620-a. Sensing amplifier 650-a in distributor 620-c may sense the charge during the transfer to determine the memory value stored in memory cell 625-a. In some instances, the transferred charge may be deposited on the capacitor plate of distributor 620-a, whereby the charge may be reused for subsequent operations of circuit 600.

[0096] After the charge is transferred, the direction of the current through inductor 615-a can be flipped using the switching circuitry 640-a and 640-b. In some instances, distributor 620-a can decouple inductor 615-a from node 606-a and couple inductor 615-a to node 606-b (e.g., by pushing the node). Based on the flipping and coupling, the current in inductor 615-a can flow to memory cell 625-a via sensing amplifier 650-a to restore the charge in memory cell 625-a as part of the write-back operation. In this way, the energy spent on the read operation can be partially reused for the write-back operation.

[0097] In some instances, memory cells 625 may belong to different rows of the memory array. Multiple inductors 615 may be associated with a distributor 620-c (e.g., a row buffer or row decoder, as shown in the reference). Figure 2 The described line decoder 225 is coupled (e.g., multiplexed) such that during operations performed at the memory device (e.g., read operations, write operations, etc.), a single inductor 615 (e.g., inductor 615-a) can be coupled to a single memory cell (e.g., memory cell 625-a).

[0098] In some instances, inductor 615-a may be selectively coupled to a plurality of memory cells 625 via distributor 620-c. The memory cells may store different types of data. For example, memory cell 625-a may store a memory value as a positive charge, and memory cell 625-b may store a memory value as a negative charge. Distributor 620-c may selectively couple inductor 615-a to memory cells 625 storing the same type of data to prevent previously sensed different types of data from canceling each other out at sense amplifier 650. In an instance read operation, distributor 620-c may couple inductor 615-a to memory cell 625-a to transfer a positive charge through sense amplifier 650-a to determine a memory value, then decouple inductor 615-a from memory cell 625-a and couple inductor 615-a to memory cell 625-b to transfer a negative charge through sense amplifier 650-b to determine a memory value.

[0099] In some instances, the allocator 620-c may use a sense amplifier 650 to separate memory cells 625 based on the stored memory values. For example, each sense amplifier 650 may be coupled to a read reference (R_Ref) node 645 and a write reference (W_Ref) node 655.

[0100] In a read operation, distributor 620-c can provide a read reference value to each sense amplifier 650 by coupling R_Ref node 645 to a common wire or bus (not shown). In some instances, the read data value may be a +1 value, a -1 value, or another value corresponding to identifiable data. Alternatively, the read reference value may correspond to a voltage offset value. Based on the read data value, distributor 620-c can configure sense amplifier 650 to pass the memory value of memory cell 625 to inductor 615-a during a read operation when the memory value equals the read data value. For example, the read reference value may enable sense amplifier 650 to detect one or more bit lines (e.g., reference lines). Figure 2 The described state of interest at bit line 215) is a memory cell 625 that identifies and stores a memory value equal to a read reference value. Alternatively, the read reference value can provide a drive voltage to power inductor 615-a after the state of interest at the bit line is detected.

[0101] In some instances, word line 630 (e.g., as referenced) Figure 2The described word line 210 can be activated to couple memory cell 625 to sense amplifier 650 via transistor 635. Based on the activation of word line 630, sense amplifier 650 can amplify data stored in memory cell 625 and transfer charge from memory cell 625 storing a memory value that matches a reference value to inductor 615-a. In some instances, sense amplifier 650 coupled to memory cell 625 storing a memory value that does not match a reference value can retain, amplify, and isolate charge transferred from memory cell 625.

[0102] In some instances, the sensing amplifier 650 may be configured to detect one or more states at the memory cell 625. For example, the sensing amplifier 650 may be configured to detect states higher than or lower than a read reference value. Alternatively, each sensing amplifier 650 may be configured with a unique read reference value, which enables the sensing amplifier 650 to detect whether the memory cell 625 contains a pattern encoded as a sequence of memory values. The sensing amplifier 650 may be further configured to detect at the sensing amplifier 650 whether the memory cell 625 contains a pattern of sets higher than or lower than the read reference value.

[0103] Similarly, in a write operation, allocator 620-c can provide a write reference value to the set of sense amplifiers 650 by coupling W_Ref node 645 to a common wire or bus (not shown). Based on the write reference value, allocator 620-c can configure the set of sense amplifiers 650 to write memory values ​​to corresponding memory cells 625, for example, using current boost from inductor 615-a. In some instances, the write operation can be part of a write-back operation, where allocator 620-c can select the set of sense amplifiers 650 based on memory cells 625 that match the read reference value used during a read operation prior to the write-back operation. In some instances, the write reference value can differ from the read reference value based on modifications according to an algorithm (such as an algorithm associated with a neural network).

[0104] In some instances, the allocator 620-c can provide multiple reference values ​​to the sense amplifier 650. For example, the allocator can provide one or more read reference values ​​via R_Ref node 645 and one or more write reference values ​​via W_Ref node 655. For example, memory cell 625 can be a multi-state memory cell, wherein each memory cell 625 can be configured to store multiple memory values ​​simultaneously.

[0105] In some instances, the distributor 620-c can achieve simultaneous reading by providing multiple read reference values ​​to the sense amplifier 650 when the word line 630 is activated. A first read reference value can be provided to the sense amplifier 650, allowing a first charge to be transferred from a first set of memory cells 625 to inductor 615-a via a set of multiplexers 660, wherein the first charge may correspond to the first read reference value. Multiplexers 660 can be configured to route current to inductor 615-a based on a first multiplexer reference value, which can be provided to multiplexers 660 via a multiplexer reference (M_Ref) node 665. The first multiplexer reference value may be based on the first read reference value.

[0106] After routing current based on a first read reference value, distributor 620-c can provide a second read reference value to sense amplifier 650. This second read reference value enables the transfer of a second charge from a second set of memory cells 625 to inductor 615-b via multiplexer 660, where the second charge may correspond to the second read reference value. Multiplexer 660 can be configured to route current to inductor 615-b based on a second multiplexer reference value, which may be based on the second read reference value. In some instances, memory values ​​can be read from both the first and second sets of memory cells 625 based on the second read reference value. In some instances, distributor 620-c can enable simultaneous writing by providing multiple write reference values ​​to sense amplifier 650 when word line 630 is activated.

[0107] Figure 7 A block diagram 700 illustrates a memory device 705 that supports inductive energy harvesting and signal generation according to an example disclosed herein. The memory device 705 may be as described in the reference... Figure 1 and 2 Examples of aspects of the described memory device or memory array. Memory device 705 may include an energy harvesting manager 710, a current routing manager 715, a component operation manager 720, a coupling component 725, a power supply manager 730, an access line manager 735, a memory value manager 740, and a sensing manager 745. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0108] The energy harvesting manager 710 can use an inductor to harvest energy associated with a memory device.

[0109] In some instances, the energy harvesting manager 710 can harvest energy associated with the corresponding current using each inductor in the inductor set during a first time interval.

[0110] In some instances, the energy harvesting manager 710 may use a second inductor to harvest energy associated with the memory device.

[0111] In some instances, the energy harvesting manager 710 may use a second inductor to harvest energy associated with a memory device, wherein the inductor is coupled to a first voltage reference and the second inductor is coupled to a second voltage reference different from the first voltage reference.

[0112] The current routing manager 715 can route current from an inductor to components of a memory device, where the routed current is based on the energy harvested using the inductor.

[0113] In some instances, the current routing manager 715 can route a second current to a second component of the memory device, wherein the second current passes through an inductor and the acquisition is based on the second current passing through the inductor.

[0114] In some instances, during a first time interval, the current routing manager 715 may route the corresponding current to each component in the set of components of the memory device, wherein the corresponding current to each component passes through the corresponding inductor in the set of inductors.

[0115] In some instances, the current routing manager 715 may route current from at least one inductor in the inductor set to a second corresponding component of the memory device during a second time interval, wherein the second time interval does not overlap with the first time interval.

[0116] In some instances, the current routing manager 715 can route a second current from the second inductor to a second access line of a memory device coupled to the second memory cell, wherein the second current is based on energy harvested using the second inductor and flows in a different direction than the current routed to the inductor.

[0117] In some instances, the current routing manager 715 can route a second current from the second inductor to components of the memory device, wherein the second current is based on energy harvested using the second inductor, and wherein reading or writing to a memory cell is based on the second current.

[0118] In some instances, the current routing manager 715 can route a second current through a second inductor, wherein the inductor is inductively coupled to the second inductor, and wherein the energy harvested using the inductor is based on a second current passing through the second inductor.

[0119] In some instances, the current routing manager 715 can route a second current through a second inductor, where the second node of the inductor is coupled to a switching assembly, wherein the inductor is inductively coupled to the second inductor.

[0120] The Component Operation Manager 720 can operate the components of the memory device based on the routed current.

[0121] Coupling component 725 can decouple the inductor from a second component of the memory device.

[0122] In some instances, the coupling component 725 can couple an inductor to a component, where routing current from the inductor to the component is based on the coupling of the inductor and the component.

[0123] In some instances, coupling component 725 may decouple the first node of the inductor from the switching component and the second node of the inductor from the node having the first voltage after routing the first current through the inductor.

[0124] In some instances, the coupling component 725 may couple a second node of the inductor to a switching component after decoupling and couple a first node of the inductor to a node having a second voltage, wherein routing current from the inductor to the component is based on coupling the second node of the inductor to the switching component; and the operation includes writing a memory value to a first memory cell or a second memory cell within the memory device.

[0125] In some instances, coupling component 725 can couple a set of memory elements in a respective memory cell of a set of memory cells to a corresponding sensing component in a set of sensing components.

[0126] In some instances, coupling component 725 can couple a set of memory elements in a respective memory cell of a set of memory cells to a corresponding sensing component in a set of sensing components.

[0127] The power supply manager 730 can determine the amount of power to be increased for components of the memory device, wherein routing current from the inductor to the components is based on the determination.

[0128] The Access Line Manager 735 can activate access lines using driver-based and route-based current.

[0129] In some instances, the access line manager 735 can read or write memory cells based on an active access line.

[0130] The memory value manager 740 can write memory values ​​to memory cells via access lines and based on routing current.

[0131] In some instances, the memory value manager 740 can write a second memory value to a second memory cell based on a second current.

[0132] In some instances, the memory value manager 740 can read memory values ​​from a first memory cell within the memory device, wherein the switching component routes a first current through an inductor based on the read memory value, and wherein the energy harvested using the inductor is based on the first current.

[0133] In some instances, the memory value manager 740 can read memory values ​​from memory cells within the memory device, wherein the switching component routes a first current through an inductor based on the read memory values, and wherein the energy harvested using the inductor is based on the first current.

[0134] In some instances, the memory value manager 740 can store charge in a capacitor based on the first current routed through the inductor, wherein the capacitor is coupled to the inductor.

[0135] In some instances, the memory value manager 740 can discharge a capacitor, wherein the operation includes writing a memory value to a memory cell or a second memory cell within the memory device based on the discharge.

[0136] In some instances, the memory value manager 740 can determine, based on a common signal, that the memory value of each of one or more memory cells is contained in a set of one or more memory values.

[0137] In some instances, the memory value manager 740 may read a second memory value from at least a second subset of the memory cell set or from the second set of memory cells based on a second set of one or more sets of sensing components of a set of coupled inductors and voltage sources associated with a second read reference voltage.

[0138] In some instances, the memory value manager 740 may write a second memory value to at least a second subset of the memory cell set or a second set of memory cells based on the nodes of the coupled inductor and one or more second sets of the switch component sets of one or more second sets of the second set of the second access line set.

[0139] In some instances, the memory value manager 740 may write a second memory value to at least a second subset of the memory cell set based on a second set of one or more sets of sensing components coupled to the second inductor and the corresponding second access line.

[0140] In some cases, memory values ​​are simultaneously written to a first set of memory cells based on energy harvested using an inductor, the first set of memory cells containing the memory cells.

[0141] In some cases, the second memory value is simultaneously written to a second set of memory cells based on the energy collected using the second inductor, the second set of memory cells containing the second memory cells.

[0142] The sensor manager 745 can bias the corresponding node of each of the sensing components in the set to the read reference voltage.

[0143] In some instances, the sensor manager 745 may use a set of one or more sensor components from the sensor component set to generate a common signal for one or more memory cells from the memory cell set based on a read reference voltage.

[0144] In some instances, the sensing manager 745 may bias a corresponding node of each of the sensing components in the set to a second read reference voltage, wherein each of the sensing components in the set is operable to couple an inductor to a voltage source associated with the second read reference voltage based on the second read reference voltage and a memory value of a corresponding memory cell.

[0145] In some instances, the sensing manager 745 may bias the corresponding input for each of the multiplexing component set to a first voltage, wherein the multiplexing component set couples the sensing component set to the inductor based on the first voltage.

[0146] In some instances, while the set of storage elements remains coupled to the set of sensing components, the sensing manager 745 may bias a corresponding node of each of the sets of sensing components to a second read reference voltage, wherein each of the sets of sensing components is operable to couple an inductor to a voltage source associated with the second read reference voltage based on the second read reference voltage and the memory value of the corresponding memory cell.

[0147] In some instances, the sensing manager 745 may bias the corresponding input for each of the multiplexing component set to a second voltage, wherein the multiplexing component set couples the sensing component set to the second inductor based on the second voltage.

[0148] In some instances, the sensing manager 745 may read a second memory value from at least a second subset of the memory cell set based on a second set of one or more of the sensing components that couple the second inductor to a voltage source associated with the second read reference voltage.

[0149] In some instances, the sensing manager 745 may bias a corresponding node of each of the sensing component sets to a write reference voltage, wherein each of the sensing component sets is operable to couple an inductor node to a corresponding memory cell based on the voltage of the inductor node and the write reference voltage, and the operation includes one or more sets of sensing components based on the coupled inductor nodes and memory cell sets writing memory values ​​to at least a subset of the memory cell set.

[0150] In some instances, the sense manager 745 may bias a corresponding node of each of the sense component sets to a second write reference voltage, wherein each of the sense component sets is operable to couple an inductor node to a corresponding memory cell based on the voltage of the inductor node and the second write reference voltage.

[0151] In some instances, the sensing manager 745 may bias the corresponding input for each of the multiplexing component set to a first voltage, wherein the multiplexing component set couples the sensing component set to the node of the inductor based on the first voltage.

[0152] In some instances, while the set of storage elements remains coupled to the set of sensing components, the sensing manager 745 can bias the corresponding node of each of the sets of sensing components to a second write reference voltage, wherein each of the sets of sensing components is operable to couple the node of an inductor to the corresponding memory cell based on the voltage of the node of the inductor and the second write reference voltage.

[0153] In some instances, the sensing manager 745 may bias the corresponding input for each of the multiplexing component set to a second voltage, wherein the multiplexing component set couples the sensing component set to the second inductor based on the second voltage.

[0154] In some cases, each of the sensing components is operable to couple an inductor to a voltage source associated with the read reference voltage based on a read reference voltage and the memory value of the corresponding memory cell.

[0155] In some cases, a common signal is generated based on a combination of one or more sensing components, including a coupled voltage source and an inductor, and energy is harvested using an inductor.

[0156] Figure 8 The illustration shows flowcharts of one or more methods 800 for inductive energy harvesting and signal generation supporting a memory device according to aspects of this disclosure. Operation of method 800 can be implemented by a memory device or its components as described herein. For example, operation of method 800 can be performed as described in reference... Figure 7 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0157] At 805, the memory device can use an inductor to harvest the energy associated with the memory device. Operation of 805 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described energy harvesting manager performs 805 operations.

[0158] At 810, the memory device can route current from the inductor to components of the memory device, where the routed current is based on the energy harvested using the inductor. Operation of 810 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 810.

[0159] At 815, the memory device can operate its components based on the routed current. Operation of 815 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs 815 operations.

[0160] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for harvesting energy associated with a memory device using an inductor, routing current from the inductor to components of the memory device, wherein the routed current is based on the energy harvested using the inductor, and the components of the memory device are operated based on the routed current.

[0161] Some examples of the methods 800 and devices described herein may further include operations, features, components, or instructions for: routing a second current to a second component of a memory device, wherein the second current passes through an inductor and capture may be based on the second current passing through the inductor; decoupling an inductor from a second component of the memory device; and coupling an inductor to a component, wherein routing current from an inductor to a component may be based on coupling an inductor to a component.

[0162] Some examples of the methods 800 and devices described herein may further include operations, features, components, or instructions for determining an amount of power to increase the power supplied to a component of a memory device, wherein routing current from an inductor to the component may be based on said determination.

[0163] In some instances of the method 800 and apparatus described herein, the inductor may be one of a set of inductors. Some instances of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: routing a corresponding current to each component of a set of components of a memory device during a first time interval, wherein the corresponding current to each component passes through a corresponding inductor in the set of inductors; harvesting energy associated with the corresponding current using each inductor in the set of inductors during the first time interval; and routing current from at least one inductor in the set of inductors to a second corresponding component of the memory device during a second time interval, wherein the second time interval may not overlap with the first time interval.

[0164] In some instances of the method 800 and apparatus described herein, components of the memory device may include drivers for access lines coupled to memory cells, and operations, features, elements, or instructions for operating components of the memory device may further include operations, features, elements, or instructions for: activating access lines using the drivers and based on routing current; and reading or writing memory cells based on the activated access lines.

[0165] In some instances of the method 800 and apparatus described herein, components of the memory device may include access lines coupled to memory cells, and operations, features, elements, or instructions for operating components of the memory device may further include operations, features, elements, or instructions for writing memory values ​​to memory cells via access lines and based on routing current.

[0166] In some instances of the method 800 and apparatus described herein, the memory cell may be charged based on a routed current. Some instances of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: harvesting energy associated with the memory device using a second inductor; routing a second current from the second inductor to a second access line of the memory device that may be coupled to the second memory cell, wherein the second current may be based on energy harvested using the second inductor and flow in a direction different from the current routed to the inductor; and writing a second memory value to the second memory cell based on the second current.

[0167] In some instances of the method 800 and device described herein, a memory value can be simultaneously written to a first set of memory cells based on energy harvested using an inductor, the first set of memory cells containing memory cells, and a second memory value can be simultaneously written to a second set of memory cells based on energy harvested using a second inductor, the second set of memory cells containing second memory cells.

[0168] Some examples of the methods 800 and devices described herein may further include operations, features, components, or instructions for: harvesting energy associated with a memory device using a second inductor, wherein the inductor may be coupled to a first voltage reference and the second inductor may be coupled to a second voltage reference different from the first voltage reference; and components for routing a second current from the second inductor to the memory device, wherein the second current may be based on the energy harvested using the second inductor, and wherein reading or writing a memory cell may be based on the second current.

[0169] Some examples of the method 800 and device described herein may further include operations, features, components, or instructions for routing a second current through a second inductor, wherein the inductor may be inductively coupled to the second inductor, and wherein the energy harvested using the inductor may be based on the second current passing through the second inductor.

[0170] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: reading a memory value from a first memory cell within a memory device, wherein a switching component routes a first current through an inductor based on reading the memory value, and wherein energy harvested using the inductor may be based on the first current; after the first current can be routed through the inductor, decoupling a first node of the inductor from the switching component and decoupling a second node of the inductor from a node having a first voltage; and after decoupling, coupling the second node of the inductor to the switching component and coupling the first node of the inductor to a node having a second voltage, wherein routing current from the inductor to the component is based on coupling the second node of the inductor to the switching component, and the operation includes writing the memory value to a first memory cell or a second memory cell within the memory device.

[0171] Some examples of the methods 800 and devices described herein may further include operations, features, components, or instructions for routing a second current through a second inductor when the second node of the inductor is coupled to a switching assembly, wherein the inductor is inductively coupled to the second inductor.

[0172] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: reading a memory value from a memory cell within a memory device, wherein a switching component routes a first current through an inductor based on reading the memory value, and wherein energy harvested using the inductor may be based on the first current; storing charge in a capacitor based on the first current routed through the inductor, wherein the capacitor may be coupled to the inductor; and discharging the capacitor, wherein the operation includes writing the memory value to a memory cell or a second memory cell within the memory device based on the discharge.

[0173] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: coupling a set of memory elements, each in a set of memory cells, to a corresponding sensing component in a set of sensing components; biasing a corresponding node of each in the set of sensing components to a read reference voltage; using a set of one or more sensing components in the set of sensing components to generate a common signal for one or more memory cells in the set of memory cells based on the read reference voltage; and determining, based on the common signal, that a memory value for each of the one or more memory cells may be included in a set of one or more memory values.

[0174] In some instances of the method 800 and device described herein, each of the sensing component sets may be operable to couple an inductor to a voltage source associated with the reading reference voltage based on a read reference voltage and a memory value of a corresponding memory cell, and using the inductor to couple the voltage source with the inductor to one or more sensing component sets may generate a common signal and harvest energy.

[0175] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: biasing a corresponding node of each of a set of sensing components to a second read reference voltage, wherein each of the set of sensing components may be operable to couple an inductor to a voltage source associated with the second read reference voltage based on the second read reference voltage and a memory value of a corresponding memory cell; and reading a second memory value from at least a second subset of a set of memory cells or from a second set of memory cells based on a second set of one or more of the set of sensing components coupled to the voltage source associated with the second read reference voltage.

[0176] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: biasing a corresponding input for each of the multiplexing component set to a first voltage, wherein the multiplexing component set couples a sensing component set to an inductor based on the first voltage; biasing a corresponding node for each of the sensing component set to a second read reference voltage while the storage element set remains coupled to the sensing component set, wherein each of the sensing component set is operable to couple an inductor to a voltage source associated with the second read reference voltage based on the second read reference voltage and a memory value of a corresponding memory cell; biasing a corresponding input for each of the multiplexing component set to a second voltage, wherein the multiplexing component set couples a sensing component set to a second inductor based on the second voltage; and reading a second memory value from at least a second subset of the memory cell set based on a second set of one or more of the sensing component sets coupling the second inductor to a voltage source associated with the second read reference voltage.

[0177] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: coupling a set of memory elements, each in a set of memory cells, to a set of sensing components; and biasing a corresponding node of each of the sets of sensing components to a write reference voltage, wherein each of the plurality of sensing components is operable to couple a node of an inductor to a corresponding memory cell based on the voltage of the node of the inductor and the write reference voltage, and operations include writing memory values ​​to at least a subset of the plurality of memory cells based on the coupling of the node of the inductor to a set of one or more of the plurality of sensing components.

[0178] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: biasing a corresponding node of each of the sets of sensing components to a second write reference voltage, wherein each of the sets of sensing components may be operable to couple a node of an inductor to a corresponding memory cell based on the voltage of the node of the inductor and the second write reference voltage; and writing a second memory value to at least a second subset of the set of memory cells or a second set of memory cells based on the coupling of the node of the inductor to one or more second sets of the set of switching components of one or more second sets of the set of second access lines.

[0179] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: biasing a corresponding input for each of the multiplexing component set to a first voltage, wherein the multiplexing component set couples the sensing component set to a node of an inductor based on the first voltage; biasing a corresponding node of each of the sensing component set to a second write reference voltage while the storage element set remains coupled to the sensing component set, wherein each of the sensing component set is operable to couple a node of an inductor to a corresponding memory cell based on the voltage of the inductor node and the second write reference voltage; biasing a corresponding input for each of the multiplexing component set to a second voltage, wherein the multiplexing component set couples the sensing component set to a second inductor based on the second voltage; and writing a second memory value to at least a second subset of the memory cell set based on a second set of one or more of the sensing component sets coupling the second inductor to a corresponding second access line.

[0180] Figure 9 The illustration includes flowcharts of one or more methods 900 for inductive energy harvesting and signal generation for supporting a memory device according to aspects of this disclosure. Operation of method 900 can be implemented by a memory device or its components as described herein. For example, operation of method 900 can be performed as described in reference... Figure 7The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0181] At 905, the memory device can route a first current to a first component of the memory device, wherein the first current passes through an inductor. Operation of 905 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 905.

[0182] At 910, the memory device can use an inductor to harvest energy associated with the memory device based on a first current passing through the inductor. Operation of 910 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The energy harvesting manager described performs the 910 operation.

[0183] At 915, the memory device can decouple the inductor from the first component of the memory device. Operation of 915 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupling component performing 915 operations.

[0184] At 920, the memory device can be coupled to the inductor and the second component. Operation of 920 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupled component performing 920 operations.

[0185] At 925, the memory device can route a second current from the inductor to the second component of the memory device based on the coupling inductor and the second component, wherein the routed second current is based on the energy harvested using the inductor. Operation of 925 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 925.

[0186] At 930, the memory device can operate a second component of the memory device based on the routed second current. Operation of 930 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs the operations of 930.

[0187] Figure 10The illustration shows a flowchart of one or more methods 1000 for inductive energy harvesting and signal generation supporting a memory device according to aspects of this disclosure. Operation of method 1000 can be implemented by a memory device or its components as described herein. For example, operation of method 1000 can be performed by, as referenced... Figure 7 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0188] At point 1005, the memory device can route a first current through a first inductor, wherein the first inductor is inductively coupled to a second inductor. Operation of point 1005 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation in 1005.

[0189] At 1010, the memory device can use a second inductor to harvest energy associated with the memory device based on a first current flowing through the first inductor. Operation of 1010 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the energy harvesting manager's operation are as follows: 1010.

[0190] At point 1015, the memory device can route a second current from the second inductor to components of the memory device, wherein the routed second current is based on energy harvested using the second inductor. Operation of point 1015 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 1015.

[0191] At 1020, the memory device can operate its components based on the routed second current. Operation of 1020 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs 1020 operations.

[0192] Figure 11 The illustration shows a flowchart of one or more methods 1100 for inductor energy harvesting and signal generation supporting a memory device according to aspects of this disclosure. The operation of method 1100 can be implemented by the memory device or its components as described herein. For example, the operation of method 1100 can be performed by, as referenced... Figure 7The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0193] At 1105, the memory device can read a memory value from a first memory cell within the memory device, wherein the switching component routes a first current through the inductor based on the read memory value. Operation of 1105 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 7 The described aspects of the memory value manager performing operation 1105.

[0194] At 1110, the memory device can harvest energy associated with the memory device using an inductor, wherein the energy is harvested based on a first current. Operation of 1110 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 7 The energy harvesting manager described performs the operations of 1110.

[0195] At 1115, the memory device may decouple the first node of the inductor from the switching assembly after routing the first current through the inductor, and decouple the second node of the inductor from the node having the first voltage. Operation of 1115 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupled component performs operation 1115.

[0196] At 1120, the memory device can, after decoupling, couple the second node of the inductor to the switching assembly and the first node of the inductor to a node having a second voltage. Operation of 1120 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupled component performing operation 1120.

[0197] At 1125, the memory device can route a second current from the inductor to components of the memory device, wherein the routed second current is based on energy harvested using the inductor. Operation of 1125 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 1125.

[0198] At 1130, the memory device can operate its components based on the routed second current. Operation of 1130 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs the operations of 1130.

[0199] Figure 12 The illustration shows a flowchart of one or more methods 1200 for inductor energy harvesting and signal generation supporting a memory device according to aspects of this disclosure. Operation of method 1200 can be implemented by a memory device or its components as described herein. For example, operation of method 1200 can be performed as described in reference... Figure 7 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0200] At 1205, the memory device can use an inductor to harvest the energy associated with the memory device. Operation of 1205 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The energy harvesting manager described performs the operations of 1205.

[0201] At 1210, the memory device can route current from the inductor to components of the memory device, where the routed current is based on energy harvested using the inductor. Operation of 1210 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 1210.

[0202] At 1215, the memory device can operate its components based on the routed current. Operation of 1215 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs the operations of 1215.

[0203] At 1220, the memory device can couple a set of memory elements within a respective memory cell of the memory cell set to a corresponding sensing element in the sensing element set. Operation of 1220 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupled component performing operation 1220.

[0204] At 1225, the memory device can bias the corresponding node of each of the sensing components in the set to a read reference voltage. Operation of 1225 can be performed according to the method described herein. In some instances, it can be achieved by, for example, a reference voltage. Figure 7 The described sensor manager performs the operation of 1225.

[0205] At 1230, the memory device may use a set of one or more sensing elements from a set of sensing elements to generate a common signal for one or more memory cells from a set of memory cells based on a read reference voltage. Operation of 1230 may be performed according to the method described herein. In some instances, it may be achieved by, for example, a reference... Figure 7 The described sensor manager performs the operations of 1230.

[0206] At 1235, the memory device can determine, based on a common signal, that the memory value of each of one or more memory cells is contained in a set of one or more memory values. Operation of 1235 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the memory value manager performing operations 1235.

[0207] Figure 13 The illustration shows a flowchart of one or more methods 1300 for inductor energy harvesting and signal generation supporting a memory device according to aspects of this disclosure. Operation of method 1300 can be implemented by a memory device or its components as described herein. For example, operation of method 1300 can be performed as described in reference... Figure 7 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0208] At 1305, the memory device can use an inductor to harvest the energy associated with the memory device. Operation of 1305 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The energy harvesting manager described performs the 1305 operation.

[0209] At 1310, the memory device can route current from the inductor to components of the memory device, where the routed current is based on energy harvested using the inductor. Operation of 1310 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspects of the current routing manager's operation of 1310.

[0210] At 1315, the memory device can couple a set of memory elements within a respective memory cell of the memory cell set to a corresponding sensing element in the sensing element set. Operation of 1315 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the coupled component performing operation 1315.

[0211] At 1320, the memory device can bias the corresponding node of each of the sensing component sets to a write reference voltage. Operation of 1320 can be performed according to the method described herein. In some instances, it can be achieved by, for example, a reference voltage. Figure 7 The described sensor manager performs 1320 operations.

[0212] At 1325, the memory device can operate its components based on the routed current. Operation of 1325 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described component operation manager performs the operations of 1325.

[0213] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0214] Describe an apparatus. The apparatus may include: a first array circuit system located within a memory device and coupled to a switching component; a second array circuit system located within the memory device and coupled to the switching component; and an inductor coupled to the switching component, wherein the switching component is operable to: couple the inductor to the first array circuit system when reading or writing to a first set of one or more memory cells coupled to the first array circuit system; and couple the inductor to the second array circuit system when reading or writing to a second set of one or more memory cells coupled to the second array circuit system.

[0215] Some examples of the device may include: a second inductor coupled to a second switching assembly, wherein the inductor may be coupled to a first voltage reference and the second inductor may be coupled to a second voltage reference different from the first voltage reference, and wherein the second switching assembly may be operable to: couple the second inductor to the first array circuitry to read or write a first set of one or more memory cells coupled to the first array circuitry; and couple the second inductor to the second array circuitry to read or write a second set of one or more memory cells coupled to the second array circuitry.

[0216] Some examples of the device may include: a second switching assembly coupled to a node configured to have a first voltage and a node configured to have a second voltage; and a switching assembly coupled to the inductor, the switching assembly, and the second switching assembly, wherein: the switching assembly is operable to switch the inductor between a first configuration and a second configuration, wherein: the first configuration includes a first node of the inductor coupled to the switching assembly and a second node of the inductor coupled to the second switching assembly; and the second configuration includes a second node of the inductor coupled to the switching assembly and a first node of the inductor coupled to the second switching assembly; and the second switching assembly may be operable to: couple the second node of the inductor to the node, the node being configured to have the second voltage when the inductor is in the first configuration; and couple the second node of the inductor to the node, the node being configured to have the first voltage when the inductor is in the second configuration.

[0217] Some examples of the device may include: a second inductor that may be coupled to the inductor and to a node inductor configured to have a third voltage, wherein the node configured to have the third voltage may be operable to increase the amount of current through the inductor based on routing current through the second inductor.

[0218] Some examples of the device may include: a sensing component, wherein: a first node of the sensing component is operable to couple with a digital line included in the first array circuit system, and wherein the sensing component is operable to selectively bias a second node of the switching component to a voltage based on a read reference voltage and the voltage of the digital line; and a third node of the sensing component is operable to couple with a word reference voltage, and wherein the sensing component is operable to selectively couple the digital line to the inductor based on the voltage of a node of the inductor and the write reference voltage.

[0219] Some examples of the device may include: a second inductor; a multiplexing component coupled to the inductor and the second inductor, wherein: the multiplexing component is operable to receive a control signal; and the multiplexing component is operable to couple a selected one of the inductor or the second inductor to the sensing component, the selected one of the inductor or the second inductor being based on a voltage of the control signal.

[0220] Describe an apparatus. The apparatus may include: a first array circuit system located within a memory device, wherein the first array circuit system includes a first set of one or more memory cells; an inductor coupled to the first array circuit system and to a first voltage reference; a second array circuit system located within the memory device, wherein the second array circuit system includes a second set of one or more memory cells; and a second inductor coupled to the second array circuit system and to a second voltage reference, wherein the second inductor is inductively coupled to the first inductor.

[0221] The information and signals described herein can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0222] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be electronically connected (or electrically contacting, connected, or coupled) to each other if there is any conductive path between them that allows the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the flow of signals between connected components for a period of time.

[0223] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, the component initially allows signals to flow between other components via conductive paths that were previously not permitted.

[0224] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller influences the conductive path used for previously permitted signal flow to prevent changes in signal flow between the components.

[0225] As used herein, the term “substantially” means that a modified characteristic (e.g., a verb or adjective modified by the term “substantially”) need not be absolute but must be close enough to obtain the advantage of the characteristic.

[0226] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0227] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0228] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0229] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0230] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0231] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0232] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributions such that portions of the functionality are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0233] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is intended to be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method implemented by a memory device, comprising: During the first time interval, the corresponding current is routed to each of the plurality of components of the memory device, wherein the corresponding current to each component passes through the corresponding inductor of the plurality of inductors; During the first time interval, energy associated with the corresponding current is harvested using each of the plurality of inductors; During a second time interval, current is routed from at least one of the plurality of inductors to a component of the memory device, wherein the second time interval does not overlap with the first time interval, and wherein the routed current is at least partially based on the energy harvested using the at least one inductor; and The components of the memory device are operated at least in part based on the current of the route.

2. The method according to claim 1, further comprising: The second current is routed to a second component of the memory device, wherein the second current passes through the at least one inductor and the acquisition is at least in part based on the second current passing through the at least one inductor; Decouple the at least one inductor from the second component of the memory device; as well as The at least one inductor is coupled to the component, wherein routing the current from the at least one inductor to the component is based at least in part on the coupling of the at least one inductor to the component.

3. The method according to claim 1, further comprising: The amount of power to be increased supplied to the components of the memory device is determined, wherein routing the current from the at least one inductor to the components is based at least in part on the determination.

4. The method of claim 1, wherein the component of the memory device includes a driver for an access line coupled to a memory cell, and wherein the operation includes: The access line is activated using the driver and at least in part based on the current of the route; as well as The memory cell is read or written at least in part based on activating the access line.

5. The method of claim 1, wherein the component of the memory device includes an access line coupled to a memory cell, and wherein the operation includes: The memory value is written to the memory cell via the access line and at least in part based on the current of the route.

6. The method of claim 5, wherein the memory cell is charged at least in part based on the current of the route, the method further comprising: A second inductor is used to harvest energy associated with the memory device; A second current is routed from the second inductor to a second access line of the memory device coupled to the second memory cell, wherein the second current is at least partially based on the energy harvested using the second inductor and flows in a direction different from the current route associated with the at least one inductor. as well as The second memory value is written to the second memory cell, at least in part, based on the second current.

7. The method according to claim 6, wherein: The memory value is simultaneously written to a first plurality of memory cells, which contain the memory cells, based at least in part on the energy collected using the inductor; and The second memory value is simultaneously written to a second plurality of memory cells, which contain the second memory cell, based at least in part on the energy collected using the second inductor.

8. The method of claim 1, further comprising: The second current is routed through the second inductor, wherein the at least one inductor is inductively coupled to the second inductor, and wherein the energy harvested using the at least one inductor is at least partially based on the second current passing through the second inductor.

9. A method implemented by a memory device, comprising: Use inductors to harvest energy associated with memory devices; A component that routes current from the inductor to the memory device, wherein the routed current is at least in part based on the energy harvested using the inductor; as well as The components of the memory device are operated at least in part based on the current of the route; A second inductor is used to harvest energy associated with the memory device, wherein the inductor is coupled to a first voltage reference and the second inductor is coupled to a second voltage reference different from the first voltage reference; as well as The second current is routed from the second inductor to the component of the memory device, wherein the second current is at least partially based on the energy harvested using the second inductor, and wherein reading or writing a memory cell is at least partially based on the second current.

10. A method implemented by a memory device, comprising: A memory value is read from a first memory cell within the memory device, wherein the switching component routes a first current through the inductor based at least in part on the read memory value; The inductor is used to harvest energy associated with the memory device, at least in part, based on the first current. After routing the first current through the inductor, the first node of the inductor is decoupled from the switching assembly and the second node of the inductor is decoupled from the node having the first voltage. After the decoupling, the second node of the inductor is coupled to the switching assembly, and the first node of the inductor is coupled to a node having a second voltage. A component that routes current from the inductor to the memory device, wherein the routed current is at least partially based on energy harvested using the inductor and at least partially based on the second node coupling the inductor to the switching component; and The components of the memory device are operated at least in part based on the current of the route, wherein the operation includes writing the memory value to a first memory cell or to a second memory cell within the memory device.

11. The method of claim 10, further comprising: When the second node of the inductor is coupled to the switching assembly, a second current is routed through the second inductor, wherein the inductor is inductively coupled to the second inductor.

12. A method implemented by a memory device, comprising: A memory value is read from a memory cell within the memory device, wherein the switching component routes a first current through the inductor based at least in part on the read memory value; The inductor is used to harvest energy associated with the memory device, at least in part, based on the first current. A component that routes current from the inductor to the memory device, wherein the routed current is at least in part based on the energy harvested using the inductor; Charge is stored in a capacitor at least in part based on the first current routed through the inductor, wherein the capacitor is coupled to the inductor; Discharge the capacitor; as well as The components of the memory device are operated at least in part based on the current of the route, wherein the operation includes writing the memory value to the memory cell or to a second memory cell within the memory device, at least in part based on the discharge.

13. A method implemented by a memory device, comprising: The energy associated with the memory device is harvested using an inductor; A component that routes current from the inductor to the memory device, wherein the routed current is at least in part based on the energy harvested using the inductor; The components of the memory device are operated at least in part based on the current of the route; Multiple storage elements, each located in a corresponding memory cell of multiple memory units, are coupled to corresponding sensing components in multiple sensing components; The corresponding node of each of the plurality of sensing components is biased to the read reference voltage; At least in part based on the read reference voltage, a common signal for one or more of the plurality of memory cells is generated using a set of one or more of the plurality of sensing components. as well as The memory value of each of the one or more memory cells is determined, at least in part, based on the common signal, and is contained in a set of one or more memory values.

14. The method of claim 13, wherein: Each of the plurality of sensing components is operable to couple a corresponding inductor to a voltage source associated with the read reference voltage, at least in part based on the read reference voltage and the memory value of the corresponding memory cell; and The common signal is generated at least in part based on the set of one or more sensing components coupled to the voltage source and the inductor, and the energy is harvested using the inductor.

15. The method of claim 14, further comprising: The respective node of each of the plurality of sensing components is biased to a second read reference voltage, wherein each of the plurality of sensing components is operable to couple the inductor to a voltage source associated with the second read reference voltage based at least in part on the second read reference voltage and the memory value of the respective memory cell; as well as A second memory value is read from at least a second subset of the plurality of memory cells or from a second plurality of memory cells, based at least in part on a second set of one or more of the plurality of sensing components that couple the inductor to the voltage source associated with the second read reference voltage.

16. The method of claim 14, further comprising: The respective input of each of the set of multiplexing components is biased to a first voltage, wherein the set of multiplexing components couples the plurality of sensing components to the inductor at least in part based on the first voltage; While the plurality of storage elements remain coupled to the plurality of sensing components, the respective node of each of the plurality of sensing components is biased to a second read reference voltage, wherein each of the plurality of sensing components is operable to couple the inductor to a voltage source associated with the second read reference voltage based at least in part on the second read reference voltage and the memory value of the respective memory cell; The respective input for each of the set of multiplexing components is biased to a second voltage, wherein the set of multiplexing components couples the plurality of sensing components to the second inductor at least in part based on the second voltage; as well as The second memory value is read from at least a second subset of the plurality of memory cells, based at least in part on a second set of one or more of the plurality of sensing components that couple the second inductor to the voltage source associated with the second read reference voltage.

17. A method implemented by a memory device, comprising: The energy associated with the memory device is harvested using an inductor; A component that routes current from the inductor to the memory device, wherein the routed current is at least in part based on the energy harvested using the inductor; The components of the memory device are operated at least in part based on the current of the route; Multiple storage elements, each located in a corresponding memory cell of multiple memory units, are coupled to corresponding sensing components in multiple sensing components; as well as The corresponding node of each of the plurality of sensing components is biased to the write reference voltage, wherein: Each of the plurality of sensing components is operable to couple the node of the inductor to the corresponding memory cell based at least in part on the voltage of the node of the inductor and the write reference voltage; and The operation includes writing memory values ​​into at least a subset of the plurality of memory cells, at least in part, based on the nodes of the inductor coupled to one or more of the plurality of memory cells.

18. The method of claim 17, further comprising: The respective node of each of the plurality of sensing components is biased to a second write reference voltage, wherein each of the plurality of sensing components is operable to couple the node of the inductor to the respective memory cell based at least in part on the voltage of the node of the inductor and the second write reference voltage; as well as The second memory value is written to at least a second subset of the plurality of memory cells or to a second plurality of memory cells, based at least in part on the node of the inductor and one or more of the second sets of the plurality of second access lines.

19. The method of claim 17, further comprising: The respective input of each of the set of multiplexing components is biased to a first voltage, wherein the set of multiplexing components couples the plurality of sensing components to the node of the inductor at least in part based on the first voltage; While the plurality of memory elements remain coupled to the plurality of sensing components, the respective node of each of the plurality of sensing components is biased to a second write reference voltage, wherein each of the plurality of sensing components is operable to couple the node of the inductor to the respective memory cell based at least in part on the voltage of the node of the inductor and the second write reference voltage; The respective input for each of the set of multiplexing components is biased to a second voltage, wherein the set of multiplexing components couples the plurality of sensing components to the second inductor at least in part based on the second voltage; as well as The second memory value is written to at least a second subset of the plurality of memory cells, based at least in part on a second set of one or more of the plurality of sensing components coupled to the second inductor and the corresponding second access line.

20. A memory device comprising: The first array circuit system is located within the memory device and coupled to the switching components. A second array circuit system, located within the memory device and coupled to the switching assembly, is provided. A switching component, coupled to the inductor and the switching assembly, wherein the switching component is operable to switch the inductor between a first configuration associated with a second voltage and a second configuration associated with the first voltage, and The inductor is coupled to the switching assembly, wherein the switching assembly is operable to: When reading or writing to a first set of one or more memory cells coupled to the first array circuit system, the inductor is coupled to the first array circuit system; as well as When reading or writing to a second set of one or more memory cells coupled to the second array circuit system, the inductor is coupled to the second array circuit system.

21. The memory device of claim 20, further comprising: A second inductor coupled to a second switching assembly, wherein the inductor is coupled to a first voltage reference and the second inductor is coupled to a second voltage reference different from the first voltage reference, and wherein the second switching assembly is operable to: Couple the second inductor to the first array circuit system to read or write the first set of one or more memory cells coupled to the first array circuit system; as well as The second inductor is coupled to the second array circuit system to read or write a second set of one or more memory cells coupled to the second array circuit system.

22. The memory device of claim 20, further comprising: A second switching assembly is coupled to a node configured to have the first voltage and to a node configured to have the second voltage; as well as The flip component is further coupled to the second switching component, wherein: The first configuration includes a first node of the inductor coupled to the switching assembly and a second node of the inductor coupled to the second switching assembly; and The second configuration includes a second node of the inductor coupled to the switching assembly and a first node of the inductor coupled to the second switching assembly; and The second switching assembly is operable to: When the inductor is in the first configuration, the second node of the inductor is coupled to the node configured to have the second voltage; as well as When the inductor is in the second configuration, the second node of the inductor is coupled to the node configured to have the first voltage.

23. The memory device of claim 22, further comprising: A second inductor is inductively coupled to the inductor and to a node configured to have a third voltage, wherein the node configured to have the third voltage is operable to increase the amount of current through the inductor, at least in part, by routing current through the second inductor.

24. A memory device comprising: The first array circuit system is located within the memory device and coupled to the switching components; A second array circuit system is located within the memory device and coupled to the switching assembly; An inductor coupled to the switching assembly, wherein the switching assembly is operable to: When reading or writing to a first set of one or more memory cells coupled to the first array circuit system, the inductor is coupled to the first array circuit system; as well as When reading or writing to a second set of one or more memory cells coupled to the second array circuit system, the inductor is coupled to the second array circuit system; as well as Sensing components, wherein: The first node of the sensing component is operable to couple with a digital line included in the first array circuit system, and the sensing component is operable to selectively bias the second node of the switching component to a voltage based at least in part on a read reference voltage and the voltage of the digital line; and The third node of the sensing component is operable to couple with a write reference voltage, and the sensing component is operable to selectively couple the digital line to the inductor based at least in part on the voltage of the inductor's node and the write reference voltage.

25. The memory device of claim 24, further comprising: Second inductor; as well as A multiplexing component coupled to the inductor and the second inductor, wherein: The multiplexing component is operable to receive control signals; and The multiplexing component is operable to couple a selected one of the inductors or the second inductor to the sensing component, wherein the selected one of the inductors or the second inductor is at least partially based on the voltage of the control signal.

26. A memory device comprising: A first array circuit system located within a memory device, wherein the first array circuit system comprises a first set of one or more memory cells; An inductor that is coupled to the first array circuit system and to a first voltage reference; A second array circuit system is located within the memory device, wherein the second array circuit system comprises a second set of one or more memory cells; as well as A second inductor is coupled to the second array circuit system and to a second voltage reference, wherein the second inductor is inductively coupled to the inductor.

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