Multiplexed signal development in memory devices

Abstract

This application is directed to signal development in memory devices. In one example, an apparatus according to the described techniques can include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus can further include a selection component, such as a signal development component multiplexer, coupled with the set of signal development components. The selection component can be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which can support instances of signal development during overlapping time intervals.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese invention patent application No. 201980082612.0, filed on December 5, 2019, entitled "Development of Multiplexed Signals in Memory Devices".

[0003] Cross-reference

[0004] This patent application claims priority to PCT application No. PCT / US2019 / 064597, filed December 5, 2019, entitled "Multiplexed Signal Development in a Memory Device" by Yudanov et al., which claims priority to U.S. Provisional Patent Application No. 62 / 783,388, filed December 21, 2018, also entitled "Multiplexed Signal Development in a Memory Device" by Yudanov et al., and to Yudanov et al.'s "Multiplexed Signal Development in a Memory Device" application. The present invention claims priority to U.S. Patent Application No. 16 / 700,983, filed December 2, 2019, each of which is assigned to the assignee of the present invention and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field of this invention relates to the development of multiplexed signals in memory devices. Background Technology

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming different states of the memory device. For example, a binary memory device typically has two logical states, usually represented by logic "1" or logic "0". Other memory devices can store more than two logical states. To access the stored information, components of the electronic device can read or sense the stored logical states in the memory device. To store information, components of the electronic device can write or program logical states into the memory device.

[0007] Various types of memory devices exist, including those employing magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and other types of memory. Memory devices can be volatile or non-volatile. For example, non-volatile memories such as PCM and FeRAM can maintain their stored logic state for extended periods, even without an external power supply. Volatile memory devices such as DRAM can lose their stored logic state over time unless the device is periodically refreshed by a power source. In some cases, non-volatile memories can use a similar device architecture to volatile memories, but can acquire non-volatile properties by employing physical phenomena such as ferroelectric capacitance or different material phases.

[0008] Improving memory devices can include increasing memory cell density, increasing read / write speeds, improving reliability, improving data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. In some cases, latency can vary for different components used in an access operation, or latency can otherwise vary for different parts of the access operation, which can affect the time required for the memory device to perform the access operation. Summary of the Invention

[0009] Describe a device. In some instances, the device may include: a set of memory cells; an amplifier assembly; a set of signal development components, each associated with one or more memory cells in the set of memory cells; and a selection component coupled to the set of signal development components and configured to selectively couple a selected signal development component in the set of signal development components to the amplifier assembly.

[0010] Describe a method. In some instances, the method may include: determining that a first memory cell and a second memory cell need to be accessed; coupling the first memory cell to a first signal development component during a first time interval and at least in part based on the determination that the first memory cell needs to be accessed; coupling the second memory cell to a second signal development component during a second time interval overlapping with the first time interval and at least in part based on the determination that the second memory cell needs to be accessed; coupling the first signal development component to an amplifier component during a third time interval following the first time interval; and coupling the second signal development component to the amplifier component during a fourth time interval following the second time interval.

[0011] Describe a method. In some instances, the method may include: determining that a first memory cell and a second memory cell need to be accessed; coupling a first signal development component to an amplifier component during a first time interval and at least in part based on the determination that the first memory cell needs to be accessed; coupling a second signal development component to the amplifier component during a second time interval following the first time interval and at least in part based on the determination that the second memory cell needs to be accessed; coupling the first signal development component to the first memory cell during a third time interval following the first time interval; and coupling the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0012] Describe a device. In some instances, the device may include: a set of memory cells; an amplifier assembly; a set of signal development assemblies; and a circuit system configured to: couple a first memory cell to a first signal development assembly in the set of signal development assemblies during a first time interval and at least in part based on a determination to access a first memory cell and a second memory cell in the set of memory cells; couple a second memory cell to a second signal development assembly in the set of signal development assemblies during a second time interval overlapping with the first time interval and at least in part based on the determination to access the first memory cell and the second memory cell; couple the first signal development assembly to the amplifier assembly during a third time interval following the first time interval; and couple the second signal development assembly to the amplifier assembly during a fourth time interval following the second time interval.

[0013] Describe a device. In some instances, the device may include: a set of memory cells; an amplifier assembly; a set of signal development components; and a circuit system configured to: couple a first signal development component to the amplifier assembly during a first time interval and at least in part based on a determination to access a first memory cell; couple a second signal development component to the amplifier assembly during a second time interval following the first time interval and at least in part based on a determination to access a second memory cell; couple the first signal development component to the first memory cell during a third time interval following the first time interval; and couple the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0014] Describe a device. In some instances, the device may include: a memory array; a set of signal development components, each associated with one or more access lines of the memory array; and a first set of selection components, each coupled to a subgroup of the set of signal development components and configured to selectively couple a selected signal development component in the subgroup to one of a set of amplifier components. Attached Figure Description

[0015] Figure 1 Illustrated examples of memory devices developed to support multiplexed signals, as illustrated in this article.

[0016] Figure 2 The illustrations illustrate exemplary circuits developed to support multiplexed signals, as shown in this article.

[0017] Figure 3 The illustrations illustrate exemplary circuits developed to support multiplexed signals, as shown in this article.

[0018] Figure 4A and 4B The illustration shows an example of a read operation developed based on the example of multiplexed signals as shown in this article.

[0019] Figure 5A and 5B The illustration shows an example of a write operation developed based on the example of multiplexed signals as revealed in this article.

[0020] Figure 6 The illustration shows an example of a signal development component that supports the development of multiplexed signals, as illustrated in this article.

[0021] Figure 7 The illustration shows an example of a sense amplifier developed to support multiplexed signals, as illustrated in the examples presented herein.

[0022] Figure 8 A block diagram is shown illustrating a system developed to support multiplexed signals, based on examples as disclosed herein.

[0023] Figure 9A and 9B The illustration shows an example of a component layout that supports the development of multiplexed signals, as shown in the examples presented herein.

[0024] Figure 10 A block diagram is shown illustrating a memory device developed to support multiplexed signals, based on examples as disclosed herein.

[0025] Figure 11A block diagram is shown illustrating a memory controller developed based on examples of multiplexed signals as disclosed herein.

[0026] Figure 12 A diagram illustrating a system containing devices supporting the development of multiplexed signals, based on examples as disclosed herein.

[0027] Figures 13 to 15 The flowchart illustrates a method for developing multiplexed signals in a supporting memory device based on examples as disclosed herein. Detailed Implementation

[0028] Different latency times associated with different components used in a memory access operation, or otherwise associated with portions of a memory access operation, can cause latency when performing a memory access operation. For example, when the duration of latency associated with developing a signal based on accessing a memory cell (e.g., involving an operation coupling a memory cell to a signal development component) is longer than the latency associated with generating an output signal at a sense amplifier (e.g., a latching operation at the sense amplifier), the memory device may be able to perform the output operation more quickly compared to the signal development operation. For a memory device with a single signal development component for each sense amplifier (e.g., a 1:1 mapping of the signal development component to the sense amplifier), the throughput of the memory device can therefore be limited by the latency or cycle duration associated with the signal development component or the signal development operation, which can affect latency-sensitive applications.

[0029] According to examples disclosed herein, a memory device may include multiple signal development components that can be selectively coupled or decoupled from a sense amplifier of the memory device. For example, the sense amplifier may be coupled to a selection component (e.g., a multiplexer (MUX), a transistor network, a transistor array, a switch network, a switch array), and the selection component may be coupled to a set of signal development components, each associated with one or more memory cells of the memory device. In some instances, cell access signals (e.g., cell read signals, cell write signals) may be developed (e.g., at least partially based on coupling to the respective memory cell or other access to the respective memory cell) independently of each of the other signal development components.

[0030] In some instances (e.g., during a read operation), signal development components may each be coupled to a corresponding memory cell or access line during overlapping time intervals, such that multiple cell access signals (e.g., multiple cell read signals associated with the corresponding memory cell or access line of each of the corresponding signal development components) can be generated during the overlapping time intervals. The signal development components may then be coupled to a sense amplifier via a selection component to generate a latch signal of the sense amplifier (e.g., the output signal of the sense amplifier, based on the corresponding cell access signal), which may be associated with a specific logic state stored by the corresponding memory cell (e.g., associated with the corresponding cell access signal). In instances where cell access signals have been developed at multiple signal development components, the multiple signal development components may be coupled to the sense amplifier sequentially to generate the latch signal of the sense amplifier sequentially.

[0031] In various instances (e.g., where the duration of the latency associated with the latch signal generating the sense amplifier is shorter than the latency associated with the development cell access signal), the throughput of the memory device can be improved by developing multiple cell access signals during overlapping time intervals and generating the associated latch signals sequentially (e.g., via a selection component). In other words, a sense amplifier multiplexed with multiple signal development components can be coupled to one of the signal development components while simultaneously generating or sharing signals between other signal development components and corresponding memory cells (e.g., in data transfer). In some instances, the sense amplifier can thus become free to support read, write, rewrite, or refresh operations of signal development components that are not currently involved in data transfer (e.g., with memory cells). Therefore, as disclosed herein, the memory device can include multiplexed signal development components to compensate for portions of access operations associated with different latency times, which in some instances can reduce the effects of access serialization (e.g., due to row buffer conflicts).

[0032] In one example, a method according to an example disclosed herein may include: coupling a first memory cell to a first signal development component during a first time interval; and coupling a second memory cell to a second signal development component during a second time interval overlapping with the first time interval. The method may further include: coupling the first signal development component to a sense amplifier during a third time interval following the first time interval; and coupling the second signal development component to the sense amplifier during a fourth time interval following one or both of the second time interval and the third time interval.

[0033] In another example, an apparatus according to an example disclosed herein may include a plurality of memory cells, a sense amplifier, and a plurality of signal development components. The apparatus may also include circuitry configured to couple a first memory cell of the plurality of memory cells to a first signal development component of the plurality of signal development components during a first time interval, and to couple a second memory cell of the plurality of memory cells to a second signal development component of the plurality of signal development components during a second time interval overlapping with the first time interval. The circuitry may be further configured to couple the first signal development component to the sense amplifier during a third time interval following the first time interval, and to couple the second signal development component to the sense amplifier during a fourth time interval following one or both of the second and third time intervals.

[0034] In another example, a device may include a plurality of memory cells, a sense amplifier, and a plurality of signal development components, wherein each of the plurality of signal development components is associated with one or more of the plurality of memory cells. The device may further include a selection component coupled to and configured to selectively couple any one of the plurality of signal development components to the sense amplifier.

[0035] refer to Figures 1 to 3 The features of the disclosures described above are further described in the context of memory arrays and memory circuits that support the development of multiplexed signals in memory devices. Then refer to... Figures 4A to 5B Describe a specific instance, Figures 4A to 5B The diagram illustrates specific read and write operations that support multiplexed signals in memory devices. (Reference) Figures 6 to 9B Describe other instances of circuits, components, and arrangements that can support the described operations. About Figures 10 to 15 Further description of these and other features of this disclosure, Figures 10 to 15 Illustrated diagrams, system diagrams, and flowcharts illustrating the device diagrams, system diagrams, and flowcharts supporting the development of multiplexed signals in memory devices.

[0036] Figure 1The diagram illustrates an exemplary memory device 100 developed to support multiplexed signals, as disclosed herein. The memory device 100 may also be referred to as an electronic memory device. The memory device 100 may include memory cells 105 programmable to store different logic states. In some cases, memory cells 105 may be programmable to store two logic states represented as logic 0 and logic 1. In some cases, memory cells 105 may be programmable to store more than two logic states. In some instances, memory cells 105 may include capacitive memory elements, ferroelectric memory elements, resistive elements, auto-memory elements, or combinations thereof.

[0037] The group of memory cells 105 may be part of a memory segment 110 of the memory device 100 (e.g., containing an array of memory cells 105), wherein in some instances, the memory segment 110 may refer to a continuous block of memory cells 105 (e.g., a group of continuous elements of a semiconductor chip). In some instances, the memory segment 110 may refer to a minimum group of memory cells 105 that can be biased in an access operation, or a minimum group of memory cells 105 sharing a common node (e.g., a common board line, a group of board lines biased to a common voltage). Although a single memory segment 110 of the memory device 100 is shown, various instances of the memory device according to the examples disclosed herein may have a group of memory segments 110. In one illustrative example, the memory device 100 or its sub-segments (e.g., the core of a multi-core memory device 100, the chip of a multi-chip memory device) may contain 32 “libraries” and each library may contain 32 segments. Therefore, according to the illustrative example, memory device 100 or its sub-segments may include 1,024 memory segments 110.

[0038] In some instances, memory cell 105 may store charges representing programmable logic states (e.g., storing charges in capacitors, capacitive memory elements, or other capacitive storage devices). In one instance, charged and uncharged capacitors may each represent two logic states. In another instance, positively charged and negatively charged capacitors may each represent two logic states. DRAM or FeRAM architectures may use such designs, and the capacitors employed may contain dielectric materials with linear or parapolar polarization properties as insulators. In some instances, different charge levels of the capacitors may represent different logic states (e.g., supporting more than two logic states in a given memory cell 105). In some instances, such as FeRAM architectures, memory cell 105 may include ferroelectric capacitors having ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different polarization levels of the ferroelectric capacitors may represent different logic states (e.g., supporting two or more logic states in a given memory cell 105). In some instances, the ferroelectric material has nonlinear polarization properties.

[0039] In some instances, memory cell 105 may include a material portion, which may be referred to as a memory element, memory storage element, selectable memory element, or selectable memory storage element. The material portion may have variable and configurable resistance representing different logic states. For example, materials that can take the form of a crystalline or amorphous atomic configuration (e.g., a crystalline or amorphous state capable of maintaining a crystalline or amorphous state over the operating temperature range surrounding memory device 100) may have different resistances depending on the atomic configuration. A more crystalline state of material (e.g., a single crystal, or a collection of relatively large, substantially crystalline grains) may have relatively low resistance and is alternatively referred to as a “set” logic state. A more amorphous state of material (e.g., a completely amorphous state, or a distribution of relatively small, substantially amorphous grains) may have relatively high resistance and is alternatively referred to as a “reset” logic state. Therefore, depending on whether the material portion of memory cell 105 is in a more crystalline or more amorphous state, the voltage applied to this memory cell 105 may cause different currents. Therefore, the magnitude of the current caused by applying the read voltage to the memory cell 105 can be used to determine the logic state stored by the memory cell 105.

[0040] In some instances, the memory element may be configured with various proportions of crystalline and amorphous regions (e.g., different degrees of atomic order and disorder) that can cause an intermediate resistance, which may represent different logic states (e.g., supporting two or more logic states in a given memory cell 105). Furthermore, in some instances, the material or memory element may have more than two atomic configurations, such as an amorphous configuration and two different crystalline configurations. Although described herein with reference to the resistance of different atomic configurations, the memory device may use another characteristic of the memory element to determine the stored logic states corresponding to an atomic configuration or combination of atomic configurations.

[0041] In some cases, a memory element in a more amorphous state may be associated with a threshold voltage. In some instances, current may flow through a memory element in a more amorphous state when a voltage greater than the threshold voltage is applied across it. In some instances, current may not flow through a memory element in a more amorphous state when a voltage less than the threshold voltage is applied across it. In some cases, a memory element in a more crystalline state may not be associated with a threshold voltage (e.g., it may be associated with a zero threshold voltage). In some instances, current may flow through a memory element in response to a non-zero voltage applied across it.

[0042] In some cases, materials in both more amorphous and more crystalline states can be associated with threshold voltage. For example, a self-selecting memory can increase the difference in threshold voltage between memory cells in different programmed states (e.g., through different compositional distributions). The logic state of a memory cell 105 having this memory element can be set by heating the memory element over time to a temperature profile that supports the formation of a specific atomic configuration or combination of atomic configurations.

[0043] Memory device 100 may include a three-dimensional (3D) memory array, wherein multiple two-dimensional (2D) memory arrays (e.g., layers, hierarchies) are formed vertically above each other. In various instances, such arrays may be divided into a set of memory segments 110, wherein each memory segment 110 may be arranged within a layer or hierarchy, distributed across multiple layers or hierarchies, or arranged in any combination thereof. Compared to 2D arrays, such arrangements can increase the number of memory cells 105 that can be placed or formed on a single die or substrate, which in turn can reduce the manufacturing cost of memory device 100 or improve the performance of memory device 100, or both. The layers or hierarchies may be separated by an electrically insulating material. Each layer or hierarchy may be aligned or positioned such that the memory cells 105 are generally aligned with each other across each layer, thereby forming a stack of memory cells 105.

[0044] In an example of memory device 100, each row of memory cells 105 in memory segment 110 can be connected to one of a set of first access lines 120 (e.g., word lines (WL), such as WL1 to WL). M One of them) and each column of memory cell 105 may be coupled to one of a set of second access lines 130 (e.g., digital lines (DL), such as DL1 to DL). N One of them). In some instances, rows of memory cells 105 in different memory segments 110 (not shown) may be coupled to one of different plurality of first access lines 120 (e.g., different from WL1 to WL). M The word lines are coupled, and columns of memory cells 105 in different memory segments 110 can be coupled to one of a plurality of second access lines 130 (e.g., different from DL1 to DL2). N The digital lines are coupled. In some cases, the first access line 120 and the second access line 130 may be substantially perpendicular to each other in the memory device 100 (e.g., when viewing the plane of the layer of the memory device 100, such as...). Figure 1 (As shown in the image). References to word lines and bit lines or the like are interchangeable without prejudice to understanding or operation.

[0045] Generally, a memory cell 105 may be located at the intersection of access lines 120 and 130 (e.g., coupled to or between access lines 120 and 130). This intersection, or the indication of this intersection, may be referred to as the address of memory cell 105. A target or selected memory cell 105 may be a memory cell 105 located at the intersection of energized or otherwise selected access lines 120 and 130. In other words, access lines 120 and 130 may be energized or otherwise selected to access (e.g., read, write, rewrite, refresh) the memory cell 105 at their intersection. Other memory cells 105 that are electronically communicating with the same access line 120 or 130 (e.g., connected to the same access line 120 or 130) may be referred to as non-target or non-selected memory cells 105.

[0046] In some architectures, the logic storage components of memory cell 105 (e.g., capacitive memory elements, ferroelectric memory elements, resistive memory elements, other memory elements) can be electrically isolated from the second access line 130 via a cell selection component (in some instances, this may be referred to as a switch component or selector device). The first access line 120 may be coupled to the cell selection component (e.g., via a control node or terminal of the cell selection component) and may control the cell selection component of memory cell 105 or a cell selection component associated with memory cell 105. For example, the cell selection component may be a transistor, and the first access line 120 may be coupled to the gate of the transistor (e.g., the gate node of the transistor may be the control node of the transistor). Activating the first access line 120 of memory cell 105 can result in an electrical connection or closed circuit between the logic storage components of memory cell 105 and its corresponding second access line 130. The second access line 130 can then be accessed to read from or write to memory cell 105.

[0047] In some instances, the memory cell 105 of memory segment 110 may also be connected to one of a plurality of third access lines 140 (e.g., board lines (PL), such as PL1 to PL2). N (One of them) coupling. Although illustrated as a single line, in some instances, multiple third access lines 140 may represent or otherwise be functionally equivalent to: common board lines, common boards, or other common nodes of memory segment 110 (e.g., common nodes for each of the memory cells 105 in memory segment 110), or other common nodes of memory device 100. In some instances, multiple third access lines 140 may couple memory cell 105 to one or more voltage sources for various sensing and / or write operations, including those described herein. For example, when memory cell 105 uses a capacitor to store logic state, second access line 130 may provide access to a first terminal or first plate of the capacitor, and third access line 140 may provide access to a second terminal or second plate of the capacitor (e.g., a terminal opposite the first terminal of the capacitor and associated with the opposite plate of the capacitor, or a terminal otherwise located on the side of the capacitor opposite the first terminal of the capacitor). In some instances, memory cells 105 in different memory segments 110 (not shown) may be connected to one of a different plurality of third access lines 140 (e.g., different from PL1 to PL2). N A set of board lines, different common board lines, different common boards, and different common nodes) are coupled, and multiple third access lines 140 can be coupled to the illustrated third access lines 140 (e.g., board lines PL1 to PL). N Electrical isolation.

[0048] Multiple third access lines 140 may be coupled to board assembly 145, which may control various operations, such as activating one or more of the multiple third access lines 140 or selectively coupling one or more of the multiple third access lines 140 to a voltage source or other circuit elements. Although the multiple third access lines 140 of the memory device 100 are shown to be substantially parallel to the multiple second access lines 130, in other instances, the multiple third access lines 140 may be substantially parallel to the multiple first access lines 120, or in any other configuration.

[0049] Although reference Figure 1 The access line described is shown as a straight line between memory cell 105 and the coupled component, but the access line may be associated with other circuit elements such as capacitors, resistors, transistors, amplifiers, voltage sources, switching components, selection components, and other elements (which may be used to support access operations, including those described herein). In some instances, electrodes may be coupled to memory cell 105 and access line 120 (e.g., coupled between memory cell 105 and access line 120), or to memory cell 105 and access line 130 (e.g., coupled between memory cell 105 and access line 130). The term electrode may refer to other electrical interfaces between electrical conductors or components, and in some cases may be used as electrical contacts to memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive layers, conductive pads, etc., providing a conductive path between elements or components of the memory device 100.

[0050] Access operations such as read, write, rewrite, and refresh can be performed on memory cell 105 by activating or selecting a first access line 120, a second access line 130, and / or a third access line 140 coupled to memory cell 105 (which may include applying voltage, charge, or current to the respective access line). Access lines 120, 130, and 140 may be made of conductive materials such as metals (e.g., copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, or other conductive or semi-conductive materials, alloys, or compounds. After selecting memory cell 105, the generated signals (e.g., cell access signal, cell read signal) can be immediately used to determine the logic state stored by memory cell 105. For example, memory cell 105 with capacitive memory elements storing logic states can be selected, and the charge flow generated via the access lines and / or the voltage generated by the access lines can be detected, converted, or amplified to determine the programmed logic state stored by memory cell 105.

[0051] Access to memory cell 105 can be controlled via row component 125 (e.g., row decoder), column component 135 (e.g., column decoder), or board component 145 (e.g., board driver), or a combination thereof. For example, row component 125 may receive a row address from memory controller 170 and select or activate the appropriate first access line 120 based on the received row address. Similarly, column component 135 may receive a column address from memory controller 170 and select or activate the appropriate second access line 130. Therefore, in some instances, memory cell 105 can be accessed by selecting or activating both the first access line 120 and the second access line 130. In some instances, these access operations may be accompanied by biasing one or more of the third access lines 140 of the board assembly 145 (e.g., biasing one of the third access lines 140 of the memory segment 110, biasing all the third access lines 140 of the memory segment, biasing a common board line of the memory segment 110 or memory device 100, biasing a common node of the memory segment 110 or memory device 100), which may be referred to as “moving the board” of the memory cell 105, memory segment 110, or memory device 100. In various instances, any or more of the row assembly 125, column assembly 135, or board assembly 145 may be referred to as or otherwise include an access line driver or access line decoder.

[0052] In some instances, the memory controller 170 may control the operation of memory cells 105 (e.g., read operations, write operations, rewrite operations, refresh operations, discharge operations, dissipation operations, equalization operations) via various components (e.g., row components 125, column components 135, board components 145, sensing components 150). In some cases, one or more of the row components 125, column components 135, board components 145, and sensing components 150 may be co-located with or otherwise included with the memory controller 170. In some instances, any or more of the row components 125, column components 135, or board components 145 may also be referred to as a memory controller or circuit for performing access operations of the memory device 100. In some instances, any or more of the row components 125, column components 135, or board components 145 may be described as controlling or performing operations for accessing the memory device 100, or controlling or performing operations for accessing memory segments 110 of the memory device 100.

[0053] The memory controller 170 can generate row and column address signals to activate the desired access lines 120 and 130. The memory controller 170 can also generate or control various voltages or currents used during operation of the memory device 100. Although a single memory controller 170 is shown, the memory device 100 may have more than one memory controller 170 (e.g., a memory controller 170 for each of a set of memory segments 110 of the memory device 100, a memory controller 170 for each of several subgroups of memory segments 110 of the memory device 100, a memory controller 170 for each of a set of chips of a multi-chip memory device 100, a memory controller 170 for each of a set of libraries of a multi-library memory device 100, a memory controller 170 for each core of a multi-core memory device 100, or any combination thereof), wherein different memory controllers 170 may perform the same and / or different functions.

[0054] Although memory device 100 is illustrated as comprising a single row assembly 125, a single column assembly 135, and a single board assembly 145, other instances of memory device 100 may include different configurations to accommodate memory segment 110 or a group of memory segments 110. For example, in various memory devices 100, row assembly 125 may be shared among a group of memory segments 110 (e.g., having a sub-assembly common to all memory segments in the group of memory segments 110, or having a sub-assembly dedicated to a specific memory segment in the group of memory segments 110), or row assembly 125 may be dedicated to one memory segment 110 within a group of memory segments 110. Similarly, in various memory devices 100, column assembly 135 may be shared among a group of memory segments 110 (e.g., having a sub-component common to all memory segments in the group of memory segments 110, or having a sub-component dedicated to a specific memory segment in the group of memory segments 110), or column assembly 135 may be dedicated to one memory segment 110 within a group of memory segments 110. Additionally, in various memory devices 100, board assembly 145 may be shared among a group of memory segments 110 (e.g., having a sub-component common to all memory segments in the group of memory segments 110, or having a sub-component dedicated to a specific memory segment in the group of memory segments 110), or board assembly 145 may be dedicated to one memory segment 110 within a group of memory segments 110.

[0055] Generally, the amplitude, shape, or duration of the applied voltage, current, or charge can be adjusted or changed, and may differ for various operations described in operating the memory device 100. Furthermore, one, more, or all memory cells 105 within the memory device 100 can be accessed simultaneously. For example, during a reset operation in which all memory cells 105 or a group of memory cells 105 (e.g., memory cells 105 of memory segment 110) are set to a single logic state, more or all memory cells 105 of the memory device 100 can be accessed simultaneously.

[0056] When accessing (e.g., cooperating with memory controller 170) memory cell 105, sensing component 150 can read (e.g., sense) memory cell 105 to determine the logic state stored by memory cell 105. For example, sensing component 150 may be configured to sense current or charge passing through memory cell 105 in response to a read operation, or voltage generated by coupling memory cell 105 to sensing component 150 or other intervening components (e.g., signal development components between memory cell 105 and sensing component 150). Sensing component 150 may provide an output signal indicating (e.g., at least in part based on) the logic state stored by memory cell 105 to one or more components (e.g., column component 135, input / output component 160, memory controller 170). In various memory devices 100, the sensing component 150 may be shared among groups or libraries of memory segments 110 (e.g., having a sub-component common to all memory segments in groups or libraries of memory segments 110, or having a sub-component dedicated to a specific memory segment in a group or library of memory segments 110), or the sensing component 150 may be dedicated to one memory segment 110 in a group or library of memory segments 110.

[0057] In some instances, during or after accessing memory cell 105, the logic storage portion of memory cell 105 may discharge or otherwise allow charge or current to flow via its corresponding access lines 120, 130, or 140. This charge or current may be generated by biasing memory cell 105 or by applying voltage from one or more voltage sources or supplies (not shown) of memory device 100 to memory cell 105, wherein such voltage sources or supplies may be part of row assembly 125, column assembly 135, board assembly 145, sensing assembly 150, memory controller 170, or some other component (e.g., bias assembly). In some instances, the discharge of memory cell 105 may cause a change in voltage on access line 130, which sensing assembly 150 may compare to a reference voltage to determine the stored state of memory cell 105. In some instances, a voltage may be applied to memory cell 105 (e.g., using corresponding access lines 120 and 130) and the presence or magnitude of the resulting current may depend on the applied voltage and the resistance state of the memory elements of memory cell 105. Sensing component 150 may use the applied voltage and the resistance state to determine the stored state of memory cell 105.

[0058] In some instances, when a read signal (e.g., read pulse, read current, read voltage) is applied across a memory cell 105 having a material memory element storing a first logical state (e.g., a set state associated with a more crystalline atomic configuration), the memory cell 105 conducts current because the read pulse exceeds a threshold voltage of the memory cell 105. In response to or at least in part based on this, the sensing component 150 can therefore detect the current passing through the memory cell 105 as part of determining the logical state stored by the memory cell 105. When a read pulse is applied to a memory cell 105 having a memory element storing a second logical state (e.g., a reset state associated with a more amorphous atomic configuration) (this can occur before or after a read pulse is applied across the memory cell 105 having the memory element storing the first logical state), the memory cell 105 may not conduct current because the read pulse does not exceed a threshold voltage of the memory cell 105. As part of determining the stored logical state, the sensing component 150 can therefore detect very little current or no current passing through the memory cell 105.

[0059] In some instances, a threshold current may be defined for sensing the logic state stored by memory cell 105. The threshold current may be set to be higher than the current passing through memory cell 105 when memory cell 105 responds to a read pulse but does not reach the threshold, but equal to or lower than the expected current passing through memory cell 105 when memory cell 105 responds to a read pulse and reaches the threshold. For example, the threshold current may be higher than the leakage current of associated access lines 120, 130, or 140. In some instances, the logic state stored by memory cell 105 may be determined at least in part based on the voltage generated by the current driven by the read pulse (e.g., across a shunt resistor). For example, the generated voltage may be compared relative to a reference voltage, where a generated voltage less than the reference voltage corresponds to a first logic state and a generated voltage greater than the reference voltage corresponds to a second logic state.

[0060] In some instances, more than one voltage may be applied when reading memory cell 105 (e.g., multiple voltages may be applied during a portion of the read operation). For example, if the applied read voltage does not induce current, one or more other read voltages may be applied (e.g., until current is detected by sensing component 150). The stored logic state of memory cell 105 may be determined at least in part based on the read voltage that induces current during access. In some cases, the read voltage may be ramped up (e.g., smoothly increased to a higher value) until current or other conditions are detected by sensing component 150. In other cases, a predetermined read voltage (e.g., a predetermined sequence of read voltages that are increased in steps to a higher value) may be applied until current is detected. Similarly, a read current may be applied to memory cell 105, and the magnitude of the voltage used to form the read current may depend on the resistance of memory cell 105 or the total threshold voltage.

[0061] Sensing component 150 may include various switching components, selection components, multiplexers, transistors, amplifiers, capacitors, resistors, voltage sources, or other components for detecting, converting, or amplifying differences in the sensed signal (e.g., the difference between a read voltage and a reference voltage, the difference between a read current and a reference current, the difference between a read charge and a reference charge) (in some instances, this may be referred to as latching or generating a latch signal). In some instances, sensing component 150 may include a set of components (e.g., circuit elements, circuit systems) that are repeated for each of a set of access lines 130 connected to sensing component 150. For example, sensing component 150 may include separate sensing circuitry or circuit systems (e.g., separate sense amplifiers, separate signal development components) for each of a set of access lines 130 coupled to sensing component 150, such that logic states can be detected individually for a corresponding memory cell 105 coupled to a corresponding access line in the set of access lines 130. In some instances, the reference signal source (e.g., a reference component) or the generated reference signal may be shared among components of the memory device 100 (e.g., shared among one or more sensing components 150, shared in individual sensing circuitry of the sensing component 150, or shared in access lines 120, 130, or 140 of the memory segment 110).

[0062] Sensing component 150 may be included in the device including memory device 100. For example, sensing component 150 may be included together with other read and write circuitry, decoding circuitry, or register circuitry of the memory (which may be coupled to or coupled to memory device 100). In some instances, the detected logic state of memory cell 105 may be output as an output via column component 135 or input / output component 160. In some instances, sensing component 150 may be part of column component 135, row component 125, or memory controller 170. In some instances, sensing component 150 may be connected to or otherwise electronically communicate with column component 135, row component 125, or memory controller 170.

[0063] Although a single sensing component 150 is shown, the memory device 100 (e.g., memory segment 110 of the memory device 100) may contain more than one sensing component 150. For example, a first sensing component 150 may be coupled to a first subgroup of access lines 130 and a second sensing component 150 may be coupled to a second subgroup of access lines 130 (e.g., different from the first subgroup of access lines 130). In some instances, this partitioning of the sensing components 150 may support parallel (e.g., simultaneous) operation of multiple sensing components 150. In some instances, this partitioning of the sensing components 150 may support matching sensing components 150 with different configurations or characteristics to specific subgroups of memory cells 105 of the memory device (e.g., supporting different types of memory cells 105, supporting different characteristics of subgroups of memory cells 105, supporting different characteristics of subgroups of access lines 130).

[0064] Alternatively, two or more sensing components 150 may be coupled to the same set of access lines 130 (e.g., selectively coupled) (e.g., to achieve component redundancy). In some instances, this configuration may support the ability to maintain functionality to overcome failure or otherwise poor or degraded operation of one of the redundant sensing components 150. In some instances, this configuration may support the ability to select one of the redundant sensing components 150 for specific operating characteristics (e.g., related to power consumption characteristics, related to access speed characteristics of a particular sensing operation, related to operating memory cell 105 in volatile or non-volatile modes).

[0065] In some memory architectures, accessing memory cell 105 can degrade or destroy the logic state stored in one or more memory cells 105 of memory segment 110, and can perform a rewrite or refresh operation to return the original logic state to memory cell 105. In DRAM or FeRAM, for example, the capacitor of memory cell 105 can be partially or completely discharged or depolarized during a sensing operation, thereby destroying the logic state stored in memory cell 105. In PCM, for example, a sensing operation can cause a change in the atomic configuration of memory cell 105, thereby changing the resistance state of memory cell 105. Therefore, in some instances, the logic state stored in memory cell 105 can be rewritten after an access operation. Furthermore, activating a single access line 120, 130, or 140 can cause all memory cells 105 coupled to the activated access line 120, 130, or 140 to be discharged. Therefore, several or all memory cells 105 coupled to the access lines 120, 130 or 140 associated with the access operation (e.g., all cells via the access row, all cells via the access column) can be rewritten after the access operation.

[0066] In some instances, reading memory cell 105 may be non-destructive. That is, it may not be necessary to rewrite the logic state of memory cell 105 after reading it. For example, in a non-volatile memory such as PCM, accessing memory cell 105 may not destroy the logic state, and therefore, memory cell 105 may not need to be rewritten after access. However, in some instances, refreshing the logic state of memory cell 105 may or may not be necessary in the absence of other access operations. For example, the stored logic state can be maintained by periodically refreshing the logic state stored by memory cell 105 by applying appropriate write, refresh, or equalization pulses or biases. Refreshing memory cell 105 can reduce or eliminate read disturbance errors or logic state corruption (attributed to charge leakage or changes in the atomic configuration of memory elements over time).

[0067] Memory cell 105 can be set, written to, or refreshed by activating the associated first access line 120, second access line 130, and / or third access line 140 (e.g., via memory controller 170). In other words, logical states can be stored in memory cell 105 (e.g., via cell access signals, via cell write signals). Row assembly 125, column assembly 135, or board assembly 145 can, for example, accept data to be written to memory cell 105 via input / output assembly 160. In some instances, the write operation can be performed at least partially by sensing assembly 150, or the write operation can be configured to bypass sensing assembly 150.

[0068] In the case of a capacitive memory element, memory cell 105 can be written to by applying a voltage to a capacitor and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write to memory cell 105, thereby causing the capacitor to float) to store the charge associated with the desired logic state in the capacitor. In the case of a ferroelectric memory, the ferroelectric memory element can be written to by applying a voltage (e.g., applying a saturation voltage) having a sufficiently high magnitude to polarize the ferroelectric memory element (e.g., a ferroelectric capacitor) of memory cell 105 with polarization associated with the desired logic state, and the ferroelectric memory element can be isolated (e.g., caused to float), or a zero net voltage or bias can be applied across the ferroelectric memory element (e.g., grounding, virtual grounding, or equalizing the voltage across the ferroelectric memory element). In the case of a PCM, the memory element can be written to by applying a current having a distribution curve that causes the memory element to form an atomic configuration associated with the desired logic state (e.g., by heating and cooling).

[0069] According to the examples disclosed herein, sensing component 150 may include a plurality of signal development components that can be selectively coupled or decoupled from corresponding components in a set of sensing amplifiers. For example, a sensing amplifier of sensing component 150 may be coupled to a selection component of sensing component 150, and the selection component may be coupled to a set of signal development components of sensing component 150, each of which is associated with one or more memory cells 105 or one or more access lines (e.g., one or more access lines 130) of memory device 100. In some instances, signal access may be developed at each of the signal development components independently of the other signal development components.

[0070] In some instances, the signal development components of sensing component 150 may each be coupled to a corresponding memory cell during overlapping time intervals, such that multiple cell access signals (e.g., cell read signals, cell write signals, each associated with a corresponding memory cell of each of the corresponding signal development components) can be generated during the overlapping time intervals. In instances where cell access signals have been developed at multiple signal development components (e.g., in read operations of multiple memory cells 105, in multi-cell read operations), the multiple signal development components may be coupled to a sensing amplifier (e.g., sequentially, stepwise) to generate latching signals of the sensing amplifier (e.g., sequentially, stepwise) at least in part based on the cell access signals. In instances where a latch signal sequence is associated with writing to or rewriting a set of memory cells 105 (e.g., in a write or refresh operation of multiple memory cells 105, or in a multi-cell write or refresh operation), multiple signal development components may be coupled to a sense amplifier (e.g., sequentially, stepwise) to generate multiple cell access signals (e.g., sequentially, stepwise) at least partially based on the latch signals of the sense amplifier. In some instances, the multiplexed signal development components of the sense component 150 may compensate for portions of the signal development components or access operations associated with different latency times, which may reduce the impact of access serialization.

[0071] Figure 2 The diagram illustrates an exemplary circuit 200 developed to support multiplexed signals, as shown in the examples disclosed herein. Circuit 200 may include a memory unit 105-a and a sensing component 150-a, which may be used as a reference. Figure 1 Examples of the described memory cell 105 and sensing component 150. Circuit 200 may also include word lines 205, digital lines 210, and board lines 215, which in some embodiments may correspond to reference lines. Figure 1The first access line 120, the second access line 130, and the third access line 140 are described (e.g., for memory segment 110). In some instances, board line 215 may illustrate a common board line, common board, or another common node for memory cell 105-a and another memory cell 105 (not shown) in the same memory segment 110. Circuit 200 illustrates a circuit system that can support the described techniques for developing multiplexed signals in memory devices.

[0072] Sensing component 150-a may include a sensing amplifier 290 (e.g., an amplifier assembly, an input / output amplifier, a "latch"), which may include a first node 291 and a second node 292. In various instances, the first node 291 and the second node 292 may be coupled to different access lines of a circuit (e.g., signal line 285 and reference line 275 of circuit 200, respectively), or may be coupled to a common access line of different circuits (not shown). In some instances, the first node 291 may be referred to as a signal node, and the second node 292 may be referred to as a reference node. The sensing amplifier 290 may be associated with (e.g., coupled to, or coupled to) one or more input / output (I / O) lines (e.g., I / O line 295), which may include access lines via a reference node. Figure 1 The described input / output component 160 is coupled to the access line of the column component 135. Although the sense amplifier 290 is illustrated as having a single I / O line 295, a sense amplifier according to the examples disclosed herein may have more than one I / O line 295 (e.g., two I / O lines 295). In various examples, other configurations and naming of the access lines and / or reference lines are possible according to the examples disclosed herein.

[0073] Memory cell 105-a may include logic storage components (e.g., memory elements, storage elements, memory storage elements), such as a capacitor 220 having a first plate (cell plate) 221 and a second plate (cell bottom) 222. The cell plate 221 and the cell bottom 222 may be capacitively coupled via a dielectric material positioned therebetween (e.g., in DRAM applications) or capacitively coupled via a ferroelectric material positioned therebetween (e.g., in FeRAM applications). The cell plate 221 may be coupled to a voltage V. plate Associated, and the bottom 222 of the cell can be connected to voltage V bottomRelatedly, as illustrated in circuit 200. Without altering the operation of memory cell 105-a, the orientation of cell board 221 and cell bottom 222 can be different (e.g., flipped). Cell board 221 is accessible via board line 215 and cell bottom 222 is accessible via digital line 210. As described herein, various logic states can be stored by charging, discharging, or polarizing capacitor 220.

[0074] Capacitor 220 can communicate electronically with digital line 210, and the stored logic state of capacitor 220 can be read or sensed by various elements represented in operating circuitry 200. For example, memory cell 105-a may also include cell selection component 225, which in some instances may be referred to as a switching component or selector device coupled to or between the access line (e.g., digital line 210) and capacitor 220. In some instances, cell selection component 225 may be considered to be outside the illustrative boundary of memory cell 105-a, and cell selection component 225 may be referred to as a switching component or selector device coupled to or between the access line (e.g., digital line 210) and memory cell 105-a.

[0075] When cell selection component 225 is activated (e.g., by activating a logic signal or voltage), capacitor 220 may be selectively coupled to digital line 210, and when cell selection component 225 is deactivated (e.g., by deactivating a logic signal or voltage), capacitor 220 may be selectively isolated or decoupled from digital line 210. A logic signal or other selection signal or voltage may be applied to control node 226 of cell selection component 225 (e.g., control node, control terminal, selection node, selection terminal) (e.g., via word line 205). In other words, cell selection component 225 may be configured to selectively couple or decouple capacitor 220 (e.g., logic memory component) from digital line 210 based on a logic signal or voltage applied to control node 226 via word line 205.

[0076] Activating cell selection component 225 may be referred to as selecting memory cell 105-a in some instances, and deactivating cell selection component 225 may be referred to as deselecting memory cell 105-a in some instances. In some instances, cell selection component 225 is a transistor (e.g., an n-type transistor) and its operation can be controlled by applying an activation or selection voltage to the transistor gate (e.g., controlling or selecting a node or terminal). The voltage used to activate the transistor (e.g., the voltage between the transistor gate terminal and the transistor source terminal) may be a voltage greater than the transistor's threshold voltage (e.g., a positive activation or selection voltage). The voltage used to deactivate the transistor may be a voltage less than the transistor's threshold voltage (e.g., ground or a negative deactivation or deselection voltage).

[0077] Word line 205 (e.g., by row component 125) can be used to activate or deactivate cell select component 225. For example, a select voltage (e.g., a word line logic signal or word line voltage) applied to word line 205 can be applied to the gate of the transistor in cell select component 225, which can selectively connect or couple capacitor 220 to digital line 210 (e.g., provide a conductive path between capacitor 220 and digital line 210). A deselect or deactivation voltage applied to word line 205 can be applied to the gate of the transistor in cell select component 225, which can selectively disconnect, decouple, or isolate capacitor 220 from digital line 210. In some instances, activating cell select component 225 may be referred to as selectively coupling memory cell 105-a to digital line 210, and deactivating cell select component 225 may be referred to as selectively decoupling or isolating memory cell 105-a from digital line 210.

[0078] In other examples, the positions of cell select component 225 and capacitor 220 in memory cell 105-a are interchangeable, such that cell select component 225 can be coupled to or between board line 215 and cell board 221, and capacitor 220 can be coupled to or between digital line 210 and another terminal of cell select component 225. In this example, cell select component 225 can be maintained connected to digital line 210 via capacitor 220 (e.g., electronic communication). This configuration can be associated with alternative timing and biasing for access operations.

[0079] In examples employing ferroelectric capacitor 220, capacitor 220 may or may not be fully discharged immediately after being connected to or coupled to digital line 210. In various embodiments, to sense the logic state stored by ferroelectric capacitor 220, a voltage may be applied to board line 215 and / or digital line 210, and word line 205 may be biased (e.g., by activating word line 205) to select memory cell 105-a. In some cases, board line 215 and / or digital line 210 may be virtually grounded and then isolated from the virtual ground before activating word line 205; this may be referred to as a floating state, idle state, or standby state.

[0080] Operating memory cell 105-a by changing the voltage of cell board 221 (e.g., via board line 215) can be termed "moving the cell board". Biasing board line 215 and / or digital line 210 can result in a voltage difference across capacitor 220 (e.g., the voltage of digital line 210 minus the voltage of board line 215). This voltage difference may be accompanied by a change in the charge stored on capacitor 220, the magnitude of which may depend on the initial state of capacitor 220 (e.g., whether the initial logic state stores logic 1 or logic 0). In some embodiments, a change in the charge stored in capacitor 220, or a portion thereof, may be used by sensing component 150-a to determine the logic state stored by memory cell 105-a (e.g., in a charge transfer sensing embodiment). In some embodiments, a change in the charge stored in capacitor 220 may result in a change in the voltage of digital line 210, which may be used by sensing component 150-a to determine the logic state stored by memory cell 105-a. Cell access signals can refer to signals generated when selecting or activating memory cell 105-a (e.g., when coupled to a signal development component), and may include cell read signals in a read operation of memory cell 105-a, or cell write signals in a write, rewrite, or refresh operation of memory cell 105-a. In various instances, cell access signals may be referred to as cell coupling signals or cell charge sharing signals.

[0081] In some instances, digital line 210 may be coupled to additional memory cells 105 (not shown), each of which may be coupled to a different word line 205 (not shown). In other words, in some instances, different memory cells 105 coupled to digital line 210 may be selected or activated at least in part based on different word line logic signals.

[0082] Digital line 210 may have the property of causing intrinsic capacitance 230 (e.g., approximately several picofarads (pF), which in some cases may be non-negligible) that couples digital line 210 to a voltage source 240-a having a voltage V0. Voltage source 240-a may represent a common ground or virtual ground voltage, or a voltage of a nearby access line (not shown) of circuit 200. Although in Figure 2 The diagram illustrates it as a single component, but the inherent nature of capacitor 230 can be associated with the distribution throughout digital line 210 or another part of circuit 200.

[0083] In some instances, the intrinsic capacitance 230 may depend on the physical characteristics of the digital line 210, including the conductor dimensions of the digital line 210 (e.g., length, width, thickness). The intrinsic capacitance 230 may also depend on the characteristics of adjacent access lines or circuit components, the proximity to such adjacent access lines or circuit components, or the insulation characteristics between the digital line 210 and such access lines or circuit components. Therefore, the change in voltage of the digital line 210 after selecting or activating memory cell 105-a may depend on the net capacitance of the digital line 210 (e.g., the net capacitance associated with the digital line 210). In other words, as charge flows along the digital line 210 (e.g., to or from the digital line 210), a finite amount of charge may be stored along the digital line 210 (e.g., stored in the intrinsic capacitance 230 or in another capacitor coupled to the digital line 210), and the voltage generated by the digital line 210 may depend on the net capacitance of the digital line 210.

[0084] Circuit 200 (e.g., sensing component 150-a) may include signal development component 250, which may be an example of a signal development component or signal development circuit coupled to or between memory cell 105-a and sensing amplifier 290. In some instances, access lines associated with signal development component 250 (e.g., access lines coupled to the input / output of signal development component 250, access lines coupled to or between signal development component 250 and sensing amplifier 290) may be referred to as signal development lines (SDLs) (e.g., signal development line 255, "cache line"). Signal development component 250 may amplify or otherwise convert signals (e.g., cell access signals) from digital line 210 and signal development line 255. For example, for a read operation, signal development component 250 may be associated with generating a cell read signal at least partially based on coupling with capacitor 220 (e.g., prior to sensing operation of sense amplifier 290) or otherwise, and at least partially, with generating the cell read signal based on coupling with capacitor 220, which may include charge sharing between signal development component 250 and capacitor 220. In another example, for a write, rewrite, or refresh operation, signal development component 250 may generate a cell write signal for capacitor 220 (e.g., at least partially based on coupling with sense amplifier 290 in response to a write command, refresh command, rewrite command, or read command) or otherwise, with generating the cell write signal for capacitor 220, which may include charge sharing between signal development component 250 and capacitor 220.

[0085] In some instances, signal development component 250 may include signal storage elements such as capacitors (e.g., integrating capacitors, amplifier capacitors (AMPCap, which in some cases may be alternatively referred to as "fast capacitors") or other types of charge storage elements. Additionally or alternatively, signal development component 250 may include transistors, amplifiers, gate-cathode amplifiers, or any other charge or voltage conversion or amplification components. For example, signal development component 250 may include a charge transfer sense amplifier (CTSA), which in some instances may include a transistor having a gate terminal coupled to a voltage source.

[0086] Although sensing component 150-a is illustrated as having a single signal development component 250, according to the examples disclosed herein, sensing component 150-a may include one or more additional signal development components 250 (not shown) to form a group of signal development components 250. Each signal development component in the group of signal development components 250 of sensing component 150-a may be associated with one or more memory cells 105 or one or more digital lines 210 (e.g., configured to selectively couple or decouple from one or more memory cells 105 or one or more digital lines 210, configured to develop cell access signals for one or more memory cells 105 or one or more digital lines 210), which may or may not include memory cells 105-a or digital lines 210. For example, each signal development component 250 in the group of signal development components 250 may be selectively coupled or decoupled from one or more digital lines 210 of a memory segment 110 of a memory array. In an example where one of the signal development components 250 is coupled to more than one memory cell 105 or more than one digital line 210, either the memory cell 105 or the digital line 210 may be selectively coupled or decoupled from the corresponding signal development component 250 by a selection component (e.g., digital line selection component, multiplexer, transistor network, transistor array, switch network, switch array, not shown) between the corresponding signal development component 250 and the associated memory cell 105 or digital line 210.

[0087] According to the examples disclosed herein, sensing component 150-a may include a selection component 280 (e.g., a signal development component selection component, multiplexer, transistor network, transistor array, switch network, switch array) coupled to or coupled between a set of signal development components 250 (e.g., a set of signal development lines 255) and sensing amplifier 290. The selection component 280 may be configured to selectively couple or decouple any of the signal development components or signal development lines from the set of signal development components 250 or signal development lines 255 to sensing amplifier 290. The selection component 280 may be associated with an access line (e.g., signal line 285) for carrying a signal (e.g., voltage, charge, current) between the selection component 280 and sensing amplifier 290. For example, the output of selection component 280 (e.g., in a read operation) may be an output signal (e.g., a signal transported via signal line 285) that is at least partially based on the input signal (e.g., the signal transported from the signal development component 250 selected by selection component 280, or the signal transported by the signal development line 255 selected by selection component 280). In some instances, the output signal of selection component 280 may be equal to or substantially equal to the input signal of selection component 280 (e.g., where V...). sig =V SDL Although described in the context of the input signal via signal development line 255 and the output signal via signal line 285, the interpretation of input and output can be reversed in specific access operations employing circuit 200 (e.g., in write, rewrite, and refresh operations).

[0088] During a read operation, the voltage of signal line 285 after selecting memory cell 105-a (e.g., after coupling memory cell 105-a or digital line 210 to signal development component 250, selecting the cell read signal after signal development component 250 at selection component 280) can be compared by sensing component 150-b with a reference (e.g., the voltage of reference line 275) to determine the logic state stored in memory cell 105-a (e.g., to generate a latch signal). In some instances, the voltage of reference line 275 may be provided by reference component 270. In other instances, reference component 270 may be omitted and the reference voltage may be provided, for example, by accessing memory cell 105-a or digital line 210 to generate the reference voltage (e.g., in a self-referenced access operation). Other operations may be used to support the selection and / or sensing of memory cell 105-a.

[0089] In some instances, circuitry 200 may include a bypass line 260 that allows for (e.g., selectively bypassing) a portion of the circuitry between signal development component 250 or memory cell 105-a and sense amplifier 290. In some instances, bypass line 260 may be selectively enabled or disabled via switch component 265. In other words, when switch component 265 is activated, digital line 210 may be coupled via bypass line 260 to signal development line 255 or selection component 280 (e.g., coupling memory cell 105-a and selection component 280 or a portion of the circuitry between said memory cell and sense amplifier 290).

[0090] In some instances, when switch component 265 is activated, signal development component 250 may be selectively isolated or decoupled from one or both of digital line 210 or signal development line 255 (e.g., via another switch component or selection component, not shown). When switch component 265 is deactivated, digital line 210 may be selectively coupled to signal development line 255 or selection component 280 via signal development component 250. In other instances, one or more additional selection components (not shown) may be used to selectively couple memory cell 105-a (e.g., digital line 210) to signal development component 250 (e.g., via signal development line 255) or bypass line 260.

[0091] Alternatively, in some instances, a switch or selection component may be used to selectively couple selection component 280 to either signal development component 250 (e.g., via signal development line 255) or bypass line 260. In some instances, the selectable bypass line 260 may support the generation of cell access signals (e.g., cell read signals) for detecting the logic state of memory cell 105-a by using signal development component 250, and the generation of cell access signals (e.g., cell write signals) bypassing signal development component 250 to write the logic state to memory cell 105-a.

[0092] Some examples of memory devices supporting multiplexed signal development may share a common access line (not shown) between memory cell 105 and sense amplifier 290 to support the generation of sense and reference signals from the same memory cell 105. In one example, the common access line between signal development component 250 and sense amplifier 290 may be referred to as a "common line," and the common access line may replace the signal line 285 and reference line 275 illustrated in circuit 200.

[0093] In such instances, the common access line may be connected to the sense amplifier 290 at two different nodes (e.g., a first node 291 and a second node 292, as described herein). In some instances, the common access line may allow self-reference read operations to share components that may exist between the sense amplifier 290 and the accessed memory cell 105 in both signal generation and reference generation operations. This configuration reduces the sensitivity of the sense amplifier 290 to operational variations of various components in the memory device, such as memory cell 105, access lines (e.g., word lines 205, digital lines 210, board lines 215), signal development circuitry (e.g., signal development component 250), transistors, voltage sources 293 and 294, and others.

[0094] Although digital line 210, signal development line 255, and signal line 285 are identified as separate lines, according to the examples disclosed herein, digital line 210, signal development line 255, signal line 285, and any other line connecting memory unit 105 and sense amplifier 290 may be referred to as a single access line. This access line component may be identified separately in various exemplary configurations for the purpose of illustrating the intervention components and intervention signals.

[0095] The sensing amplifier 290 may include various transistors or amplifiers to detect, convert, or amplify the difference in signals, which may be referred to as latching or generating a latched signal. For example, the sensing amplifier 290 may include a receiver that receives the sensed signal voltage at the first node 291 (e.g., a cell readout signal, V). sig ) and the reference signal voltage at the second node 292 (e.g., V ref The circuit element that compares the sensed signal voltage with the reference signal voltage. The output of the sense amplifier 290 (e.g., a latched signal) can be driven to a higher voltage (e.g., a positive voltage) or a lower voltage (e.g., a negative voltage, ground voltage) based on the comparison at the sense amplifier 290.

[0096] For example, if the first node 291 has a lower voltage than the second node 292, then the output of the sensing amplifier 290 can be driven to a relatively low voltage (e.g., V) of the low voltage source 293. L The voltage, which can be a ground voltage or a negative voltage that is substantially equal to V0. The sensing component 150, which includes the sensing amplifier 290, can latch the output of the sensing amplifier 290 to determine a logic state stored in the memory cell 105-a (e.g., logic 0 is detected when the first node 291 has a voltage lower than that of the second node 292).

[0097] If the first node 291 has a higher voltage than the second node 292, then the output of the sensing amplifier 290 can be driven to the voltage of the high voltage source 294 (e.g., V).H The sensing component 150, which includes a sensing amplifier 290, can latch the output of the sensing amplifier 290 to determine a logic state stored in memory cell 105-a (e.g., a logic 1 is detected when the first node 291 has a voltage higher than the second node 292). The latched output of the sensing amplifier 290 corresponding to the detected logic state of memory cell 105-a can then be output via one or more input / output (I / O) lines (e.g., I / O line 295).

[0098] To perform a write, rewrite, or refresh operation on memory cell 105-a, a voltage (e.g., a cell write signal) may be applied across capacitor 220. Various methods can be used. In one example, capacitor 220 may be electrically connected to digital line 210 by selecting or activating cell selection component 225 via word line 205 (e.g., by selecting or activating word line 205). The voltage may be applied across capacitor 220 by the voltage across control board 221 (e.g., through board line 215) and cell bottom 222 (e.g., through digital line 210). In some examples, the write, rewrite, or refresh operation may be at least partially based on a latch signal at sense amplifier 290, which may be based on a signal received via I / O line 295 (e.g., a write signal, refresh signal) or on a signal generated at sense amplifier 290 (e.g., a rewrite signal).

[0099] For example, to write logic 0, cell board 221 can be taken high (e.g., a positive voltage is applied to board line 215), and cell bottom 222 can be taken low (e.g., digital line 210 is grounded, digital line 210 is dummy grounded, or a negative voltage is applied to digital line 210). The reverse process can be performed to write logic 1, where cell board 221 is taken low and cell bottom 222 is taken high. In some cases, the voltage applied across capacitor 220 during the write operation can have an amount equal to or greater than the saturation voltage of the ferroelectric material in capacitor 220, causing capacitor 220 to be polarized and thus maintaining charge even when the amount of the applied voltage is reduced or when zero net voltage is applied across capacitor 220. In some instances, sense amplifier 290 or signal development component 250 can be used to perform the write operation, which may involve coupling a low voltage source 293 or a high voltage source 294 to the digital line. When the sense amplifier 290 is used to perform a write operation, the signal development component 250 may or may not be bypassed (e.g., by applying a write signal via bypass line 260).

[0100] The circuit 200, which includes sensing component 150-a, cell selection component 225, signal development component 250, switching component 265, reference component 270, selection component 280, or sensing amplifier 290, may contain various types of transistors. For example, the circuit 200 may include an n-type transistor, wherein applying a relatively positive voltage (e.g., an applied voltage having a positive value relative to the source terminal that is greater than the threshold voltage) above the threshold voltage of the n-type transistor to the gate of the n-type transistor will establish a conductive path between the other terminals of the n-type transistor (e.g., the source terminal and the drain terminal).

[0101] In some instances, an n-type transistor can act as a switching component, wherein the applied voltage is a logic signal used to selectively enable conductivity through the transistor by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic 1 state, which may be associated with a positive logic signal voltage supply), or to selectively disable conductivity through the transistor by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic 0 state, which may be associated with ground or virtual ground voltage or a negative voltage). In some instances where an n-type transistor is used as a switching component, the voltage of the logic signal applied to the gate terminal can be selected to operate the transistor at a specific operating point (e.g., in the saturation region or in the active region).

[0102] In some instances, the behavior of an n-type transistor may differ from that of a logic switch (e.g., be more complex), and the selective conductivity across the transistor may vary with changing source and drain voltages. For example, the voltage applied at the gate terminal may have a specific voltage level (e.g., a clamping voltage, a control voltage) used to achieve conductivity between the source and drain terminals when the source terminal voltage is below a specific level (e.g., below the gate terminal voltage minus a threshold voltage). When either the source or drain terminal voltage rises above the specific level, the n-type transistor can be deactivated, breaking the conductive path between the source and drain terminals.

[0103] Alternatively, circuit 200 may include a p-type transistor, wherein applying a relatively negative voltage (e.g., an applied voltage having a negative value relative to the source terminal) above the threshold voltage of the p-type transistor to the gate of the p-type transistor will achieve a conductive path between the other terminals of the p-type transistor (e.g., the source terminal and the drain terminal).

[0104] In some instances, a p-type transistor can act as a switching component, wherein the applied voltage is a logic signal used to selectively enable conductivity by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic "1" state, which may be associated with a negative logic signal voltage supply), or to selectively deactivate conductivity by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic "0" state, which may be associated with a ground or virtual ground voltage, or a positive voltage). In some instances where a p-type transistor is used as a switching component, the voltage of the logic signal applied to the gate terminal can be selected to operate the transistor at a specific operating point (e.g., in the saturation region or in the active region).

[0105] In some instances, the behavior of a p-type transistor may differ from that of a logic switch via a gate voltage (e.g., it may be more complex than a logic switch), and the selective conductivity across the transistor may vary with changing source and drain voltages. For example, the voltage applied at the gate terminal may have a specific voltage level used to achieve conductivity between the source and drain terminals, as long as the source terminal voltage is above a specific level (e.g., above the gate terminal voltage plus a threshold voltage). When the source terminal voltage drops below the specific level, the p-type transistor can be deactivated, thus breaking the conductive path between the source and drain terminals.

[0106] The transistors of circuit 200 may be field-effect transistors (FETs), including metal-oxide-semiconductor FETs, which may be referred to as MOSFETs. These and other types of transistors may be formed from doped material regions on a substrate. In some instances, the transistors may be formed on a substrate dedicated to a specific component of circuit 200 (e.g., a substrate for sense amplifier 290, a substrate for signal development component 250, a substrate for memory cell 105-a), or the transistors may be formed on a substrate common to specific components of circuit 200 (e.g., a substrate common to sense amplifier 290, signal development component 250, and memory cell 105-a). Some FETs may have metallic portions comprising aluminum or other metals, but some FETs may be implemented with other non-metallic materials such as polycrystalline silicon, including those FETs that may be referred to as MOSFETs. Furthermore, although oxide portions may be used as dielectric portions of FETs, other non-oxide materials may be used in the dielectric material of FETs (including those FETs that may be referred to as MOSFETs).

[0107] In some instances, different portions of circuit 200 or different operations using portions of circuit 200 may be associated with different latency times. For example, in one portion of an access operation (e.g., a first sub-operation, a first set of sub-operations), a cell access signal may be developed by coupling memory cell 105-a with signal development component 250 (e.g., at least partially based on activating or selecting cell selection component 225, at least partially based on activating another switching component, isolation component, or selection component between memory cell 105-a and signal development component 250). In some instances, the cell access signal may be developed at least partially based on charge sharing between memory cell 105-a (e.g., capacitor 220) and signal development component 250 (e.g., charge flowing from capacitor 220 to signal development component 250, charge flowing from signal development component 250 to capacitor 220), or the cell access signal may otherwise be associated with the charge sharing. In some instances (e.g., during a read operation), the developed cell access signal (e.g., a cell read signal) or charge sharing may be based at least in part on the logic state stored by memory cell 105-a. In some instances (e.g., during a write operation, a rewrite operation, or a refresh operation), the developed cell access signal (e.g., a cell write signal) or charge sharing may be based at least in part on the developed latch signal (e.g., at sense amplifier 290, at signal line 285). As disclosed herein, charge sharing between memory cell 105-a and signal development component 250 may be associated with a voltage change on digital line 210 or a voltage change on signal development line 255, or both.

[0108] The development of a cell access signal for an access operation can be associated with a latency period, which can refer to the amount of time (e.g., duration) required to develop the cell access signal, the delay between the start of the cell access signal development operation and the cell access signal reaching a threshold level suitable for the subsequent portion of the access operation (e.g., in a read operation), or the delay between the start of the cell access signal development operation and the writing of a logic value to memory cell 105 (e.g., in a write operation, rewrite operation, or refresh operation). In some instances (e.g., in a read operation), the duration or latency period can be referred to as a "row-to-column address latency," and in some instances (e.g., in a write operation), the duration or latency period can be referred to as a "row precharge latency," which can be longer or shorter than the row-to-column address latency.

[0109] In some instances, charge sharing among memory cell 105-a, digital line 210 (e.g., intrinsic capacitor 230), and signal development components may be consistent with time constant behavior (e.g., voltage V). DL The changing time constant behavior, voltage V SDLThe duration or latency of the development cell access signal may be associated with the changing time constant behavior, or otherwise include logarithmic or exponential behavior.

[0110] In some instances, the duration or latency for developing a cell access signal can be expressed as a time constant (e.g., the duration for reaching 63% of the change between the initial voltage and the steady-state voltage) or as multiple time constants. For example, the duration or latency for developing a cell access signal can be expressed as a duration of three time constants, or otherwise associated with a duration within 5% of the steady-state value of the cell access signal. In another instance, the duration or latency for developing a cell access signal can be expressed as a duration of five time constants, or otherwise associated with a duration within 1% of the steady-state value of the cell access signal.

[0111] In some instances, charge-sharing behavior and associated time constants or other latency may be based at least in part on the capacitance of memory cell 105-a, the capacitance of signal development component 250, or other capacitances between memory cell 105-a and signal development component 250 (e.g., intrinsic capacitance, such as intrinsic capacitance 230). For example, a relatively high capacitance of digital line 210 (e.g., relatively high intrinsic capacitance 230) may be associated with a relatively high latency (e.g., a relatively long duration of development unit read signals), and a relatively low capacitance of digital line 210 may be associated with a relatively low latency (e.g., a relatively short duration of development unit read signals). In another instance, a relatively high capacitance of memory cell 105-a (e.g., capacitor 220) may be associated with a relatively low latency (e.g., a relatively short duration of development unit read signals), and a relatively low capacitance of memory cell 105-a may be associated with a relatively high latency (e.g., a relatively long duration of development unit read signals).

[0112] Although described with reference to time constant behavior, the duration or latency associated with a development unit access signal may additionally or alternatively include other behaviors, such as ramping, stepping, or oscillating (e.g., underdamped) behavior. In some instances, a development unit access signal may include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with developing the unit access signal may include the associated circuitry behavior of each of these operations. For example, a development unit access signal may include activating a switch or selection component along digital line 210 or signal development line 255, activating a switch or selection component between the digital line or signal development line and another component (e.g., selectively coupling a voltage source (not shown) to digital line 210 or signal development line 255), or other operations or combinations thereof.

[0113] In another part of the access operation (e.g., a second sub-operation, a second set of sub-operations), a latched signal (e.g., an output signal, an input / output signal) can be developed by activating the sense amplifier 290 (e.g., at least partially based on selectively coupling the signal development component 250 to the sense amplifier 290, at least partially based on selectively coupling the sense amplifier to one or both of a low voltage source 293 or a high voltage source 294). In some instances, the latched signal can be developed at least partially based on charge sharing between the signal development component 250 and the sense amplifier 290, or the latched signal can be otherwise associated with charge sharing. In some instances (e.g., in a read operation), the latched signal or charge sharing can be at least partially based on the developed cell access signal (e.g., at the signal development component 250, at the signal development line 255). As described herein, charge sharing between the signal development component 250 and the sense amplifier 290 can be associated with a voltage change on the I / O line 295, which can be at least partially based on voltage V. sig With voltage V ref Comparison between them. (For example, when V) sig Less than V ref When it is V L The output of V sig Greater than V ref When it is V H (output).

[0114] Developing a latch signal for an access operation can also be associated with a latency period, which may refer to the amount of time required to develop the latch signal, or the delay between the initiation of the latch signal generation operation and the latch signal reaching a threshold level suitable for a subsequent portion of the access operation (e.g., an output indicating a logic state stored by memory cell 105-a). For example, charge sharing between the signal development component 250 and the sense amplifier 290 can also be associated with time constant behavior (e.g., the time constant behavior of a voltage change on I / O line 295) or other logarithmic or exponential behavior. The duration or waiting time used for developing the latch signal can refer to the duration between the coupling or activation operation (e.g., the selection or activation of a switching component or selection component of selection component 280 (which is configured to selectively couple signal development component 250 to sense amplifier 290), or the coupling of sense amplifier 290 to one or both of low voltage source 293 or high voltage source 294) and a threshold proportion (e.g., 90% or 95% of the steady-state voltage) at which I / O line 295 reaches a steady-state voltage.

[0115] The duration or latency used for developing a latch signal can also be expressed as a time constant, or as multiple time constants. Although described with reference to time constant behavior, the duration or latency associated with a developing latch signal may additionally or alternatively include other behaviors, such as ramping, stepping, or oscillating (e.g., underdamped) behavior. In some instances, a developing latch signal may include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with developing the latch signal may include the associated circuit behavior of each of the set of operations.

[0116] In some instances of circuit 200, the duration of latency associated with accessing a development unit signal may be longer than the latency associated with generating a latch signal. For example, charge sharing between signal development component 250 and memory cell 105-a may be associated with a different amount of charge than charge sharing between signal development component 250 and sense amplifier 290, or with a slower charge transfer. In other words, signal development component 250 or memory cell 105-a may be associated with or otherwise considered a relatively high latency portion of circuit 200, and sense amplifier 290 may be associated with or considered a relatively low latency portion of circuit 200. In such instances, circuit 200 may support performing input or output operations more rapidly than performing signal development operations.

[0117] According to the examples disclosed herein, a memory device 100 including circuitry 200 may couple each of a set of signal development components 250 to a corresponding memory cell 105 during overlapping time intervals, such that a plurality of cell access signals (e.g., associated with a corresponding memory cell 105 of each of the corresponding signal development components 250) can be generated during the overlapping time intervals. Each signal development component in the set of signal development components 250 may be selectively coupled (e.g., sequentially) to a sense amplifier 290 via a selection component 280 to generate a latch signal sequence at the sense amplifier 290, or vice versa. For example, in a read operation or a set of read operations, the latch signal sequence generated at the sense amplifier 290 may be based on a corresponding cell access signal (e.g., a cell read signal) developed at the set of signal development components 250 during the overlapping time intervals, which may be associated with a specific logic state stored by the corresponding memory cell 105. Therefore, as disclosed herein, the memory device 100 including circuitry 200 may include a signal development component 250 multiplexed via selection component 280, which in some instances may compensate for portions of access operations associated with different latency times.

[0118] Figure 3 The diagram illustrates an exemplary circuit 300 for supporting multiplexed signal development based on examples as disclosed herein. It should be understood that circuit 300 is merely an illustrative example, and many implementations of other specific circuits and topologies are possible when following the principles and techniques disclosed herein, as will be understood by one of ordinary skill in the art.

[0119] Circuit 300 includes a set of memory cells 105-b (e.g., memory cells 105-b-111 to 105-b-srm) and sensing components 150-b. Although memory cells 105-b are illustrated as including capacitors and cell selection components, memory cells 105-b according to the examples disclosed herein may include various configurations (e.g., with or without cell selection components) and various types of logic memory elements (e.g., capacitive memory elements, ferroelectric memory elements, resistive memory elements, other memory elements) to support various types of memory devices (e.g., DRAM memory devices, FeRAM memory devices, PCM devices). Circuit 300 is illustrated as a circuit system that can support the described techniques for the development of multiplexed signals in memory devices.

[0120] Sensing component 150-b may include a set of signal development components 250-a (e.g., signal development components 250-a-1 to 250-as) each associated with one or more of the memory cells 105-b. Sensing component 150-b may also include selection components 280-a (e.g., signal development component selection components, MUX, transistor networks, transistor arrays, switch networks, switch arrays) coupled to the set of signal development components 250-a (e.g., via signal development lines 255-a-1 to 255-as). Selection components 280-a may be configured to selectively couple one of the signal development components 250-a (e.g., one of the signal development lines 255-a) to a sensing amplifier 290-a of sensing component 150-b (e.g., via signal line 285-a, in response to a logic OR selection signal, such as a signal development component multiplexed (SDCM) signal). The sensing amplifier 290-a can exchange (e.g., transmit, receive, transfer) input or output signals with other components of the memory device (e.g., input / output component 160) via I / O line 295-a.

[0121] In an example of circuit 300, memory cells 105-b may be arranged according to a set of domains 310-a (e.g., domains 310-a-1 to 310-as). In other words, circuit 300 may graphically illustrate an example of a set of memory cells 105-b that spans s domain partitions or is otherwise associated with s domains. In an example of circuit 300, each of the domains 310-a may be associated (e.g., coupled) with one of the signal development components 250-a (e.g., domain 310-a-1 is associated with signal development component 250-a-1). However, in various examples of circuit systems supporting the described techniques for multiplexing signal development in memory devices, a domain 310 may be associated with more than one signal development component 250, or a signal development component 250 may be associated with more than one domain 310, or both.

[0122] Although the exemplary domain 310-a of circuit 300 is described with reference to specific characteristics, alternative domain definitions or organization can be used to support the described techniques for developing multiplexed signals in memory devices. As such an example, the memory cells 105 or access lines (e.g., word lines 205, digital lines 210, board lines 215) of a domain may be organized or subdivided in a manner different from that of domain 310-a illustrated in circuit 300, or the domain may be defined in a manner different from that of domain 310-a illustrated in circuit 300 (e.g., the components are contained within the illustrative boundaries of the domain), or the domain may be coupled to the signal development component 250 or the sense amplifier 290 in a manner different from that of domain 310-a illustrated in circuit 300 (e.g., using different multiplexing organizations or schemes, different selected components).

[0123] In an example of circuit 300, each of domains 310-a may include a memory cell 105-b coupled to or coupled between one of a set of digital lines 210-a and one of a set of board lines 215-a. For example, for domain 310-a-1, each memory cell in the group of memory cells 105-b (e.g., each of memory cells 105-b-111 to 105-b-1rm) may be coupled to one of digital lines 210-a-11 to 210-a-1r and may be coupled to one of board lines 215-a-11 to 215-a-1r. In other words, domain 310-a may graphically illustrate the arrangement of memory cells 105-b that span or are otherwise associated with r digital lines 210-a or "columns". Although the exemplary circuit 300 is illustrated as having a single board line 215-a, in some instances, a set of board lines 215-a (e.g., a set of two or more of board lines 215-a-11 to 215-a-1r) may represent or otherwise be functionally equivalent to a common board line of domain 310-a (e.g., domain 310-a-1), or may represent or otherwise be functionally equivalent to a portion (e.g., a “subdomain”) of domain 310-a, or a different set of board lines 215-a (e.g., a set of two or more of board lines 215-a-11 to 215-a-sr) may represent or otherwise be functionally equivalent to a set of common board lines of domain 310-a (e.g., a set of common board lines of domains 310-a-1 to 310-as).

[0124] Domain 310-a may also illustrate the arrangement of memory cells 105-b spanning m word lines 205-a or "rows" or otherwise associated with m word lines 205-a or "rows". For example, domain 310-a-1 may include m memory cells 105-b in a corresponding group between each of the digital lines 210-a of domain 310-a and each of the board lines 215-a of the domain (e.g., a group of memory cells 105-b-111 to 105-b-11m coupled to or coupled between digital lines 210-a-11 and board lines 215-a-11). For a group of memory cells 105-b coupled to the same digital line 210-a and the same board line 215-a, the logic signal WL can be used at least in part based on the associated logic signal WL (e.g., for domain 310-a, logic signal WL). 11 To WL 1mEach memory cell in the group can be individually selected or accessed. Although illustrated as a common group of word lines 205-a in a shared domain 310-a (e.g., word lines 205-a-11 to 205-a-1m shared by each column in a column of domain 310-a-1), other instances of the memory device may have different arrangements of word lines 205 in domain 310.

[0125] In an example of circuit 300, each of domains 310-a may further include a selection component 320-a coupled to each digital line in the group of digital lines 210-a of domain 310-a (e.g., a digital line selection component, MUX, transistor network, transistor array, switch network, switch array) or otherwise associated with selection component 320-a. For example, domain 310-a-1 may include a selection component 320-a-1 coupled to each of digital lines 210-a-11 to 210-a-1r. For example, selection component 320-a-1 may be configured to selectively couple one of digital lines 210-a-11 to 210-a-1r or one of memory cells 105-b-111 to 105-b-11m to signal development component 250-a-1 (e.g., in response to a logic OR selection signal, such as a digital line multiplexing (DLM) signal DLM1). Therefore, each of the selected components 320-a-1 to 320-as can be associated with a corresponding one of the signal development components 250-a-1 to 250-as.

[0126] In an example of circuit 300, each of the signal development components 250-a may be associated with a corresponding group of memory cells 105-b or a corresponding group of digital lines 210-a. In some examples, selection components 320-a-1 to 320-as may be examples of a plurality of second selection components, each of which is associated with a corresponding signal development component 250 and configured to selectively couple any one of the memory cells 105-b or digital lines 210-a in the group to the corresponding signal development component 250.

[0127] In an illustrative example, each of domains 310-a may contain 1,048,576 memory cells 105-b arranged in 1,024 uniquely addressed rows and 1,024 columns (e.g., where m = 1024 and r = 1024). According to an illustrative example of circuitry 300, a signal development component 250-a may be mapped to a specific domain 310-a, but in other examples, a group of more than one signal development component 250-a may be mapped to a specific domain 310-a (e.g., corresponding sets of digital lines 210-a mapped to domain 310-a). In some examples, this mapping may be fixed (e.g., where corresponding sets of digital lines 210-a map to corresponding signal development components 250-a within each domain 310-a), which in some examples reduces the complexity of multiplexing or selection circuitry. In various other instances (not shown), signal development component 250 may be mapped to more than one domain 310, (e.g., more than one set of digital lines 210) or other configurations. Alternatively, domain 310 or a set of digital lines 210 may be mapped to more than one signal development component 250. In other words, the memory device may contain various configurations of signal development component 250 to support the instances of multiplexed signal development described herein.

[0128] In an example of circuit 300, each of the digital lines 210-a is associated with a single signal development component (e.g., configured to selectively couple with a single signal development component) (e.g., via a corresponding one of the selection components 320-a-1). For example, digital line 210-a-11 may be associated with signal development component 250-a-1 but not signal development component 250-as. However, in various instances of circuit systems supporting the described techniques for multiplexing signal development in memory devices, a particular digital line 210-a may be associated with more than one signal development component 250-a (e.g., configured to selectively couple with more than one signal development component 250-a), and signal development component 250-a may include selection components different from the selection components 320-a-1 to 320-as group illustrated in circuit 300. For example, digital line 210-a-11 may be associated with signal development component 250-a-1 or signal development component 250-as or any other signal development component 250-a of circuit 300 (e.g., configured to selectively couple with signal development component 250-a-1 or signal development component 250-as or any other signal development component 250-a of circuit 300).

[0129] In another illustrative example supporting the described technique for multiplexed signal development, another circuit may include several fields, each having 1,048,576 memory cells 105 arranged in 1,024 uniquely addressed rows and 1,024 columns, which may refer to a component organization different from that of circuit 300. Each of the fields in this other circuit may be arranged such that m = 1024 and r = 1024, and the digital lines 210 of the corresponding field of this other circuit may be collectively mapped to an array of 64 signal development components 250 (e.g., according to a many-to-one mapping, according to a many-to-many mapping). In one example of this other circuit, each of the signal development components 250 may be mapped to a corresponding subgroup of the digital lines 210 of the field (e.g., one signal development component 250 may be mapped to 1024 / 64 = 16 digital lines 210 within each field). In some instances, this mapping can be fixed (e.g., where groups or subgroups of 16 digital lines 210 are mapped to corresponding signal development components 250 within each domain), which in some instances reduces the complexity of multiplexing or selection circuitry.

[0130] In this further example, rows of 1024 memory cells 105 (e.g., spanning a domain of the other circuitry) can be selected by a single word line 205 in each domain. In other words, with 64 signal development components 250 per domain and r = 1024, activation of a word line in one domain and activation of another word line in another domain (e.g., including other independent word lines in other domains) can select the memory cell 105 associated with the corresponding row. With 64 signal development components 250 per domain of the circuitry, 64 memory cells out of a group of 1024 memory cells 105 can be accessed at once in each domain (e.g., by selectively coupling a corresponding digital line 210 to each of the 64 signal development components 250 via a corresponding selection component). During this access, other digital lines 210 can be selectively isolated from the corresponding signal development component 250 and other signal development components 250 interfacing with the same domain. Furthermore, other digital lines 210 can be shunt or shielded, as described herein.

[0131] Therefore, examples of the technology described herein may include instances where word lines 205 within a domain or word lines 205 spanning multiple domains, or a combination thereof, are independent (e.g., selectable independently of each other). Examples of the technology described herein may also include instances where word lines 205 within a domain or word lines 205 spanning multiple domains, or a combination thereof, are locked (e.g., hardwired) to be selected jointly (in conjunction). It should be understood that in instances where word lines 205 are selectable independently, these word lines 205 can still operate simultaneously, at least at a specific time or under specific conditions (e.g., even if locked). Furthermore, examples of the technology described herein may include instances where a plurality of digital lines 210 are mapped to a plurality of signal development components 250 within a domain, and instances where a plurality of digital lines 210 are mapped to a single signal development component 250 within a domain (e.g., selection component 280 may have many-to-one or many-to-multifunctionality). Throughout this disclosure (including references) Figure 8 This describes aspects of these and other instance variations.

[0132] In some instances, the operation associated with word line selection may be time-limited to prevent data loss or corruption, which may require waiting for the completion of ongoing operations regarding the accessed cell. For example, when switching from a first word line 205-a of domain 310-a to a second word line 205-a of the same domain 310-a, this switch may require waiting for the completion of cell access signal development for domain 310-a (e.g., of signal development component 250-a) before the switch occurs. In an instance where word line 205-a is shared across several domains (e.g., word line 205-a shared between domains 310-a-1 and 310-as, word line 205-a-11 being functionally equivalent to word line 205-a-s1), when switching from the first shared word line 205-a to the second shared word line 205-a, this switch may require waiting for the completion of cell access signal development for each of domains 310-a-1 and 310-as (e.g., each of signal development components 250-a-1 and 250-as) before the switch occurs.

[0133] In an example of circuit 300, each of the domains 310-a may also include a set of current transformers 330-a (e.g., a digital line shunt, a digital-to-board shunt) or otherwise associated with a set of current transformers 330-a. For example, domain 310-a-1 may include a set of current transformers 330-a-11 to 330-a-1r. Each of the current transformers 330-a may be coupled to or between digital line 210-a and board line 215-a. For example, for domain 310-a-1, current transformer 330-a-11 may be coupled to or between digital line 210-a-11 and board line 215-a-11. For example, shunt 330-a-11 can be configured to selectively couple digital line 210-a-11 to board line 215-a-11 (e.g., in response to logic OR switching signal DLS). 11 In some instances, shunt 330-a may be configured to selectively equalize the bias between digital line 210-a and board line 215-a, or to equalize one or more memory cells 105-b coupled to or between digital line 210-a and board line 215-a. In some instances, shunt 330-a may be configured to selectively discharge one or more memory cells 105-b coupled to or between digital line 210-a and board line 215-a.

[0134] In some instances, circuit 300 can be operated based on shunt shielding. For example, when multiplexing is performed on domain 310-a (e.g., using selection component 320-2), shunt 330-a via shielded digital line 210-a (e.g., digital line 210-a not associated with the currently performed access operation) can support selective coupling with board line 215-a to prevent or reduce data loss (e.g., charge leakage) of memory cell 105-b associated with shielded digital line 210-a. In other words, shunt 330-a can shut off bit transfers on shielded digital line 210-a not associated with the currently performed access operation.

[0135] Selection components 280-a and 320-a may comprise various component configurations and may each be referred to as a multiplexer, transistor network, transistor array, switch network, or switch array. In one example, selection component 280-a may comprise a set of transistors each coupled to sense amplifier 290-a (e.g., each coupled to signal line 285-a). Each transistor in the transistor set may also be coupled to a corresponding one in signal development components 250-a (e.g., a corresponding one of signal development lines 255-a-1 to 255-as). Each transistor in the transistor set may be configured to selectively couple a corresponding one in signal development component 250-a to sense amplifier 290-a in response to one of a set of switching or logic signals provided to the gate of the transistor.

[0136] In some instances, selection component 280-a or selection component 320-a may include a decoder or other logic OR selection signal conversion component. For example, the decoder of selection component 280-a may receive a logic OR selection signal (e.g., a signal SDCM), which may be a digital signal received via a signal bus (e.g., a signal having or otherwise representing multiple bits). In some instances, the decoder may receive the digital signal as input to generate a set of binary signals (e.g., switch or logic signals) that can be applied to the gates of a group of transistors configured in a switch arrangement. For example, the decoder of selection component 280-a may receive the selection signal SDCM as a 4-bit digital input signal and generate 16 binary (e.g., on / off) switch signals, each of which is applied to the gate of one of the group of 16 transistors configured in a switch arrangement.

[0137] In various instances, selection component 280-a can be configured such that only one of the signal development components 250-a-1 to 250-as is coupled to sense amplifier 290-a at a given time (e.g., selectively coupled), and the others of signal development components 250-a-1 to 250-as can be decoupled from sense amplifier 290-a at said time (e.g., when said one of the signal development components 250-a-1 to 250-as is selectively coupled to sense amplifier 290-a) (e.g., selectively decoupled). In some instances, selection component 280-a can also be configured to support operation in which none of the signal development components 250-a-1 to 250-as is coupled to sense amplifier 290-a at a given time (e.g., where each of the signal development components 250-a-1 to 250-as is selectively isolated from sense amplifier 290-a). In various instances of circuit 300, selection component 320-a may contain features or feature groups similar to selection component 280-a, or selection component 320-a may contain features or feature groups different from selection component 280-a.

[0138] In some instances of circuit 300, signal development component 250-a or memory cell 105-b may be associated with or otherwise considered as a relatively high latency portion of circuit 300, and sense amplifier 290-a may be associated with or considered as a relatively low latency portion of circuit 300. According to an example disclosed herein, sense component 150-b may illustrate an example of dividing a memory cell access circuitry system into a high latency portion (e.g., signal development component 250-a) and a low latency portion (e.g., sense amplifier 290-a) and coupling a set of high latency portions to a set of low latency portions via a multiplexer (e.g., selection component 280-a).

[0139] In the example of circuit 300, selection component 280-a can provide a first degree of data pipelinedization, which reduces the impact of data access serialization (due to row buffer conflicts). For example, selection component 280-a can support overlapping data transfers on different sets of digital lines 210-a (e.g., different domains 310-a). Therefore, sense amplifier 290-a is free to support read, write, rewrite, or refresh operations (e.g., when coupled to one of the signal development components 250-a), which occurs while other signal development components 250-a are involved in data transfer (e.g., while other signal development components 250-a are coupled to digital lines 210-a or memory cell 105-b).

[0140] The signal development component 250-a group can be considered as a small, fast local cache memory that reduces line buffer collision rate and increases internal bandwidth. In some instances, the selection component 320-a can provide additional gains by providing a second level of data pipelinedization via multiplexed digital lines 210-a. Thus, according to the examples disclosed herein, the memory device 100 including circuitry 300 may include a signal development component 250-a multiplexed via selection component 280-a or a digital line 210-a multiplexed via one or more selection components 320-a, which can compensate for portions of access operations or access circuitry associated with different latency times.

[0141] Various memory devices (e.g., memory device 100) may include various arrangements of circuitry 300. For example, memory device 100 may include a set of sensing components 150-b, or sensing components 150 may otherwise include a set of sensing amplifiers 290-a and a corresponding set of multiplexed signal development components 250-a. In one example, memory device 100 or a portion thereof may include 16 sensing amplifiers 290-a multiplexed with 1024 digital lines 210-a (this may or may not include multiplexing via selection component 320-a). In some instances, a set of sensing amplifiers 290-a may be included in a composite array, wherein the set of sensing amplifiers 290-a is accessed as a single sensing amplifier "row" of the composite array. In various instances, the multiplexed digital lines 210-a may be in the same domain 310-a or in different domains 310. In some instances, each of the domains 310-a may be independently controllable and accessible via the same row component 125 or different row components 125.

[0142] Figure 4A The illustration depicts an example of a read operation 400 that supports multiplexed signal development, as disclosed herein. The read operation 400 can be illustrated as a portion (e.g., a time interval) of an access operation associated with the generation of cell access signals (e.g., cell read signal, cell write signal) and latch signals when accessing memory cell 105. For example, the read operation 400 can be divided into a read signal development portion 410 (e.g., a cell read portion), a latch signal generation portion 420, and a rewrite signal development portion 430 (e.g., a cell rewrite portion). The read operation 400 can employ a circuit system that supports multiplexed signal development, such as referenced in [reference needed]. Figure 3 The circuit 300 is described. As an illustrative example, reference is made to the description of read operation 400, which reads the logic state stored in memory cells 105-b-111 of circuit 300, but read operation 400 may illustrate operations that can be performed on any or more of the memory cells 105-b of circuit 300.

[0143] The read signal development section 410 may be associated with charge sharing between memory cell 105-b-111 (e.g., capacitive storage elements, linear capacitors, or ferroelectric capacitors of memory cell 105-b-111), digital line 210-a-11 (e.g., intrinsic capacitor 230), and signal development component 250-a-1. The read signal development section 410 may be an example of developing a signal at signal development component 250-a-1 based at least in part on selectively coupling signal development component 250-a-1 to memory cell 105-b-111. In some instances, developing a read signal at signal development component 250-a-1 is associated with a first latency time (e.g., a relatively high latency time or a long duration). During the read signal development section 410, signal development component 250-a-1 may be selectively decoupled from sense amplifier 290-a.

[0144] In some instances of reading signal development section 410, the access lines of signal development component 250-a-1 (e.g., signal development line 255-a-1) may be biased with a relatively high voltage, which may be associated with storing a relatively high voltage charge at signal development component 250-a-1 (e.g., in a signal storage component (e.g., an integrating capacitor) of signal development component 250-a-1). In some instances, this bias may be associated with a “board low” read operation, wherein during reading signal development section 410, board line 215-a-11 associated with memory cell 105-b-111 is biased with a voltage lower than (e.g., ground voltage) than the digital line 210-a-1 associated with the accessed memory cell 105-b-111.

[0145] The read signal development section 410 may also include selectively coupling memory cell 105-b-111 to signal development component 250-a-1. In some instances, the read signal development section 410 may include activating word line 205-a-11 associated with the memory cell 105-b-111 being read (e.g., activating logic signal WL1), which can selectively couple memory storage elements (e.g., capacitor 220) to corresponding digital lines 210-a-11 (e.g., via cell selection component 225 of memory cell 105-b-111). In some instances, the read signal development section 410 may include selectively coupling corresponding digital lines 210-a-11 to signal development component 250-a-1 (e.g., via selection component 320-a-1, based on selection signal DLM1, or some other switching component). The charge can therefore be shared between memory cell 105-b-111 and signal development component 250-a-1, and can stabilize after a certain time (e.g., according to time constant behavior), wherein the change in voltage of digital line 210-a-11 and signal development line 255-a-1 is at least partially based on the logic state stored by memory cell 105-b-111.

[0146] In some instances, the read signal development section 410 may include a delay (e.g., a delay portion, a delay duration) between developing the read signal (e.g., the read signal at signal development component 250 reaching a steady state, the read signal reaching a maximum value at signal development component 250) and providing the developed read signal (e.g., maintained by signal development component 250) to the sense amplifier 290. In other words, a delay or inactivity period may exist during the read signal development section 410 before the start latch signal generation section 420, which in some instances may include attenuation of the developed read signal (e.g., attenuation of the maintained read signal). In some instances, circuitry 300 may be configured to tolerate the duration of this delay or inactivity period or the amount of attenuation of the developed read signal while still reliably detecting the logic state stored by memory unit 105. This configuration may enable signal development component 250 to perform buffering functions in circuitry 300 (e.g., buffering of the developed read signal over a certain amount of time).

[0147] In some instances, charge sharing of the read signal development section 410 may be associated with a destructive read operation (e.g., where the initially stored logic state of memory cell 105-b-111 is lost or otherwise degraded at memory cell 105-b-111), and thus may be followed by a rewrite operation (e.g., rewriting the signal development section 430). In some instances, the rewrite operation may not immediately follow the read signal development section 410, for example, when stored data is transferred to the signal development component 250, where the stored data may be stored and further read, written, or modified. In various instances, data may be transferred back to the same memory cell 105 or a different memory cell 105, which may be associated with operations that make the signal development component 250 available for other operations. In some instances, charge sharing of the read signal development section 410 may be associated with a non-destructive read operation (e.g., where the initially stored logic state of memory cell 105-b-111 is maintained at memory cell 105-b-111), and therefore a subsequent rewrite operation may not be necessary (e.g., the rewrite signal development section 430 may be omitted).

[0148] The charge sharing of the read signal development section 410 can be associated with a delay or latency, referred to as row-to-column address delay. In DRAM applications, data can be stored as electrode charge at memory cell 105 and can be responded to relatively quickly (e.g., with relatively low latency). In FeRAM applications, data can be stored at memory cell 105 as cell states in the form of dipole orientation or polarization. The dynamics of these dipoles can be relatively slow (e.g., with relatively high latency), which can result in longer sensing times in FeRAM applications (e.g., longer than in DRAM applications). Therefore, in some instances (e.g., in FeRAM applications), the read signal development section 410 can be associated with relatively high latency or long durations (e.g., compared to latch signal generation section 420). In some FeRAM applications, for example, the latency associated with the operation of the read signal development section 410 can be approximately 50 nanoseconds.

[0149] In some instances of the read signal development section 410, a shunt 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunt 330-a-12 (not shown, which may be associated with digital line 210-a-12 or board line 215-a-12) can be selected or activated to 330-a-1r. This allows for bias equalization across unaccessed memory cells 105-b (e.g., bias equalization between digital line 210-a-12 and board line 215-a-12, bias equalization between digital line 210-a-1r and board line 215-a-1r, etc.). In FeRAM applications, for example, this bias equalization can prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than those accessed during the read signal development section 410.

[0150] The latch signal generation section 420 may be associated with charge sharing between the signal development component 250-a-1 and the sense amplifier 290-a. The latch signal generation section 420 may be an example of generating an output signal of the sense amplifier 290-a (e.g., an amplifier assembly) based at least in part on a developed signal (e.g., a cell read signal) at the signal development component 250-a-1. In some instances, the generation of the latch signal at the sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). The transition from the read signal development section 410 to the latch signal generation section 420 may include selectively coupling the signal development component 250-a-1 to the sense amplifier 290-a.

[0151] In some instances, selective coupling of the signal development component 250-a-1 to the sense amplifier 290-a may include selection via the selection component 280-a based on the logic selection signal SDCM. In some instances, selective coupling of the signal development component 250-a-1 to the sense amplifier 290-a may include selective coupling via another switching component (e.g., an isolation switching component) between the signal development component 250-a-1 and the sense amplifier 290-a. In some instances, charge sharing of the latch signal generation section 420 may be relatively rapid and may take a fraction of the time required for charge sharing between the memory cell 105-b-11 and the signal development component 250-a-1. In other words, the duration of the latch signal generation section 420 may be shorter than that of the read signal development section 410. In some FeRAM applications, for example, the latency associated with the operation of the latch signal generation section 420 may be approximately 5 nanoseconds to 10 nanoseconds.

[0152] In some instances, the latch signal generation section 420 may include an "excitation" sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Thus, an output signal at the sense amplifier 290-a, at least partially based on a cell read signal (e.g., at least partially based on a logic state stored by memory cell 105-b-111), may be generated. This output signal may be passed from the sense amplifier 290-a via I / O line 295 to another component of the memory device (e.g., input / output component 160) to provide an indication of the data stored by memory cell 105-b-111. In some instances, the output signal, or some other signal associated with the generated latch signal, may also be passed back to or otherwise shared with the signal development component 250-a-1, which in some instances may support rewrite operations (e.g., after a destructive read operation). For example, as part of the latch signal generation section 420, based on the generated latch signal or output signal (e.g., based on whether memory cell 105-b-111 stores logic 0 or logic 1), a rewrite signal (e.g., via signal development line 255-a-1) can be transmitted, shared, or generated using the signal development component 250-a-1. In some instances, the generated latch signal or output signal can be passed back to the signal development component 250-a-1 to reinforce the charge or other signals maintained at the signal development component 250-a-1, which can support rewrite operations on memory cell 105-b-111.

[0153] In some instances of the latch signal generation section 420, a shunt 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunt 330-a-12 (not shown, which may be associated with digital line 210-a-12 or board line 215-a-12) can be selected or activated to 330-a-1r. This allows for bias equalization across unaccessed memory cells 105-b (e.g., bias equalization between digital line 210-a-12 and board line 215-a-12, bias equalization between digital line 210-a-1r and board line 215-a-1r, etc.). In FeRAM applications, for example, this bias equalization can prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than those accessed during the latch signal generation section 420.

[0154] The rewrite signal development section 430 may be associated with charge sharing between memory cell 105-b-111, digital line 210-a-11, and signal development component 250-a-1. The rewrite signal development section 430 may be an instance of accessing signals (e.g., cell write signals, cell rewrite signals) at or using the signal development component 250-a-1 development unit. In some cases, accessing signals (e.g., cell write signals, cell rewrite signals) at or using the signal development component 250-a-1 development unit may be at least partially based on latched signals of sense amplifier 290-a (e.g., generated during latched signal generation section 420). In some instances, cell access signals (e.g., cell write signals, cell rewrite signals) at or using signal development component 250-a-1 may be based on a charge or voltage maintained at signal development component 250-a-1 (e.g., at least partially based on read signal development section 410), wherein the charge or voltage maintained at signal development component 250-a-1 may indicate a logic state initially stored by memory cell 105-b-111. In some instances, the charge or voltage maintained at signal development component 250-a-1 may be independent of the latch signal at sense amplifier 290-a, or may be amplified by the latch signal at sense amplifier 290-a (e.g., amplified during latch signal generation section 420).

[0155] In some instances, the rewrite signal developed at signal development component 250-a-1 is associated with a third latency (e.g., a relatively high latency or long duration) that may be equal to or different from the first latency. The transition from latch signal generation section 420 to rewrite signal development section 430 may include selectively decoupling or isolating signal development component 250-a-1 from sense amplifier 290-a (e.g., via selection component 280-a or isolation switch component). Although rewrite signal development section 430 may support rewriting logic states to memory cells 105 that have been discharged, depolarized, or otherwise destroyed or degraded during a read operation, in instances of non-destructive read operations (e.g., when 105-b-111 maintains the stored logic state after read signal development section 410), rewrite signal development section 430 may be omitted, and latch signal generation section 420 may subsequently be followed by another access operation (e.g., a read operation, a write operation, a refresh operation).

[0156] In various instances, the rewriting of memory cell 105-b-111 during rewrite signal development section 430 may be performed or modified based on whether the rewrite signal is generated or otherwise provided by sense amplifier 290-a or by signal development component 250-a. For example, the rewrite operation of rewrite signal development section 430 may be performed without relying on the rewrite signal of sense amplifier 290-a, for instance, when signal development component 250-a is configured to locally maintain the charge or other states associated with the initially stored logical state of memory cell 105-b-111 until it is transferred back to memory cell 105-b-111 (e.g., providing local cache functionality as associated with the rewrite operation). In other words, depending on whether the signal development component 250-a relies on the latch signal of the sense amplifier 290-a to rewrite the memory cell 105-b-111, from the perspective of the signal development component 250-a, reading the signal development section 410 or the latch signal generation section 420 may be "destructive" or not "destructive". In some instances (e.g., when the signal development component 250-a is configured to maintain a charge or other state indicating the initially stored logic state of the memory cell 105-b-111), the rewriting of the memory cell 105-b-111 may occur after a certain delay period (e.g., rewriting the signal development section 430) depending on the duration for which the signal development component 250-a-1 is configured to maintain this charge or other state or the type of control logic implementing the write-back (e.g., First-In-First-Out (FIFO), Least Recently Used (LRU), or others).

[0157] In some instances of a rewrite operation, circuitry 300 may be configured to couple memory cell 105-b-111 to a high-voltage source (e.g., a high-voltage rail, via signal development component 250-a-1), which may be direct coupling via a pull-up or pull-down circuitry system (e.g., a transistor or other switching component of signal development component 250-a-1). In some instances, signal development component 250-a-1 may be configured with a capacitor or other charge storage component, and latch signal generation section 420 or rewrite signal development section 430 may include charge sufficient to charge or refresh the capacitor or other charge storage component for rewriting memory cell 105-b-111 (e.g., during rewrite signal development section 430). Therefore, in various instances, signal development component 250-a-1 can rewrite logic states to memory cell 105-b-111, which can be performed when signal development component 250-a-1 is selectively decoupled from sense amplifier 290-a, allowing sense amplifier 290-a to freely support operation with respect to other signal development components 250-a.

[0158] The charge sharing of the rewrite signal development section 430 may be associated with a delay or wait time called a row precharge delay, which may involve completely or partially rewriting the logic state initially stored at memory cell 105-b-111. For example, to rewrite logic 0, digital line 210-a-11 may be biased to a positive voltage (e.g., 1.5V) and board line 215-a-11 may be biased to ground or a negative voltage (e.g., 0V). To rewrite logic 1, digital line 210-a-11 may be biased to ground or a negative voltage (e.g., 0V) and board line 215-a-11 may be biased to a positive voltage (e.g., 1.5V). In some cases, the biasing of digital line 210-a-11 and board line 215-a-11 may be at least partially based on the generated latch signal (e.g., before the sense amplifier 290-a is selectively isolated from the signal development component 250-a-1). For example, during the rewriting of signal development section 430, signal development component 250-a-1 may bias digital line 210-a-11 to a positive voltage or ground voltage, at least in part, based on a latch signal. In some cases, this bias may be based on a charge or other state maintained at signal development component 250-a-1, which may be independent of the generated latch signal (e.g., generated using sense amplifier 290-a).

[0159] In DRAM applications, data can be written to memory cell 105 as electrode charges and can be responded to relatively quickly (e.g., with relatively low latency). In FeRAM applications, data can be written to memory cell 105 as cell states in the form of dipole orientation or polarization. The dynamics of these dipoles can be relatively slow (e.g., with relatively high latency), which can result in longer write times for FeRAM applications (e.g., longer than for DRAM applications). Therefore, in some instances (e.g., in FeRAM applications), the rewrite signal development section 430 can be associated with relatively high latency or long duration (e.g., compared to the latch signal generation section 420). At the end of the rewrite signal development section 430, all digital lines 210-a-11 and all board lines 215-a of the ground voltage bias domain 310-a-1 can be grounded, thereby effectively equalizing the bias of each of the memory cells 105-b spanning the domain 310-a-11, which can support the maintenance of the logic states stored by the memory cells 105-b over time.

[0160] In some instances, during the rewrite signal development section 430, a shunt 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunt 330-a-12 (not shown, which may be associated with digital line 210-a-12 or board line 215-a-12) can be selected or activated to 330-a-1r. This allows for bias equalization across unaccessed memory cells 105-b (e.g., bias equalization between digital line 210-a-12 and board line 215-a-12, bias equalization between digital line 210-a-1r and board line 215-a-1r, etc.). This bias equalization prevents or reduces data loss (e.g., due to charge leakage) of memory cells 105-b other than those being rewritten during the rewrite signal development section 430.

[0161] Read operation 400 can be performed with a total duration t A1 -t A0 The reading of a single memory cell 105-b-111 is associated with a read signal development section 410, a latch signal generation section 420, and a rewrite signal development section 430 for reading the single memory cell 105-b-111. In instances where the read operation 400 does not employ multiplexing signal development techniques (e.g., a sequence of read operations 400 using the same signal development component 250), subsequent read operations using the sense amplifier 290-a can be followed by the rewrite signal development section 430. Therefore, performing multiple read operations 400 (e.g., reading multiple memory cells 105-b) using the same signal development component 250 may require a duration t. A1 -t A0 Integer multiples of (e.g., at least 2*(t) A1 -t A0 (to read two memory cells 105-b). However, multiplexing the signal development component 250-a (e.g., via the selection component 280-a) can reduce the amount of time required for the sense amplifier 290-a to read multiple memory cells 105-b.

[0162] Figure 4BThe illustration depicts an example of a read operation 450 supported by multiplexed signal development, as disclosed herein. The read operation 450 can be illustrated as a portion (e.g., a time interval) of an access operation (e.g., a multi-cell access operation) associated with the generation of cell access signals (e.g., cell read signals, cell write signals) and latch signals when accessing four memory cells 105 (e.g., via four signal development components 250). For example, the read operation 450 can be divided into a read signal development portion 410-a, a latch signal generation portion 420-a, and a rewrite signal development portion 430-a for each of a group of memory cells 105-b, which may be referenced. Figure 4A Examples of the corresponding parts described. The read operation 450 can employ a circuit system that supports multiplexed signal development, such as the reference... Figure 3 The circuit 300 described. The illustration of the read operation 450 illustrates an example of separating signal development operations from input / output operations, which can improve data throughput in a memory device.

[0163] As an illustrative example, a read operation 450 is described with reference to reading the logic states stored in four memory cells 105-b of four different domains 310-a, each of which is associated with a corresponding signal development component 250-a multiplexed with a sense amplifier 290-a. For example, the read signal development section 410-a-1, the latch signal generation section 420-a-1, and the rewrite signal development section 430-a-1 may refer to a read operation of memory cell 105-b-111 (e.g., of domain 310-a-1 associated with signal development component 250-a-1). For example, the read signal development section 410-a-2, the latch signal generation section 420-a-2, and the rewrite signal development section 430-a-2 may refer to a read operation of memory cell 105-b-211 (e.g., of domain 310-a-2 (not shown) associated with signal development component 250-a-2). For example, the read signal development section 410-a-3, the latch signal generation section 420-a-3, and the rewrite signal development section 430-a-3 may refer to a read operation of memory cell 105-b-311 (e.g., a domain 310-a-3 (not shown) that may be associated with signal development component 250-a-3). Similarly, the read signal development section 410-a-4, the latch signal generation section 420-a-4, and the rewrite signal development section 430-a-4 may refer to a read operation of memory cell 105-b-411 (e.g., a domain 310-a-4 (not shown) that may be associated with signal development component 250-a-4). Each of the signal development components 250-a-1, 250-a-2, 250-a-3 and 250-a-4 can be selectively coupled to the same sense amplifier 290-a via a selection component 280-a (e.g., based on a logic selection signal SDCM).

[0164] Each of the read signal development sections 410-a may be associated with charge sharing (which may occur during overlapping time intervals) between the corresponding memory cell 105-b, the corresponding digital line 210-a, and the corresponding signal development component 250-a. The read signal development section 410-a may be an example of developing a signal (e.g., a cell read signal) at said signal development component 250-a based at least in part on selectively coupling the signal development component 250-a of the plurality of signal development components 250-a to the memory cells 105-b of the plurality of memory cells 105-b. The read signal development section 410-a-1 may be an instance of coupling memory cell 105-b-111 (e.g., the first memory cell) with signal development component 250-a-1 (e.g., the first signal development component) (e.g., via selection component 280-a, via selection component 320-a-1) during a first time interval (e.g., and at least in part based on determining that memory cell 105-b-111 needs to be accessed), and the read signal development section 410-a-2 may be an instance of coupling memory cell 105-b-211 (e.g., the second memory cell) with signal development component 250-a-2 (e.g., the second signal development component) (e.g., via selection component 280-a, via selection component 320-a-2) during a second time interval overlapping with the first time interval (e.g., and at least in part based on determining that memory cell 105-b-211 needs to be accessed) during a second time interval (e.g., and at least in part based on determining that memory cell 105-b-211 needs to be accessed).

[0165] Therefore, charge can be shared between memory cell 105-b-111 and signal development component 250-a-1, between memory cell 105-b-211 and signal development component 250-a-2, between memory cell 105-b-311 and signal development component 250-a-3, and between memory cell 105-b-411 and signal development component 250-a-4. In other words, charge can be shared via signal development components 250-a-1 to 250-a-4 during overlapping time intervals. In some instances, the development cell read signal at signal development components 250-a-1 to 250-a-4 is associated with a first latency time (e.g., a relatively high latency time or a long duration).

[0166] In some instances of read signal development section 410-a, a shunt 330-a associated with other memory cells 105-b of the corresponding domain 310-a can be selected or activated, which allows for bias equalization across unaccessed memory cells 105-b. For example, for domain 310-a-1, during read signal development section 410-a-1, bias equalization between digital line 210-a-12 and board line 215-a-12 can be achieved via shunt 330-a-12, and bias equalization between digital line 210-a-13 and board line 215-a-13 can be achieved via shunt 330-a-13, and so on. In FeRAM applications, for example, this bias equalization can prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than those being accessed during the corresponding read signal development section 410.

[0167] The latch signal generation section 420-a may be associated with charge sharing (which may occur within non-overlapping time intervals) between corresponding components in the signal development component 250-a-1 and the sense amplifier 290-a. Each of the latch signal generation sections 420-a may be instances where the output signal of the sense amplifier 290-a is generated at least in part based on a developed signal (e.g., a cell read signal) at the corresponding signal development component 250-a. In some instances, the generation of the latch signal at the sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). The transition from the read signal development section 410 to the corresponding latch signal generation section 420-a may include selectively coupling the corresponding signal development component 250-a to the sense amplifier 290-a.

[0168] The latch signal generation section 420-a-1 may be an example of coupling the signal development component 250-a-1 (e.g., the first signal development component) to the sense amplifier 290-a (e.g., via the selection component 280-a) during a third time interval following the first time interval. In some instances, the third time interval may at least partially overlap with the second time interval, or the third time interval may be within the second time interval. The latch signal generation section 420-a-2 may be an example of coupling the signal development component 250-a-2 (e.g., the second signal development component) to the sense amplifier 290-a (e.g., via the selection component 280-a) during a fourth time interval following the second time interval (e.g., and following the third time interval).

[0169] Latch signal generation sections 420-a-1 to 420-a-4 can be executed according to a sequence, which may be at least partially based on a sequence selected by the logic select signal SDCM or otherwise indicated by the signal development components. In some instances, each of the latch signal generation sections 420-a may be separated by a gap or delay period (e.g., the period between latch signal generation section 420-a-1 and latch signal generation section 420-a-2), which may be associated with: a gap or delay of the selection component 280-a, a gap or delay associated with changing the value of the logic select signal SDCM, or a period during which no signal development component 250-a is coupled to the sense amplifier 290-a. In other words, an access operation may include a gap or delay period between when one signal development component 250-a is selectively decoupled from the sense amplifier 290-a and when another signal development component 250-a is selectively coupled to the sense amplifier 290-a. In other instances, this decoupling and coupling may be configured to occur simultaneously.

[0170] In some instances, the latch signal generation section 420-a may include an "excitation" sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Thus, according to the sequence of latch signal generation sections 420-a-1 to 420-a-4, an output signal sequence at the sense amplifier 290-a can be generated at least in part based on the corresponding cell read signal sequence (e.g., according to said sequence or read signal development sections 410-a-1 to 410-a-4, at least in part based on the logic states stored via access memory cells 105-b-111 to 105-b-411).

[0171] The output signal can be passed from sense amplifier 290-a via I / O line 295 to another component of the memory device (e.g., input / output component 160) to provide an indication of the data stored by memory cell 105-b. In some instances, the output signal, or some other signal associated with the generated latch signal, can also be passed back to signal development components 250-a-1 to 250-a-4 or otherwise shared using signal development components 250-a-1 to 250-a-4, which in some instances can support rewrite operations (e.g., after a destructive read operation). For example, as part of latch signal generation section 420, a rewrite signal can be passed or otherwise shared using one of the signal development components 250-a-1 to 250-a-4 based on the generated latch signal or output signal (e.g., based on whether memory cell 105-b stores logic 0 or logic 1).

[0172] In some instances of latch signal generation section 420-a, a shunt 330-a associated with other memory cells 105-b in the corresponding domain 310-a can be selected or activated, which allows bias equalization across unaccessed memory cells 105-b. For example, for domain 310-a-1, during latch signal generation section 420-a-1, bias equalization between digital line 210-a-12 and board line 215-a-12 can be achieved via shunt 330-a-12, and bias equalization between digital line 210-a-13 and board line 215-a-13 can be achieved via shunt 330-a-13, and so on. In FeRAM applications, for example, this bias equalization can prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than those being accessed during the corresponding latch signal generation section 420.

[0173] The rewrite signal development section 430-a may be associated with charge sharing between a corresponding one in memory cell 105-b, a corresponding one in digital line 210-a, and a corresponding one in signal development component 250-a. The rewrite signal development section 430-a may each be an example of developing cell access signals (e.g., cell write signals, cell rewrite signals) at signal development component 250-a based at least in part on the latch signal of sense amplifier 290-a, or it may be independent of the latch signal of sense amplifier 290-a. In some instances, the development of the rewrite signal at signal development component 250-a-1 is associated with a third latency time (e.g., a relatively high latency time or a long duration), which may be equal to or different from the first latency time. The transition from latch signal generation section 420-a to the corresponding rewrite signal development section 430-a may include selectively isolating the corresponding signal development component 250-a from sense amplifier 290-a (e.g., via selection component 280-a or another isolation switch component). Although the rewrite signal development section 430-a can support rewriting logic states to memory cells 105 that have been discharged, depolarized, or otherwise damaged or degraded during a read operation, the rewrite signal development section 430-a can be omitted in instances of non-destructive read operations (e.g., in connection with charge sharing between the SDC and the memory cell).

[0174] In some instances of the rewrite signal development section 430-a, a shunt 330-a associated with other memory cells 105-b of the corresponding domain 310-a can be selected or activated, which allows for bias equalization across unaccessed memory cells 105-b. For example, for domain 310-a-1, during the rewrite signal development section 430-a-1, bias equalization can be achieved between digital line 210-a-12 and board line 215-a-12 via shunt 330-a-12, and bias equalization can be achieved between digital line 210-a-13 and board line 215-a-13 via shunt 330-a-13, and so on. This bias equalization prevents or reduces data loss (e.g., due to charge leakage) of memory cells 105-b other than those accessed during the rewrite signal development section 430-a.

[0175] Similar to read operation 400, read operation 450 can also be associated with a total duration t. A1 -t A0 A read operation of a single memory cell 105 (e.g., via a sense amplifier 290-a) may include a read signal development section 410-a-1, a latch signal generation section 420-a-1, and a rewrite signal development section 430-a-1 for reading a single memory cell 105-b-111. However, by employing multiplexed signal development as disclosed herein, multiple read operations can be performed via the same sense amplifier 290-a without incurring a duration t. A1 -t A0 The integer multiple of the number of memory cells 105-b accessed in parallel (e.g., the integer multiple may correspond to the number of memory cells 105-b accessed in parallel). Specifically, by generating cell access signals in overlapping time intervals (e.g., the time interval of the read signal development section 410-a or rewrite signal development section 430-a of signal development component 250-a-1 that overlaps with the time interval of the read signal development section 410-a or rewrite signal development section 430-a of signal development component 250-a-2, etc.), multiple memory cells 105-b can be read in a shorter time than this integer multiple. In other words, according to the described technique for multiplexed signal development, the sense amplifier 290-a can support t A3 -t A2 Four memory cells 105-b are read within a duration that may be shorter than 4*(t). A1 -t A0 (For example, shorter than an integer multiple of the duration used to read a single memory cell 105-b).

[0176] In one example, the rewrite signal development sections 430-a-1, 430-a-2, 430-a-3, and 430-a-4 of the first group of reads may be subsequently followed by the read signal development sections 410-a-5, 410-a-6, 410-a-7, and 410-a-8 of the second group of reads, respectively. The first group of reads may be associated with a first digital line index (e.g., the value of "1", as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second group of reads may be associated with a second digital line index (e.g., the value of "2", as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Alternatively, more generally, the first group of reads and the second group of reads may differ at least in part based on the selected digital line 210-a of the read operation.

[0177] In some instances (e.g., where the selection component 320-a spanning domain 310-a is independently controllable, and the logic selection signal DLM spanning domain 310-a is independently controllable), a new digital line 210-a can be selected for the same signal development component 250 (e.g., via selection component 320-a) once the rewrite signal development portion 430 is completed for the signal development component 250. In other words, as illustrated in the example of operation 450, for the signal development component 250-a multiplexed with the same sense amplifier 290-a, the first set of read rewrite signal development portions 430-a can overlap in time with the second set of read read signal development portions 410-a (e.g., read signal development portion 410-a-5 overlaps with rewrite signal development portion 430-a-4). Therefore, in the example of operation 450 where domains 310-a-1 to 310-a-4 are independently controllable, the periodicity for reading the four memory cells 105 can be determined by time t. A3 -t A2 Diagram illustrating time t A3 -t A2 In some instances, it can be equal to or nearly equal to time t. A1 -t A0 , or t A1 -t A0 In addition to a certain delay or gap period (e.g., associated with selecting a new digital line 210-a via selection component 320-a), or some other duration based on: the total duration associated with the read operation (e.g., t A1 -t A0 The corresponding waiting time of the sub-operation (e.g., the relative duration of the read signal development section 410, the latch signal generation section 420, and the rewrite signal development section 430) and the degree of multiplexing (e.g., the number of signal development components 250-a that are multiplexed with the sense amplifier 290-a).

[0178] In some instances, subsequent reads can be performed on memory cell 105-b, which is coupled to a digital line 210-a different from the previous read operation but to the same activated word line 205-a (this reduces latency). For example, maintaining the selected word line 205-a eliminates word line deselection operations and subsequent word line selection operations. Such instances may involve shunting the digital line 210-a associated with an earlier read operation (e.g., a previously un-shunted digital line 210-a) and not shunting the digital line 210-a associated with a later read operation (e.g., a digital line 210-a shunted during an earlier write operation).

[0179] In another instance not shown, a set of reads may be associated with a first common word line (e.g., where logic word lines WL are activated simultaneously). 11 WL 21 WL 31 and WL 41 The second set of reads can be associated with the second common word line (e.g., where logic word line WL is activated simultaneously). 12 WL 22 WL 32 and WL 42 Alternatively, and more generally, the first set of reads and the second set of reads may differ at least in part based on the selection of a common word line 205-a for the read operation. In some instances (e.g., where word lines 205-a spanning domain 310-a are not independently controllable), a new word line 205-a may be selected for all multiplexed signal development components 250-a (e.g., associated with sense amplifier 290-a or other sets of domain 310-a that are not independently controllable) upon completion of latch signal generation section 420 or completion of rewrite signal development section 430. In other words, in some instances, for signal development components multiplexed with the same sense amplifier 290-a, the latch signal generation section 420 or rewrite signal development section 430 of the first set of reads may not overlap in time with the read signal development section 410 of the second set of reads.

[0180] For example, when word line 205-a spanning domains 310-a-1 to 310-a-4 is not independently controllable, read signal development section 410-a-5 may follow rewrite signal development section 430-a-4 or otherwise follow rewrite signal development section 430-a-4. Therefore, in instances where domain 310-a is not independently controllable, the periodicity for reading four memory cells 105 may be equal to or nearly equal to the combined time of a read signal development section 410-a, each of the latch signal generation sections 420-a-1 to 420-a-4 of multiplexed signal development components 250-a-1 to 250-a-4, and a rewrite signal development section 430-a, plus any associated delay or gap period (e.g., associated with selecting a new word line 205-a or selecting a new signal development component 250-a via selection component 280-a). Therefore, in some instances, where domain 310-a is not independently controllable, this periodicity is comparable to that determined by time t. A2 -t A0 The illustrated explanations have long periods of time.

[0181] Therefore, according to the various examples disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when multiple memory cells 105-b are accessed in parallel) can be scaled proportionally to the relative latency difference (e.g., duration) between the read signal development section 410, the latch signal generation section 420, and the rewrite signal development section 430. The advantages provided by the described signal development multiplexing can also depend on whether the domain 310-a is configured to be independently controllable or controlled via a common access line or a common logic signal.

[0182] Figure 5A The diagram illustrates an example of a write operation 500 that supports multiplexed signal development, as disclosed herein. The write operation 500 can be illustrated as a portion (e.g., a time interval) of an access operation associated with the generation of latch signals and cell access signals (e.g., cell write signals) when accessing memory cell 105. For example, the write operation 500 can be divided into a latch signal generation portion 510 and a write signal development portion 520 (e.g., a cell write portion). The write operation 500 can employ a circuit system that supports multiplexed signal development, such as referenced in [reference needed]. Figure 3 The circuit 300 is described. As an illustrative example, a write operation 500 is described with reference to writing logic states to memory cells 105-b-111 of the circuit 300, but the write operation 500 may illustrate an operation that can be performed on any or more of the memory cells 105-b of the circuit 300.

[0183] The latch signal generation section 510 may be associated with charge sharing between the signal development component 250-a-1 and the sense amplifier 290-a. The latch signal generation section 510 may be an example of generating a latch signal at the sense amplifier 290-a or the signal development component 250-a-1 based at least in part on a write command or write signal received via I / O line 295-a (e.g., from the input / output component 160 or the memory controller 170). In some instances, the generation of a latch signal at the sense amplifier 290-a or the signal development component 250-a-1 is associated with a fourth latency time (e.g., a relatively low latency time or short duration), which may be the same as or different from the second latency time of the latch signal generation section 420 described in reference read operations 400 and 450.

[0184] The latch signal generation section 510 may include selective coupling of the signal development component 250-a-1 to the sense amplifier 290-a (e.g., at the beginning of the latch signal generation section 510, or at another time after other operations of the latch signal generation section 510, such as after receiving a write command or write signal via I / O line 295-a). In some instances, selective coupling of the signal development component 250-a-1 to the sense amplifier 290-a may include selection via the selection component 280-a based on the logic selection signal SDCM. In some instances, selective coupling of the signal development component 250-a-1 to the sense amplifier 290-a may include selective coupling via another switching component (e.g., an isolation switching component) between the signal development component 250-a-1 and the sense amplifier 290-a.

[0185] In some instances, the latch signal generation section 510 may include an "excitation" sense amplifier 290-a, which may involve selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Thus, a latch signal, at least in part based on a write command or write signal (e.g., received via I / O line 295-a), may be generated at the sense amplifier 290-a. The generated latch signal, or some other signal associated with the generated latch signal, may be passed to or otherwise shared with the signal development component 250-a-1 to support writing to the memory cell 105-b-111. For example, as part of the latch signal generation section 510, based on the generated latch signal (e.g., based on whether the memory cell 105-b-111 stores logic 0 or logic 1), a write signal (e.g., via signal development line 255-a-1) can be transmitted or otherwise shared or generated using the signal development component 250-a-1.

[0186] The write signal development section 520 may be associated with charge sharing between memory cell 105-b-111, digital line 210-a-11, and signal development component 250-a-1. The write signal development section 520 may be an instance of developing a cell access signal (e.g., a cell write signal) at or using the signal development component 250-a-1 based at least in part on a latch signal from the sense amplifier 290-a. In some instances, developing a write signal at the signal development component 250-a-1 is associated with a fifth latency time (e.g., a relatively high latency time or a long duration), which may or may not be equal to the third latency time of the rewrite signal development section 430 described with reference to read operations 400 and 450. The transition from the latch signal generation section 510 to the write signal development section 520 may include selectively decoupling or isolating the signal development component 250-a-1 from the sense amplifier 290-a (e.g., via a selection component 280-a or an isolation switch component).

[0187] In some instances of write operations, circuitry 300 may be configured to couple memory cell 105-b-111 to a high-voltage source (e.g., a high-voltage rail, via signal development component 250-a-1), which may be direct coupling via a pull-up or pull-down circuitry system (e.g., a transistor or other switching component of signal development component 250-a-1). In some instances, signal development component 250-a-1 may be configured with capacitors or other charge storage components, and latch signal generation section 510 or write signal development section 520 may contain charge sufficient to rewrite memory cell 105-b-111 (e.g., during write signal development section 520) to charge or refresh the capacitors or other charge storage components. Therefore, in various instances, signal development component 250-a-1 can write logic states to memory cell 105-b-111, which can be performed when signal development component 250-a-1 is selectively decoupled from sense amplifier 290-a, allowing sense amplifier 290-a to freely support operation with respect to other signal development components 250-a.

[0188] The charge sharing of the write signal development section 520 can also be associated with a delay or latency period called row precharge delay, which may include writing logic states to memory cell 105-b-111 based on a write command. For example, to write logic 0, digital line 210-a-11 can be biased to a positive voltage (e.g., 1.5V) and board line 215-a-11 can be biased to ground or a negative voltage (e.g., 0V). To write logic 1, digital line 210-a-11 can be biased to ground or a negative voltage (e.g., 0V) and board line 215-a-11 can be biased to a positive voltage (e.g., 1.5V). The biasing of digital line 210-a-11 and board line 215-a-11 may be at least partially based on the generated latch signal (e.g., before the sense amplifier 290-a is selectively isolated from the signal development component 250-a-1). For example, during the write signal development section 520, the signal development component 250-a-1 may bias digital lines 210-a-11 to a positive voltage or ground voltage, at least in part based on latch signals (e.g., at least in part based on write commands). At the end of the write signal development section 520, all digital lines 210-a-11 and all board lines 215-a of the domain 310-a-1 may be grounded, thereby effectively equalizing the bias of each of the memory cells 105-b spanning the domain 310-a-11, which can support the maintenance of the logic state stored by the memory cells 105-b over time.

[0189] In some instances, during the write signal development section 520, shunts 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunts 330-a-12 to 330-a-1r, can be selected or activated. This allows for bias equalization across unaccessed memory cells 105-b (e.g., bias equalization between digital line 210-a-12 and board line 215-a-12, bias equalization between digital line 210-a-1r and board line 215-a-1r, etc.). This bias equalization prevents or reduces data loss (e.g., due to charge leakage) of memory cells 105-b other than those being written to during the write signal development section 520.

[0190] Write operation 500 can be performed with a total duration t B1 -t B0The write operation of a single memory cell 105-b-111 is associated with a latch signal generation section 510 and a write signal development section 520 for writing to the single memory cell 105-b-111. In instances where the write operation 500 does not employ a multiplexed signal development technique (e.g., a sequence of write operations 500 using the same signal development component 250), subsequent write operations using the sense amplifier 290-a may follow the write signal development section 520. Therefore, performing multiple write operations 500 (e.g., writing to multiple memory cells 105-b) using the same signal development component 250 may require a duration t. B1 -t B0 Integer multiples of (e.g., at least 2*(t) B1 -t B0 (to read two memory cells 105-b). However, multiplexing the signal development component 250-a (e.g., via the selection component 280-a) can reduce the amount of time required for the sense amplifier 290-a to write to multiple memory cells 105-b.

[0191] Figure 5B The diagram illustrates an example of a write operation 550 supporting multiplexed signal development, as disclosed herein. The write operation 550 can be illustrated as a portion (e.g., a time interval) of an access operation (e.g., a multi-cell access operation) associated with the generation of latch signals and cell access signals (e.g., cell write signals) when accessing four memory cells 105 (e.g., via four signal development components 250). For example, the write operation 550 can be divided into a latch signal generation portion 510-a and a write signal development portion 520-a for each of a group of memory cells 105-b, which can be referenced. Figure 5A Examples of the corresponding parts described. Write operation 550 can employ a circuit system that supports multiplexed signal development, such as referenced... Figure 3 The circuit 300 described. The write operation 550 diagram illustrates an example of separating signal development operations from input / output operations, which can improve data throughput in a memory device.

[0192] As an illustrative example, a write operation 550 is described with reference to four memory cells 105-b that write logic states to four different domains 310-a, each of which is associated with a corresponding signal development component 250-a multiplexed with a sense amplifier 290-a. For example, the latch signal generation section 510-a-1 and the write signal development section 520-a-1 may refer to a write operation to memory cell 105-b-111 (e.g., of domain 310-a-1 associated with signal development component 250-a-1). For example, the latch signal generation section 510-a-2 and the write signal development section 520-a-2 may refer to a write operation to memory cell 105-b-211 (e.g., of domain 310-a-2 (not shown) associated with signal development component 250-a-2). For example, the latch signal generation section 510-a-3 and the write signal development section 520-a-3 may refer to a write operation of memory cell 105-b-311 (e.g., domain 310-a-3 (not shown) associated with signal development component 250-a-3). For example, the latch signal generation section 510-a-4 and the write signal development section 520-a-4 may refer to a write operation of memory cell 105-b-411 (e.g., domain 310-a-4 (not shown) associated with signal development component 250-a-4). Each of the signal development components 250-a-1, 250-a-2, 250-a-3, and 250-a-4 may be selectively coupled to the same sense amplifier 290-a via selection component 280-a (e.g., based on logic select signal SDCM).

[0193] Each of the latch signal generation sections 510-a may be associated with charge sharing (which may occur within non-overlapping time intervals) between a corresponding member of the signal development component 250-a-1 and the sense amplifier 290-a. Each of the latch signal generation sections 510-a may be instances where a signal is generated at the signal development component 250-a based at least in part on selectively coupling the signal development component 250-a to the sense amplifier 290-a (e.g., an amplifier assembly). In some instances, this signal may be generated at least in part based on a write command or write signal. In some instances, the generation of the latch signal is associated with a fourth latency time (e.g., a relatively low latency time or short duration).

[0194] The latch signal generation section 510-a-1 may be an example of coupling the signal development component 250-a-1 (e.g., a first signal development component) to the sense amplifier 290-a (e.g., an amplifier component) (e.g., via the selection component 280-a) during a first time interval and at least in part based on determining that memory cell 105-b-111 (e.g., a first memory cell) needs to be accessed. The latch signal generation section 510-a-2 may be an example of coupling the signal development component 250-a-2 (e.g., a second signal development component) to the sense amplifier 290-a (e.g., via the selection component 280-a) during a second time interval following the first time interval and at least in part based on determining that memory cell 105-b-211 (e.g., a second memory cell) needs to be accessed.

[0195] Latch signal generation sections 510-a-1 to 510-a-4 can be executed according to a sequence that can be at least partially based on a sequence of commands or signals written to memory cells (e.g., received via I / O line 295-a). This sequence can also correspond to a sequence selected by the logic select signal SDCM or otherwise indicated by the signal development component 250-a. In some instances, each of the latch signal generation sections 510-a can be separated by a gap or delay period (e.g., the period between latch signal generation section 510-a-1 and latch signal generation section 510-a-2), which can be associated with: a gap or delay of the selection component 280-a, a gap or delay associated with changing the value of the logic select signal SDCM, or a period during which no signal development component 250-a is coupled to the sense amplifier 290-a. In other words, the access operation may include a gap or delay period between when one signal development component 250-a is selectively decoupled from the sense amplifier 290-a and when another signal development component 250-a is selectively coupled to the sense amplifier 290-a. In other instances, this decoupling and coupling may be configured to occur simultaneously.

[0196] In some instances, the latch signal generation section 510-a may include an "excitation" sense amplifier 290-a, which may involve selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Thus, according to the latch signal generation sections 510-a-1 to 510-a-4 sequence, a signal sequence at least partially based on the corresponding write command or signal sequence can be generated at the sense amplifier 290-a or the signal development component 250-a.

[0197] As part of or in conjunction with a write operation, one or more signals may be transmitted between the sense amplifier 290 and the signal development component 250. For example, the generated latch signal may also be passed back to signal development components 250-a-1 to 250-a-4 or otherwise shared using signal development components 250-a-1 to 250-a-4 to support the corresponding write operation. For example, as part of the latch signal generation section 510-a, based on the generated latch signal (e.g., based on whether memory cell 105-b stores logic 0 or logic 1), a write signal may be passed through or otherwise shared using one of the signal development components 250-a-1 to 250-a-4.

[0198] The write signal development section 520-a may be associated with charge sharing between a corresponding one in memory cell 105-b, a corresponding one in digital line 210-a, and a corresponding one in signal development component 250-a. Each write signal development section 520-a may be an instance of developing a cell access signal (e.g., a cell write signal) at signal development component 250-a based at least in part on a latch signal from sense amplifier 290-a. The transition from latch signal generation section 510 to the corresponding write signal development section 520-a may include selectively isolating the corresponding signal development component 250-a from sense amplifier 290-a (e.g., via selection component 280-a or another isolation switch component). The write signal development section 520-a-1 may be an instance of coupling signal development component 250-a-1 (e.g., a first signal development component) to memory cell 105-b-111 (e.g., a first memory cell) during a third time interval following the first time interval. In some instances, the second time interval occurs within, or at least partially overlaps with, the third time interval. Writing the signal development section 520-a-2 may be an example of coupling the signal development component 250-a-2 (e.g., a second signal development component) to the memory cell 105-b-211 (e.g., a second memory cell) during a fourth time interval following the second time interval which overlaps with the third time interval.

[0199] In some instances of the write signal development section 520-a, a shunt 330-a associated with other memory cells 105-b in the corresponding domain 310-a can be selected or activated, which allows for bias equalization across unaccessed memory cells 105-b. For example, for domain 310-a-1, during the write signal development section 520-a-1, the bias between digital line 210-a-12 and board line 215-a-12 can be equalized via shunt 330-a-12, and the bias between digital line 210-a-13 and board line 215-a-13 can be equalized via shunt 330-a-13, and so on. This bias equalization prevents or reduces data loss (e.g., due to charge leakage) of memory cells 105-b other than those accessed during the write signal development section 520-a.

[0200] Similar to write operation 500, write operation 550 can also be associated with a total duration t. B1 -t B0 A write operation to a single memory cell 105 (e.g., via a sense amplifier 290-a) may include a latch signal generation section 510-a-1 and a write signal development section 520-a-1 for writing to a single memory cell 105-b-111. However, by employing a multiplexed signal development according to an example disclosed herein, multiple write operations can be performed via the same sense amplifier 290-a without incurring a duration t. B1 -t B0 The integer multiple of the number of memory cells 105-b written in parallel (e.g., the integer multiple may correspond to the number of memory cells 105-b written in parallel). Specifically, by generating cell access signals in overlapping time intervals (e.g., the time interval of the write signal development portion 520-a of signal development component 250-a-1 overlapping with the time interval of the write signal development portion 520-a of signal development component 250-a-2, etc.), multiple memory cells 105-b can be written in a shorter time than this integer multiple. In other words, according to the described technique for multiplexed signal development, the sense amplifier 290-a can support t B2 -t B0 Writes are performed on four memory cells 105-b over a duration that may be shorter than 4*(t). B1– t B0 (For example, shorter than an integer multiple of the duration for writing to a single memory cell 105-b).

[0201] In one example, the write signal development portions 520-a-1, 520-a-2, 520-a-3, and 520-a-4 of the first group of writes may be subsequently followed by the latch signal generation portions 510-a-5, 510-a-6, 510-a-7, and 510-a-8 of the second group of writes, respectively. The first group of writes may be associated with a first digital line index (e.g., the value of "1", as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second group of writes may be associated with a second digital line index (e.g., the value of "2", as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Alternatively, more generally, the first group of writes and the second group of writes may be at least partially different based on the selected digital line 210-a of the write operation. In some instances (e.g., where the selection component 320-a spanning domain 310-a is independently controllable, and the logic selection signal DLM spanning domain 310-a is independently controllable), once the write signal development portion 520-a is completed for the signal development component 250, a new digital line 210-a can be selected for the same signal development component 250 (e.g., via the selection component 320-a). In other words, as illustrated in the example of operation 550, for a signal development component 250-a multiplexed with the same sense amplifier 290-a, the first set of write signal development portions 520-a can overlap in time with the second set of write latch signal generation portions 510-a (e.g., latch signal generation portion 510-a-5 overlaps with write signal development portion 520-a-4). Therefore, in an instance where domains 310-a-1 to 310-a-4 are independently controllable operations 550, the periodicity for writing to the four memory cells 105 can be determined by time t. B2 -t B0 Diagram illustrating time t B2 -t B0 This can be based on the total duration associated with the write operation (e.g., t). B1 -t B0 The corresponding waiting time of the sub-operation (e.g., the relative duration of the latch signal generation section 510-a and the write signal development section 520-a) and the degree of multiplexing (e.g., the number of signal development components 250-a that are multiplexed with the sense amplifier 290-a).

[0202] In some instances, subsequent writes can be performed on memory cell 105-b, which is coupled to a digital line 210-a different from the previous write operation, but to the same activated word line 205-a (this reduces latency). For example, maintaining the selected word line 205-a eliminates word line deselection operations and subsequent word line selection operations. Such instances can be implemented by shunting the digital line 210-a associated with an earlier write operation (e.g., a previously unshunted digital line 210-a) and not shunting the digital line 210-a associated with a later write operation (e.g., a digital line 210-a shunted during an earlier write operation).

[0203] In another instance not shown, a set of writes may be associated with a first common word line (e.g., where logical word lines WL of different domains are activated simultaneously). 11 WL 21 WL 31 and WL 41 The second set of writes can be associated with a second common word line (e.g., where logic word lines WL of different domains are activated simultaneously). 12 WL 22 WL 32 and WL 42 Alternatively, and more generally, the first set of writes and the second set of writes may differ at least in part based on the selection of a common word line 205-a for the write operation. In some instances (e.g., where word lines 205-a spanning domain 310-a are not independently controllable), a new word line 205-a may be selected once the write signal development portion 520 is completed for all multiplexed signal development components 250-a (e.g., associated with sense amplifier 290-a or other groups of domain 310-a that are not independently controllable). In other words, in some instances, for signal development components 250 multiplexed with the same sense amplifier 290-a, the write signal development portion 520 of the first set of writes may not overlap in time with the latch signal generation portion 510 of the second set of writes.

[0204] For example, when word line 205-a spanning domains 310-a-1 to 310-a-4 is not independently controllable, latch signal generation section 510-a-5 may follow write signal development section 520-a-4 or otherwise follow write signal development section 520-a-4. Therefore, in instances where domain 310-a is not independently controllable, the periodicity for writing to the four memory cells 105 may be equal to or nearly equal to the combined time of each of the latch signal generation sections 510-a-1 to 510-a-4 for multiplexing signal development components 250-a-1 to 250-a-4 with one of the write signal development sections 520-a. Therefore, in some instances, this periodicity where domain 310-a is not independently controllable may be greater than that determined by time t. B2 -t B0 The illustrated explanations have long periods of time.

[0205] Therefore, according to the various examples disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when multiple memory cells 105-b are accessed in parallel) can be scaled proportionally to the relative latency difference (e.g., duration) between the latch signal generation section 510 and the write signal development section 520. The advantages of the described signal development multiplexing can also depend on whether the domain 310-a is configured to be independently controllable or controlled via a common access line or a common logic signal.

[0206] Figure 6 The illustration shows an example of a signal development component 250-b that supports the development of multiplexed signals, as shown in the examples disclosed herein. The signal development component 250-b can be used as a reference. Figure 1 Examples of signal development components 250 described in section 5. Signal development component 250-b may be coupled to or between digital line 210-b and signal development line 255-b. Signal development component 250-b may include a capacitor 610 (e.g., an integrating capacitor) and a transistor 620 that can be configured as an amplifier configuration (e.g., as a charge transfer sensing amplifier, as a gate-cathode amplifier).

[0207] Capacitor 610 may be an example of a signal storage component or charge storage component of signal development assembly 250-b. In examples of signal development assembly 250-b, capacitor 610 may be coupled to or between a line of signal development assembly 250-b (e.g., signal development line 255-b) and a voltage source 615 (e.g., a ground voltage source, a voltage source having a reference voltage for capacitor 610) and a voltage source 615. Although illustrated as including capacitor 610, according to examples disclosed herein, signal development assembly 250 may additionally or alternatively include or otherwise employ transistors, diodes, or other components in a particular state that can provide functionality as a signal storage component or charge storage component in signal development assembly 250. In some examples, a group of signal development assemblies 250-b may include a group of capacitors 610, which can provide a cache memory in a fast local memory in a device containing a group of signal development assemblies 250-b.

[0208] In some instances, the memory device including signal development component 250-b may include memory cells 105 employing logic storage elements, which include capacitive elements (e.g., linear capacitors in DRAM applications, ferroelectric capacitors in FeRAM applications). In various instances, capacitor 610 may include the same capacitive elements or techniques as the logic storage elements (e.g., capacitor 610 may be a linear capacitor in DRAM applications, capacitor 610 may be a ferroelectric capacitor in FeRAM applications), or different capacitive elements or techniques (e.g., capacitor 610 may be a linear capacitor in FeRAM applications).

[0209] Transistor 620 may be an example of an amplifier or voltage regulator for signal development assembly 250-b, and may be configured to transfer charge between signal development line 255-b and digital line 210-b based at least in part on one or both of the voltage of signal development line 255-b (e.g., a first access line) and digital line 210-b (e.g., a second access line). For example, the gate node of transistor 620 may be coupled to voltage source 625, and charge may be transferred across the transistor based at least in part on the relationship between the voltage of voltage source 625 (e.g., V2) and the voltage of digital line 210-b. In various instances, transistor 620 may be associated with one or more digital lines 210 (e.g., multiplexed digital lines 210) and may be located outside the illustrative boundary of signal development assembly 250-b (e.g., in an example of a memory device that includes transistor 620 for each of a set of multiplexed digital lines 210).

[0210] Transistor 620 provides signal conversion between digital line 210-b and signal development line 255-b. For example, transistor 620 can immediately allow a charge flow (e.g., current) from signal development line 255-b (e.g., from capacitor 610) to digital line 210-b, such as being fed or enabled by voltage source 625, after a voltage drop on digital line 210-b (e.g., after selecting memory cell 105 via selection component 320 and selecting digital line 210). A relatively small charge flow to digital line 210-b may be associated with a relatively small voltage change on signal development line 255-b, while a relatively large charge flow to digital line 210-b may be associated with a relatively large voltage change on signal development line 255-b. Depending on the net capacitance of signal development line 255-b (e.g., including capacitor 610), for example, signal development line 255-b may experience a relatively small or relatively large voltage change after selecting memory cell 105, depending on the charge flow across transistor 620. In some instances, transistor 620 or signal development component 250-b may be isolated from digital line 210-b by a switching component or selection component (e.g., selection component 320). Transistor 620 may also be referred to as a "voltage regulator" or "bias component," which relates to how transistor 620 regulates charge flow in response to voltage on digital line 210-b.

[0211] In some instances, signal development component 250-b may include circuitry configured to support selective coupling (e.g., of signal development line 255-b) to a relatively high voltage (e.g., voltage source 635). For example, signal development component 250-b may include a switching component 630 operable based on logic signal SW1. In some instances, voltage source 645 may be coupled to a relatively high voltage rail or supply, which may support charging capacitor 610 (e.g., for use in development cell access signals).

[0212] In some instances, signal development component 250-b may include circuitry configured to support (e.g., digital line 210-b) selective coupling to a reference voltage (e.g., voltage source 645). For example, signal development component 250-b may include a switching component 640 operable based on logic signal SW2. In some instances, voltage source 645 may be coupled to a ground or virtual ground rail or supply. In some instances, voltage source 645 may be coupled to the same rail or supply as voltage source 615 (e.g., V1 may equal V4).

[0213] In some instances, signal development component 250-b may include a circuitry configured to support selective coupling (e.g., signal development line 255-b, signal development component 250-b) with another component (e.g., selection component 280, sense amplifier 290). For example, signal development component 250-b may include a switching component 650, which may be referred to as an isolation switch component and may be operable based on a logic signal ISO. Alternatively or additionally, according to examples disclosed herein, the isolation switch component may be included within sense amplifier 290.

[0214] Figure 7 The illustration depicts an example of a sense amplifier 290-b developed to support multiplexed signals, as shown in the examples disclosed herein. The sense amplifier 290-b can be used as a reference. Figure 1 Examples of the sense amplifier 290 described in section 5. The sense amplifier 290-b may be coupled to or between signal line 285-b and reference line 275-b. The sense amplifier 290-b may also be associated with (e.g., coupled to) I / O lines 295-b and 295-c. In some instances, the sense amplifier 290-b may be referred to as an amplifier component of a memory device.

[0215] The sensing amplifier 290-b may include a pair of opposing amplifiers 710-a and 710-b. Although illustrated as amplifier 710, the sensing amplifier 290-b may alternatively or equivalently include several pairs of cross-coupled transistors (e.g., a pair of cross-coupled p-type transistors and a pair of cross-coupled n-type transistors).

[0216] In some instances, the sense amplifier 290-b may include circuitry configured to support (e.g., amplifiers 710-a and 710-b) selective coupling with low and high voltage sources of the sense amplifier (e.g., voltage sources 293-b and 294-b). For example, the sense amplifier 290-b may include switching components 730-a and 730-b, respectively operable based on logic signals SW3 and SW4. In some instances, activating or selecting logic signals SW3 and SW4 may be referred to as activating or latching the sense amplifier 290-b.

[0217] In some instances, the sense amplifier 290-b may include circuitry configured to support selective coupling or decoupling from another component (e.g., signal development component 250, selection component 280, reference component 270). For example, the sense amplifier 290-b may include switching components 720-a and 720-b, which may be referred to as isolation switching components and may be operable based on logic signals ISO1 and ISO2. Alternatively or additionally, according to the examples disclosed herein, the isolation switching components may be included within the signal development component 250 or the selection component 280.

[0218] In some instances (e.g., supporting readout operations), the sense amplifier 290-a may generate an output signal at least partially based on the cell readout signal. For example, a signal development component 250 (e.g., one of a set of signal development components 250) may transmit the cell access signal via signal line 285-b, or otherwise share a charge at least partially based on the cell access signal with the sense amplifier 290-b. A reference component 270 may transmit a reference signal via reference line 275-b, or otherwise share a charge at least partially based on the reference signal with the sense amplifier 290-a. When the signal line 285-b has a higher voltage than the reference line 275-b, a relatively higher voltage (e.g., V) may be utilized. H I / O line 295-b and having a relatively low voltage (e.g., V) L The I / O line 295-c generates the output signal. When the reference line 275-b has a higher voltage than the signal line 285-b, a relatively high voltage (e.g., V) can be used. H I / O lines 295-c and those with relatively low voltages (e.g., V) L The I / O line 295-b of the sensor amplifier 290-b generates an output signal. In some instances, the switching components 720-a and 720-b can be closed to receive a cell read signal or a cell reference signal, and then the switching components 720-a and 720-b can be opened when the sense amplifier 290-b is activated (e.g., "latched").

[0219] In some instances, the generated latch signal or the generated output signal may be shared with or otherwise associated with a write signal or rewrite signal transmitted via signal line 285-b to a selected signal development component 250 (e.g., after closing switch component 720-a). In some instances, a write command or write signal may be received at sense amplifier 290-b (e.g., from input / output component 160 via I / O lines 295-b and 295-c), and the received write command or write signal may be latched, shared (e.g., via signal line 285-b), or otherwise associated with a unit write signal generated by the selected signal development component 250.

[0220] Figure 8 A block diagram of a system 800 supporting multiplexed signal development according to an example disclosed herein is shown. System 800 may include a memory array 805, a selection component 815, a signal development component array 825, a selection component 830, and a sense amplifier array 835.

[0221] Memory array 805 may include a set of memory cells 105, which can be used with, for example, reference... Figures 1 to 3 The access lines described are associated with the access lines (e.g., word lines 205, number lines 210, board lines 215). In some instances, the memory array may be associated with A rows (e.g., A independently accessible word lines 205) and B columns (e.g., B independently accessible number lines 210). In one instance, the memory array 805 may be associated with 1,048,576 memory cells 105 arranged according to 1,024 word lines 205 and 1,024 number lines 210.

[0222] In some instances, the memory array 805 may be arranged in a set of domains (which may be similar to the reference). Figure 3 In the described domain 310). In one example, the memory array 805 may be split into four domains, and each of the four domains may have four independent bands with board control (e.g., each domain of the memory array 805 may have four bands with a common bias board line 215). In such an example, the memory array 805 may be arranged according to 16 control bands, which may be associated with selecting 64 bits of data.

[0223] Signal development component array 825 may include a set of signal development components 250, which may include references Figures 2 to 7The signal development component 250 is described in various aspects. In some instances, the signal development components 250 of the signal development component array 825 can be arranged in a grid with C rows and D columns. In some instances, each of the D columns can be associated with a cache block, and each of the C rows can be associated with a position in the corresponding cache block. In one instance, the signal development component array 825 can be associated with eight cache blocks, each having 64 positions. Each position in each of the cache blocks can correspond to a single signal development component 250.

[0224] Selection component 815 may include various components that support mapping memory cells 105 of memory array 805 to signal development components 250 of signal development component array 825. For example, selection component 815 may provide selective coupling and decoupling of individual digital lines 210 of memory array 805 to individual signal development components 250 of signal development component array 825 to support various instances of multiplexed signal development described herein.

[0225] Selection component 815 may be coupled to memory array 805 via bus 810 having N signal paths, and selection component 815 may be coupled to signal development component array 825 via bus 820 having M signal paths. In some instances, selection component 815 may be coupled to each of the digital lines 210 of memory array 805 (e.g., where N = B). In some instances, bus 820 may have fewer signal paths than bus 810, where M is associated with the number of cache memory blocks of the signal development component array. For example, bus 810 may have N = 1,024 signal paths, and bus 820 may have M = 8 signal paths or M = 4 signal paths.

[0226] In various instances, each digital line 210 of the memory array 805 may be configured for selective coupling with a specific one, a specific group of signal development components 250 in the signal development component array 825, or may be configured for selective coupling with any of the signal development components 250 in the signal development component array. Alternatively, the signal development components 250 of the signal development component array 825 may be configured for selective coupling with a specific one, a specific group of digital lines 210 in the memory array 805, or may be configured for selective coupling with any of the digital lines 210 in the memory array 805. In other words, the mapping between the digital lines 210 and the signal development components 250 according to the described technology may include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0227] The sense amplifier array 835 may include a set of sense amplifiers 290, which may include a reference Figures 2 to 7 The description covers various aspects of the sense amplifier 290. In some instances, the sense amplifiers of the sense amplifier array 835 may be arranged in a strip or other grouped arrangement. A selection component 830 may be coupled between the signal development component array 825 and the sense amplifier array 835 to support various mappings between the signal development component 250 and the sense amplifier 290. In various instances, the sense amplifier 290 (e.g., of the sense amplifier array 835) may be integrated between (e.g., of the signal development component array 825) cache memory blocks or may be located outside the signal development component cache memory region (e.g., outside the signal development component array 825).

[0228] In some instances, the signal development component array 825 may be coupled to a strip or other group of sense amplifiers 290 (e.g., of the sense amplifier array 835), each of which may also be independently accessible. For example, each sense amplifier in a strip of sense amplifiers 290 may be configured for selective coupling to a specific one, a specific group of sense amplifiers 250 in the signal development component array 825, or may be configured for selective coupling to any one of the sense amplifiers 250 in the signal development component array. Alternatively, the signal development components 250 in the signal development component array 825 may be configured for selective coupling to a specific one, a specific group of sense amplifiers in the sense amplifier strip, or may be configured for selective coupling to any one of the sense amplifiers 290 in the sense amplifier strip. In other words, the mapping between the signal development component 250 of the signal development component array 825 and the sense amplifier 290 of the sense amplifier array 835 (e.g., via the selection component 830) according to the described technology may include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0229] In an illustrative example where memory array 805 is associated with 1,024 digital lines 210, each of the 1,024 digital lines 210 can be coupled to a multiplexer (e.g., of selector 815), reducing the number of digital lines to 64 × 4 = 256. This can support signal transmission of four groups of 64 digital lines that overlap in time (e.g., simultaneous transmission between memory cell 105 and signal development component 250). In some instances, each of these four groups can be routed to any one of eight cache blocks (e.g., of signal development component array 825), where each cache block can contain 8 lines multiplied by 64 bits. In other words, the total cache size associated with this signal development component array 825 can be 64 × 64 bits. According to this example of array routing, any 64-bit sub-row from the memory array can be routed to any one of the 64-bit signal development component cache lines.

[0230] In another illustrative example, system 800 may include (e.g., memory array 805) several domains, each having 1,048,576 memory cells 105 arranged in 1,024 uniquely addressed rows and 1,024 columns. Each of the domains of system 800 may be mapped (e.g., signal development component array 825) to 64 signal development components (e.g., via selection component 815). In other words, the 64 signal development components may be mapped to 1,024 digital lines 210 within each domain. In some instances, a particular signal development component 250 may be mapped to 16 digital lines 210 within each domain (e.g., 1,024 digital lines 210 divided by 64 signal development components 250). In some instances, this mapping may be fixed (e.g., a group of 16 digital lines 210 mapped to a corresponding signal development component 250 within each domain), which in some instances reduces the complexity of multiplexing or selection circuitry. In various other instances, signal development component 250 may be mapped to more than one domain, (e.g., more than one set of digital lines 210) or other configurations. Alternatively, digital line 210 domains or sets may be mapped to more than one signal development component 250. In other words, the memory device may contain various configurations of signal development component 250 to support the instances of multiplexed signal development described herein.

[0231] In this illustrative example, rows of 1024 memory cells 105 (e.g., spanning a domain 310) can be selected by a single word line 205 in each domain. In the case of 64 signal development components 250 per domain, 64 memory cells out of a group of 1024 memory cells 105 can be accessed at once in each domain (e.g., by selectively coupling a corresponding digital line 210 to each of the 64 signal development components 250-a via a selection component 815). During this access, other digital lines 210 can be selectively isolated from signal development components 250 interfacing with the same domain. Furthermore, other digital lines 210 can be shunt or shielded, as described herein.

[0232] Figure 9A and 9B The diagram illustrates examples of component arrangements 900 and 950 supporting multiplexed signal development, as disclosed herein. Each of component arrangements 900 and 950 may include a domain 310-c, a signal development component 250-c, and a sense amplifier 290-c. Component arrangements 900 and 950 may illustrate a layered structure of components, which may include one or more additive, subtractive, or other supporting operations. In some instances, component arrangements 900 and 950 may illustrate layers of a CMOS process.

[0233] The component arrangement 900 can illustrate a layered structure in which signal development components 250-c and domains 310-c are formed or located on the same layer. For example, layer 920 may include domains 310-c-1 and 310-c-2, as well as signal development components 250-c-1 and 250-c-2. For example, layer 930 may include domains 310-c-310 and 310-c-4, as well as signal development components 250-c-3 and 250-c-4. Layer 920 may also include a sense amplifier 290-c, but in various other embodiments, the sense amplifier 290-c may be formed or located on layer 930, or distributed across layers 920 and 930. In various embodiments, layers 920 and 930 may be formed on substrate layer 910 (e.g., on substrate 915). The component arrangement 900 may be an example in which multiple memory cells are distributed across one or more layers and signal development components 250 (e.g., signal storage elements) are distributed across the same one or more layers.

[0234] In some instances, component arrangement 900 may include conductors running from one layer to another, which may be referred to as jacks, electrodes, vias, or traces. In examples of component arrangement 900, jacks may not be associated with charge sharing between domain 310-c and the corresponding signal development component 250-c. Specifically, this charge sharing between domain 310-c and signal development component 250-c may be achieved through in-plane or in-layer conductors, and charge sharing between signal development component 250-c and sense amplifier 290-c may or may not be achieved via jacks. Thus, component arrangement 900 may illustrate signal development component 250-c supporting cache memory in the vertical direction or domain.

[0235] In one instance, each digital line 210 of domain 310-c may be mapped or routed to at least one signal development component 250-c (e.g., at least one capacitor 610), which may be a continuation of the corresponding digital line 210. In some instances, at least one capacitor 610 (e.g., of signal development component 250-c) may be part of at least one row of a capacitor array. This array of capacitors 610 may be implemented as a continuation of the FeRAM array in a logical portion at the memory cell level (e.g., FeRAM array). For example, the FeRAM formation process associated with ferroelectric capacitors may be performed or modified, such as by masking specific steps associated with ferroelectric capacitors, to form a set of linear capacitors 610.

[0236] In such instances, each digital line 210 of domain 310-c can be mapped or routed to an array of integrating capacitors 610. From the sense amplifier side, this arrangement may include a multiplexer (e.g., selection component 280), and the array of capacitors 610 may be partitioned to isolate and overlap transmissions to or from FeRAM memory cells. This arrangement may support charge transfers to or from sense amplifier 290-c via subgroups of the array of integrating capacitors 610 that do not participate in current transfers with FeRAM memory cells 105. Thus, instances of component arrangement 900 address the problem of charge sharing across jacks (vertical metal wires connected to multiple layers), which in some instances may be shared across several layers or layers. For example, where the number of layers or layers increases proportionally in some instances, the charge-sharing load on the jacks may be too high. Therefore, having at least one capacitor 610 on each layer (e.g., closely adjacent to the DL jack) as a temporary cache memory supports the cache memory of the vertical organization of the multiplexed signal development component 250. This "tree" arrangement supports charge sharing in the layer between the FeRAM memory cell 105 and the integrating capacitor 610, as well as parallel read / write operations via the bottom logic through the capacitor 610 and the sense amplifier 290-c.

[0237] Component arrangement 950 can illustrate a layered structure in which signal development components 250-d and domains 310-d are formed or located on different layers. For example, layer 970 may include signal development components 250-d-1, 250-d-2, 250-d-3, and 250-d-4. For example, layer 980 may include domains 310-d-1 and 310-d-2. For example, layer 990 may include domains 310-d-3 and 310-d-4. Layer 970 may also include a sense amplifier 290-d, but in various other embodiments, the sense amplifier 290-d may be formed or located on layers 980 and 990, or distributed across two or more of layers 970, 980, or 990. In various embodiments, layers 970, 980, and 990 may be formed on substrate layer 960 (e.g., on substrate 965). The component arrangement 950 can be an example in which multiple memory cells are distributed across one or more layers and signal development components 250 (e.g., signal storage elements) are distributed across one or more different layers.

[0238] In some instances, component arrangement 950 may include conductors running from one layer to another, which may be referred to as vias, electrodes, through-holes, or traces. In examples of component arrangement 950, vias may be associated with charge sharing between domain 310-d and the corresponding signal development component 250-d. Although component arrangement 950 may be associated with relatively slow charge sharing across vias, component arrangement 950 may advantageously group forming operations for specific component types. For example, in some instances, signal development component 250-d may include linear capacitor 610, while domain 310-a may include memory cell 105 with ferroelectric capacitors. Thus, forming layer 370 may include forming a group of linear capacitors, and forming layers 980 and 990 may include forming several groups of ferroelectric capacitors. This arrangement can support higher density domain 310-d because ferroelectric capacitors can have higher array density (e.g., due to construction in silicon operations), and linear capacitor 610 can have lower array density (e.g., due to construction in CMOS operations). Therefore, in some instances, the signal development component 250-d group may be formed or located below domain 310-d (e.g., closer to substrate layer 960).

[0239] The fabrication of component arrangements 900 and 950 can be performed using layered fabrication methods or any other methods for forming the illustrated arrangements. For example, fabricating component arrangements 900 and 950 may include fabricating a plurality of memory cells, an amplifier assembly, and a plurality of signal development components, each associated with one or more of the plurality of memory cells, on a substrate. The fabrication may further include fabricating selection components on the substrate, the selection components being coupled to and configured to selectively couple selected signal development components of the plurality of signal development components to the amplifier assembly. In some instances, fabricating the plurality of memory cells includes fabricating a plurality of ferroelectric capacitors. In some instances, fabricating each of the plurality of signal development components includes fabricating a capacitor, fabricating an amplifier, or both. In some instances, the capacitors of the plurality of signal development components may include fabricating a linear dielectric portion of each of the capacitors. Different fabrication steps and arrangements may be performed to fabricate component arrangements 900 or 950.

[0240] Figure 10 A block diagram 1000 illustrates a memory device 1005 developed to support multiplexed signals, based on examples disclosed herein. The memory device 1005 may be referred to as an electronic memory device and may be used as a reference. Figure 1 Examples of components of the described memory device 100.

[0241] Memory device 1005 may include one or more memory cells 1010, which may be used as a reference. Figures 1 to 8 Examples of memory cells 105 described herein (e.g., memory segment 110). Memory device 1005 may also include a memory controller 1015, word lines 1020, board lines 1025, sensing components 1035, and digital lines 1040. These components may communicate electronically with each other and perform one or more of the functions described herein. In some cases, memory controller 1015 may include biasing components 1050 and timing components 1055.

[0242] The memory controller 1015 can be connected to word lines 1020, board lines 1025, digital lines 1040, and sensing components 1035 (which may be referenced). Figures 1 to 8 The described word line 205, board line 215, digital line 210, and sensing component 150 (examples) communicate electronically. In some examples, the memory device 1005 may also include an I / O component 1045, which may be an example of an input / output component 160 as described herein. The components of the memory device 1005 can communicate electronically with each other and perform reference operations. Figures 1 to 8 The functions described. In some cases, the sensing component 1035 or the I / O component 1045 may be a component of the memory controller 1015.

[0243] In some instances, digital line 1040 may electronically communicate with sensing component 1035 (e.g., via selection component 320, via bypass line 260, as described herein) and capacitors or ferroelectric capacitors of memory cell 1010. Memory cell 1010 may be written to in a logical state (e.g., a first or second logical state). Word line 1020 may electronically communicate with memory controller 1015 (e.g., row components or row decoders of memory controller 1015) and cell selection components (e.g., switching components, transistors) of memory cell 1010. Board line 1025 may electronically communicate with the memory controller 1015 and the board of capacitors or ferroelectric capacitors of memory cell 1010. Sensing component 1035 may electronically communicate with memory controller 1015, digital line 1040, and I / O component 1045. The sensing control line 1065 can electronically communicate with the sensing component 1035 and the memory controller 1015, and can be used to control various aspects of the sensing component 1035 (e.g., selecting one of a set of multiplexed signal development components 250 of the sensing component 1035 to support multiplexed signal development). In addition to components not listed above, these components can also electronically communicate with other components inside or outside the memory device 1005 via other components, connections, or buses.

[0244] Memory controller 1015 may be an example of memory controller 170 as described herein, and may be configured to activate word line 1020, board line 1025, or digital line 1040 by applying voltage to various nodes. For example, bias component 1050 may be configured to apply a voltage to operating memory cell 1010 to read or write to memory cell 1010 as described herein. In some instances, memory controller 1015 may include one or more of row component 125, column component 135, or board component 145, or may otherwise perform one or more operations described with reference to row component 125, column component 135, or board component 145, or may otherwise communicate with row component 125, column component 135, board component 145, or combinations thereof, as described herein. Figures 1 to 8 As described, this allows the memory controller 1015 to access one or more memory cells 1010. The biasing component 1050 can provide a voltage (e.g., a voltage source) for coupling with the memory cell 1010. Alternatively, the biasing component 1050 can provide a voltage (e.g., a voltage source) for operation of the sensing component 1035.

[0245] In some cases, the memory controller 1015 may use timing component 1055 to perform one or more of its operations. For example, timing component 1055 may control the timing of various word line selections, signal development component selections, or board biases, including timing for switching and voltage application to perform the memory functions discussed herein (e.g., read and write operations) (e.g., according to read operation 400 or 450, write operation 500 or 550). In some cases, timing component 1055 may control the operation of bias component 1050. In some cases, timing component 1055 may include a timer or clock associated with memory segment 110 of memory device 1005.

[0246] Sensing component 1035 can compare a sensed signal from memory cell 1010 (e.g., via digital line 1040) with a reference signal. After determining a logic state, sensing component 1035 can then provide an output in I / O component 1045, which can be used according to the operation of an electronic device that may include memory device 1005. Sensing component 1035 may include one or more sensing amplifiers 290 that are in electronic communication with I / O component and memory cell 1010.

[0247] The memory controller 1015 or its sub-components may be implemented in hardware, processor-executable code (e.g., software, firmware), or any combination thereof. If implemented in processor-executable code, the functionality of the memory controller 1015 or its sub-components may be performed by a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof, designed to perform the functions disclosed herein.

[0248] The memory controller 1015 or its sub-components may be physically located in various locations, including distributed components that enable functionality to be implemented by one or more physical devices at different physical locations. In some instances, the memory controller 1015 or its sub-components may be separate and distinct components. In other instances, the memory controller 1015 or its sub-components may be combined with one or more other hardware components (including, but not limited to, I / O components, transceivers, network servers, another computing device, one or more other components described herein, or combinations thereof). The memory controller 1015 may be a reference. Figure 11 The memory controller 1115 described or referenced Figure 12 An example of the memory controller 1215 described.

[0249] In some instances, the memory controller 1015, including any of its sub-components, may support the described instances of multiplexed signal development in the memory device 1005. For example, the memory device 1005 may include a plurality of memory cells, an amplifier assembly, and a plurality of signal development components, each associated with one or more of the plurality of memory cells. The memory device 1005 may also include a selection component coupled to and configured to selectively couple a selected signal development component from the plurality of signal development components to the amplifier assembly.

[0250] The memory controller 1015 may be operable, for example, such that the memory device 1005 develops a signal at the signal development component based at least in part on selectively coupling the signal development component of the plurality of signal development components to the memory cells of the plurality of memory cells, and generates the output signal of the amplifier component based at least in part on the developed signal at the signal development component. Alternatively, the memory controller 1015 may be operable, for example, such that the memory device generates a signal at the signal development component based at least in part on selectively coupling the signal development component of the plurality of signal development components to the amplifier component, and develops a cell write signal at the memory cells of the plurality of memory cells based at least in part on the generated signal at the signal development component.

[0251] Figure 11 A block diagram 1100 illustrates a memory controller 1115 developed to support multiplexed signals, based on examples disclosed herein. The memory controller 1115 may be used as a reference. Figure 1 The memory controller 170 described or referenced Figure 10 An example of the described memory controller 1015. The memory controller 1115 may include a bias component 1120 and a timing component 1125, which may be referenced. Figure 10 Examples of the bias component 1050 and timing component 1055 described herein. The memory controller 1115 may also include a voltage selector 1130, a memory cell selector 1135, and a sense controller 1140, which may be examples of the selection component 280 described herein or include the selection component 280. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0252] Voltage selector 1130 can initiate the selection of a voltage source to support various access operations of the memory device. For example, voltage selector 1130 can generate or trigger control signals for activating or deactivating various switching components or voltage sources, or generate or trigger signals that can be provided to, as in reference... Figures 1 to 10The control signals described are for the row assembly 125, board assembly 145, sensing assembly 150, or reference assembly 270. For example, voltage selector 1130 may generate one or more of the following logic signals for selecting (e.g., enabling or disabling) the voltage of word line 205, digital line 210, or board line 215, or for activating or deactivating shunt 330.

[0253] Memory cell selector 1135 can select memory cells for access operations (e.g., read, write, rewrite, refresh, and other operations). In some instances, memory cell selector 1135 can generate logic signals for activating or deactivating memory segment 110 of the memory device. In some instances, memory cell selector 1135 can generate logic signals or address signals for activating or deactivating cell selection components (e.g., cell selection component 225 described herein). In some instances, memory cell selector 1135 can start or otherwise control the word line voltages described herein.

[0254] The sense controller 1140 can control various operations of a sensing component (such as sense component 150 described herein). For example, the sense controller 1140 can generate logic signals (e.g., isolation signals) for activating or deactivating a sense component isolation component (e.g., a switching component between sense component 150 and memory segment 110 or reference component 270). In some instances, the sense controller 1140 can generate logic signals (e.g., equalization signals, shunt signals) for balancing the nodes of sense component 150. In some instances, the sense controller 1140 can generate logic signals for coupling or decoupling the sense component from a sense voltage source or from input / output component 160 or I / O component 1235.

[0255] The sensing controller 1140 may be operable, for example, to develop a signal at a signal development component based at least in part on selectively coupling a signal development component of a plurality of signal development components to a memory cell of a plurality of memory cells, and to generate an output signal of an amplifier component based at least in part on the developed signal at the signal development component. Alternatively, the sensing controller 1140 may be operable, for example, to generate a signal at a signal development component based at least in part on selectively coupling a signal development component of a plurality of signal development components to an amplifier component, and to develop a cell write signal at a memory cell of a plurality of memory cells based at least in part on the generated signal at the signal development component.

[0256] Figure 12A diagram illustrating a system 1200 including a device 1205 supporting the development of multiplexed signals, according to an example disclosed herein. Device 1205 may be, for example, referenced... Figure 1 The described memory device 100 is an example of a memory device 100 or a component comprising a memory device 100. Device 1205 may include components for bidirectional communication, components for transmitting and receiving communication, and includes a memory controller 1215, a memory cell 1220, a basic input / output system (BIOS) component 1225, a processor 1230, I / O components 1235, and peripheral components 1240. These components may communicate electronically via one or more buses (e.g., bus 1210).

[0257] The memory controller 1215 can operate on one or more memory cells as described herein. Specifically, the memory controller 1215 can be configured to support the described schemes for accessing memory cells, including multiplexed signal development. In some cases, the memory controller 1215 may include row components, column components, board components, or combinations thereof, as referenced herein. Figures 1 to 8 As described.

[0258] Memory cell 1220 may be used as a reference Figures 1 to 10 The memory cell 105 or 1010 described herein is an instance of a memory cell that can store information (e.g., in the form of logical states), as described herein.

[0259] BIOS component 1225 is a software component containing a BIOS that operates as firmware, which initializes and runs various hardware components. BIOS component 1225 also manages data flow between the processor and various other components (e.g., peripheral components, I / O control components, and other components). BIOS component 1225 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0260] Processor 1230 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, central processing units (CPUs), microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components). In some cases, processor 1230 may be configured to operate a memory array using a memory controller. In other cases, the memory controller may be integrated into processor 1230. Processor 1230 may be configured to execute computer-readable instructions stored in memory to perform various functions (e.g., functions or tasks supporting access schemes for access line failures in the memory device).

[0261] I / O component 1235 manages input and output signals for device 1205. I / O component 1235 can also manage peripheral devices not integrated into device 1205. In some cases, I / O component 1235 may represent a physical connection or port to an external peripheral device. In some cases, I / O component 1235 may utilize an operating system, such as... Or another known operating system. In other cases, I / O component 1235 may represent or interact with a modem, keyboard, mouse, touchscreen, or similar device. In some cases, I / O component 1235 may be implemented as part of a processor. In some cases, a user may interact with device 1205 via I / O component 1235 or via hardware components controlled by I / O component 1235. I / O component 1235 may support access to memory units 1220, including receiving information associated with the sensed logical state of one or more memory units 1220, or providing information associated with the logical state of one or more memory units 1220.

[0262] Peripheral component 1240 may include any input or output device, or an interface for such devices. Examples may include a disk controller, sound controller, graphics controller, Ethernet controller, modem, Universal Serial Bus (USB) controller, serial or parallel port, or peripheral card slot, such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot.

[0263] Input 1245 may represent a device or signal external to device 1205 that provides input to device 1205 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 1245 may be managed by I / O component 1235 and may interact with device 1205 via peripheral component 1240.

[0264] Output 1250 may represent a device or signal external to device 1205 configured to receive output from any of device 1205 or its components. Examples of output 1250 may include a display, audio speaker, printing device, another processor or printed circuit board, or other device. In some cases, output 1250 may be a peripheral element that interfaces with device 1205 via peripheral component 1240. In some cases, output 1250 may be managed by I / O component 1235.

[0265] The components of device 1205 may include circuitry designed to perform its functions. This may include various circuit elements configured to perform the functions described herein, such as conductive wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components. Device 1205 may be a computer, server, laptop computer, notebook computer, tablet computer, mobile phone, wearable electronic device, personal electronic device, etc. Alternatively, device 1205 may be part of or a component of such a device.

[0266] Figure 13 The diagram illustrates a method 1300 for developing support multiplexed signals, as illustrated in the examples presented herein. See references. Figures 1 to 12 The described methods, circuit systems, and devices perform the operations of method 1300. In some instances, the operations of method 1300 may be performed by memory device 100 or components or circuit systems of memory device 100, as referenced. Figures 1 to 12 As described. In some instances, the memory device may execute a set of instructions to control functional elements of the device (e.g., circuitry, voltage supply, logic signals, transistors, amplifiers, switching components, selection components) to perform the described functions. Alternatively or concurrently, the memory device may use dedicated hardware to perform some or all of the described functions. In some instances, it may be based on references... Figure 4A The described read operation 400 or reference Figure 4B The described read operation 450 executes method 1300.

[0267] At 1305, the memory device can determine whether to access the first memory cell and the second memory cell.

[0268] At 1310, the memory device may couple the first memory cell to the first signal development component during a first time interval and based on determining that the first memory cell needs to be accessed.

[0269] At 1315, the memory device may couple the second memory cell to the second signal development component during a second time interval that overlaps with the first time interval and based on determining that the second memory cell needs to be accessed.

[0270] At 1320, the memory device may couple the first signal development component to the amplifier component during a third time interval following the first time interval.

[0271] At 1325, the memory device may couple the second signal development component to the amplifier component during a fourth time interval following the second time interval.

[0272] In some instances, an apparatus capable of performing the methods described herein (including method 1300) may include: means for determining to access a first memory cell and a second memory cell; means for coupling the first memory cell to a first signal development component during a first time interval and based on determining to access the first memory cell; means for coupling the second memory cell to a second signal development component during a second time interval overlapping with the first time interval and based on determining to access the second memory cell; means for coupling the first signal development component to an amplifier component during a third time interval following the first time interval; and means for coupling the second signal development component to the amplifier component during a fourth time interval following the second time interval.

[0273] In some instances, an apparatus capable of performing the methods described herein (including method 1300) may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: determine that a first memory cell and a second memory cell are to be accessed; couple the first memory cell to a first signal development component during a first time interval and based on the determination that the first memory cell is to be accessed; couple the second memory cell to a second signal development component during a second time interval overlapping with the first time interval and based on the determination that the second memory cell is to be accessed; couple the first signal development component to an amplifier component during a third time interval following the first time interval; and couple the second signal development component to the amplifier component during a fourth time interval following the second time interval.

[0274] In some instances, instructions for performing the methods described herein (including method 1300) may be stored as code on a non-transitory computer-readable medium. The code may contain instructions executable to: determine that a first memory cell and a second memory cell are to be accessed; couple the first memory cell to a first signal development component during a first time interval and based on the determination to access the first memory cell; couple the second memory cell to a second signal development component during a second time interval overlapping with the first time interval and based on the determination to access the second memory cell; couple the first signal development component to an amplifier component during a third time interval following the first time interval; and couple the second signal development component to the amplifier component during a fourth time interval following the second time interval.

[0275] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the first memory cell to the first signal development component may include operations, features, elements, or instructions for selectively coupling the first signal development component to a first selected access line in the first set of access lines associated with the first memory cell via a first selection component coupled to a first set of access lines.

[0276] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the second memory cell to the second signal development component may include operations, features, elements, or instructions for selectively coupling the second signal development component to a second selected access line in the second set of access lines associated with the second memory cell via a second selection component coupled to a second set of access lines.

[0277] Examples of the methods, apparatus, and non-transitory computer-readable media may include operations, features, components, or instructions for decoupling the first signal development component from the amplifier component after coupling the first signal development component to the amplifier component.

[0278] In some instances of the methods, apparatus, and non-transitory computer-readable media, the first signal development component may be decoupled from the amplifier component before the second signal development component is coupled to the amplifier component.

[0279] In some instances of the methods, apparatus, and non-transitory computer-readable media, the coupling of the second signal development component to the amplifier component may begin after a delay following the decoupling of the first signal development component from the amplifier component.

[0280] In some instances of the methods, apparatus, and non-transitory computer-readable media, the third time interval at least partially overlaps with the second time interval.

[0281] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the first signal development component to the amplifier component may include operations, features, components, or instructions for selectively coupling the first signal development component via a selection component, and coupling the second signal development component to the amplifier component may include operations, features, components, or instructions for selectively coupling the second signal development component via the selection component.

[0282] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the second signal development component to the amplifier component may occur after the third time interval.

[0283] In some instances of the methods, apparatuses, and non-transitory computer-readable media described herein, the third time interval may be within the second time interval.

[0284] Figure 14 The diagram illustrates a method 1400 for developing supported multiplexed signals, as illustrated in the examples presented herein. See references. Figures 1 to 12 The described methods, circuit systems, and devices perform the operations of method 1400. In some instances, the operations of method 1400 may be performed by memory device 100 or components or circuit systems of memory device 100, as referenced. Figures 1 to 12 As described. In some instances, the memory device may execute a set of instructions to control functional elements of the device (e.g., circuitry, voltage supply, logic signals, transistors, amplifiers, switching components, selection components) to perform the described functions. Alternatively or concurrently, the memory device may use dedicated hardware to perform some or all of the described functions. In some instances, it may be based on references... Figure 5A The described write operation 500 or reference Figure 5B The described write operation 550 executes method 1400.

[0285] At 1405, the memory device can determine whether to access the first memory cell and the second memory cell.

[0286] At 1410, the memory device may couple the first signal development component to the amplifier component during a first time interval and based on determining that the first memory cell needs to be accessed.

[0287] At 1415, the memory device may couple the second signal development component to the amplifier component during a second time interval following the first time interval and based on determining that the second memory cell needs to be accessed.

[0288] At 1420, the memory device may couple the first signal development component to the first memory cell during a third time interval following the first time interval.

[0289] At 1425, the memory device may couple the second signal development component to the second memory cell during a fourth time interval following the second time interval which overlaps with the third time interval.

[0290] In some instances, an apparatus capable of performing the methods described herein (including method 1400) may include components for performing the following operations: determining access to a first memory cell and a second memory cell; coupling a first signal development component to an amplifier component during a first time interval and based on determining access to the first memory cell; coupling a second signal development component to the amplifier component during a second time interval following the first time interval and based on determining access to the second memory cell; coupling the first signal development component to the first memory cell during a third time interval following the first time interval; and coupling the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0291] In some instances, an apparatus capable of performing the methods described herein (including method 1400) may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: determine that a first memory cell and a second memory cell are to be accessed; couple a first signal development component to an amplifier component during a first time interval and based on the determination that the first memory cell is to be accessed; couple a second signal development component to the amplifier component during a second time interval following the first time interval and based on the determination that the second memory cell is to be accessed; couple the first signal development component to the first memory cell during a third time interval following the first time interval; and couple the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0292] In some instances, instructions for performing the methods described herein (including method 1400) may be stored as code on a non-transitory computer-readable medium. The code may contain instructions executable to: determine that a first memory cell and a second memory cell are to be accessed; couple a first signal development component to an amplifier component during a first time interval and based on the determination to access the first memory cell; couple a second signal development component to the amplifier component during a second time interval following the first time interval and based on the determination to access the second memory cell; couple the first signal development component to the first memory cell during a third time interval following the first time interval; and couple the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0293] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the first signal development component to the first memory cell may include operations, features, elements, or instructions for selectively coupling the first signal development component to a first selected access line in the first set of access lines that may be associated with the first memory cell via a first selection component that may be coupled to a first set of access lines.

[0294] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the second signal development component to the second memory cell may include operations, features, elements, or instructions for selectively coupling the second signal development component to a second selected access line in the second set of access lines that may be associated with the second memory cell via a second selection component that may be coupled to a second set of access lines.

[0295] Examples of the methods, apparatus, and non-transitory computer-readable media may include operations, features, components, or instructions for decoupling the first signal development component from the amplifier component after coupling the first signal development component to the amplifier component.

[0296] In some instances of the methods, apparatus, and non-transitory computer-readable media, the first signal development component may be decoupled from the amplifier component before the second signal development component is coupled to the amplifier component.

[0297] In some instances of the methods, apparatus, and non-transitory computer-readable media, the coupling of the second signal development component to the amplifier component may begin after a delay following the decoupling of the first signal development component from the amplifier component.

[0298] In some instances of the methods, apparatus, and non-transitory computer-readable media, the third time interval at least partially overlaps with the second time interval.

[0299] In some instances of the methods, apparatus, and non-transitory computer-readable media, coupling the first signal development component to the amplifier component may include operations, features, components, or instructions for selectively coupling the first signal development component via a selection component, and coupling the second signal development component to the amplifier component may include operations, features, components, or instructions for selectively coupling the second signal development component via the selection component.

[0300] In some instances of the method, apparatus, and non-transitory computer-readable media, the second time interval may be within the third time interval.

[0301] Figure 15The diagram illustrates a method 1500 for developing support multiplexed signals based on examples as disclosed herein. The operations of method 1500 can be performed to create a reference. Figures 1 to 12 Examples of the described circuit systems and devices. In some examples, references may be used. Figure 9A The described component arrangement 900 or reference Figure 9B The described component arrangement 950 executes method 1500.

[0302] At 1505, method 1500 may include fabricating a set of memory cells on a substrate.

[0303] At 1510, method 1500 may include fabricating an amplifier assembly on the substrate.

[0304] At 1515, method 1500 may include fabricating a set of signal development components on the substrate, each associated with one or more memory cells in the group of memory cells.

[0305] At 1520, method 1500 may include fabricating a selection component on the substrate, the selection component being coupled to and configured to selectively couple a selected signal development component in the group signal development component to the amplifier component.

[0306] In some instances of method 1500, the fabrication of each signal development component in the group of signal development components may include operations for fabricating a capacitor.

[0307] In some instances of method 1500, fabricating the group memory cell may include operations for fabricating the group memory cell across one or more layers on the substrate, and fabricating the capacitor of the group signal development component may include operations for fabricating the capacitor across the one or more layers on the substrate.

[0308] In some instances of method 1500, fabricating the group memory cell may include operations for fabricating the group memory cell across one or more layers on the substrate, and fabricating the capacitor of the group signal development component may include operations for fabricating the capacitor across one or more different layers on the substrate.

[0309] In some instances of method 1500, the capacitors used to fabricate the group signal development components may include operations for fabricating a linear dielectric portion of each of the capacitors.

[0310] In some instances of method 1500, fabricating the group of memory cells may include operations for fabricating a group of ferroelectric capacitors.

[0311] Some instances of method 1500 may include operations for fabricating a set of second selection components on the substrate, each of the set of second selection components being associated with and configured to selectively couple any one of the set of memory cells to the corresponding signal development component.

[0312] In some instances of method 1500, the fabrication of the group signal development component may include operations for fabricating a group of amplifiers.

[0313] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, aspects from two or more of the methods can be combined.

[0314] Describe an apparatus. The apparatus may include: a plurality of memory cells; an amplifier assembly; a plurality of signal development components, each associated with one or more of the plurality of memory cells; and a selection component coupled to the plurality of signal development components and configured to selectively couple a selected signal development component of the plurality of signal development components to the amplifier assembly.

[0315] In some instances, each of the plurality of signal development components may be associated with a set of memory cells in the plurality of memory cells, and the device may further include a plurality of second selection components, each of the plurality of second selection components being associated with a corresponding signal development component and configured to selectively couple any one of the set of memory cells to the corresponding signal development component.

[0316] In some instances, each of the plurality of signal development components includes a signal storage element.

[0317] In some instances, the plurality of memory cells may be distributed across one or more layers, and the signal storage elements of the plurality of signal development components may be distributed across the one or more layers.

[0318] In some instances, the plurality of memory cells may be distributed across one or more layers, and the signal storage elements of the plurality of signal development components may be distributed across one or more different layers.

[0319] In some instances, each signal storage element of the plurality of signal development components may include a capacitor.

[0320] In some instances, each of the plurality of signal development components may include a charge transfer sensing amplifier.

[0321] In some instances, the amplifier may be configured to transfer charge between the first access line and the second access line based at least in part on one or both of the voltage of the first access line and the voltage of the second access line.

[0322] In some instances, the plurality of memory cells may be distributed across one or more layers, and the plurality of signal development components may be distributed at least partially across the one or more layers.

[0323] In some instances, the plurality of memory cells may be distributed across one or more layers, and the plurality of signal development components may be distributed at least partially across one or more different layers.

[0324] In some instances, each of the plurality of memory cells may contain a ferroelectric capacitor.

[0325] In some instances, the device may be configured to: develop a signal at a signal development component based at least in part on selectively coupling a signal development component of the plurality of signal development components to a memory cell of the plurality of memory cells, wherein the development of the signal at the signal development component is associated with a first waiting time; and generate an output signal of the amplifier component based at least in part on the developed signal at the signal development component, wherein the generation of the output signal of the amplifier component is associated with a second waiting time of a duration shorter than the first waiting time.

[0326] In some instances, the device may be configured to: generate a signal at a signal development component based at least in part on selectively coupling the signal development component of the plurality of signal development components to the amplifier component, wherein the generation of the signal at the signal development component is associated with a third waiting time; and develop a cell write signal at a memory cell of the plurality of memory cells based at least in part on the generated signal at the signal development component, wherein the development of the cell write signal at the memory cell is associated with a fourth waiting time having a duration longer than the third waiting time.

[0327] Describe another device. The device may include a plurality of memory cells, an amplifier assembly, and a plurality of signal development assemblies. The device may also include circuitry configured to: couple a first memory cell to a first signal development assembly of the plurality of signal development assemblies during a first time interval and at least in part based on a determination to access a first memory cell and a second memory cell of the plurality of memory cells; couple a second memory cell to a second signal development assembly of the plurality of signal development assemblies during a second time interval overlapping with the first time interval and at least in part based on the determination to access the first memory cell and the second memory cell; couple the first signal development assembly to the amplifier assembly during a third time interval following the first time interval; and couple the second signal development assembly to the amplifier assembly during a fourth time interval following the second time interval.

[0328] In some instances, the device may include a selection component coupled to the plurality of signal development components, and the circuitry may be configured to couple the first signal development component to the amplifier component via the selection component, and the second signal development component to the amplifier component via the selection component.

[0329] Describing another device. The device may include multiple memory cells, an amplifier assembly, and multiple signal development components. The device may also include circuitry configured to: couple a first signal development component to the amplifier assembly during a first time interval and at least in part based on a determination to access a first memory cell; couple a second signal development component to the amplifier assembly during a second time interval following the first time interval and at least in part based on a determination to access a second memory cell; couple the first signal development component to the first memory cell during a third time interval following the first time interval; and couple the second signal development component to the second memory cell during a fourth time interval following the second time interval overlapping with the third time interval.

[0330] In some instances, the device may include a selection component coupled to the plurality of signal development components, and the circuitry may be configured to couple the first signal development component to the amplifier component via the selection component, and the second signal development component to the amplifier component via the selection component.

[0331] Describing another device. The device may include: a memory array; a plurality of signal development components, each associated with one or more access lines of the memory array; and a first plurality of selection components, each coupled to a subgroup of the plurality of signal development components and configured to selectively couple a selected signal development component in the subgroup to one of a plurality of amplifier components.

[0332] In some instances, each of the plurality of signal development components may be associated with a plurality of access lines of the memory array, and the device may include a second plurality of selection components, each of the second plurality of selection components being coupled to and configured to selectively couple a selected access line of the plurality of access lines to the corresponding one of the signal development components.

[0333] The description herein provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various operations, procedural steps, or components may be omitted, substituted, or added as appropriate in some examples. Furthermore, features described with respect to some examples may be combined in other examples.

[0334] The information and signals described herein can be represented using any of a variety of different techniques and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips mentioned above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, which can have various bit widths.

[0335] As used herein, the term "virtual ground" refers to a node of a circuit that maintains a voltage of approximately zero volts (0V), or more generally, to the reference voltage of said circuit or device containing said circuit (which may or may not be directly coupled to ground). Thus, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V or a virtual 0V in steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "via virtual ground" means connected to approximately 0V, or some other reference voltage of the device.

[0336] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between them. This may include direct connection or coupling between components or may include intermediate components. In other words, components "connected to" or "coupled to" communicate electronically with each other. Components communicating electronically may actively exchange electrons or signals (e.g., in an energized circuit) or passively exchange electrons or signals (e.g., in an unenergized circuit), but may be configured and operable to exchange electrons or signals immediately after the circuit is energized. By way of example, two components physically connected or coupled via a switch (e.g., a transistor) communicate electronically regardless of the state of the switch (e.g., open or closed).

[0337] The phrase "coupled between" can refer to the order of components relative to each other, and can also refer to electrical coupling. In one instance, component "B" electrically coupled between component "A" and component "C" can refer to the component order of "ABC" or "CBA" in inductive sensing. In other words, an electrical signal (e.g., voltage, charge, current) can be transmitted from component A to component C through component B.

[0338] The statement that component B is "coupled" "between" components A and C should not necessarily be interpreted as excluding other intervening components in the described order. For example, component "D" may be coupled between the described components A and B (e.g., referring to the component order of "ADBC" or "CBDA" as examples), while still supporting component B's electrical coupling between components A and C. In other words, the phrase "coupled between" should not be interpreted as requiring reference to an exclusive order.

[0339] Furthermore, the statement that component B is "coupled" "between" components A and C does not preclude a second, distinct coupling between components A and C. For example, components A and C may be coupled to each other in a separate coupling (which is in parallel with the coupling via component B). In another instance, components A and C may be coupled via another component "E" (e.g., component B is coupled between components A and C, and component E is coupled between components A and C). In other words, the phrase "coupled between" should not be interpreted as an exclusive coupling between components.

[0340] The term "isolation" refers to a relationship between components in which electrons are currently unable to flow; if there is an open circuit between the components, then the components are isolated from each other. For example, two components physically coupled by a switch can be isolated from each other when the switch is open.

[0341] As used herein, the term "short circuit" refers to a relationship between components in which a conductive path is established between the components in question via the activation of a single intermediate component between the two components. For example, when a switch between two components is closed, the first component shorted to the second component can exchange electrons with the second component. Thus, a short circuit can enable dynamic operation that allows the application of voltage and / or charge flow between components (or lines) that are communicating electronically.

[0342] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory device 100.

[0343] As used herein, the term "terminal" does not necessarily imply a physical boundary or connection point of a circuit element. More precisely, "terminal" can refer to a reference point in the circuit associated with a circuit element, and may also be referred to as a "node" or "reference point".

[0344] As used herein, the term "layer" can refer to a hierarchical or sheet-like geometric structure, each layer having three dimensions (e.g., height, width, and depth) and covering some or all of a surface. For example, a layer can be a three-dimensional structure where two dimensions are greater than the third, such as a thin film. Layers can contain different elements, components, and / or materials. In some cases, a layer may consist of two or more sublayers. In some figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that the layer is inherently three-dimensional.

[0345] Chalcogenide materials can be materials or alloys containing at least one of the elements S, Se, and Te. The phase change materials discussed in this article can be chalcogenide materials. Chalcogenide materials can include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition designations indicate elements contained in a particular compound or alloy and are intended to represent all stoichiometry relating to the indicated element. For example, Ge-Te may include GexTey, where x and y can be any positive integers. Other examples of variable resistance materials may include binary metal oxide materials or mixed-valence oxides (containing two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals). Examples are not limited to one or more specific variable resistance materials associated with memory elements of memory cells. For example, other examples of variable resistance materials may be used to form memory elements and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, as well as other materials.

[0346] Includes reference Figure 1 , 2 The memory devices 100, 200, and 300 described herein, and the devices discussed herein, can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial semiconductor material layer on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0347] The transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped or degraded semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (e.g., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (e.g., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0348] The descriptions herein, taken in conjunction with the accompanying drawings, depict exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or diagram" and is not necessarily "preferred" or "superior to other instances." Detailed descriptions include specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0349] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by a dash following the reference label and a second label distinguishing them among similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0350] The various illustrative blocks and modules described herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0351] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Moreover, as used herein (including in the claims), "or" as used in a list of items (for example, a list of items preceded by phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (e.g., A and B and C).

[0352] As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term “substantially”) is not necessarily absolute, but close enough to be absolute to achieve the advantage of the characteristic, or close enough to be absolute for the mentioned characteristic to hold true in the context of the relevant aspect of this disclosure.

[0353] As used herein, the phrase “based on” should not be construed as a reference to a set of closed conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on”.

[0354] The descriptions herein are provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will readily become apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: Determine whether to access the first memory unit and the second memory unit; The first memory cell is coupled to the first signal development component during the first time interval and at least in part based on the determination that the first memory cell needs to be accessed; During a second time interval that overlaps with the first time interval and at least in part based on the determination that the second memory cell needs to be accessed, the second memory cell is coupled to the second signal development component; During a third time interval following the first time interval, the first signal development component is coupled to the amplifier component; and The second signal development component is coupled to the amplifier component during a fourth time interval following the second time interval.

2. The method of claim 1, wherein coupling the first memory cell to the first signal development component comprises selectively coupling the first signal development component to a first selected access line of the first plurality of access lines associated with the first memory cell via a first selection component coupled to the first plurality of access lines.

3. The method of claim 2, wherein coupling the second memory cell to the second signal development component comprises selectively coupling the second signal development component to a second selected access line of the second plurality of access lines associated with the second memory cell via a second selection component coupled to the second plurality of access lines.

4. The method of claim 1, further comprising: After coupling the first signal development component to the amplifier component, the first signal development component is decoupled from the amplifier component.

5. The method of claim 4, wherein the first signal development component is decoupled from the amplifier component before coupling the second signal development component to the amplifier component.

6. The method of claim 5, wherein the second signal development component is coupled to the amplifier component after a delay following the decoupling of the first signal development component from the amplifier component.

7. The method of claim 1, wherein the third time interval at least partially overlaps with the second time interval.

8. The method according to claim 1, wherein: Coupling the first signal development component to the amplifier component includes selectively coupling the first signal development component via a selection component; and Coupling the second signal development component to the amplifier component includes selectively coupling the second signal development component via the selection component.

9. A method for memory operations, comprising: Determine whether to access the first memory unit and the second memory unit; During the first time interval and at least in part based on the determination that the first memory cell needs to be accessed, the first signal development component is coupled to the amplifier component; During a second time interval following the first time interval and at least in part based on the determination to access the second memory cell, the second signal development component is coupled to the amplifier component; During a third time interval following the first time interval, the first signal development component is coupled to the first memory cell; and The second signal development component is coupled to the second memory cell during a fourth time interval following the second time interval which overlaps with the third time interval.

10. The method of claim 9, wherein coupling the first signal development component to the first memory cell comprises: The first signal development component is coupled to the first access line of the first plurality of access lines associated with the first memory cell via a first selection component coupled to the first plurality of access lines.

11. The method of claim 10, wherein coupling the second signal development component to the second memory cell comprises: The second signal development component is coupled to the second access line of the second plurality of access lines associated with the second memory cell via a second selection component coupled to the second plurality of access lines.

12. The method of claim 9, further comprising: After coupling the first signal development component to the amplifier component, the first signal development component is decoupled from the amplifier component.

13. The method of claim 12, wherein the first signal development component is decoupled from the amplifier component before coupling the second signal development component to the amplifier component.

14. The method of claim 13, wherein the second signal development component is coupled to the amplifier component after a delay following the decoupling of the first signal development component from the amplifier component.

15. The method of claim 9, wherein the second time interval at least partially overlaps with the third time interval.

16. The method according to claim 9, wherein: Coupling the first signal development component to the amplifier component includes coupling the first signal development component via a selection component; and Coupling the second signal development component to the amplifier component includes coupling the second signal development component via the selection component.

17. A memory device comprising: Multiple memory units; Amplifier components; Multiple signal development components; and The circuit system is configured as follows: During a first time interval and at least in part based on the determination that a first memory cell among the plurality of memory cells and a second memory cell among the plurality of memory cells are to be accessed, the first memory cell is coupled to a first signal development component among the plurality of signal development components; During a second time interval that overlaps with the first time interval and at least in part based on the determination to access the first memory cell and the second memory cell, the second memory cell is coupled to the second signal development component of the plurality of signal development components; During a third time interval following the first time interval, the first signal development component is coupled to the amplifier component; and The second signal development component is coupled to the amplifier component during a fourth time interval following the second time interval.

18. The memory device of claim 17, further comprising: Select a component, which is coupled to the plurality of signal development components, wherein the circuit system is configured to: The first signal development component is coupled to the amplifier component via the selection component; and The second signal development component is coupled to the amplifier component via the selection component.

19. A memory device comprising: Multiple memory units; Amplifier components; Multiple signal development components; and The circuit system is configured as follows: The first signal development component is coupled to the amplifier component during the first time interval and at least in part based on the determination that the first memory cell needs to be accessed; During a second time interval following the first time interval and at least in part based on the determination to access the second memory cell, the second signal development component is coupled to the amplifier component; During a third time interval following the first time interval, the first signal development component is coupled to the first memory cell; and The second signal development component is coupled to the second memory cell during a fourth time interval following the second time interval which overlaps with the third time interval.

20. The memory device of claim 19, further comprising: Select a component, which is coupled to the plurality of signal development components, wherein the circuit system is configured to: The first signal development component is coupled to the amplifier component via the selection component; and The second signal development component is coupled to the amplifier component via the selection component.

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